A storage device and an interface
chip thereof are provided, wherein the interface
chip can be applied to the storage device. The interface
chip comprises a slave interface circuit, a master interface circuit, and a
control circuit. The storage device comprises a
memory controller and a non-volatile (NV) memory, and the NV memory comprises a plurality of NV memory chips. The slave interface circuit is arranged for
coupling the interface chip to the
memory controller. The master interface circuit is arranged for
coupling the interface chip to a set of NV memory chips within the plurality of NV memory chips. A hierarchical architecture in the storage device comprises the
memory controller, the interface chip, and the set of NV memory chips. The
control circuit is arranged for controlling operations of the interface chip.