Integrated circuit layout generation method and system

Abstract

The present invention relates to an integrated circuit layout generation method and system, wherein the method includes receiving a layout diagram of the IC device, wherein the IC layout diagram includes: a gate region having a width on an active area; and a gate through hole located at a position along the width. The width is divided into a plurality of width segments using the position, an effective resistance of the gate region is calculated based on the plurality of width segments, and the effective resistance is used to determine whether the IC layout diagram complies with design specifications.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method and system for generating an integrated circuit layout. Background Art

[0002] The continuing trend toward integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but provide more functionality at higher speeds. Miniaturization has been achieved through design and manufacturing innovations that rely on increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify designs for semiconductor devices while ensuring compliance with design and manufacturing specifications. Summary of the invention

[0003] According to one embodiment of the present invention, a method for generating a layout diagram of an integrated circuit IC device includes: receiving the layout diagram of the IC device, the IC layout diagram including: a gate region having a width on an active area; and a gate through hole positioned at a position along the width; using the position to divide the width into a plurality of width segments; calculating the effective resistance of the gate region based on the plurality of width segments; and using the effective resistance to determine whether the IC layout diagram complies with design specifications.

[0004] According to one embodiment of the present invention, an integrated circuit (IC) layout diagram generating system includes: a processor; and a non-transitory computer-readable storage medium, which contains computer program codes for one or more programs, and the non-transitory computer-readable storage medium and the computer program codes are configured to enable the system through the processor to: receive an IC layout diagram, the IC layout diagram including: a gate region having a width on an active area; and a gate through hole positioned at a position along the width; divide the width into multiple width segments based on the position; calculate the effective resistance of the gate region based on the width segments; and perform circuit simulation based on the effective resistance.

[0005] According to one embodiment of the present invention, a method for generating a layout diagram of an integrated circuit IC device includes: receiving the layout diagram of the IC device, the IC layout diagram including: a gate region having a width on an active area; and a gate through hole positioned at a position along the width; using the position to divide the width into a plurality of width segments; calculating a resistance value based on a distributed resistance model applied to the plurality of width segments; modeling the gate region using a triangular resistor network, wherein each resistor of the triangular resistor network has a value based on the resistance value; and using the triangular resistor network to determine whether the IC layout diagram complies with design specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the embodiments of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a flow chart of a method of generating a layout diagram of an IC device according to some embodiments.

[0008] Figure 2A Depicted is a layout diagram of an IC device according to some embodiments.

[0009] Figure 2B A gate resistance model according to some embodiments is depicted.

[0010] Figure 3A Depicted is a layout diagram of an IC device according to some embodiments.

[0011] Figure 3B A gate resistance model according to some embodiments is depicted.

[0012] Figure 4A Depicted is a layout diagram of an IC device according to some embodiments.

[0013] Figure 4B A gate resistance model according to some embodiments is depicted.

[0014] Figure 5A Depicted is a layout diagram of an IC device according to some embodiments.

[0015] Figure 5B A gate resistance model according to some embodiments is depicted.

[0016] Figure 6 A gate resistance model according to some embodiments is depicted.

[0017] Figure 7 is a block diagram of an IC device design system according to some embodiments.

[0018] Figure 8 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0019] The following invention embodiments provide many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components, values, operations, materials, arrangements or the like are described below to simplify the embodiments of the present invention. Of course, these are just examples and are not intended to be restrictive. Other components, values, operations, materials, arrangements or the like are contemplated. For example, in the following description, a first feature is formed above or on a second feature and may include an embodiment in which the first feature is directly contacted with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the embodiments of the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly.

[0021] In some embodiments, compared to gate resistance modeling methods that do not divide the gate width based on one or more gate via locations, the effective gate resistance of the IC device is modeled by dividing the gate width into width segments based on one or more gate via locations along the gate width in a layout diagram of the IC device, thereby improving accuracy and avoiding underestimation of gate resistance values. Additional accuracy improvement is provided by applying a distributed resistance model to each width segment and by applying an effective resistance value to a triangular resistor network in some embodiments.

[0022] Figure 1 1 is a flow chart of a method 100 of generating a layout diagram of an IC device according to some embodiments. Generating a layout diagram of an IC device includes modeling the IC device based on an initial IC layout diagram of the IC device, and the initial IC layout diagram includes a gate region having a width on an active area and at least one gate via located at a position along the width. In some embodiments, modeling the IC device includes modeling the gate region using a resistor network model (e.g., a triangle resistor network or a star resistor network).

[0023] In some embodiments, modeling the IC device includes modeling a transistor, such as a planar transistor or a fin field effect transistor (FinFET). In some embodiments, the transistor is one of a plurality of transistors included in the IC device, non-limiting examples of which include a memory circuit, a logic device, a processing device, a signal processing circuit, or the like.

[0024] In some embodiments, some or all of method 100 is performed by a processor of a computer. In some embodiments, by referring to Figure 7 The processor 702 of the discussed EDA system 700 performs some or all of the method 100 .

[0025] Some or all of the operations of method 100 can be performed as in a design studio (e.g., as described below). Figure 8 This is done as part of the design process performed in the design studio 820 discussed above.

[0026] In some embodiments, Figure 1 The operations of method 100 are performed in the order depicted in FIG. Figure 1 In some embodiments, one or more operations of method 100 are performed before, between, during, and / or after one or more operations of method 100 are performed. Figures 2A to 6 The operation of method 100 is described.

[0027] Figure 2A , 3A , 4A, and 5A each depict a non-limiting example of a corresponding IC layout diagram 200A, 300A, 400A, or 500A of an IC device having a direction X and a direction Y perpendicular to the direction X. The orientation of the IC layout diagrams 200A, 300A, 400A, and 500A depicted with reference to the directions X and Y are non-limiting examples for illustration purposes. In various embodiments, except Figure 2A , 3A One or more of IC layout diagrams 200A, 300A, 400A, or 500A have an orientation with reference to directions X and Y other than the orientation depicted in a corresponding one or more of 4A, or 5A.

[0028] Each IC layout 200A, 300A, 400A and 500A includes an active region A and a gate region G. IC layout 200A includes a gate via VG1, IC layout 300A includes gate vias VG2 and VG3, IC layout 400A includes gate vias VG4, VG5 and VG6, and IC layout 500A includes gate vias VG4, VG6, VG7 and VG8.

[0029] The active area A is a region in an IC layout diagram included in the manufacturing process as part of defining an active region (also referred to as oxide diffusion or definition (OD)) in a semiconductor substrate where one or more IC device features (e.g., source / drain regions) are formed. In various embodiments, the active area is an n-type or p-type active region of a planar transistor or FinFET.

[0030] The gate region G is a region in an IC layout diagram included in a manufacturing process as part of defining a gate structure in an IC device that includes at least one of a conductive material or a dielectric material. In various embodiments, the gate structure corresponding to the gate region G includes at least one conductive material (e.g., metal and / or polysilicon material) overlying at least one dielectric material (e.g., silicon dioxide and / or high-k dielectric material).

[0031] Each gate via VG1-VG8 is a region in an IC layout diagram included in a manufacturing process as part of defining one or more segments of one or more conductive layers in an IC device that is configured to form an electrical connection between a gate structure corresponding to a gate region G and one or more conductive layer segments overlying the gate structure corresponding to the gate region G. In various embodiments, the one or more conductive layer segments formed based on each gate via VG1-VG8 include a metal, such as copper, and form an electrical connection with a metal zero, metal one, or metal two layers of the IC device.

[0032] In various embodiments, each IC layout diagram 200A, 300A, 400A, and 500A includes features other than the active region A, the gate region G, and the gate vias VG1 to VG8, which are not shown in the figure for clarity purposes. Figure 2A , 3A , one or more additional active regions, gate regions and / or gate vias, and / or one or more isolation regions, source / drain regions, well regions and / or interconnect features depicted in 4A and 5A.

[0033] The gate region G extends on the active region A from a position N1 on a first edge of the active region A to a position N2 on a second edge of the active region A opposite to the first edge, thereby defining a width W. The gate region G includes a position T along the width W midway between the positions N1 and N2. Figure 2A , 3A, 4A, and 5A, the width W extends along the direction Y. In some embodiments, the width W extends along the direction X.

[0034] exist Figure 2A , 3A , 4A, and 5A, the gate region G extends beyond the locations N1 and N2 such that a portion of the gate region G is outside the active region A. In various embodiments, one or both portions of the gate region G extending beyond the locations N1 and N2 overlap with one or more isolation regions. In various embodiments, the gate region G does not extend beyond one or both of the locations N1 or N2. In various embodiments, the entirety of the gate region G is inside the active region A or the gate region G includes one or more boundaries shared with the active region A.

[0035] exist Figure 2A In the embodiment depicted in , the IC layout diagram 200A includes a gate via VG1 located at a position L1 along the width W and an additional reference position L1 ′ along the width W. Figure 3A In the embodiment depicted in , the IC layout 300A includes gate vias VG2 and VG3 located at respective locations L2 and L3 along the width W. Figure 4A In the embodiment depicted in , the IC layout diagram 400A includes a gate via VG4 located at position N1, a gate via VG5 located at position T, and a gate via VG6 located at position N2. Figure 5A In the embodiment depicted in , IC layout diagram 500A includes gate via VG4 positioned at position N1 , gate via VG6 positioned at position N2 , and gate vias VG7 and VG8 positioned at respective positions L7 and L8 along width W.

[0036] each Figure 2B , 3B , 4B and 5B depict a corresponding one of the gate resistance models 200B, 300B, 400B and 500B corresponding to the corresponding IC layout diagrams 200A, 300A, 400A and 500A. Each gate resistance model 200B, 300B, 400B and 500B includes positions N1, N2 and T, the gate resistance model 200B includes gate vias VG1 and position L1, the gate resistance model 300B includes gate vias VG2 and VG3 and positions L2 and L3, the gate resistance model 400B includes gate vias VG4, VG5 and VG6, and the gate resistance model 500B includes gate vias VG4, VG6, VG7 and VG8 and positions L7 and L8, each of which is referred to above. Figure 2A , 3AAs discussed below, each gate resistance model 200B, 300B, 400B, and 500B is configured as a triangular resistance network based on a corresponding one of the IC layout diagrams 200A, 300A, 400A, or 500A.

[0037] At operation 110, an IC layout of an IC device is received. The IC layout includes a gate region (the gate region has a width on the active region) and a gate via positioned at a position along the width. The width extends from a first edge of the active region to a second edge of the active region opposite the first edge. In some embodiments, the width extends from position N1 to position N2, as described above with reference to Figures 2A to 5B Discussed.

[0038] In some embodiments, the gate via is one of a plurality of gate vias, the position is one of a corresponding plurality of positions along the width, and at least one of the plurality of positions is between the first and second edges of the active region.

[0039] In various embodiments, receiving an IC layout diagram includes receiving an IC layout diagram 200A, wherein the IC layout diagram 200A includes a location as described above with reference to Figures 2A to 5B One or more gate vias at the locations discussed.

[0040] Receiving an IC layout diagram includes using a processor of a computer (e.g., see below) Figure 7 A processor 702 of the discussed EDA system 700 receives an IC layout diagram.

[0041] At operation 120, the position is used to divide the width into a plurality of width segments. Dividing the width into a plurality of width segments includes dividing the entirety of the width into a plurality of width segments. Thus, each width segment in the plurality of width segments has a length such that a sum of the lengths corresponding to each width segment in the plurality of width segments is equal to the width.

[0042] In various embodiments, dividing the width into a plurality of width segments includes dividing the width into two, three, or four width segments. In some embodiments, dividing the width into a plurality of width segments includes dividing the width into greater than four width segments.

[0043] In some embodiments, the plurality of width segments include a first width segment extending from the location to a first edge of the active region. In some embodiments, the plurality of width segments include a second width segment extending from the location to a second edge of the active region. In some embodiments, the plurality of width segments include a width segment extending from the location to a center of the width.

[0044] In some embodiments, the gate via is one of a plurality of gate vias located at a corresponding plurality of locations along the width, and dividing the width into a plurality of width segments includes using more than one of the plurality of locations. In some embodiments, dividing the width into a plurality of width segments includes using each of the plurality of locations.

[0045] In some embodiments, the gate via is one of a plurality of gate vias located at corresponding plurality of positions along the width, and the plurality of width segments include a first width segment extending from a first position to a first edge of the active region and a second width segment extending from a second position to a second edge of the active region.

[0046] In some embodiments, the IC layout is the IC layout 200A, and dividing the width into a plurality of width segments includes using the positions N1, L1, T, L1', and N2 to divide the width W into width segments h, t1, d1, and g, such as Figure 2A Width segment h extends from position N1 to position L1, width segment t1 extends from position L1 to position T, width segment d1 extends from position T to position L1', and width segment g extends from position L1' to position N2.

[0047] exist Figure 2A In the embodiment depicted in , positions L1 and L1' are symmetrical about position T, such that width segments t1 and d1 have the same length, and width segments h and g have the same length. In some embodiments, positions L1 and L1' are not symmetrical about position T, width segments t1 and d1 have different lengths, and width segments h and g have different lengths. In various embodiments, one or both of width segments t1 or d1 have a length that is less than, equal to, or greater than the length of one or both of width segments h and g.

[0048] In some embodiments, dividing the width into a plurality of width segments includes dividing the width W into less than 10000 segments by combining two or more of the width segments h, t1, d1, or g into a single width segment. Figure 2A In some embodiments, dividing the width into multiple width segments includes dividing the width W into a first width segment h and a second width segment including t1, d1, and g, thereby using only positions N1, L1, and N2 to divide the width W into multiple width segments.

[0049] In some embodiments, the IC layout is IC layout 300A, and dividing the width into a plurality of width segments includes using positions N1, L2, T, L3, and N2 to divide the width W into width segments h, t1, d1, and g, such as Figure 3AWidth segment h extends from position N1 to position L2, width segment t1 extends from position L2 to position T, width segment d1 extends from position T to position L3, and width segment g extends from position L3 to position N2.

[0050] exist Figure 3A In the embodiment depicted in , each of the width segments h, t1, d1, and g has a length different from the lengths of the others of the width segments h, t1, d1, and g. In various embodiments, two or more of the width segments h, t1, d1, and g have the same length.

[0051] In some embodiments, the IC layout is the IC layout 400A, and dividing the width into a plurality of width segments includes using the positions N1, T, and N2 to divide the width W into width segments w1 and w2, such as Figure 4A Depicted in . Width segment w1 extends from position N1 to position T, and width segment w2 extends from position T to position N2.

[0052] exist Figure 4A In the embodiment depicted in , because gate vias VG4 and VG6 are positioned at respective positions N1 and N2, and gate via VG5 is positioned at position T in the middle between positions N1 and N2, width segments w1 and w2 have the same length. In some embodiments, gate via VG5 is positioned at a position other than position T, and width segments w1 and w2 have different lengths.

[0053] In some embodiments, one or both of gate vias VG4 or VG6 are positioned at positions (not shown) along width W other than respective positions N1 and N2, and dividing the width into a plurality of width segments includes dividing the width W into one or more width segments (not shown) other than width segments w1 and w2.

[0054] In some embodiments, the IC layout is IC layout 500A, and dividing the width into a plurality of width segments includes using positions N1, L7, T, L8, and N2 to divide the width W into width segments h, t1, d1, and g, such as Figure 5A Width segment h extends from position N1 to position L7, width segment t1 extends from position L7 to position T, width segment d1 extends from position T to position L8, and width segment g extends from position L8 to position N2.

[0055] exist Figure 5AIn the embodiment depicted in , each of the width segments h, t1, d1, and g has a length different from the lengths of the others of the width segments h, t1, d1, and g. In various embodiments, two or more of the width segments h, t1, d1, and g have the same length.

[0056] In some embodiments, one or both of gate vias VG4 or VG6 are positioned at positions (not shown) along width W other than respective positions N1 and N2, and dividing the width into a plurality of width segments includes dividing the width W into one or more width segments (not shown) other than width segments h, t1, d1, and g.

[0057] At operation 130, an effective resistance of the gate region is calculated based on the plurality of width segments. The effective resistance is expressed in terms of an expected resistance of the gate structure fabricated from the gate region. In some embodiments, the expected resistance is an expected resistance Rg of the gate structure corresponding to the gate region G between positions corresponding to positions N1 and N2 along the width W, as described above with reference to Figures 2A to 5B Discussed.

[0058] Calculating the effective resistance based on the plurality of width segments includes using the length of at least one of the width segments to derive the effective resistance based on the expected resistance of the gate structure. In various embodiments, calculating the effective resistance based on the plurality of width segments includes using the lengths of some or all of the width segments of the plurality of width segments.

[0059] In some embodiments, calculating the effective resistance includes applying a distributed resistance model to each width segment of the plurality of width segments. In some embodiments, calculating the effective resistance includes applying the distributed resistance model to thermal noise calculations for each width segment. In some embodiments, calculating the effective resistance includes applying each width segment to a distributed resistance model based on a contact located at one end of the gate, the distributed resistance model being found in Razavi B., Yan R., and Lee KF, "Impact of Distributed Gate Resistance on the Performance of MOS Devices'," IEEE Transactions on Circuits and Systems-I: Fundamentals and Applications, Vol. 41, No. II, pp. 750-754 (November 1994, hereinafter "Razavi"), which is hereby incorporated by reference in its entirety.

[0060] In some embodiments, calculating the effective resistance of the gate region includes modeling the gate region using a resistor network (e.g., a triangle resistor network or a star resistor network). In various embodiments, calculating the effective resistance of the gate region includes using the following and above reference Figure 2B , 3B , 4B or 5B discussed in one of the gate resistance models 200B, 300B, 400B and 500B.

[0061] In some embodiments, calculating the effective resistance based on the plurality of width segments includes calculating the effective resistance based on the above reference IC layout diagram 200A and Figure 2A The effective resistance R1 is calculated for the discussed width segments h, t1, d1, and g. At least one ratio of the length to the width W of the width segment h, t1, d1, or g is used to derive the effective resistance R1 from the expected gate resistance Rg.

[0062] In some embodiments, by applying Razavi's distributed resistance model to the width segments h, t1, d1, and g of the IC layout diagram 200A, the effective resistance R1 is obtained by the following formula:

[0063] R1=(Rg / 3)×(1-3x+3x 2 ), (1)

[0064] Where x is defined as the ratio of the length of each width segment t1 and d1 divided by the width W, and the effective resistance R2 is given by:

[0065] R2=Rg-(3×R1). (2)

[0066] Based on the positioning of position L1 relative to positions N1 and N2, x has a value ranging from zero to one, R1 has a value ranging from Rg / 12 to Rg / 3, and R2 has a value ranging from zero to 3 / 4×Rg.

[0067] In some embodiments, calculating the effective resistance includes applying the effective resistances R1 and R2 to Figure 2B . The gate resistance model 200B thus includes a triangular resistor network of two lumped resistors connected at position T, each having a value of 1 / 2×R1, and a lumped resistor located between positions N1 and N2 having a value of -3 / 2×R1. The gate resistance model 200B thus also includes a lumped resistor between position N1 and the triangular resistor network having a value of h / W×R2, a lumped resistor between the triangular resistor network and position N2 having a value of g / W×R2, and a lumped resistor representing a gate via VG1 connected to the triangular resistor network at position L1.

[0068] By applying the effective resistances R1 and R2 to the Figure 2BThe lumped resistance depicted in FIG. 1 may be determined based on one or more modeling operations performed on the circuit based on an IC layout diagram including IC layout diagram 200A (e.g., as described below with reference to FIG. 1 ). Figure 7 The gate resistance model 200B is used in one or more modeling operations performed by the EDA system 700 discussed above.

[0069] In some embodiments, calculating the effective resistance based on the plurality of width segments includes calculating the effective resistance based on the IC layout diagram 300A and Figure 3A The effective resistance R11 is calculated for the discussed width segments h, t1, d1, and g. At least one ratio of the length to the width W of the width segment h, t1, d1, or g is used to derive the effective resistance R11 from the expected gate resistance Rg.

[0070] Figure 6 A non-limiting example of a gate resistance model 600 that can be used to apply Razavi's distributed resistance model to width segments h, t1, d1, and g of IC layout 300A to calculate effective resistance R11 is depicted. For simplicity, gate resistance model 600 is based on width segments t1 and d1 that have the same length rather than having a gate resistance model based on the example of FIG. Figure 3A The length of the position T depicted.

[0071] Razavi's distributed resistance model is based on a gate contacted at one end of the gate. Gate resistance model 600 applies Razavi's distributed resistance model to each of width segment h contacted by gate via VG2, width segment t1 contacted by gate via VG2, width segment d1 contacted by gate via VG3, and width segment g contacted by gate via VG3.

[0072] The gate resistance model 600 represents a single transistor (not shown) having a transconductance Gm as a plurality of individual transistors (not labeled) configured in parallel between a gate voltage Vg and ground, thereby representing a portion of a gate region G distributed along a width W. Each width segment includes a distributed gate resistance represented as a series of resistors, and each resistor corresponds to a noise voltage and resulting noise current used to derive an effective resistance expression.

[0073] Width segment h includes n resistors Rh1 to Rhn, noise voltages Vh1 to Vhn, and currents ih1 to ihn, width segment g includes k resistors Rg1 to Rgk, noise voltages Vg1 to Vgk, and currents ig1 to igk, and each width segment t1 and d1 includes k1 resistors Rtd1 to Rtdk1, noise voltages Vtd1 to Vtdk1, and currents itd1 to itdk1. Each individual transistor has a fractional transconductance gm equal to the single transistor transconductance Gm divided by the total number of individual transistors w, which is equal to n+k+(2×k1).

[0074] The total noise current iT includes the noise currents through each width segment h, g, t1, and d1, and is given by the following formula:

[0075] iT=ih1+ih2+…+ihn+ig1+ig2+…+igk+2×(itd 1+itd2+…+itdk1)

[0076] =gm×[Vh1+(Vh1+Vh2)+…+(Vh1+Vh2+…+Vhn)+Vg1+(Vg1+Vg2)+…+(Vg1+Vg2+…+Vgk)+2×(Vtd1+(Vtd1+Vtd2)+…+(Vtd1+Vtd2+…+Vtdk1)]

[0077] =gm×[n×Vh1+(n-1)Vh2+…+Vgn+k×Vg1+(k-1)Vg2+…+Vgk+2×(k1×Vtd1+(k1-1)Vtd2+…+Vtdk1)].

[0078] According to Razavi implementation substitution we get:

[0079] iT 2 =Gm 2 (4kTB)Rg[2(n 3 +k 3 +2k1 3 )+3(n 2 +k 2 +2k1 2 )+(n+k+2k1)] / 6w 3 =Gm 2 (4kTB)×R11,

[0080] Where k is the Boltzmann constant, T is the absolute temperature, and B is the transistor bandwidth. This gives the effective resistance R11 as:

[0081] R11=(Rg / 12)*(3x 3 +3y 3 +3x 2+3y 2 +6xy-3x 2 y-3y 2 x-3x-3y+1), (3)

[0082] Where x is defined as the ratio of the length of width segment h divided by the width W, and y is defined as the ratio of the length of width segment g divided by the width W. The effective resistance R22 is further derived by the following formula:

[0083] R22=Rg-(3×R11). (4)

[0084] In some embodiments, calculating the effective resistance includes applying the effective resistances R11 and R22 to Figure 3B . The gate resistance model 300B thus includes a triangular resistor network of two lumped resistors connected at position T, each having a value of 1 / 2×R11, and a lumped resistor located between positions N1 and N2 having a value of -3 / 2×R11. The gate resistance model 300B thus also includes a lumped resistor between position N1 and the triangular resistor network having a value of h / W×R22, a lumped resistor between the triangular resistor network and position N2 having a value of g / W×R22, a lumped resistor representing a gate via VG2 connected to the triangular resistor network at position L2, and a lumped resistor representing a gate via VG3 connected to the triangular resistor network at position L3.

[0085] By applying the effective resistances R11 and R22 to Figure 3B The lumped resistance depicted in FIG. 1 may be determined based on one or more modeling operations performed on the circuit based on an IC layout diagram including IC layout diagram 300A (e.g., as described below with reference to FIG. 1 ). Figure 7 The gate resistance model 300B is used in one or more modeling operations performed by the EDA system 700 discussed above.

[0086] In some embodiments, calculating the effective resistance based on the plurality of width segments includes calculating the effective resistance based on the above reference IC layout diagram 400A and Figure 4A The effective resistance R11 is calculated for the width segments w1 and w2 discussed. At least one ratio of the length of the width segment w1 or w2 to the width W is used to derive the effective resistance R11 from the expected gate resistance Rg.

[0087] In some embodiments, by applying Razavi's distributed resistance model to the width segments w1 and w2 of the IC layout 400A, the effective resistance R11 is obtained by the following formula:

[0088] R11=(Rg / 12)×(1-3x+3x 2 ), (5)

[0089] Where x is defined as the ratio of the length of each width segment w1 and w2 divided by the width W, and the effective resistance R22 is obtained by equation (4).

[0090] In some embodiments, calculating the effective resistance includes applying the effective resistances R11 and R22 to Figure 4B . The gate resistance model 400B thus includes a triangular resistor network of two lumped resistors connected at position T, each having a value of 1 / 2×R11, and a lumped resistor located between positions N1 and N2 having a value of -3 / 2×R11. The gate resistance model 400B thus also includes a lumped resistor between position N1 and the triangular resistor network having a value of h / W×R22, a lumped resistor between the triangular resistor network and position N2 having a value of g / W×R22, and a lumped resistor representing a gate via VG5 connected to the triangular resistor network.

[0091] By applying the effective resistances R11 and R22 to Figure 4B The lumped resistance depicted in FIG. 4 may be determined based on one or more modeling operations performed on the circuit based on an IC layout diagram including IC layout diagram 400A (e.g., as described below with reference to FIG. 4). Figure 7 The gate resistance model 400B is used in one or more modeling operations performed by the EDA system 700 discussed above.

[0092] In some embodiments, calculating the effective resistance based on the plurality of width segments includes calculating the effective resistance based on the above reference IC layout diagram 500A and Figure 5A The effective resistance R11 is calculated for the discussed width segments h, t1, d1, and g. At least one ratio of the length to the width W of the width segment h, t1, d1, or g is used to derive the effective resistance R11 from the expected gate resistance Rg.

[0093] In some embodiments, by applying Razavi's distributed resistance model to the width segments h, t1, d1, and g of the IC layout 500A, the effective resistance R11 is obtained by the following formula:

[0094] R11=(Rg / 12)*(3x 2 +3y 2 +6xy-3x 2 y-3y 2 x-3x-3y+1), (6)

[0095] Where x is defined as the ratio of the length of width segment h divided by the width W, y is defined as the ratio of the length of width segment g divided by the width W, and the effective resistance R22 is obtained by equation (4).

[0096] In some embodiments, calculating the effective resistance includes applying the effective resistances R11 and R22 to Figure 5B . The gate resistance model 500B thus includes a triangular resistor network of two lumped resistors connected at position T, each having a value of 1 / 2×R11, and a lumped resistor located between positions N1 and N2 having a value of -3 / 2×R11. The gate resistance model 500B thus also includes a lumped resistor between position N1 and the triangular resistor network having a value of h / W×R22, a lumped resistor between the triangular resistor network and position N2 having a value of g / W×R22, a lumped resistor representing a gate via VG7 connected to the triangular resistor network at position L7, and a lumped resistor representing a gate via VG8 connected to the triangular resistor network at position L8.

[0097] By applying the effective resistances R11 and R22 to Figure 5B The lumped resistance depicted in FIG. 5 may be determined based on one or more modeling operations performed on the circuit based on an IC layout diagram including IC layout diagram 500A (e.g., as described below with reference to FIG. 5 ). Figure 7 The gate resistance model 500B is used in one or more modeling operations performed by the EDA system 700 discussed above.

[0098] In some embodiments, at operation 140, the effective resistance is used to determine whether the IC layout conforms to the design specification. In some embodiments, determining whether the IC layout conforms to the design specification includes performing a simulation based on the IC layout.

[0099] In various embodiments, the design specification includes the speed of the IC, the noise performance of the IC, the transient response time of the IC, the cutoff frequency of the IC, or another circuit characteristic potentially affected by the gate resistance.

[0100] In some embodiments, at operation 150, the IC layout is modified in response to determining that the IC layout does not comply with the design specification. In various embodiments, modifying the IC layout includes one or more of: changing the position of the gate via along the width or adding another gate via positioned at another position along the width.

[0101] In some embodiments, at operation 160, the IC layout diagram is stored in a storage device. In various embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in a non-volatile computer-readable memory or a cell library (e.g., a database), and / or includes storing the IC layout diagram on a network. In some embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in a computer program product described below with reference to Figure 7On the network 714 of the EDA system 700 discussed.

[0102] In some embodiments, at operation 170, at least one of one or more semiconductor masks or at least one component in a layer of a semiconductor IC is fabricated based on the IC layout diagram, or one or more manufacturing operations are performed. Figure 8 The invention discusses making one or more semiconductor masks or at least one component in a layer of a semiconductor IC based on an IC layout diagram and performing one or more manufacturing operations (eg, one or more photolithography exposures).

[0103] By performing some or all of the operations of method 100, the effective gate resistance of an IC device is modeled by dividing the gate width into width segments based on one or more gate via locations along the gate width as part of generating a layout diagram of the IC device, thereby improving accuracy and avoiding underestimation of gate resistance values, compared to gate resistance modeling methods that do not divide the gate width based on one or more gate via locations. Additional accuracy improvements are provided by applying a distributed resistance model to each width segment and by applying an effective resistance value to a triangular resistor network in some embodiments.

[0104] Because the improved accuracy and avoidance of underestimation of gate resistance values ​​serve to reduce the number of IC layout revisions, manufacturing IC devices based on the method is more efficient than manufacturing IC devices based on methods that do not divide the gate width based on one or more gate via locations.

[0105] Figure 7 is a block diagram of an IC device design system 700 according to some embodiments. According to some embodiments, the above reference Figure 1 One or more operations of the discussed method 100 may be implemented using the IC device design system 700 .

[0106] In some embodiments, IC device design system 700 is a computing device including hardware processor 702 and non-transitory computer-readable storage medium 704. Non-transitory computer-readable storage medium 704 is encoded with (i.e., stores) computer program code 706, i.e., a set of executable instructions. Execution of instructions 706 by hardware processor 702 (at least in part) represents implementations such as those described above with reference to Figure 1 An IC device design system that includes a portion or all of the discussed method 100 (hereinafter referred to as the mentioned process and / or method).

[0107] The processor 702 is electrically coupled to a non-transitory computer-readable storage medium 704 via a bus 708. The processor 702 is also electrically coupled to an I / O interface 710 via the bus 708. A network interface 712 is also electrically connected to the processor 702 via the bus 708. The network interface 712 is connected to a network 714 to enable the processor 702 and the non-transitory computer-readable storage medium 704 to be connected to external components via the network 714. The processor 702 is configured to execute a computer program code 706 encoded in the non-transitory computer-readable storage medium 704 so that the IC device design system 700 can be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0108] In one or more embodiments, the non-transitory computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the non-transitory computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the non-transitory computer-readable storage medium 704 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0109] In one or more embodiments, the non-transitory computer-readable storage medium 704 stores computer program code 706, which is configured to enable the IC device design system 700 to perform some or all of the processes and / or methods mentioned. In one or more embodiments, the non-transitory computer-readable storage medium 704 also stores information that facilitates performing some or all of the processes and / or methods mentioned. In various embodiments, the non-transitory computer-readable storage medium 704 stores one or a combination of at least one IC layout diagram 720 or at least one design specification 722, the IC layout diagram and the design specification being described above with reference to the method 100 and Figures 1 to 6 Discussion.

[0110] IC device design system 700 includes an I / O interface 710. I / O interface 710 is coupled to external circuitry. In various embodiments, I / O interface 710 includes one or a combination of a keyboard, a keypad, a mouse, a navigation ball, a track pad, a display, a touch screen, and / or cursor direction keys for communicating information and commands to and / or from processor 702.

[0111] The IC device design system 700 also includes a network interface 712 coupled to the processor 702. The network interface 712 allows the system 700 to communicate with a network 714 that connects one or more other computer systems. The network interface 712 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the processes and / or methods mentioned are implemented in two or more than two systems 700.

[0112] The IC device design system 700 is configured to receive information through the I / O interface 710. The information received through the I / O interface 710 includes one or a combination of at least one design rule directive, at least one criteria set, at least one design rule, at least one DRM, and / or other parameters for processing by the processor 702. The information is transmitted to the processor 702 via the bus 708. The IC device design system 700 is configured to send and / or receive information related to the user interface through the I / O interface 710.

[0113] In some embodiments, some or all of the processes and / or methods mentioned are implemented as a standalone software application for execution by a processor. In some embodiments, some or all of the processes and / or methods mentioned are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the processes and / or methods mentioned are implemented as a plug-in to a software application. In some embodiments, some or all of the processes and / or methods mentioned are implemented as a software application that is part of an EDA tool. In some embodiments, a tool (e.g., available from CADENCE DESIGN SYSTEMS) is used to implement the process and / or methods. or another suitable layout generation tool) to generate an IC layout diagram.

[0114] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs, RAMs, memory cards), and the like.

[0115] By can be used to implement as mentioned above Figures 1 to 6 One or more operations of the method 100 discussed, the IC device design system 700 , and the non-transitory computer-readable recording medium (eg, the non-transitory computer-readable recording medium 704 ) can achieve the benefits discussed above with reference to the method 100 .

[0116] Figure 8 8 is a block diagram of an IC manufacturing system 800 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 800 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0117] exist Figure 8 In the embodiment, the IC manufacturing system 800 includes entities that interact with each other in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 860, such as design studio 820, mask room 830 and IC manufacturer / fabricator ("factory") 850. The entities in the system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design studio 820, mask room 830 and IC factory 850 are owned by a single larger company. In some embodiments, two or more of the design studio 820, mask room 830 and IC factory 850 coexist in a common facility and use common resources.

[0118] Design studio (or design team) 820 based on the above reference Figures 1 to 6 The method 100 discussed is used to generate an IC design layout 822. The IC design layout 822 includes various geometric patterns corresponding to the patterns of metal, oxide, or semiconductor layers that make up the various components of the IC device 860 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 822 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon chip) and various material layers disposed on the semiconductor substrate, such as active areas, gate electrodes, sources and drains, metal lines or vias for interconnecting between layers, and openings for bonding pads. The design studio 820 implements the above-referenced method. Figures 1 to 6 The appropriate design process of the method 100 discussed is to form an IC design layout diagram 822. The design process includes one or more of logic design, physical design, or placement and routing. The IC design layout diagram 822 is presented in the form of one or more data files with geometric pattern information. For example, the IC design layout diagram 822 can be expressed in a GDSII file format or a DFII file format.

[0119] The mask room 830 includes data preparation 832 and mask making 844. The mask room 830 uses the IC design layout drawing 822 to manufacture one or more masks 845, which will be used to make various layers of the IC device 860 according to the IC design layout drawing 822. The mask room 830 performs mask data preparation 832, in which the IC design layout drawing 822 is translated into a representative data file ("RDF"). The mask data preparation 832 provides the RDF to the mask making 844. The mask making 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 845 or a semiconductor chip 853. The design layout drawing 822 is manipulated by the mask data preparation 832 to comply with the specific characteristics of the mask writer and / or the requirements of the IC factory 850. In Figure 8 , mask data preparation 832 and mask production 844 are illustrated as separate components. In some embodiments, mask data preparation 832 and mask production 844 may be collectively referred to as mask data preparation.

[0120] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may result from diffraction, interference, or other process effects, and the like. OPC adjusts the IC design layout 822. In some embodiments, mask data preparation 832 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, an inverse lithography technique (ILT) that treats OPC as an inverse imaging problem is also used.

[0121] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that checks an IC design layout 822 that has been subjected to a process in OPC using a set of mask creation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 822 to compensate for the constraints during mask fabrication 844, which may undo portions of the modifications made by the OPC to comply with the mask creation rules.

[0122] In some embodiments, mask data preparation 832 includes a lithography process check (LPC) that simulates a process to be performed by the IC factory 850 to make an IC device 860. The LPC simulates this process based on the IC design layout diagram 822 to produce a simulated manufactured device, such as the IC device 860. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. The LPC considers various factors, such as projection contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or a combination thereof. In some embodiments, after the simulated manufactured device has been created by the LPC, if the shape of the simulated device is not close enough to meet the design rules, then the OPC and / or MRC are repeated to further optimize the IC design layout diagram 822.

[0123] It should be understood that the above description of mask data preparation 832 has been simplified for the purpose of clarity. In some embodiments, data preparation 832 includes additional features such as logic operations (LOPs) to modify IC design layout 822 according to manufacturing rules. In addition, the processes applied to IC design layout 822 during data preparation 832 can be performed in a variety of different orders.

[0124] After mask data preparation 832 and during mask fabrication 844, a mask 845 or a group of masks 845 are fabricated based on the modified IC design layout 822. In some embodiments, mask fabrication 844 includes performing one or more photolithographic exposures based on the IC design layout 822. In some embodiments, a pattern is formed on a mask (photomask or photomask) 845 based on the modified IC design layout 822 using an electron beam (e-beam) or a plurality of e-beam mechanisms. Mask 1045 can be formed using various techniques. In some embodiments, mask 845 is formed using a binary technique. In some embodiments, the mask pattern includes an opaque region and a transparent region. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) coated on a chip is blocked by the opaque region and transmitted through the transparent region. In one example, a binary mask pattern of mask 845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque region of the binary mask. In another example, mask 845 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 845, various features of the pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask making 844 is used in various processes. For example, such a mask can be used in an ion implantation process to form various doped regions in semiconductor chip 853, in an etching process to form various etched regions in semiconductor chip 853, and / or in other suitable processes.

[0125] IC factory 850 includes chip fabrication 852. IC factory 850 is an IC fabrication enterprise that includes one or more fabrication facilities for fabricating a variety of different IC products. In some embodiments, IC factory 850 is a semiconductor foundry. For example, there may be a fabrication facility for front-end fabrication (Front End of Line (FEOL) fabrication) of multiple IC products, while a second fabrication facility may provide back-end fabrication (Back End of Line (BEOL) fabrication) for interconnection and packaging of IC products, and a third fabrication facility may provide other services for the foundry enterprise.

[0126] IC factory 850 uses mask 845 made by mask chamber 830 to make IC device 860. Thus, IC factory 850 uses IC design layout 822 at least indirectly to make IC device 860. In some embodiments, IC factory 850 uses mask 845 to make semiconductor chip 853 to form IC device 860. In some embodiments, IC production includes performing one or more photolithography exposures based on IC design layout 822 at least indirectly. Semiconductor chip 853 includes a silicon substrate or other appropriate substrate having a material layer formed thereon. Semiconductor chip 853 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed at subsequent manufacturing steps).

[0127] Regarding IC manufacturing systems (such as Figure 8 Details of the system 800 and the IC manufacturing process associated therewith are found, for example, in U.S. Patent No. 9,256,709 issued on February 9, 2016, U.S. Pregrant Publication No. 20150278429 published on October 1, 2015, U.S. Pregrant Publication No. 20140040838 published on February 6, 2014, and U.S. Patent No. 7,260,442 issued on August 21, 2007, the entire text of each of which is hereby incorporated by reference.

[0128] In some embodiments, a method for generating a layout diagram of an IC device includes: receiving a layout diagram of an IC device, the IC layout diagram including: a gate region having a width on an active area; and a gate via positioned at a position along the width; using the position to divide the width into a plurality of width segments; calculating an effective resistance of the gate region based on the plurality of width segments; and using the effective resistance to determine whether the IC layout diagram complies with design specifications.

[0129] In some embodiments, an IC layout generation system includes a processor and a non-transitory computer-readable storage medium including computer program code for one or more programs. The non-transitory computer-readable storage medium and the computer program code are configured to cause the system to: receive an IC layout through the processor, the IC layout including: a gate region having a width on an active area; and a gate via located at a position along the width; divide the width into a plurality of width segments based on the position; calculate the effective resistance of the gate region according to the width segments; and perform circuit simulation based on the effective resistance.

[0130] In some embodiments, a method for generating a layout diagram of an IC device includes: receiving a layout diagram of an IC device, the IC layout diagram including: a gate region having a width over an active area; and a gate via positioned at a position along the width; using the position to divide the width into a plurality of width segments; calculating a resistance value based on a distributed resistance model applied to the plurality of width segments; modeling the gate region using a triangular resistor network, wherein each resistor of the triangular resistor network has a value based on the resistance value; and using the triangular resistor network to determine whether the IC layout diagram complies with design specifications.

[0131] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the embodiments of the present invention. Those skilled in the art will appreciate that they can readily use the embodiments of the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or obtaining the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present invention, and those skilled in the art can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A method for generating an IC layout diagram of an integrated circuit (IC) device, the method comprising: receiving the IC layout diagram of the IC device, the IC layout diagram comprising: a gate region having a width over the active region; and a gate via positioned along the width; using the position to divide the width into a plurality of width segments; calculating an effective resistance of the gate region based on the plurality of width segments; and The effective resistance is used to determine whether the IC layout complies with design specifications. 2 . The method of claim 1 , wherein said dividing said width into said plurality of width segments comprises dividing said width into four width segments. 3 . The method of claim 1 , wherein the calculating the effective resistance of the gate region comprises applying a distributed resistance model to the plurality of width segments. 4 . The method of claim 1 , wherein said calculating the effective resistance of the gate region comprises modeling the gate region using a triangle resistor network. 5 . The method of claim 1 , wherein the determining whether the IC layout diagram complies with the design specification comprises performing a simulation based on the IC layout diagram. The method of claim 1 , wherein the design specification includes a speed of the IC device. The method of claim 1 , wherein the design specification includes noise performance of the IC device.

8. The method according to claim 1, wherein The gate through hole is one of a plurality of gate through holes positioned at a corresponding plurality of locations along the width, and The plurality of gate through holes include two, three or four gate through holes.

9. The method of claim 1, further comprising modifying the IC layout drawing in response to determining that the IC layout drawing does not comply with the design specification.

10. The method of claim 9, wherein the modifying the IC layout comprises changing the position of the gate via along the width or adding another gate via positioned at another position along the width.

11. An integrated circuit IC layout diagram generation system, comprising: processor; as well as A non-transitory computer readable storage medium comprising computer program code for one or more programs, the non-transitory computer readable storage medium and the computer program code being configured to cause, by the processor, the system to: An IC layout diagram is received, wherein the IC layout diagram includes: a gate region having a width over the active region; and a gate via positioned along the width; dividing the width into a plurality of width segments based on the position; calculating an effective resistance of the gate region based on the plurality of width segments; and A circuit simulation was performed based on the effective resistance.

12. The IC layout generation system according to claim 11, wherein The width extends from a first edge of the active area to a second edge of the active area, and The computer readable storage medium and the computer program code are configured to cause the system, with the processor, to divide the width into the plurality of width segments including a first width segment extending from the location to the first edge.

13. The IC layout generation system according to claim 12, wherein the gate via located at the position along the width is a first gate via located at a first position along the width, The IC layout diagram further includes a second gate via positioned at a second position along the width, and the computer readable storage medium and the computer program code are configured to cause the system, via the processor, to divide the width into the plurality of width segments, the plurality of width segments further including a second width segment extending from the second position to the second edge.

14. The IC layout diagram generating system of claim 13, wherein the computer-readable storage medium and the computer program code are configured to cause the system, through the processor, to divide the width into the plurality of width segments, the plurality of width segments further comprising a third width segment and a fourth width segment extending between the first position and the second position.

15. The IC layout generation system according to claim 12, wherein the computer readable storage medium and the computer program code are configured to cause the system to calculate the effective resistance of the gate region by the following steps through the processor: determining a first resistance value according to a ratio of a length of the first width segment to the width, and The first resistance value is applied to the triangle resistor network.

16. The IC layout generation system according to claim 15, wherein the computer readable storage medium and the computer program code are configured to cause the system to calculate the effective resistance of the gate region by the following steps through the processor: determining a second resistance value according to the first resistance value, and The second resistance value is applied to the triangle resistor network. 17 . The IC layout generation system according to claim 11 , wherein the computer readable storage medium and the computer program code are configured to cause the system to perform the circuit simulation including the total noise current of the gate region through the processor.

18. A method for generating an IC layout diagram of an integrated circuit (IC) device, the method comprising: receiving the IC layout diagram of the IC device, the IC layout diagram comprising: a gate region having a width over the active region; and a gate via positioned along the width; using the position to divide the width into a plurality of width segments; calculating a resistance value based on a distributed resistance model applied to the plurality of width segments; modeling the gate region using a triangular resistor network, wherein each resistor of the triangular resistor network has a resistance based on the resistance value; and The triangular resistor network is used to determine whether the IC layout complies with design specifications.

19. The method of claim 18, wherein the calculating the resistance value comprises using the following equation: R=(Rg / 3)×(1-3x+3x 2 ), Wherein R is the resistance value, Rg is the resistance corresponding to the gate region along the width, and x is the length of a width segment of the plurality of width segments divided by the width.

20. The method of claim 18, wherein said calculating said resistance value comprises using the following equation: R=(Rg / 12)×(3x 3 +3y 3 +3x 2 +3y 2 +6xy-3x 2 y-3y 2 x-3x-3y+1), Wherein R is the resistance value, Rg is the resistance corresponding to the gate region along the width, x is the length of a first width segment of the plurality of width segments divided by the width, and y is the length of a second width segment of the plurality of width segments divided by the width.

21. A method for generating an IC layout diagram of an integrated circuit (IC) device, the method comprising: receiving the IC layout of the IC device, the IC layout including a gate region having a width above an active region; dividing the width into a plurality of width segments based on the location of the gate via; as well as A simulation is performed based on the IC layout diagram including an effective resistance calculated using at least one of the plurality of width segments.

22. The method of claim 21, wherein said dividing said width into said plurality of width segments comprises dividing said width into four width segments.

23. The method according to claim 22, wherein A first width segment extends from a first edge of the active area to the location of the gate through hole, a second width segment extending from the location of the gate via to a second location midway along the width, A third width segment extends from the second position to a third position between the second position and a second edge of the active area, and A fourth width segment extends from the third location to the second edge of the active region. 24 . The method of claim 23 , wherein the position and the third position of the gate via are symmetrical about the second position.

25. The method of claim 21, further comprising calculating the effective resistance by applying a distributed resistance model to the plurality of width segments.

26. The method of claim 25, wherein the calculating the effective resistance comprises modeling the gate region using a triangle resistor network.

27. The method of claim 26, wherein said using said triangular resistor network comprises positioning said effective resistor between said location of said gate via and a location midway along said width.

28. The method of claim 27, wherein said calculating said effective resistance comprises using the following equation: R=(Rg / 6)×(1-3x+3x 2 ), Wherein R is the effective resistance value, Rg is the resistance corresponding to the gate region along the width, and x is the length of a width segment of the plurality of width segments divided by the width.

29. The method of claim 21, wherein said performing said simulation based on said IC layout is part of determining whether said IC layout complies with design specifications.

30. A method for generating an IC layout diagram of an integrated circuit (IC) device, the method comprising: receiving the IC layout of the IC device, the IC layout including a gate region having a width above an active region; dividing the width into a plurality of width segments based on a plurality of locations of the gate vias; as well as A simulation is performed based on the IC layout diagram including an effective resistance of the gate region calculated using the plurality of width segments.

31. The method of claim 30, further comprising: calculating the effective resistance by applying a distributed resistance model to the plurality of width segments; as well as The gate region is modeled using a triangular resistor network.

32. The method of claim 31, wherein The plurality of positions include a first position between a first edge and a second edge of the active region and a second position between the first edge and the second edge of the active region, and The modeling of the gate region using the triangular resistor network includes positioning the effective resistance between the first position and a third position along the middle of the width and between the second position and the third position.

33. The method of claim 32, wherein said calculating said effective resistance comprises using the following equation: R=(Rg / 24)×(3x 3 +3y 3 +3x 2 +3y 2 +6xy-3x 2 y-3y 2 x-3x-3y+1), Wherein R is the resistance value, Rg is the resistance corresponding to the gate region along the width, x is the length of a first width segment of the plurality of width segments divided by the width, and y is the length of a second width segment of the plurality of width segments divided by the width.

34. The method of claim 33, wherein the plurality of locations further comprises a fourth location at the first edge of the active region and a fifth location at the second edge of the active region.

35. The method of claim 31, wherein The plurality of locations include a first location at a first edge of the active region, a second location along the middle of the width, and a third location at a second edge of the active region, and The modeling of the gate region using the triangular resistor network includes positioning the effective resistance between the second location and a gate via corresponding to the second location.

36. The method of claim 35, wherein said calculating said effective resistance comprises using the following equation: R=(Rg / 24)×(1-3x+3x 2 ), Wherein R is the effective resistance value, Rg is the resistance corresponding to the gate region along the width, and x is the length of a width segment of the plurality of width segments divided by the width.

37. The method of claim 36, wherein The modeling of the gate region using the triangular resistor network includes positioning another effective resistor between the first location and the gate via corresponding to the second location, and The method further includes calculating the other effective resistance by using the following equation: Ran=Rg-(3×R), wherein Ran is the other effective resistance.

38. An integrated circuit IC layout diagram generation system, comprising: processor; as well as A non-transitory computer readable storage medium comprising computer program code for one or more programs, the non-transitory computer readable storage medium and the computer program code being configured to cause, by the processor, the system to: receiving an IC layout diagram including a gate region having a width above an active area; identifying a width segment of the width based on a location of the gate via; as well as Whether the IC layout complies with design specifications is determined based on the effective resistance calculated according to the width segment.

39. The IC layout drawing generation system of claim 38, wherein the computer readable storage medium and the computer program code are configured to cause the system to store the IC layout drawing in a storage device through the processor.

40. The IC layout generation system according to claim 38, wherein The IC layout diagram corresponds to an IC device, and The design specification is one of a speed of the IC device or a noise performance of the IC device.

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