Source / drain diffusion barrier for germanium NMOS transistors

By introducing a dopant diffusion barrier into a Ge-rich n-MOS transistor, the problem of increased contact resistance caused by dopant diffusion is solved, the transistor performance is improved, and it is suitable for the manufacture of small-size transistors.

CN111066151BActive Publication Date: 2025-09-12INTEL CORP
2 Cites 0 Cited by

Patent Information

Application Number
CN201780094218.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2017-09-26
Publication Date
2025-09-12
Estimated Expiration
2037-09-26

AI Technical Summary

Technical Problem

In the fabrication of Ge-rich n-MOS transistors, it is difficult to maintain a high level of n-type dopant, which causes the dopant to diffuse from the source/drain region to the adjacent shallow trench isolation region, resulting in increased contact resistance and performance degradation, especially in small-sized transistors.

Method used

A dopant diffusion barrier is employed, which reduces dopant diffusion and improves surface charge passivation characteristics and anti-diffusion capability by depositing an insulating material layer, such as silicon dioxide, silicon nitride, hafnium oxide, or aluminum oxide, between the n-MOS transistor and the STI region.

Benefits of technology

It effectively suppressed the diffusion of dopants into the STI region, improved contact resistance, and enhanced transistor performance, especially maintaining good device characteristics at the sub-30nm technology node.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

An integrated circuit transistor structure is disclosed that reduces n-type dopant diffusion, such as phosphorus or arsenic, from the source and drain regions of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intermediate diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide having a carbon concentration between 5% and 50% by atomic percentage. In some embodiments, the diffusion barrier layer may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier layer thickness in the 1-5 nanometer range.
Need to check novelty before this filing date? Find Prior Art