Semiconductor structure, test pad structure and manufacturing method thereof

Abstract

The present disclosure proposes a semiconductor structure, a test pad structure and a method for manufacturing the test pad structure, and relates to the field of semiconductor technology. The test pad structure includes a passivation layer, a dielectric layer, a through hole and a test pad. The dielectric layer is arranged on one side of the passivation layer, and includes a redistribution layer and a conductor, the redistribution layer has a test portion, the conductor is located on the side of the redistribution layer away from the passivation layer, and is arranged opposite to the test portion; the through hole passes through the passivation layer and the test portion, and exposes the conductor, and a partial area of ​​the test portion extends into the through hole; the test pad is filled in the through hole and has a first end and a second end, the first end is connected to the conductor, and the second end protrudes from the passivation layer. The test pad structure disclosed in the present disclosure can improve the conductivity and facilitate testing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure, a test pad structure and a method for manufacturing the test pad structure. Background Art

[0002] With the development of semiconductor technology, integrated circuit (IC) component packaging has also become a focus of attention. In order to ensure chip reliability, it is usually necessary to test semiconductor devices. In order to facilitate connection with the detection device, the semiconductor device generally has a test pad, and the detection device can detect the performance of the semiconductor device through the test pad.

[0003] In the prior art, the surface of the test pad is lower than the surface of the passivation layer, which makes the test inconvenient and requires additional test pads to ensure smooth testing. At the same time, in the prior art, the contact area between the redistribution layer and the test pad is small and the conductivity is weak.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0005] The purpose of the present disclosure is to provide a semiconductor structure, a test pad structure and a method for manufacturing the test pad structure, which can improve the conductivity and facilitate testing.

[0006] According to one aspect of the present disclosure, there is provided a test pad structure, comprising:

[0007] Passivation layer;

[0008] A dielectric layer is disposed on one side of the passivation layer, comprising a redistribution layer and a conductor, wherein the redistribution layer has a test portion, and the conductor is located on a side of the redistribution layer away from the passivation layer and is disposed opposite to the test portion;

[0009] a through hole, passing through the passivation layer and the test portion and exposing the conductor, wherein a partial area of ​​the test portion extends into the through hole;

[0010] The test pad is filled in the through hole and has a first end and a second end, wherein the first end is connected to the conductor, and the second end protrudes from the passivation layer.

[0011] In an exemplary embodiment of the present disclosure, the through hole comprises a plurality of hole segments connected in sequence, and the plurality of hole segments at least comprises:

[0012] A first hole section is located between the conductor and the testing portion and exposes the conductor;

[0013] A second hole segment is located in the testing portion and is connected to the first hole segment;

[0014] A third hole segment is located at a side of the test portion away from the conductor and is butted against the second hole segment;

[0015] A hole diameter of at least one of the first hole segment and the third hole segment is larger than a hole diameter of the second hole segment.

[0016] In an exemplary embodiment of the present disclosure, the apertures of the first hole segment and the third hole segment are both larger than the aperture of the second hole segment, and the aperture of the third hole segment is larger than the aperture of the first hole segment.

[0017] In an exemplary embodiment of the present disclosure, the plurality of hole segments that are connected in sequence further include:

[0018] The fourth hole segment is located in the passivation layer, and one end of the fourth hole segment is connected to the third hole segment, and the other end is located on the surface of the passivation layer away from the dielectric layer. The aperture of the fourth hole segment is larger than the aperture of the third hole segment.

[0019] In an exemplary embodiment of the present disclosure, an outer diameter of the second end of the test pad is larger than a hole diameter of the through hole.

[0020] In an exemplary embodiment of the present disclosure, the material of the redistribution layer includes at least one of aluminum, tungsten, copper and titanium.

[0021] In an exemplary embodiment of the present disclosure, the material of the test pad is at least one of tin, copper, nickel and gold.

[0022] According to one aspect of the present disclosure, there is provided a method for manufacturing a test pad structure, comprising:

[0023] forming a dielectric layer, wherein the dielectric layer has a redistribution layer and a conductor, and the redistribution layer has a test portion;

[0024] A passivation layer is formed to cover the dielectric layer, wherein the conductor is located on a side of the redistribution layer away from the passivation layer and is arranged opposite to the test portion;

[0025] forming a through hole, wherein the through hole passes through the passivation layer and the test portion and exposes the conductor, and a partial area of ​​the test portion extends into the through hole;

[0026] A test pad is formed in the through hole. The test pad fills the through hole and has a first end and a second end. The first end is connected to the conductor, and the second end protrudes from the passivation layer.

[0027] In an exemplary embodiment of the present disclosure, a dielectric layer is formed, wherein the dielectric layer has a redistribution layer and a conductor, and the redistribution layer has a test portion, including:

[0028] forming a substrate, the substrate comprising the conductor and a first insulating layer covering the conductor;

[0029] forming the redistribution layer on the substrate;

[0030] A second insulating layer covering the redistribution layer is formed.

[0031] In an exemplary embodiment of the present disclosure, a through hole is formed, the through hole passes through the passivation layer and the test part, and exposes the conductor, and a partial area of ​​the test part extends into the through hole, including:

[0032] Forming a preset hole by an anisotropic etching process, wherein the preset hole passes through the passivation layer and the test portion and exposes the conductor;

[0033] The inner wall of the preset hole is etched by an isotropic etching process to obtain the through hole, a partial area of ​​the testing portion extends into the through hole, and the through hole has a plurality of hole sections connected in sequence.

[0034] In an exemplary embodiment of the present disclosure, the plurality of hole segments that are connected in sequence at least include:

[0035] A first hole section is located between the conductor and the testing portion and exposes the conductor;

[0036] A second hole segment is located in the testing portion and is connected to the first hole segment;

[0037] A third hole segment is located at a side of the test portion away from the conductor and is butted against the second hole segment;

[0038] A hole diameter of at least one of the first hole segment and the third hole segment is larger than a hole diameter of the second hole segment.

[0039] In an exemplary embodiment of the present disclosure, the plurality of hole segments that are connected in sequence further include:

[0040] a fourth hole segment, located in the passivation layer, with one end connected to the third hole segment and the other end located on a surface of the passivation layer away from the dielectric layer;

[0041] The hole diameter of the fourth hole section is larger than the hole diameter of the third hole section.

[0042] In an exemplary embodiment of the present disclosure, an outer diameter of the second end of the test pad is greater than an outer diameter of the through hole.

[0043] According to one aspect of the present disclosure, a semiconductor structure is provided, comprising any one of the semiconductor devices described above.

[0044] The semiconductor structure, test pad structure and manufacturing method disclosed herein, since the second end of the test pad is protruded from the surface of the passivation layer, avoids the need to establish an additional test pad while ensuring the test function of the test pad, thereby reducing costs; and since part of the test part of the redistribution layer extends into the through hole, the contact area between the test pad and the test part can be increased, the series resistance can be reduced, and the conductivity can be improved.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0047] Figure 1 Schematic diagram of a test pad structure according to an embodiment of the present disclosure.

[0048] Figure 2 FIG. 4 is a top view of a test pad structure according to an embodiment of the present disclosure.

[0049] Figure 3 Schematic diagram of a through hole according to an embodiment of the present disclosure.

[0050] Figure 4 The figure is a flow chart of a method for manufacturing a test pad structure according to an embodiment of the present disclosure.

[0051] Figure 5 Flow chart of step S110 of the manufacturing method according to the embodiment of the present disclosure.

[0052] Figure 6 It is a schematic diagram of the structure after step S1102 of the manufacturing method according to an embodiment of the present disclosure.

[0053] Figure 7 It is a schematic diagram of the structure after step S1103 of the manufacturing method according to an embodiment of the present disclosure.

[0054] Figure 8 Flow chart of step S130 of the manufacturing method according to the embodiment of the present disclosure.

[0055] Fig. 9 A schematic diagram of forming a preset hole in the manufacturing method according to an embodiment of the present disclosure.

[0056] Fig.10 It is a schematic diagram of the structure after step S1302 of the embodiment of the present disclosure.

[0057] In the figure: 100, preset hole; 200, photoresist layer; 1, passivation layer; 2, dielectric layer; 21, redistribution layer; 22, conductor; 23, first insulating layer; 24, second insulating layer; 3, through hole; 31, first hole segment; 32, second hole segment; 33, third hole segment; 34, fourth hole segment; 4, test pad. DETAILED DESCRIPTION

[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0059] The features, structures or characteristics described above may be combined in one or more embodiments in any suitable manner, and if possible, the features discussed in each embodiment are interchangeable. In the above description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention may be practiced without one or more of the specific details, or other methods, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0060] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0061] The terms "a", "an", "the", "said", "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc. The terms "first", "second", "third", and "fourth" are used only as labels and are not intended to limit the quantity of their objects.

[0062] The present disclosure provides a test pad structure that can be used for packaging semiconductor devices. Figure 1-Figure 3As shown, the test pad structure may include a passivation layer 1, a dielectric layer 2, a through hole 3 and a test pad 4, wherein:

[0063] The dielectric layer 2 may be disposed on one side of the passivation layer 1, and may include a redistribution layer 21 and a conductor 22. The redistribution layer 21 may have a test portion 211. The conductor 22 may be located on a side of the redistribution layer 21 away from the passivation layer 1, and may be disposed opposite to the test portion 211.

[0064] The through hole 3 may pass through the passivation layer 1 and the test portion 211 and may expose the conductor 22 , and a partial area of ​​the test portion 211 may extend into the through hole 3 ;

[0065] The test pad 4 may be filled in the through hole 3 and may have a first end and a second end. The first end may be connected to the conductor 22 , and the second end may protrude from the passivation layer 1 .

[0066] The semiconductor structure, test pad structure and manufacturing method disclosed herein, since the second end of the test pad 4 protrudes from the surface of the passivation layer 1, avoids the need to establish an additional test pad while ensuring the test function of the test pad, thereby reducing costs; and since a portion of the test portion 211 of the redistribution layer 21 extends into the through hole 3, the contact area between the test pad 4 and the test portion 211 can be increased, the series resistance can be reduced, and the conductivity can be improved.

[0067] The following is a detailed description of each part of the test pad structure of the embodiment of the present disclosure:

[0068] The passivation layer 1 can cover the surface of the dielectric layer 2 and can be used to protect the dielectric layer 2. The passivation layer 1 can be a single-layer or multi-layer structure, and its material can be an insulating material, specifically, a polymer material or a non-metallic oxide material. For example, it can be polyimide (PI), or it can be silicon oxide, silicon nitride, etc. Of course, it can also be other insulating materials, which are not listed here one by one.

[0069] like Figure 3 As shown, the dielectric layer 2 may be disposed on one side of the passivation layer 1, and the dielectric layer 2 may include a redistribution layer 21 and a conductor 22, the redistribution layer 21 may have a test portion 211, and the conductor 22 may be located on a side of the redistribution layer 21 away from the passivation layer 1, and may be disposed opposite to the test portion 211. The shape of the dielectric layer 2 may be circular, elliptical, rectangular or other irregular shapes, and the material of the dielectric layer 2 may be silicon nitride, silicon dioxide, etc., and the material is not particularly limited herein.

[0070] The redistribution layer 21 may be embedded in the dielectric layer 2, and the redistribution layer 21 may include one or more conductive wires. The material of the redistribution layer 21 may be a metal, for example, it may be at least one of aluminum, tungsten, copper and titanium, and of course, it may be other materials as long as it is conductive. The redistribution layer 21 may have a test portion 211, and the test portion 211 may be used to connect the test pad 4 to other test pads 4 or welding pads, and the test portion 211 may have an opening to expose the conductor 22.

[0071] The conductor 22 may be disposed on a side of the redistribution layer 21 away from the passivation layer 1, and may be disposed opposite to the test portion 211. The conductor 22 may be a plate-like structure, and its shape may be circular, rectangular or other irregular shapes, and its material may be a metal material with strong conductivity, for example, it may be at least one of aluminum, tungsten, copper and titanium, and of course, it may be other materials, and the shape and material of the conductor 22 are not particularly limited here.

[0072] The through hole 3 can pass through the passivation layer 1 and the test portion 211, and can expose the conductor 22, and a part of the test portion 211 can extend into the through hole 3. One end of the through hole 3 can be connected to the conductor 22, and the other end can be located on the surface of the passivation layer 1 away from the dielectric layer 2. The shape of its cross section can be circular, rectangular, etc., or other irregular shapes. The shape of the through hole 3 is not particularly limited here. The through hole 3 can be a straight hole or a stepped hole including multiple hole segments.

[0073] For example, Figure 3 As shown, the through hole 3 may include a plurality of hole segments connected in sequence, and the plurality of hole segments may include a first hole segment 31, a second hole segment 32, a third hole segment 33 and a fourth hole segment 34. Wherein:

[0074] The first hole segment 31 may be located between the conductor 22 and the testing portion 211 and may expose the conductor 22. Specifically, the first hole segment 31 may be disposed on the dielectric layer 2, a first end of the first hole segment 31 may be connected to the surface of the conductor 22, a second end of the first hole segment 31 may be connected to the testing portion 211, and a hole diameter of the first end may be smaller than a hole diameter of the second end.

[0075] The second hole segment 32 may be located in the test portion 211 and may be connected to the first hole segment 31. For example, one end of the second hole segment 32 may be connected to the first hole segment 31, and the other end may be located on a side of the redistribution layer 21 away from the conductor 22. It should be noted that the aperture of the end of the second hole segment 32 connected to the first hole segment 31 is smaller than the aperture of the end of the second hole segment 32 away from the conductor 22.

[0076] The third hole segment 33 may be located on a side of the test portion 211 away from the conductor 22, and may be connected to the second hole segment 32. Specifically, the third hole segment 33 may be disposed on the dielectric layer 2, one end of the third hole segment 33 may be connected to the second hole segment 32, and the other end may be connected to the passivation layer 1, and the aperture of the end connected to the second hole segment 32 may be smaller than the aperture of the end connected to the passivation layer 1.

[0077] The fourth hole segment 34 may be located in the passivation layer 1 , and one end of the fourth hole segment 34 may be connected to the third hole segment 33 , and the other end may be located on the surface of the passivation layer 1 away from the dielectric layer 2 .

[0078] It should be noted that the aperture of at least one of the first hole segment 31 and the third hole segment 33 may be larger than the aperture of the second hole segment 32. The aperture of the fourth hole segment 34 may be larger than the aperture of the third hole segment 33. Specifically, the minimum value of the aperture of the first hole segment 31 may be larger than the maximum value of the aperture of the second hole segment 32; or the minimum value of the aperture of the third hole segment 33 may be larger than the maximum value of the aperture of the second hole segment 32; in one embodiment, the minimum values ​​of the apertures of the first hole segment 31 and the third hole segment 33 may both be larger than the maximum value of the aperture of the second hole segment 32, and the minimum value of the aperture of the third hole segment 33 may be larger than the maximum value of the aperture of the first hole segment 31, and at the same time, the minimum value of the aperture of the fourth hole segment 34 may be larger than the maximum value of the aperture of the third hole segment 33.

[0079] like Figure 1 As shown, the test pad 4 can be filled in the through hole 3, and its shape can match the shape of the through hole 3. It can have a first end and a second end, the first end can be connected to the conductor 22, the second end can protrude from the passivation layer 1, and the outer diameter of the second end of the test pad 4 can be larger than the aperture of the through hole 3.

[0080] The test pad 4 can be filled in the through hole 3 in the form of electroplating, and can sequentially contact the conductor 22, the first insulating layer 23 of the dielectric layer 2, the test portion 211, the second insulating layer 24 of the dielectric layer 2, and the passivation layer 1. The material of the test pad 4 can be a conductive material, for example, the material can be a metal, for example, can include at least one of tin, copper, nickel and gold, of course, can also be other materials, and the material of the test pad 4 is not particularly limited here, as long as it can conduct electricity and can achieve the function of the test pad 4.

[0081] like Figure 1-Figure 3As shown, the number of the conductor 22, the test part 211, the test pad 4 and the through hole 3 can be multiple, and the multiple conductors 22, the multiple test parts 211, the multiple contact bodies 3 and the multiple test pads 4 can be arranged one by one, and the multiple test pad structures can be connected through the redistribution layer 21. Of course, the number of the conductor 22, the test part 211, the test pad 4 and the through hole 3 can be one, and the conductor 22, the test part 211, the contact body 3 and the test pad 4 can be arranged correspondingly with reference to the above description to form a test pad structure.

[0082] The present disclosure also provides a method for manufacturing a test pad structure. Figure 4 As shown, the manufacturing method may include:

[0083] Step S110, forming a dielectric layer, wherein the dielectric layer has a redistribution layer and a conductor, and the redistribution layer has a test portion;

[0084] Step S120, forming a passivation layer covering the dielectric layer, wherein the conductor is located on a side of the redistribution layer away from the passivation layer and is arranged opposite to the test portion;

[0085] Step S130, forming a through hole, wherein the through hole passes through the passivation layer and the test part and exposes the conductor, and a partial area of ​​the test part extends into the through hole;

[0086] Step S140 , forming a test pad in the through hole, wherein the test pad fills the through hole and has a first end and a second end, wherein the first end is connected to the conductor, and the second end protrudes from the passivation layer.

[0087] In the manufacturing method of the embodiment of the present disclosure, since the second end of the test pad 4 protrudes from the surface of the passivation layer 1, the test pad 4 will not sink into the passivation layer 1 when it is worn, and the normal test function can be maintained, avoiding the need to set up additional test pads, thereby reducing costs; and since part of the test portion 211 of the redistribution layer 21 extends into the through hole 3, the contact area between the test pad 4 and the test portion 211 can be increased, the series resistance can be reduced, and the conductivity can be improved. The steps of the manufacturing method of the embodiment of the present disclosure are described in detail below:

[0088] In step S110 , a dielectric layer is formed, wherein the dielectric layer has a redistribution layer and a conductor, and the redistribution layer has a test portion.

[0089] The material of the dielectric layer 2 can be silicon nitride, silicon dioxide, etc., and there is no special limitation on the material. The shape of the dielectric layer 2 can be circular, elliptical, rectangular or other irregular shapes.

[0090] The conductor 22 can be arranged opposite to the test part 211. The shape of the conductor 22 can be circular, rectangular or other irregular shapes. Its material can be a metal material with strong conductive properties. For example, it can be at least one of aluminum, tungsten, copper and titanium. Of course, it can also be other materials. There is no special limitation on the shape and material of the conductor 22.

[0091] For example, Figure 5 As shown, step S110 may include:

[0092] Step S1101, forming a substrate, wherein the substrate includes the conductor and a first insulating layer covering the conductor;

[0093] like Figure 6 As shown, the substrate may include a plurality of conductors 22 spaced apart, the conductors 22 may be connected to an external circuit, and the plurality of conductors 22 may be covered under a first insulating layer 23. The material of the first insulating layer 23 may be a polymer, for example, an inorganic silicon compound, such as silicon nitride, silicon dioxide, etc., and no special limitation is made to the material thereof.

[0094] Step S1102, forming the redistribution layer on the substrate;

[0095] In one embodiment, if Figure 7 As shown, the redistribution layer 21 may be a wire embedded in the dielectric layer 2. Specifically, it may be one or more wires that penetrate the dielectric layer 2 and may be arranged parallel to the substrate. The material of the redistribution layer 21 may be a metal. Specifically, it may be at least one of aluminum, tungsten, copper and titanium. Of course, it may also be other materials as long as it is conductive. The redistribution layer 21 may have a test portion 211. The test portion 211 may be used to connect the test pad to other test pads or welding pads, and the test portion 211 may have an opening that exposes the conductor 22.

[0096] In another embodiment, the redistribution layer 21 may include a testing portion 211 , and the testing portion 211 may have an opening facing the conductive body 22 and exposing the conductive body 22 .

[0097] Step S1103 , forming a second insulating layer on the redistribution layer.

[0098] The second insulating layer 24 may be located on a side of the redistribution layer 21 away from the conductor 22 and cover the surface of the redistribution layer 21 . When the test portion 211 has an opening facing the conductor 22 and exposing the conductor 22 , the second insulating layer 24 may also cover the opening of the test portion 211 facing the conductor 22 .

[0099] In step S120, a passivation layer covering the dielectric layer is formed, and the conductor is located on a side of the redistribution layer away from the passivation layer and is disposed opposite to the test portion.

[0100] The passivation layer 1 can cover the surface of the dielectric layer 2 and can be used to protect the dielectric layer 2. The passivation layer 1 can be a single layer or a multi-layer structure, and its material can be an insulating material, specifically, a polymer material or a non-metallic oxide material, such as polyimide (PI), silicon oxide, silicon nitride, etc., and of course other insulating materials, which are not listed here. The passivation layer 1 can be located on the side of the redistribution layer 21 away from the conductor 22, that is, the conductor 22 can be located on the side of the redistribution layer 21 away from the passivation layer 1.

[0101] Step S130, forming a through hole, wherein the through hole passes through the passivation layer and the test part and exposes the conductor, and a partial area of ​​the test part extends into the through hole;

[0102] The through hole 3 can pass through the passivation layer 1 and the test part 211, and can expose the conductor 22. Part of the test part 211 can extend into the through hole 3, which is beneficial to expand the contact area between the through hole 3 and the test part 211, reduce the series resistance, and improve the conductivity. The specific structure of the through hole 3 can refer to the above description, which will not be repeated here.

[0103] In one embodiment, if Figure 8 As shown, step S130 may include:

[0104] Step S1301: forming a preset hole by an anisotropic etching process, wherein the preset hole passes through the passivation layer and the test portion and exposes the conductor.

[0105] A photoresist layer 200 is formed on the passivation layer 1, and the passivation layer 1 and the dielectric layer 2 are anisotropically etched to form a preset hole 100. One end of the preset hole 100 can be connected to the surface of the conductor 22, and the other end can be located on the surface of the passivation layer 1 away from the dielectric layer 2. The preset hole 100 can pass through the test part 211, so that the test part 211 has an opening exposing the conductor 22.

[0106] Step S1302: etching the inner wall of the preset hole by an isotropic etching process to obtain the through hole, wherein a partial area of ​​the testing portion extends into the through hole, and the through hole has a plurality of hole segments connected in sequence.

[0107] In one embodiment, if Fig. 9As shown, the preset hole 100 can be etched in sections. For example, the side wall of the preset hole 100 in contact with the first insulating layer 24, the side wall of the preset hole 100 in contact with the redistribution layer 21, the side wall of the preset hole 100 in contact with the second insulating layer 24, and the side wall of the preset hole 100 in contact with the passivation layer 1 can be etched respectively. After the etching is completed, the photoresist layer 200 can be removed to form a through hole 3 with a preset shape. The preset shape can be circular, rectangular or other shapes, and the shape of the through hole 3 is not particularly limited here. For example, the through hole 3 can be obtained by etching each layer by an isotropic wet etching method, such as Fig.10 As shown, the through hole 3 may include a plurality of hole segments connected in sequence, and the plurality of hole segments may include a first hole segment 31, a second hole segment 32, a third hole segment 33 and a fourth hole segment 34. Wherein:

[0108] The first hole segment 31 may be located between the conductor 22 and the testing portion 211 and may expose the conductor 22. Specifically, the first hole segment 31 may be disposed on the dielectric layer 2, a first end of the first hole segment 31 may be connected to the surface of the conductor 22, a second end of the first hole segment 31 may be connected to the testing portion 211, and a hole diameter of the first end may be smaller than a hole diameter of the second end.

[0109] The second hole segment 32 may be located in the test portion 211 and may be connected to the first hole segment 31. For example, one end of the second hole segment 32 may be connected to the first hole segment 31, and the other end may be located on a side of the redistribution layer 21 away from the conductor 22. It should be noted that the aperture of the end of the second hole segment 32 connected to the first hole segment 31 is smaller than the aperture of the end of the second hole segment 32 away from the conductor 22.

[0110] The third hole segment 33 may be located on a side of the test portion 211 away from the conductor 22, and may be connected to the second hole segment 32. Specifically, the third hole segment 33 may be disposed on the dielectric layer 2, one end of the third hole segment 33 may be connected to the second hole segment 32, and the other end may be connected to the passivation layer 1, and the aperture of the end connected to the second hole segment 32 may be smaller than the aperture of the end connected to the passivation layer 1.

[0111] The fourth hole segment 34 may be located in the passivation layer 1 , and one end of the fourth hole segment 34 may be connected to the third hole segment 33 , and the other end may be located on the surface of the passivation layer 1 away from the dielectric layer 2 .

[0112] It should be noted that the aperture of at least one of the first hole segment 31 and the third hole segment 33 may be larger than the aperture of the second hole segment 32. The aperture of the fourth hole segment 34 may be larger than the aperture of the third hole segment 33. Specifically, the minimum value of the aperture of the first hole segment 31 may be larger than the maximum value of the aperture of the second hole segment 32; or the minimum value of the aperture of the third hole segment 33 may be larger than the maximum value of the aperture of the second hole segment 32; in one embodiment, the minimum values ​​of the apertures of the first hole segment 31 and the third hole segment 33 may both be larger than the maximum value of the aperture of the second hole segment 32, and the minimum value of the aperture of the third hole segment 33 may be larger than the maximum value of the aperture of the first hole segment 31, and at the same time, the minimum value of the aperture of the fourth hole segment 34 may be larger than the maximum value of the aperture of the third hole segment 33.

[0113] Step S140 , forming a test pad in the through hole, wherein the test pad fills the through hole and has a first end and a second end, wherein the first end is connected to the conductor, and the second end protrudes from the passivation layer.

[0114] The test pad 4 can be filled in the through hole 3 in the form of electroplating, evaporation, etc., and of course other methods are also possible. The method of filling the test pad 4 in the through hole 3 is not particularly limited here, as long as it can fill the through hole 3 and conduct electricity. The shape of the test pad 4 can match the shape of the through hole 3. The test pad 4 can have a first end and a second end, the first end can be connected to the conductor 22, the second end can protrude from the passivation layer 1, and the outer diameter of the second end of the test pad 4 can be larger than the aperture of the through hole 3. The material and specific structure of the test pad 4 can refer to the above description, and will not be repeated here.

[0115] It should be noted that the number of the test pad structures manufactured by the manufacturing method can be one or more, and the multiple test pad structures can be connected through the redistribution layer 21 .

[0116] The present disclosure also provides a semiconductor device, which may include the test pad structure of the above embodiment. The semiconductor device may be an integrated circuit including a plurality of test pad structures, or may be other forms of semiconductor structures, which are not specifically limited here. At the same time, the beneficial effects of the semiconductor device may refer to the beneficial effects of the test pad structure in the above embodiment, which will not be described in detail here.

[0117] It should be noted that, although the steps of the manufacturing method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0118] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A test pad structure, characterized in that: include: Passivation layer; A dielectric layer is disposed on one side of the passivation layer, comprising a redistribution layer and a conductor, wherein the redistribution layer has a test portion, and the conductor is located on a side of the redistribution layer away from the passivation layer and is disposed opposite to the test portion; a through hole, passing through the passivation layer and the test portion and exposing the conductor, wherein a partial area of ​​the test portion extends into the through hole; A test pad, filled in the through hole, having a first end and a second end, wherein the first end is connected to the conductor, and the second end protrudes from the passivation layer; Wherein, the through hole comprises a plurality of hole segments connected in sequence, and the plurality of hole segments at least comprises: A first hole segment is located between the conductor and the testing portion and exposes the conductor; a first end of the first hole segment contacts the conductor, a second end of the first hole segment connects to the testing portion, and a hole diameter of the first end of the first hole segment is smaller than a hole diameter of the second end of the first hole segment.

2. The test pad structure according to claim 1, characterized in that: The through hole also includes: A second hole segment is located in the testing portion and is connected to the first hole segment; A third hole segment is located at a side of the test portion away from the conductor and is butted against the second hole segment; A hole diameter of at least one of the first hole segment and the third hole segment is larger than a hole diameter of the second hole segment.

3. The test pad structure according to claim 2, characterized in that: The apertures of the first hole segment and the third hole segment are both larger than the aperture of the second hole segment, and the aperture of the third hole segment is larger than the aperture of the first hole segment.

4. The test pad structure according to claim 2, characterized in that: The plurality of hole segments connected in sequence also include: The fourth hole segment is located in the passivation layer, and one end of the fourth hole segment is connected to the third hole segment, and the other end is located on the surface of the passivation layer away from the dielectric layer. The aperture of the fourth hole segment is larger than the aperture of the third hole segment.

5. The test pad structure according to claim 1, characterized in that: The outer diameter of the second end of the test pad is larger than the hole diameter of the through hole.

6. The test pad structure according to claim 1, characterized in that: The material of the redistribution layer includes at least one of aluminum, tungsten, copper and titanium.

7. The test pad structure according to claim 1, characterized in that: The material of the test pad is at least one of tin, copper, nickel and gold.

8. A method for manufacturing a test pad structure, characterized in that: include: forming a dielectric layer, wherein the dielectric layer has a redistribution layer and a conductor, and the redistribution layer has a test portion; A passivation layer is formed to cover the dielectric layer, wherein the conductor is located on a side of the redistribution layer away from the passivation layer and is arranged opposite to the test portion; forming a through hole, wherein the through hole passes through the passivation layer and the test portion and exposes the conductor, and a partial area of ​​the test portion extends into the through hole; A test pad is formed in the through hole. The test pad fills the through hole and has a first end and a second end. The first end is connected to the conductor, and the second end protrudes from the passivation layer.

9. The method for manufacturing a test pad structure according to claim 8, characterized in that: A dielectric layer is formed, wherein the dielectric layer has a redistribution layer and a conductor, and the redistribution layer has a test portion, including: forming a substrate, the substrate comprising the conductor and a first insulating layer covering the conductor; forming the redistribution layer on the substrate; A second insulating layer covering the redistribution layer is formed.

10. The method for manufacturing a test pad structure according to claim 8, characterized in that: Forming a through hole, wherein the through hole passes through the passivation layer and the test part and exposes the conductor, and a partial area of ​​the test part extends into the through hole, comprising: Forming a preset hole by an anisotropic etching process, wherein the preset hole passes through the passivation layer and the test portion and exposes the conductor; The inner wall of the preset hole is etched by an isotropic etching process to obtain the through hole, a partial area of ​​the testing portion extends into the through hole, and the through hole has a plurality of hole sections connected in sequence.

11. The method for manufacturing a test pad structure according to claim 10, characterized in that: The plurality of hole segments connected in sequence at least include: A first hole section is located between the conductor and the testing portion and exposes the conductor; A second hole segment is located in the testing portion and is connected to the first hole segment; A third hole segment is located at a side of the test portion away from the conductor and is butted against the second hole segment; A hole diameter of at least one of the first hole segment and the third hole segment is larger than a hole diameter of the second hole segment.

12. The method for manufacturing a test pad structure according to claim 11, characterized in that: The plurality of hole segments connected in sequence also include: a fourth hole segment, located in the passivation layer, with one end connected to the third hole segment and the other end located on a surface of the passivation layer away from the dielectric layer; The hole diameter of the fourth hole section is larger than the hole diameter of the third hole section.

13. The method for manufacturing a test pad structure according to claim 8, characterized in that: The outer diameter of the second end of the test pad is greater than the outer diameter of the through hole.

14. A semiconductor structure, characterized in that: The test pad structure comprises any one of claims 1 to 7.

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