Mask plate assembly and contact plug manufacturing method, semiconductor device and manufacturing method thereof

Abstract

The present invention provides a mask combination and a contact plug manufacturing method, a semiconductor device and a manufacturing method thereof. The mask combination provided by the present invention is used to define the formation position of the contact plugs, so that there are no contact plugs above some active areas at the core area boundary, while there are contact plugs above other active areas at the core area boundary and the active areas inside the core area. Therefore, when the existing process is subsequently used to form corresponding electrical structures inside and at the boundary of the core area, some electrical structures at the core area boundary become virtual structures because there are no contact plugs contacting the active areas below them. This can avoid the problem that the manufactured semiconductor device fails related tests due to problems with the electrical structure at the core area boundary, thereby improving the performance and pass rate of the manufactured semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a mask assembly and a contact plug manufacturing method, a semiconductor device and a manufacturing method thereof. Background Art

[0002] Various technologies have been used to integrate more circuit patterns within the limited area of ​​a semiconductor substrate or wafer. Due to the different pitches between circuit patterns, integrated circuits are generally divided into dense regions (Dense), sparse regions (ISO), and isolated regions. Dense regions are areas with higher device density (i.e., denser devices), sparse regions are areas with lower device density (i.e., sparser devices), and isolated regions are areas separated from the dense and sparse regions. As the critical dimensions of semiconductor devices continue to decrease, the density of circuit patterns and / or device heights continue to increase. This, due to the resolution limitations of optical exposure tools and the density difference between dense and sparse regions (i.e., the dense / sparse effect of circuit patterns), significantly increases the difficulty in performing photolithography and / or etching processes (e.g., reduces process margins), thereby affecting the performance of the manufactured semiconductor devices.

[0003] For example, in a dynamic random access memory (DRAM) device, a large number of memory cells are gathered to form an array memory area, and a peripheral circuit area exists next to the array memory area. The peripheral circuit area includes other transistor elements and contact structures. The array memory area serves as a device-intensive area of ​​the DRAM and is used to store data. The peripheral circuit area serves as a device-sparse area of ​​the DRAM and is used to provide input and output signals required by the array memory area. Each memory cell in the array memory area may be composed of a metal oxide semiconductor (MOS) transistor and a capacitor structure connected in series. The capacitor is located in the array memory area, wherein the capacitor is stacked above the bit line and electrically coupled to the storage node contact corresponding to the capacitor, and the storage node contact is electrically coupled to the active area thereunder. With the continuous advancement of semiconductor technology, the critical dimensions of devices continue to decrease, and the gaps between memory cells in DRAM devices have become narrower. When forming storage node contacts through the self-aligned contact (SAC) process, the resolution limit of the optical exposure tool (optical exposure tool) and the density difference between dense and sparse device areas are affected. After the capacitors are connected to the contact plugs in the array storage area, the capacitors at the boundaries of the array storage area are prone to collapse or partial failure. These problems affect the performance of the manufactured DRAM devices and are very likely to cause the manufactured DRAM devices to fail relevant tests, thereby reducing the qualified rate of the produced DRAM devices. Summary of the Invention

[0004] The object of the present invention is to provide a mask assembly and a contact plug manufacturing method, a semiconductor device and a manufacturing method thereof, so as to improve the performance and the qualified rate of the manufactured semiconductor device.

[0005] In order to solve the above technical problems, the present invention provides a mask assembly for manufacturing contact plugs, wherein the mask assembly comprises:

[0006] The first mask has a plurality of parallel first light-shielding stripes, and a first light-transmitting area is formed between two adjacent first light-shielding stripes;

[0007] The second mask has a plurality of parallel second light-shielding stripes intersecting each first light-shielding stripe, and a second light-transmitting area is formed between two adjacent second light-shielding stripes;

[0008] The third mask plate has a light-shielding block and a third light-transmitting area complementary to the light-shielding block, wherein the light-shielding block covers at least one first light-shielding stripe at the boundary of the first mask plate and the portion of the first light-transmitting area nearest to the first light-shielding stripe, and covers at least two second light-shielding stripes at the boundary of the second mask plate and the portion of the second light-transmitting area between the two second light-shielding stripes. The overlapping area of ​​the third light-transmitting area, the first light-transmitting area and the second light-transmitting area is the area where the contact plug is formed.

[0009] Based on the same inventive concept, the present invention further provides a contact plug fabrication method, which is fabricated using the mask assembly of the present invention. The contact plug fabrication method comprises:

[0010] Providing a semiconductor substrate having a plurality of active areas, and sequentially forming an interlayer dielectric layer and a first mask layer on the semiconductor substrate;

[0011] Using a process combining photolithography and etching, the pattern on the first mask in the mask assembly is transferred to the first mask layer to form a corresponding plurality of first lines in the first mask layer, wherein each first line corresponds to a corresponding first light-shielding stripe on the first mask, and the grooves between adjacent first lines correspond to corresponding first light-transmitting areas on the first mask and expose the corresponding interlayer dielectric layer;

[0012] Covering the interlayer dielectric layer and the first mask layer with a second mask layer, and transferring the pattern on the second mask sheet in the mask sheet assembly to the second mask layer using a photolithography-etching process to form a plurality of corresponding second lines, wherein each second line corresponds to a corresponding second light-shielding stripe on the second mask sheet, and the grooves between adjacent second lines correspond to corresponding second light-transmitting areas on the second mask sheet and expose the corresponding first lines and the interlayer dielectric layer in the first light-transmitting areas;

[0013] Covering the first mask layer, the second mask layer, and the interlayer dielectric layer with a third mask layer, and transferring the pattern on the third mask plate in the mask plate assembly to the third mask layer using a photolithography process, with the remaining third mask layer corresponding to the light shielding block of the third mask plate, and the interlayer dielectric layer exposed by the remaining third mask layer, the first mask layer, and the second mask layer being the area where the contact plug is to be formed;

[0014] Using the first mask layer, the second mask layer, and the third mask layer as masks, etching the exposed interlayer dielectric layer to form contact holes exposing corresponding active areas;

[0015] Contact plugs are formed in the contact holes, and bottoms of the contact plugs are in contact with corresponding active regions.

[0016] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, comprising: using the method for manufacturing contact plugs described in the present invention to form contact plugs on a semiconductor substrate having a core area, wherein the bottom of each contact plug contacts the active area of ​​the corresponding core element in the core area.

[0017] Based on the same inventive concept, the present invention further provides a semiconductor device manufactured using the method for manufacturing a semiconductor device according to the present invention, comprising:

[0018] A semiconductor substrate having a core region formed therein, wherein the core region has an active region of a plurality of core elements;

[0019] an interlayer dielectric layer formed on the semiconductor substrate;

[0020] a plurality of contact plugs formed in the interlayer dielectric layer and contacting the active regions of corresponding core components;

[0021] Wherein, there is no contact plug above a portion of the active area at the boundary of the core area.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] The mask combination provided by the present invention is used to define the formation positions of contact plugs, so that there are no contact plugs above some active areas at the core area boundary, while there are contact plugs above other active areas at the core area boundary and the active areas inside the core area. Therefore, when the existing process is subsequently used to form corresponding electrical structures inside and at the boundary of the core area, some electrical structures at the core area boundary become virtual structures because there are no contact plugs contacting the active areas below them. This can avoid the problem that the manufactured semiconductor device fails related tests due to problems with the electrical structure at the core area boundary, thereby improving the performance and qualification rate of the manufactured semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a structural schematic diagram of a first mask according to a specific embodiment of the present invention;

[0025] Figure 2 is a schematic structural diagram of a second mask according to a specific embodiment of the present invention;

[0026] Figure 3 is a structural schematic diagram of a first mask according to a specific embodiment of the present invention;

[0027] Figure 4A 1 is a schematic structural diagram of the first mask and the active area of ​​the core area after pattern alignment and overlap in a specific embodiment of the present invention (some layers that affect the observation of pattern alignment and overlap are omitted);

[0028] Figure 4B 3 is a schematic structural diagram of the second mask, the first mask, and the active area of ​​the core area after pattern alignment and overlap in a specific embodiment of the present invention (some layers that affect the observation of pattern alignment and overlap are omitted);

[0029] Figure 4C 1 is a schematic structural diagram of the third mask, the second mask, the first mask, and the active area of ​​the core area after pattern alignment and overlap in a specific embodiment of the present invention (some layers that affect the observation of pattern alignment and overlap are omitted);

[0030] Figure 5 1 is a schematic diagram of the distribution of contact plugs fabricated on the core region using a mask assembly in a specific embodiment of the present invention, wherein there are no contact plugs above a portion of the active region at the boundary of the core region;

[0031] Figure 6 The specific embodiment of the present invention is Figure 5 Schematic diagram of the cross-sectional structure at the boundary of the central core area and along the aa' line;

[0032] Figure 7 It is a schematic diagram of the cross-sectional structure of a semiconductor device at the boundary of the core region according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following is a detailed description of the memory device and its formation method proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0034] Please refer to Figures 1 to 3 An embodiment of the present invention provides a mask plate assembly for manufacturing contact plugs, wherein the mask plate assembly includes: a first mask plate 10 , a second mask plate 20 and a third mask plate 30 .

[0035] Please refer to Figure 1The first mask plate 10 has a plurality of parallel first light-shielding stripes, with a first light-transmitting area 102 formed between two adjacent first light-shielding stripes. In this embodiment, the first first light-shielding stripe 101a at the boundary of the first mask plate 10 (i.e., the boundary extending along the length of the first light-shielding stripe) has a first width W1, the second first light-shielding stripe 101b has a width less than W1, and the remaining first light-shielding stripes 101c have a second width W2. The first width W1 is greater than the second width W2, for example, W1>1.5*W2, and the second first light-shielding stripe 101b has a width greater than W2. Therefore, during the photolithography and etching process of transferring the pattern on the first mask plate 10 to the corresponding film layer, the gradual width variation of the first first light-shielding stripe 101a, the second first light-shielding stripe 101b, and the remaining first light-shielding stripes 101c in the first mask plate 10 can be utilized to improve the pattern density / sparseness effect between the core area and the peripheral area of ​​the semiconductor device, thereby enhancing the pattern transfer effect of the first mask plate 10. In other embodiments of the present invention, the width of the second first light-shielding stripe 101b can be equal to that of the first first light-shielding stripe 101a. Furthermore, optionally, the width of the first light-transmitting region 102 between the first first light-shielding stripe 101a and the second first light-shielding stripe 101b is greater than the width of the remaining first light-transmitting regions 102, thereby facilitating sufficient process margin for fabricating contact plugs at the core region boundary of the semiconductor device.

[0036] Please refer to Figure 2 The second mask 20 has a plurality of parallel second light-shielding stripes 201 that intersect vertically with each first light-shielding stripe 101a, 101b, 101c, and a second light-transmitting area 202 is located between two adjacent second light-shielding stripes 201. Figure 2The widths of the second shading stripes 201 shown in the figure are basically the same, but in other embodiments of the present invention, optionally, at least one second shading stripe (not shown) at the boundary of the second mask plate 20 (i.e., the boundary extending along the length of the second shading stripe) has a third width (not shown), and the remaining second shading stripes have a fourth width (not shown), and the third width is greater than the fourth width, for example, the third width is greater than 1.5 times the fourth width. Therefore, in the lithography and etching process of transferring the pattern on the second mask plate 20 to the corresponding film layer, the width gradient of the second shading stripes in the second mask plate 20 can be used to improve the pattern density / sparseness effect between the core area and the peripheral area of ​​the semiconductor device, thereby improving the pattern transfer effect of the second mask plate 20. In other embodiments of the present invention, optionally, the width of the second light-transmitting area 202 between the first second light-shielding stripe and the second second light-shielding stripe at the boundary of the second mask plate 20 (i.e., the boundary extending along the length of the first light-shielding stripe) is greater than the width of the remaining second light-transmitting areas 202, thereby facilitating providing sufficient process margin for the fabrication of contact plugs at the boundary of the core area of ​​the semiconductor device.

[0037] Please refer to Figure 3 The third mask plate 30 has a light shielding block 301 and a third light-transmitting area 302 complementary to the light shielding block 301. The light shielding block 301 may have a serrated edge facing the core area to mask a portion of the area at the boundary of the core area where the contact hole is to be formed.

[0038] It should be noted that Figures 1 to 3 Only patterns of a corner area of ​​the first mask plate 10, the second mask plate 20 and the third mask plate 30 are shown respectively. Those skilled in the art should be able to Figures 1 to 3 The displayed area is extended accordingly to obtain a substantially rectangular complete mask. Furthermore, the light shielding block 301 on the complete third mask 30 is a closed annular structure or a non-closed annular structure with at least one opening. The jagged edges of the light shielding block 301 facing the center of the third mask 30 are asymmetrical, i.e., the light shielding blocks 301 on the top and bottom sides of the third mask 30 are asymmetrical, and the light shielding blocks 301 on the left and right sides of the third mask 30 are asymmetrical.

[0039] Please refer to Figure 4C and Figure 5When the mask assembly of this embodiment is used to form a contact plug on a semiconductor substrate having a core region I, an interface region III, and a peripheral region II, the light-shielding block 301 covers at least one first light-shielding stripe at the boundary of the first mask 10 and the portion of the first light-transmitting region nearest to the first light-shielding stripe, and covers at least two second light-shielding stripes 201 at the boundary of the second mask 20 and the portion of the second light-transmitting region 202 between the two second light-shielding stripes. Furthermore, the overlapping area between the third light-transmitting region 302, the first light-transmitting region 102, the second light-transmitting region 202, and the core region I constitutes the region CT where the contact plug is formed. Optionally, based on the shapes of the first and second light-shielding stripes, the shape of the region CT where the contact plug is formed includes at least one of a square, a circle, an ellipse, a triangle, a rectangle, a polygon, and a heart.

[0040] In addition, in order to take into account device density, performance, qualified rate and other issues as much as possible, the number of second light-shielding stripes 201 covered by the light-shielding block 301 is 2 to 5 times the number of first light-shielding stripes covered by the light-shielding block 301.

[0041] Please refer to Figures 1 to 3 、 Figures 4A to 4C as well as Figures 5-6 An embodiment of the present invention further provides a method for manufacturing a contact plug. The method is implemented using the mask assembly of the present invention and specifically includes the following steps:

[0042] First, please refer to Figure 4A and Figure 6 A semiconductor substrate 400 having a plurality of active areas AA1 is provided, and an interlayer dielectric layer 500 and a first mask layer P1 are sequentially formed on the semiconductor substrate 400, wherein the semiconductor substrate 400 further has a core area I, a peripheral area II, and a junction area III located between the core area I and the peripheral area II, a shallow trench isolation structure 400b defining each active area AA1 is formed in the core area I, and a shallow trench isolation structure 400a defining the core area I and the peripheral area II is formed in the junction area III, and the material of the first mask layer P1 can be silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0043] Next, please refer to Figure 1 、 Figure 4A and Figure 6, by using a process combining photolithography and etching, the pattern on the first mask in the mask assembly is transferred to the first mask layer P1, that is, the first mask layer P1 is patterned using the first mask 10. Specifically, a bottom anti-reflection layer (not shown) and a photoresist layer (not shown) are first sequentially covered on the first mask layer P1, and the photoresist layer is exposed and developed using the first mask 10 to transfer the pattern on the first mask 10 to the first mask layer P1. The bottom anti-reflection layer and the photoresist layer can then be removed. A plurality of first lines are formed in the patterned first mask layer P1, wherein each first line corresponds to a corresponding first light-shielding stripe on the first mask 10, and the grooves (not shown) between adjacent first lines correspond to corresponding first light-transmitting areas 102 on the first mask 10 and expose the corresponding interlayer dielectric layer 500. Specifically, for example, the outermost first line P11 at the boundary of the core area I (i.e., the boundary of the core area I extending along the length direction of the first line) corresponds to the first first light-shielding stripe 101a at the boundary of the first mask plate 10, the second first line P12 corresponds to the second first light-shielding stripe 101b at the boundary of the first mask plate 10, and the remaining first lines P10 correspond to the remaining first light-shielding stripes 101c inside the first mask plate 10.

[0044] Then, please refer to Figure 2 、 Figure 4B and Figure 6 A second mask layer P2 is formed over the first mask layer P1 and the interlayer dielectric layer 500. A photolithography-etching process is used to transfer the pattern on the second mask sheet 20 in the mask sheet assembly to the second mask layer P2 to form a plurality of corresponding second lines P20. In other words, the second mask layer P2 is patterned using the second mask sheet 20. The specific process is substantially the same as the process for patterning the first mask layer P1 using the first mask sheet and will not be described in detail here. Each second line P20 corresponds to a corresponding second light-shielding stripe 201 on the second mask plate 20, and the grooves (not labeled) between adjacent second lines P20 correspond to corresponding second light-transmitting areas 202 on the second mask plate 20. Each second line P20 perpendicularly intersects all first lines P11, P12, and P10 and covers the corresponding portion of the grooves between these first lines P11, P12, and P10 and the adjacent first lines within its line width region. The grooves between adjacent second lines P20 expose the interlayer dielectric layer 500 within the corresponding first lines P11, P12, and P10 and the grooves between the adjacent first lines within the groove width region. At this point, all first and second lines overlap, defining trenches CTa (not labeled) arranged in a checkerboard pattern. The material of the second mask layer P2 is different from that of the first mask layer P1, so that the above-mentioned etching process can retain the first lines between adjacent second lines.

[0045] Next, please refer to Figure 3 、 Figure 4C and Figure 6 , covering the second mask layer P2, the first mask layer P1 and the interlayer dielectric layer 500 with a third mask layer P3, wherein the material of the third mask layer P3 is different from the material of the second mask layer P2 and the material of the first mask layer P1, so that the first line and the second line exposed by the third mask layer P3 can be retained after the subsequent patterning of the third mask layer P3. Optionally, the material of the third mask layer P3 is photoresist; a photolithography process is used to transfer the pattern on the third mask template 30 in the mask template combination to the third mask layer P3, that is, the third mask layer P3 is patterned using the third mask template 30, and the remaining third mask layer P3 (that is, the patterned third mask layer P3) corresponds to the light shielding block 301 of the third mask template 30, and the trench CTa area (that is, the exposed interlayer dielectric layer 500 area) exposed by the remaining third mask layer P3 and the remaining second mask layer P2 and the first mask layer P1 is the area where the contact plug is to be formed. The remaining third mask layer P3 covers the trenches defined by the intersection of the first and second lines in the boundary region III, and also covers portions of the trenches defined by the intersection of the first and second lines at the outermost edges of the core region I in all directions. It should be noted that in this embodiment, the word lines WL can overlap with the second lines P20, and the first lines P10-P12 can overlap with the bit lines BL. Therefore, the first mask plate 10 can be a bit line mask plate, and the second mask plate 20 can be a word line mask plate.

[0046] Next, please refer to Figure 4C 、 Figure 5 and Figure 6 , using the remaining third mask layer P3, the second mask layer P2, and the first mask layer P1 as masks, the exposed interlayer dielectric layer 500 is etched until the active area AA1 in the semiconductor substrate 400 is exposed, thereby forming a contact hole exposing the corresponding active area AA1. In this embodiment, due to the masking effect of the third mask layer P3, a contact hole is formed on the active area AA1 at the boundary of the core area I extending along the length direction of the first line (such as Figure 5 The other part of the active area AA1 has no contact hole (as shown in the solid line frame box CT on the aa' line in the middle). Figure 5 (as shown in the block dCT with a dotted border on line aa').

[0047] Afterwards, please refer to Figure 5 and Figure 6 , forming a contact plug CT in each of the contact holes, with the bottom of each of the contact plugs CT contacting the corresponding active area AA1. Figure 6As can be seen from FIG, there is no contact plug above a portion of the active area AA1 at the boundary of the core area I along the length extension direction of the first line or the second line, as shown in FIG. Figure 6 As shown in dCT in . Furthermore, in some embodiments, the contact plugs CT are asymmetrically distributed at the boundaries of the core region I on opposite sides, for example, the contact plugs are asymmetrically distributed at the upper and lower boundaries of the core region I, and / or the contact plugs are asymmetrically distributed at the left and right boundaries of the core region I. As can be seen from the contact plug fabrication method of the present invention, by adjusting the shape and size of the light-shielding blocks of the third mask, the position of the trench defined by the intersection of the first and second lines covered by the patterned third mask layer can be adjusted, thereby achieving the requirement of having no contact plugs above the active area at certain specific locations at the boundary of the core region. Thus, in actual production, areas prone to problems at the boundary of the core region can be collected based on historical production data, so that contact plugs are no longer formed in these areas. This allows the electrical structures (e.g., capacitors or resistors, etc.) previously connected to the contact plug positions in these areas to become dummy structures and not be tested in subsequent yield tests, thereby improving the test pass rate and ultimately achieving the goal of improving product qualification rate.

[0048] The following takes semiconductor devices as dynamic random access memory as an example, and combines Figures 1 to 3 、 Figures 4A to 4C as well as Figure 5 and Figure 7 , to explain in detail how to manufacture the semiconductor device of the present invention by the above-mentioned method for manufacturing the contact plug. That is, the method for manufacturing the semiconductor device of the present invention specifically includes the following steps:

[0049] First, please refer to Figure 4A and Figure 7A semiconductor substrate 400 having multiple core components (i.e., memory transistors) is provided. The specific process includes: first, providing a semiconductor substrate 400a, which includes a core region I, a peripheral region II, and an interface region III. In this embodiment, core region I is a memory region. The core components to be formed in core region I include a selection element. Subsequently, a data storage element is connected above the core element. The selection element is, for example, a MOS transistor or a diode, and the data storage element is, for example, a capacitor or a variable resistor. A selection element and a corresponding data storage element constitute a memory cell. Peripheral circuits (e.g., NMOS transistors and PMOS transistors, diodes, or resistors) can be formed in peripheral region II to control the memory cell. Multiple shallow trench isolation structures 401b are formed in the semiconductor substrate 400a of core region I, and shallow trench isolation structures 401a are formed in the semiconductor substrate 400a of interface region III. The shallow trench isolation structures 401a define the boundary between core region I and peripheral region II in a two-dimensional plane. The shallow trench isolation structures 401b define the active area AA1 corresponding to each core component in core region I. The active areas AA1 are distributed in a strip shape on a two-dimensional plane and extend along a first direction. The active areas AA1 may be arranged in a staggered manner on the surface of the semiconductor substrate 400a. Then, a buried word line WL is formed in the semiconductor substrate 400a. The buried word line WL is generally buried at a predetermined depth in the semiconductor substrate 400a, extending along a second direction (i.e., the row direction) and passing through the shallow trench isolation structure 401b and the active area AA1. The second direction is not perpendicular to the first direction of the active area AA1. The buried word line WL serves as a gate to control the switching of the memory cell. Typically, the sidewalls and bottom of the buried word line WL are surrounded by a gate dielectric layer (not shown), and the top of the buried word line WL is buried within the gate cap layer 402. Since the buried word line WL is not the focus of the present invention, its related manufacturing process can refer to the known technical solutions in the field and will not be described in detail here. Furthermore, the gate dielectric layer may comprise silicon oxide or other suitable dielectric materials, the buried word line WL may comprise aluminum, tungsten, copper, titanium-aluminum alloy, polysilicon, or other suitable conductive materials, and the gate cap layer 402 may comprise silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable insulating materials. Furthermore, a second type of dopant, such as a P-type or N-type dopant, may be doped into the active area AA1 on both sides of the buried word line WL to form source and drain regions (collectively defined as S / D). One of the AA1 regions on either side of the buried word line WL is located at a predetermined position corresponding to a bitline contact structure at the center of AA1, and the other is located at a predetermined position corresponding to a storage node contact structure at the end of the active area AA1. The word line WL and the S / D regions may constitute or define multiple MOS storage transistors formed in the core region I of the semiconductor device. Furthermore, while forming the S / D regions, source and drain regions corresponding to peripheral transistors may also be formed in the peripheral region II (not shown).After forming the S / D, an etch stop layer 403 may be further formed on the semiconductor substrate 400a. The etch stop layer 303 may be made of, for example, silicon nitride (SiN) and / or silicon oxide (SiO2), covering the S / D and shallow trench isolation structures 401a and 401b. Subsequently, a plurality of bit line contact plugs (not shown) and bit lines BL located above the bit line contact plugs are formed on the S / D serving as drain regions in the core region I. The bit line contact plugs may be formed by first etching the S / D between two adjacent WLs formed in an active area AA1 to form a groove, and then forming metal silicide in the groove. The plurality of bit lines BL are parallel to each other and extend along a third direction (i.e., the column direction) perpendicular to the buried word lines WL, while simultaneously crossing the active area AA1 and the buried word lines WL. Each bit line BL, for example, includes a semiconductor layer (e.g., polysilicon, not shown), a barrier layer (e.g., including Ti or TiN, not shown), a metal layer (e.g., tungsten, aluminum, or copper, not shown), and a mask layer (e.g., including silicon oxide, silicon nitride, or silicon carbonitride, not shown) stacked in sequence.

[0050] Then, please refer to Figure 4A and Figure 7 After providing a semiconductor substrate 400 having bit lines BL and source and drain regions S / D of core components, an interlayer dielectric layer 500 is formed on the semiconductor substrate 400. The interlayer dielectric layer 500 may be made of silicon oxide, silicon nitride, or a low-K dielectric. Specifically, the interlayer dielectric layer 500 is first deposited on the semiconductor substrate 400 through a deposition process, so that the interlayer dielectric layer 500 fills the spaces between the bit lines BL and buries the bit lines BL. The interlayer dielectric layer 500 is then planarized through a process such as chemical mechanical polishing to form an interlayer dielectric layer 500 having a flat top surface. The top surface of the planarized interlayer dielectric layer 500 is at least higher than the top surface of the bit lines BL.

[0051] Next, please refer to Figures 1 to 3 、 Figures 4A to 4C 、 Figure 5 as well as Figure 7Using the above-described contact plug fabrication method, a first mask layer P1 having a pattern similar to the first mask plate 10, a second mask layer P2 having a pattern similar to the second mask plate 10, and a third mask layer P3 having a pattern similar to the third mask plate 30 are sequentially formed on the interlayer dielectric layer 500. The specific process steps can be referred to above and will not be described in detail here. The second mask layer P2 is formed on the first mask layer P1 and the exposed interlayer dielectric layer 500, and the third mask layer P3 is formed on the second mask layer P2 and the exposed first mask layer P1 and interlayer dielectric layer 500. The first lines in the first mask layer P1 and the second lines in the second mask layer P2 intersect perpendicularly and define a plurality of trenches arranged in a checkerboard pattern. The third mask layer P3 masks all of the trenches in the boundary region III and a portion of the trenches at the boundary of the core region I, thereby defining the locations of the effective storage node contact structures.

[0052] Then, please continue to refer to Figure 4C 、 Figure 5 as well as Figure 7 Using the third mask layer P3, the second mask layer P2, and the first mask layer P1 as masks, the interlayer dielectric layer 500 is anisotropically etched to form contact holes that penetrate the interlayer dielectric layer 500 and expose the corresponding S / D regions below that serve as source regions. At this time, contact holes (not shown) that expose the corresponding regions in the peripheral region II can be formed simultaneously. The size of the contact holes at the boundary of the core region I can be larger than the size of the contact holes within the core region I. In other embodiments of the present invention, contact holes can also be formed in the region of the junction region III near the boundary of the core region I. The contact plugs in the contact holes in the subsequent junction region III can be connected to the tops of the corresponding contact plugs at the boundary of the core region I.

[0053] Next, please continue to refer to Figure 5 and Figure 7After the contact holes are formed, an ashing process or wet cleaning or other suitable process may be performed to remove the third mask layer P3, the second mask layer P2 and the first mask layer P1 above the interlayer dielectric layer 500, and a barrier metal layer (not shown) and a conductive metal layer (not shown) may be sequentially filled in each contact hole. The barrier metal layer may cover the inner wall of the contact hole and the top surface of the interlayer dielectric layer 500 with a uniform thickness. The barrier metal layer may reduce or prevent the metal material disposed in the contact hole from diffusing into the interlayer dielectric layer 500. The barrier metal layer may be formed of Ta, TaN, TaSiN, Ti, Ti N, TiSiN, W, WN or any combination thereof, and may be formed using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD) (e.g., sputtering). The conductive metal layer may be formed of (one or more) refractory metals (e.g., cobalt, iron, nickel, tungsten and / or molybdenum). In addition, a conductive metal layer can be formed using a deposition process with good step coverage properties, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering). The formed conductive metal layer also covers the surface of the interlayer dielectric layer 500 around the contact hole. Thereafter, a chemical mechanical polishing (CMP) process can be used to chemically mechanically polish the top surface of the deposited conductive metal layer until the top surface of the interlayer dielectric layer 500 is exposed, thereby forming a contact plug CT located in the interlayer dielectric layer 500. Figure 7 FIG. 4 shows that there is no contact plug above the active area AA1 at the boundary of the core area I (contact plugs are formed at these locations in the prior art, but not in the present invention, i.e., Figure 7 A contact plug CT is provided above the other active area AA1 (for comparison). The contact plug CT serves as a storage node contact structure in the core area I and is used to connect to a capacitor subsequently formed above the core area I.

[0054] Afterwards, please continue to refer to Figure 7, a conventional capacitor manufacturing method in the art can be used to manufacture the corresponding capacitor on the core area I, and the specific process will not be described in detail here. A capacitor 705 is formed above each S / D in the core area I. At the boundary of the core area I, the capacitor 705 whose bottom is electrically connected to the corresponding S / D through the corresponding contact plug CT is an effective capacitor and participates in subsequent testing and device operation, while the capacitor without a contact plug CT between the bottom and the corresponding S / D is a virtual capacitor and no longer participates in device-related testing and device operation, thereby improving the product qualification rate. In this embodiment, each capacitor 705 includes a lower electrode layer 701, a capacitor dielectric layer 702, and an upper electrode layer 703. There are a bottom support layer 600, an intermediate support layer 601, and a top support layer 602 for lateral support and interleaved stacking between the capacitors 705. The bottom support layer 600 is used to provide bottom support for the subsequently formed lower electrode layer on the one hand, and to isolate the internal components of the semiconductor substrate 400 from the components above, such as the capacitor. The formation process of the bottom support layer 600 can also be a thermal oxidation process. The materials of the bottom support layer 600, the middle support layer 601 and the top support layer 602 include but are not limited to silicon nitride. In other embodiments of the present invention, in order to better support the lower electrode layer, more than two layers of middle support layers 601 may be stacked between the bottom support layer 600 and the top support layer 602. Optionally, all capacitors 705 may be arranged in a hexagonal close-packed manner. Furthermore, the lower electrode layer 701 is a tubular structure and may be a polysilicon electrode or a metal electrode. When the lower electrode layer 701 is a metal electrode, a stacked structure of titanium nitride (TiN) and Ti may also be used. When the lower electrode layer 701 is a polysilicon electrode, it may be formed using zero-doped and / or doped polysilicon material. The capacitor dielectric layer 702 covers the inner and outer surfaces of the tubular structure of the lower electrode layer 701 to fully utilize the two opposite surfaces of the lower electrode layer 701 to form a capacitor with a larger electrode surface area. Preferably, the capacitor dielectric layer 702 may be a high-K dielectric layer such as a metal oxide. Furthermore, the capacitor dielectric layer 702 is a multilayer structure, for example, a two-layer structure of halogen oxide and zirconium oxide. The upper electrode layer 703 can be a single-layer structure or a multilayer structure. When the upper electrode layer 703 is a single-layer structure, it can be, for example, a polysilicon electrode, or a metal electrode. When the upper electrode layer 703 is a metal electrode, it can be formed of, for example, titanium nitride (TiN). The upper electrode layer 703 can form a capacitor with the capacitor dielectric layer 702 and the lower electrode layer 701 both inside and outside the cylindrical structure.In addition, in the edge area of ​​the core area I (i.e., the boundary area of ​​the capacitor hole array), due to the presence of the lateral support layer (i.e., the middle support layer 601 and the top support layer 602), the capacitor dielectric layer 702 and the upper electrode layer 703 both have an uneven sidewall structure, and the uneven sidewall structure corresponds to the middle support layer 601 and the top support layer 602 outside the tubular structure of the lower electrode layer 701, thereby making the portion of the upper electrode layer 703 on the edge area of ​​the core area I (i.e., the boundary area of ​​the capacitor hole array) protrude in the direction away from the lower electrode layer 701 corresponding to the middle support layer 601 and the top support layer 602, making the boundary of the capacitor array in the core area I uneven. Furthermore, in this embodiment, the capacitor dielectric layer 702 and the upper electrode layer 703 extend sequentially to cover the surface of the underlying support layer 600 retained in the peripheral region II. Furthermore, an upper electrode filling layer 704 is also covered on the surface of the upper electrode layer 703. The upper electrode filling layer 704 fills the gaps between the upper electrode layers 703. In other words, the upper electrode filling layer 704 fills the gaps between adjacent tubular structures and covers the structure formed above. Preferably, the material of the upper electrode filling layer 704 includes undoped or boron-doped polysilicon.

[0055] Please refer to Figure 7 The present invention also provides a semiconductor device manufactured using the above-mentioned semiconductor device manufacturing method, comprising: a semiconductor substrate 400, an interlayer dielectric layer 500, and a plurality of contact plugs CT. The semiconductor substrate 400 comprises a core region I, a peripheral region II, and an interface region III located between the core region I and the peripheral region II. A shallow trench isolation structure 400b is formed in the core region I to define each active area AA1, and a shallow trench isolation structure 400a is formed in the interface region III to define the core region I and the peripheral region II. The interlayer dielectric layer 500 is formed on the semiconductor substrate 400 and may be silicon dioxide, silicon nitride, or a low-K dielectric (with a dielectric constant K less than 3). A plurality of contact plugs CT are formed in the interlayer dielectric layer 500 and contact the active areas AA1 of the corresponding core components. No contact plugs are present above some of the active areas AA1 at the boundary of the core region I. In addition, in some embodiments, the contact plugs CT at the boundaries on two opposite sides of the core region I are asymmetrically distributed, for example, the contact plugs at the upper boundary and the lower boundary of the core region I are asymmetrically distributed, and / or, the contact plugs at the left boundary and the right boundary of the core region I are asymmetrically distributed.

[0056] Optionally, the semiconductor device may be a memory device, further comprising a plurality of word lines WL, source and drain regions S / D, bit line contacts (not shown), and a plurality of bit lines BL (not shown). Each word line WL is a buried word line formed in the semiconductor substrate 400 and intersecting the active area AA1. Source and drain regions S / D are formed in the active area AA1 on either side of the word line. Bit line contacts are formed on the drain regions, and each bit line is formed on a corresponding bit line contact and intersecting the word line. The interlayer dielectric layer 500 buries the semiconductor substrate 400, the word lines WL, the source and drain regions S / D, the bit line contacts, and the bit lines. At the boundary of the core region I, at least a portion of the active area between the outermost two bit lines BL is free of contact plugs, and / or (alternatively or both of these) a portion of the active area between at least two word lines WL is free of contact plugs.

[0057] To sum up, in the technical solution of the present invention, the mask combination provided by the present invention is used to define the formation position of the contact plug, so that there is no contact plug above some active areas at the boundary of the core area, while there are contact plugs above other active areas at the boundary of the core area and the active areas inside the core area. Therefore, when the existing process is subsequently used to form the corresponding electrical structure inside and at the boundary of the core area, some electrical structures at the boundary of the core area become virtual structures because there are no contact plugs contacting the active area below them. This can avoid the problem that the manufactured semiconductor device fails to pass relevant tests due to problems with the electrical structure at the boundary of the core area, thereby improving the performance and pass rate of the manufactured semiconductor device.

[0058] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between the various embodiments can be referred to in detail. Furthermore, the above description is merely a description of preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes or modifications made by a person skilled in the art based on the above disclosure are considered to fall within the scope of protection claimed by the technical solution of the present invention.

[0059] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first," "second," and "third" in this specification are used solely to distinguish between components, elements, steps, and the like, and are not used to indicate a logical or sequential relationship between the components, elements, and steps. The term "and / or" herein means either or both.

Claims

1. A mask assembly for making contact plugs, characterized in that: The mask assembly comprises: The first mask has a plurality of parallel first light-shielding stripes, and a first light-transmitting area is formed between two adjacent first light-shielding stripes; The second mask has a plurality of parallel second light-shielding stripes intersecting each first light-shielding stripe, and a second light-transmitting area is formed between two adjacent second light-shielding stripes; a third mask having a light-shielding block and a third light-transmitting area complementary to the light-shielding block, wherein the light-shielding block has a serrated edge facing the center of the third mask, so as to cover at least one first light-shielding stripe at the boundary of the first mask and a portion of the first light-transmitting area nearest to the first light-shielding stripe, and at least two second light-shielding stripes at the boundary of the second mask and a portion of the second light-transmitting area between the two second light-shielding stripes, wherein an overlapping area of ​​the third light-transmitting area, the first light-transmitting area, and the second light-transmitting area serves as an area for forming a contact plug; In which, when defining the formation position of the contact plug by the combination of the first mask plate, the second mask plate and the third mask plate, the jagged edge of the third mask plate is used to mask the active area at the boundary of the core area of ​​the semiconductor device to be manufactured, which is prone to problems, so that no contact plug is formed above it, and at the same time, other active area positions at the boundary of the core area of ​​the semiconductor device to be manufactured are exposed, so that contact plugs are formed above them.

2. The mask assembly according to claim 1, wherein: The shape of the region where the contact plug is formed includes at least one of a circle, an ellipse, a polygon, and a heart.

3. The mask assembly according to claim 1, wherein: The number of the second light-shielding stripes covered by the light-shielding block is 2 to 5 times the number of the first light-shielding stripes covered by the light-shielding block.

4. The mask assembly according to claim 1, wherein: At least one first light-shielding stripe at a boundary of the first mask has a first width, and the remaining first light-shielding stripes have a second width, and the first width is greater than the second width.

5. The mask assembly according to claim 4, wherein: The first width is greater than 1.5 times the second width.

6. The mask assembly according to claim 1, wherein: At least one second light-shielding stripe at a boundary of the second mask has a third width, and the remaining second light-shielding stripes have a fourth width, and the third width is greater than the fourth width.

7. The mask assembly according to claim 6, wherein: The third width is greater than 1.5 times the fourth width.

8. The mask assembly according to claim 1, wherein: The edge of the light shielding block facing the core area is asymmetric.

9. A method for manufacturing a contact plug, characterized in that: The contact plug manufacturing method is manufactured using the mask assembly according to any one of claims 1 to 8, comprising: Providing a semiconductor substrate having a plurality of active areas, and sequentially forming an interlayer dielectric layer and a first mask layer on the semiconductor substrate; Using a process combining photolithography and etching, the pattern on the first mask in the mask assembly is transferred to the first mask layer to form a corresponding plurality of first lines in the first mask layer, wherein each first line corresponds to a corresponding first light-shielding stripe on the first mask, and the grooves between adjacent first lines correspond to corresponding first light-transmitting areas on the first mask and expose the corresponding interlayer dielectric layer; Covering the interlayer dielectric layer and the first mask layer with a second mask layer, and transferring the pattern on the second mask sheet in the mask sheet assembly to the second mask layer using a photolithography-etching process to form a plurality of corresponding second lines, wherein each second line corresponds to a corresponding second light-shielding stripe on the second mask sheet, and the grooves between adjacent second lines correspond to corresponding second light-transmitting areas on the second mask sheet and expose the corresponding first lines and the interlayer dielectric layer in the first light-transmitting areas; Covering the first mask layer, the second mask layer, and the interlayer dielectric layer with a third mask layer, and transferring the pattern on the third mask plate in the mask plate assembly to the third mask layer using a photolithography process, with the remaining third mask layer corresponding to the light shielding block of the third mask plate, and the interlayer dielectric layer exposed by the remaining third mask layer, the first mask layer, and the second mask layer being the area where the contact plug is to be formed; Using the first mask layer, the second mask layer, and the third mask layer as masks, etching the exposed interlayer dielectric layer to form contact holes exposing corresponding active areas; Contact plugs are formed in the contact holes, and bottoms of the contact plugs are in contact with corresponding active regions.

10. A method for manufacturing a semiconductor device, characterized in that: include: The method for manufacturing contact plugs according to claim 9 is used to form contact plugs on a semiconductor substrate having a core region, wherein the bottom of each contact plug contacts the active region of the corresponding core element in the core region.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The core area is a storage area, the core element is a storage transistor, the contact plug is a storage node contact portion, and the manufacturing method of the semiconductor device further includes: forming a lower electrode of a capacitor on the contact plug; forming a capacitor dielectric covering the lower electrode; and An upper electrode of the capacitor is formed on the capacitor dielectric.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The step of providing a semiconductor substrate having a core region includes: Providing a semiconductor substrate having a core region, wherein an active region of a plurality of core elements is formed in the core region; forming a word line in the semiconductor substrate, wherein the word line intersects the active area and overlaps the second line; forming a source region and a drain region in the active regions on both sides of the word line respectively; forming a bit line contact on the drain region; and A bit line is formed on the bit line contact portion, the bit line intersects the word line, and the first line overlaps the bit line.

13. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 10 to 12, characterized in that: include: A semiconductor substrate having a core region formed therein, wherein the core region has an active region of a plurality of core elements; an interlayer dielectric layer formed on the semiconductor substrate; a plurality of contact plugs formed in the interlayer dielectric layer and contacting the active regions of corresponding core components; Wherein, there is no contact plug above a portion of the active area at the boundary of the core area.

14. The semiconductor device according to claim 13, wherein The contact plugs at the boundaries of two opposite sides of the core region are asymmetrically distributed.

15. The semiconductor device according to claim 13, wherein The semiconductor device further includes: a plurality of word lines formed in the semiconductor substrate and crossing the active area; A source region and a drain region are formed in the active region on both sides of the word line; a bit line contact portion formed on the drain region; a plurality of bit lines formed on the bit line contacts, the bit lines intersecting the word lines; The interlayer dielectric layer buries the semiconductor substrate, word lines, source regions, drain regions, bit line contacts and bit lines.

16. The semiconductor device according to claim 15, wherein At the boundary of the core region, there is no contact plug above a portion of the active region between at least two bit lines, and there is no contact plug above a portion of the active region between at least two word lines.

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