An Active-Passive Noise Shaping Successive Approximation ADC

Abstract

The present invention discloses an active-passive noise shaping successive approximation ADC, including DAC capacitor arrays DAC1 and DAC2, an active-passive noise shaping module (including a passive integrator PINT1 and a positive feedback active-passive integrator APINT2), a six-input comparator COMP, a successive approximation logic module SAR, a clock generation module CKG, and a reference voltage generation module BGVG. The present invention uses the simplest MOS transistor common source stage structure in the active-passive noise shaping module, combines a low-gain active amplifier with positive feedback, and consumes only tens of microwatts to obtain good noise shaping characteristics, which can increase the number of effective bits by more than 5 bits on the basis of a traditional successive approximation ADC. The invention can be used in low-power, high-precision analog-to-digital conversion scenarios, such as biomedical signal acquisition, high-precision instrument design and other fields, and has good application prospects.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit design, and in particular to an active-passive noise shaping successive approximation ADC. Background Art

[0002] As the only bridge between the analog and digital worlds, ADC (Analog-to-Digital Converter) plays an important role in communications, aviation, medical and other fields. In view of the characteristics of biomedical signals and the requirements of portability, ADC needs to have the characteristics of high precision and low power consumption. Successive approximation ADC is the best choice in the field of low power consumption and medium precision with its efficient algorithm and ultra-low power dynamic circuit. Oversampling ADC uses oversampling and noise shaping technology to achieve ultra-high precision with medium power consumption and speed. Noise-shaping successive approximation ADC will combine the advantages of both - retaining the low power consumption of successive approximation ADC while using noise shaping to achieve high precision.

[0003] Traditional noise shaping modules can be divided into active and passive types. Passive noise shaping has low power consumption, but its disadvantage is that the noise shaping capability is limited, and it can only increase the effective number of bits by 1 to 2 on the basis of 10-bit successive approximation ADC, which has a poor effect on performance improvement. Active noise shaping can provide a more ideal noise shaping function, which can increase the effective number of bits by more than 5 on the basis of 10-bit successive approximation ADC, but the high gain of the active part makes the power consumption higher. Due to the higher gain requirements, the power consumption is often sub-milliwatt, which is not suitable for portable applications. Summary of the invention

[0004] The present invention aims to solve the problem that the existing active noise shaping circuit has high power consumption and the existing passive noise shaping circuit has weak shaping ability. The present invention combines active noise shaping and passive noise shaping technologies, utilizes low gain and positive feedback, and provides an active-passive noise shaping successive approximation ADC.

[0005] To solve the above problems, the present invention is achieved through the following technical solutions:

[0006] An active-passive noise shaping successive approximation ADC is composed of DAC capacitor arrays DAC1 and DAC2, an active-passive noise shaping module, a six-input comparator COMP, a successive approximation logic module SAR, a clock generation module CKG and a reference voltage generation module BGVG; wherein the active-passive noise shaping module includes a passive integrator PINT1 and a positive feedback active-passive integrator APINT2; a signal input in-phase terminal VINP is connected to a signal input terminal SGI1 of a DAC capacitor array DAC1, and a signal input inverting terminal VINN is connected to a signal input terminal SGI2 of a DAC capacitor array DAC2; the DAC The output terminal DO1 of the capacitor array DAC1 is connected to the non-inverting input terminal RESP of the passive integrator PINT1 and the first non-inverting input terminal P1 of the six-input comparator COMP; the output terminal DO2 of the DAC capacitor array DAC2 is connected to the inverting input terminal RESN of the passive integrator PINT1 and the first inverting input terminal N1 of the six-input comparator COMP; the inverting output terminal PT1ON of the passive integrator PINT1 is connected to the inverting input terminal G2IN of the positive feedback active-passive integrator APINT2 and the second inverting input terminal N2 of the six-input comparator COMP; the non-inverting output terminal PT1OP of the passive integrator PINT1 Connect the non-inverting input terminal G2IP of the positive feedback active-passive integrator APINT2 and the second non-inverting input terminal P2 of the six-input comparator COMP; the non-inverting output terminal AT2OP of the positive feedback active-passive integrator APINT2 is connected to the third non-inverting input terminal P3 of the six-input comparator COMP; the inverting output terminal AT2ON of the positive feedback active-passive integrator APINT2 is connected to the third inverting input terminal N3 of the six-input comparator COMP; the output terminal of the six-input comparator COMP is connected to the input terminal of the successive approximation logic module SAR, and the non-inverting output terminal SARP of the successive approximation logic module SAR is connected back to the DAC The feedback input terminal FBI1 of the capacitor array DAC1 and the inverting output terminal SARN of the successive approximation logic module SAR are connected back to the feedback input terminal FBI2 of the DAC capacitor array DAC2; the digital output bus DOUT is derived from the successive approximation logic module SAR; the global clock signal CLK is connected to the input terminal CK of the clock generation module CKG; the output terminal KFS of the clock generation module CKG is commonly connected to the sampling clock input terminals FS of the DAC capacitor array DAC1 and the DAC capacitor array DAC2; the output terminal KRES of the clock generation module CKG is connected to the residual sampling clock input terminal Φ of the passive integrator PINT1 RES; The output terminal K1 of the clock generation module CKG is respectively connected to the first-order integration clock input terminal Φ1 of the passive integrator PINT1 and the first-order integration clock input terminal Φ1 of the positive feedback active-passive integrator APINT2; the output terminal K2 of the clock generation module CKG is connected to the second-order integration clock input terminal Φ2 of the positive feedback active-passive integrator APINT2; the output terminal KCMP of the clock generation module CKG is connected to the clock input terminal COMPCLK of the six-input comparator COMP; the output terminal BGVCM of the reference voltage generation module BGVG is connected to the common mode voltage input terminal VCM of the passive integrator PINT1; the output terminal BGVB of the reference voltage generation module BGVG is connected to the bias voltage input terminal VB of the positive feedback active-passive integrator APINT2.

[0007] In the above scheme, the passive integrator PINT1 is composed of switches I1~I8 and capacitors C1~C4; one end of the switch I1 forms the in-phase input terminal RESP of the passive integrator PINT1, and the other end of the switch I1 is connected to the upper plate of the capacitor C1 and one end of the switch I3; one end of the switch I2 forms the inverting input terminal RESP of the passive integrator PINT1, and the other end of the switch I2 is connected to the upper plate of the capacitor C2 and one end of the switch I4; one end of the switches I5 and I7 is connected to the lower plate of the capacitor C1; one end of the switches I6 and I8 The other end of switch I7 is connected to the lower plate of capacitor C2; the other end of switch I7 is connected to the upper plate of capacitor C3 to form the inverting output terminal PT1ON of passive integrator PINT1; the other end of switch I8 is connected to the upper plate of capacitor C4 to form the in-phase output terminal PT1OP of passive integrator PINT1; the other ends of switches I3, I4, I5 and I6 form the common mode voltage input terminal VCM of passive integrator PINT1; the control ends of switches I1, I2, I5 and I6 form the residual sampling clock Φ of passive integrator PINT1 RES The control terminals of switches I3, I4, I7 and I8 form the first-order integration clock input terminal Φ1 of the passive integrator PINT1; the lower plates of capacitors C3 and C4 are grounded GND.

[0008] In the above scheme, the positive feedback active-passive integrator APINT2 is composed of resistors R1-R2, PMOS transistors MP1-MP6, switches I9-I12, capacitors C5-C8 and a common-mode feedback module CMFB; the input end of the common-mode feedback module CMFB forms the bias voltage input end VB of the positive feedback active-passive integrator APINT2; the gate of the PMOS transistor MP1 forms the in-phase input end G2IP of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP2 and the drain of the PMOS transistor MP3, and the drain of the PMOS transistor MP1 is connected to one end of the resistor R1 and the drain of the PMOS transistor MP5; The gate of the PMOS transistor MP2 forms the inverting input terminal G2IN of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP1 and the drain of the PMOS transistor MP3, the drain of the PMOS transistor MP2 is connected to one end of the resistor R2 and the drain of the PMOS transistor MP4; the source of the PMOS transistor MP3 is connected to the power supply VDD, the gate of the PMOS transistor MP3 is connected to the output terminal VCMFB of the common mode feedback module CMFB, the drain of the PMOS transistor MP3 is connected to the sources of the PMOS transistors MP1 and MP2; the gate of the PMOS transistor MP4, the upper plate of the capacitor C8 and the switch I12 are connected to the gate of the PMOS transistor MP4. After one end is connected, an inverting output terminal AT2ON of a positive feedback active-passive integrator APINT2 is formed; the source of the PMOS transistor MP4 is connected to the source of the PMOS transistor MP5 and the drain of the PMOS transistor MP6; the drain of the PMOS transistor MP4 is connected to one end of the resistor R2, the drain of the PMOS transistor MP2 and one end of the switch I9; the gate of the PMOS transistor MP5, the upper plate of the capacitor C7 and one end of the switch I11 are connected to form a non-inverting output terminal AT2OP of the positive feedback active-passive integrator APINT2; the source of the PMOS transistor MP5 is connected to the source of the PMOS transistor MP4 and the drain of the PMOS transistor MP6; the gate of the PMOS transistor MP5, the upper plate of the capacitor C7 and one end of the switch I11 are connected to form a non-inverting output terminal AT2OP of the positive feedback active-passive integrator APINT2; the source of the PMOS transistor MP5 is connected to the source of the PMOS transistor MP4 and the drain of the PMOS transistor MP6; The drain is connected to one end of the resistor R1, the drain of the PMOS transistor MP1 and one end of the switch I10; the source of the PMOS transistor MP6 is connected to the power supply VDD, the gate of the PMOS transistor MP6 is connected to the output terminal VCMFB of the common mode feedback module CMFB, and the drain of the PMOS transistor MP6 is connected to the sources of the PMOS transistors MP4 and MP5; the control ends of the switches I9 and I10 form the first-order integration clock input terminal Φ1 of the positive feedback active-passive integrator APINT2; the control ends of the switches I11 and I12 form the second-order integration clock input terminal Φ2 of the positive feedback active-passive integrator APINT2; the other end of the switch I9 is ​​connected to the upper plate of the capacitor C5 and the other end of the switch I11;The other end of the switch I10 is connected to the upper plate of the capacitor C6 and the other end of the switch I12; the other ends of the resistors R1 and R2 and the lower plates of the capacitors C5-C8 are grounded to GND. ;

[0009] Compared with the prior art, the present invention uses the simplest MOS transistor common source structure in the active-passive noise shaping module, combines a low-gain active amplifier with positive feedback, consumes only tens of microwatts to obtain good noise shaping characteristics, and can increase the number of effective bits by more than 5 bits on the basis of the traditional successive approximation ADC. The invention can be used in low-power, high-precision analog-to-digital conversion scenarios, such as biomedical signal acquisition, high-precision instrument design and other fields, and has good application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The overall structure diagram of the active-passive noise shaping successive approximation ADC;

[0011] Figure 2 This is an example diagram of an active-passive noise shaping circuit;

[0012] Figure 3 Successive approximation of ADC duty cycle for active-passive noise shaping;

[0013] Figure 4 Signal flow graph for noise shaping successive approximation ADC;

[0014] Figure 5 The signal flow graph for active-passive noise shaping successive approximation ADC;

[0015] Figure 6 The active-passive noise shaping successively approximates the ADC noise transfer function amplitude-frequency characteristic curve;

[0016] Figure 7 The spectrum diagram of the successive approximation ADC output without the active-passive noise shaping module;

[0017] Figure 8 Figure 2. Spectrum of the active-passive noise shaping successive approximation ADC output. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific examples.

[0019] An active-passive noise shaping successive approximation ADC, such as Figure 1As shown, it consists of DAC capacitor arrays DAC1 and DAC2, an active-passive noise shaping module (including a passive integrator PINT1 and a positive feedback active-passive integrator APINT2), a six-input comparator COMP, a successive approximation logic module SAR, a clock generation module CKG and a reference voltage generation module BGVG.

[0020] The signal input non-inverting terminal VINP is connected to the signal input terminal SGI1 of DAC1, and the signal input inverting terminal VINN is connected to the signal input terminal SGI2 of DAC2. The output terminal DO1 of DAC1 is connected to the non-inverting input terminal RESP of the passive integrator PINT1, and is also connected to the first non-inverting input terminal P1 of the six-input comparator COMP; the output terminal DO2 of DAC2 is connected to the inverting input terminal RESN of PINT1, and is also connected to the first inverting input terminal N1 of the six-input comparator COMP. The inverting output terminal PT1ON of the passive integrator PINT1 is connected to the inverting input terminal G2IN of the positive feedback active-passive integrator APINT2, and is also connected to the second inverting input terminal N2 of COMP; the non-inverting output terminal PT1OP of PINT1 is connected to the non-inverting input terminal G2IP of APINT2, and is also connected to the second non-inverting input terminal P2 of COMP. The non-inverting output terminal AT2OP of APINT2 is connected to the third non-inverting input terminal P3 of COMP; the inverting output terminal AT2ON of APINT2 is connected to the third inverting input terminal N3 of COMP. The COMP output is connected to the successive approximation logic module SAR, the SAR in-phase output SARP is connected back to the feedback input FBI1 of DAC1, and the SAR inverting output SARN is connected back to the feedback input FBI2 of DAC2, forming a complete differential successive approximation structure. The digital output bus DOUT is derived from the successive approximation logic module SAR. The global clock signal CLK is connected to the input CK of the clock generation module CKG, and the output KFS of the clock generation module CKG is connected to the sampling clock input FS of DAC1 and DAC2; the output KRES is connected to the residual sampling clock input Φ of the passive integrator PINT1. RES ; Output K1 is connected to the first-order integration clock input terminal Φ1 of PINT1 and the first-order integration clock input terminal Φ1 of APINT2 respectively; Output K2 is connected to the second-order integration clock input terminal Φ2 of APINT2; Output KCMP is connected to the clock input terminal COMPCLK of the six-input comparator COMP. The output terminal BGVCM of the reference voltage generation module BGVG is connected to the common mode voltage input terminal VCM of the passive integrator PINT1; Output terminal BGVB is connected to the bias voltage input terminal VB of APINT2.

[0021] The active-passive noise shaping module of the present invention, such as Figure 2 As shown, it includes a passive integrator PINT1 and a positive feedback active-passive integrator APINT2.

[0022] The passive integrator PINT1 of the active-passive noise shaping module is composed of eight switches I1-I8 and four capacitors C1-C4. The control terminals of switches I1 and I2 are connected to the residual sampling clock Φ RES , one end of I1 is connected to the residual positive input terminal RESP, the other end of I1 is connected to the upper plate of capacitor C1, and one end of switch I3; one end of I2 is connected to the residual negative input terminal RESN, and the other end is connected to the upper plate of capacitor C2, and one end of switch I4. The other ends of I3 and I4 are connected to the common mode level VCM, and the control end is connected to the first-order integration clock Φ1. The control ends of switches I5 and I6 are connected to Φ RES , one end is connected to the common mode level VCM; the other end of I5 is connected to the lower plate of C1 and one end of switch I7; the other end of I6 is connected to the lower plate of C2 and one end of switch I8. The control ends of I7 and I8 are connected to the second-order integration clock Φ2, the other end of I7 is connected to the upper plate of capacitor C3 and the inverting output port PT1ON of passive integrator PINT1; the other end of I8 is connected to the upper plate of capacitor C4 and the inverting output port PT1OP of passive integrator PINT1. The lower plates of C3 and C4 are connected to the ground GND. The inverting output port PT1ON of passive integrator PINT1 is connected to the inverting input port G2IN of positive feedback active-passive integrator APINT2; the inverting output port PT1OP of passive integrator PINT1 is connected to the inverting input port G2IP of positive feedback active-passive integrator APINT2.

[0023] The positive feedback active-passive integrator APINT2 of the active-passive noise shaping module is composed of two resistors R1-R2, six PMOS transistors MP1-MP6, four switches I9-I12, four capacitors C5-C8 and a common mode feedback module CMFB. The bias voltage VB is input to the common mode feedback module CMFB to generate a common mode feedback output VCMFB. The source of the active gain current source PMOS transistor MP3 is connected to the power supply VDD, the gate is connected to the common mode feedback module output VCMFB, and the drain is connected to the source of MP1 and MP2. The gate of the active gain non-inverting input PMOS transistor MP1 is connected to the non-inverting input terminal G2IP of APINT2, the source is connected to the source of MP2 and the drain of the active gain current source PMOS transistor MP3, and the drain is connected to one end of the load resistor R1 and the drain of the positive feedback input tube MP5; the gate of the active gain inverting input PMOS transistor MP2 is connected to the inverting input terminal G2IN of APINT2, the source is connected to the source of MP1 and the drain of the active gain current source PMOS transistor MP3, and the drain is connected to one end of the load resistor R2 and the drain of the positive feedback inverting input tube MP4. The source of the positive feedback current source PMOS transistor MP6 is connected to the power supply VDD, the gate is connected to the common mode feedback module output terminal VCMFB, and the drain is connected to the sources of MP4 and MP5. The gate of the positive feedback inverting input PMOS transistor MP4 is connected to the upper plate of the second-stage integrating capacitor C8, the source is linked to the source of MP5 and the drain of the positive feedback current source PMOS transistor MP6, and the drain is connected to one end of the resistor R2, the drain of MP2, and one end of the switch I9; the gate of the positive feedback inverting input PMOS transistor MP5 is connected to the upper plate of the second-stage integrating capacitor C7, the source is linked to the source of MP4 and the drain of the positive feedback current source PMOS transistor MP6, and the drain is connected to one end of the resistor R1, the drain of MP1, and one end of the switch I10. One end of the load resistor R1 is connected to the drains of MP1 and MP5, and one end is grounded GND; one end of the load resistor R2 is connected to the drains of MP2 and MP4, and one end is grounded GND. The control ends of switches I9 and I10 are connected to Φ1, the other end of I9 is ​​connected to the upper plate of the second-stage sampling capacitor C5 and one end of I11, and the other end of I10 is connected to the upper plate of the second-stage sampling capacitor C6 and one end of I12. The lower plates of C5 and C6 are connected to the ground GND. The control terminals of switches I11 and I12 are connected to Φ2. The other end of I11 is connected to the upper plate of the second-stage integrating capacitor C7 and the gate of the positive feedback in-phase input PMOS transistor MP5, serving as the in-phase output terminal AT2OP of APINT2; the other end of I12 is connected to the upper plate of the second-stage integrating capacitor C8 and the gate of the positive feedback inverting input PMOS transistor MP4, serving as the inverting output AT2ON of APINT2. The lower plates of C7 and C8 are grounded.

[0024] The active-passive noise shaping successive approximation ADC of the present invention adopts a fully differential structure, which can basically eliminate even harmonics, and compared with the single-ended structure, the overall signal-to-noise ratio can be improved by 3dB. The differential input signal is input to the input terminals VINP and VINN respectively, sampled by the DAC capacitor array, and then input to the comparator in-phase and inverting terminals respectively for comparison, and the comparison result is input to the successive approximation logic module SAR, and the generated control signal is fed back to DAC1 and DAC2 respectively to realize the successive approximation algorithm.

[0025] The present invention performs noise shaping on the example of a ten-bit successive approximation ADC, so eleven cycles are required for successive approximation conversion. After the result of the last bit is fed back to the DAC, what remains in the DAC is the residual voltage of this conversion. The differential residual voltage is input into the first-stage passive integrator PINT1 to generate first-order noise shaping, and then the result of the first-order noise shaping is input into the second-stage positive feedback active-passive integrator APINT2 to generate second-order noise shaping. Then the results of the first-order noise shaping and the results of the second-order noise shaping are provided to the comparator to correct the next conversion.

[0026] The working sequence of active-passive noise shaping successive approximation ADC is as follows Figure 3 As shown. It takes fifteen clock cycles for the ADC to complete a conversion. Since the residual has been differentially sampled to capacitors C1 and C2 at the end of a conversion, the noise shaping module can work simultaneously when the successive approximation ADC samples the signal. This design reduces the number of cycles required for the conversion. The first three cycles are used to sample the input signal, and the active-passive noise shaping module works simultaneously. The first-order and second-order residual integration voltages generated by the previous conversion are input to the comparator to correct the result of this conversion. The next eleven cycles complete the function of the successive approximation ADC. Compared with ordinary successive approximation ADCs, the active-passive noise shaping module needs to sample and convert the residual voltage, and the successive approximation logic needs to output the result once more, so it takes eleven cycles. In the last cycle, the active-passive noise shaping module samples the residual voltage of this conversion.

[0027] The working principle of noise shaping successive approximation ADC is as follows Figure 4 As shown. Since the input signal is sampled, let the input signal be represented as Vin(z) in the z domain, and the voltage generated by the output digital code fed back to the DAC is represented as Dout(z), then the successive approximation conversion residual RES(z) is:

[0028] RES(z)=Vin(z)-Dout(z)

[0029] Assuming the transfer function of the loop filter is H(z), the output of the filter YO(z) is:

[0030] YO(z)=H(z)·RES(z)

[0031] Let the SAR ADC quantization noise be Q(z) and the comparator noise be NCOMP(z), then Dout(z) can be obtained as:

[0032] Dout(z)=Q(z)+NCOMP(z)+Vin(z)+YO(z)

[0033] Substituting YO(z) and RES(z) into the above formula, the output of the entire system is:

[0034]

[0035] The output of the system includes the signal Vin(z) and noise (including comparator noise NCOMP(z) and quantization noise Q(z)). Let the coefficient before the signal be the signal transfer function STF, and the coefficient before the noise be the noise transfer function NTF, then:

[0036] STF=1

[0037] NTF=1 / [1+H(z)]

[0038] It can be seen that the signal is completely retained, and when the gain of H(z) is large enough within the signal bandwidth, the noise within the signal bandwidth will be greatly reduced. At this time, the NTF is similar to a high-pass filter for noise, which can push the noise from low frequency to high frequency, reduce the noise within the signal bandwidth, and increase the effective number of bits.

[0039] The signal flow graph abstracted by the active-passive noise shaping module is as follows: Figure 5 As shown. The NTF of the noise shaping module can be calculated as:

[0040]

[0041] Then we can get the amplitude-frequency characteristic curve of the active-passive noise shaping successive approximation ADC noise transfer function, such as Figure 6 As shown in the figure, within the signal bandwidth of 5KHz, the noise is attenuated by more than -30dB, and the dynamic performance of the ADC output result is greatly improved.

[0042] The positive feedback active-passive integrator APINT2 in the active-passive noise shaping module of the present invention uses the simplest MOS transistor common source stage structure, and utilizes the combination of relatively low gain (less than 20 dB) and positive feedback. In the example, only 50 microwatts are consumed to obtain good noise shaping characteristics. Traditional active noise shaping modules need to provide relatively high gain (often greater than 80 dB) to achieve good noise shaping characteristics, so the active part consumes a lot of power. The power consumption of traditional active noise shaping modules is often in the milliwatt level. In summary, the active-passive noise shaping module of the present invention can greatly reduce power consumption compared to traditional active noise shaping modules.

[0043] Figure 7 To remove the successive approximation ADC output spectrum of the active-passive noise shaping module, Figure 8 The output spectrum of the active-passive noise shaping successive approximation ADC is shown in Figure 2. After comparison, it can be found that when the input signal is the same, the active-passive noise shaping can increase the effective number of bits by nearly 7 bits based on the traditional successive approximation ADC. The present invention uses a simple active amplifier with a lower gain and positive feedback, and in the example, it consumes only 50 microwatts of power consumption to increase the effective number of bits by more than 5 bits.

[0044] It should be noted that the present invention is aimed at the field of integrated circuit design, rather than system design based on existing commercial chips, so there is no model for the integrated circuit sub-module. Figure 2 The values ​​of the resistors and capacitors and the width-to-length ratio of the MOS tube in the example are marked on the figure. In addition, although the embodiments of the present invention described above are illustrative, this is not a limitation of the present invention, and therefore the present invention is not limited to the above specific implementations. Without departing from the principles of the present invention, any other implementations obtained by those skilled in the art under the enlightenment of the present invention are deemed to be within the protection of the present invention.

Claims

1. An active-passive noise shaping successive approximation ADC, characterized in that: It is composed of DAC capacitor arrays DAC1 and DAC2, an active-passive noise shaping module, a six-input comparator COMP, a successive approximation logic module SAR, a clock generation module CKG and a reference voltage generation module BGVG; wherein the active-passive noise shaping module includes a passive integrator PINT1 and a positive feedback active-passive integrator APINT2; The positive feedback active-passive integrator APINT2 is composed of resistors R1-R2, PMOS transistors MP1-MP6, switches I9-I12, capacitors C5-C8 and a common-mode feedback module CMFB; the input end of the common-mode feedback module CMFB forms a bias voltage input end VB of the positive feedback active-passive integrator APINT2; the gate of the PMOS transistor MP1 forms a non-inverting input end G2IP of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP1 is connected to the source of the PMOS transistor MP2 and the drain of the PMOS transistor MP3, and the drain of the PMOS transistor MP1 is connected to the drain of the PMOS transistor MP3. The gate of the PMOS transistor MP2 is connected to one end of the resistor R1 and the drain of the PMOS transistor MP5; the gate of the PMOS transistor MP2 forms the inverting input terminal G2IN of the positive feedback active-passive integrator APINT2, the source of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP1 and the drain of the PMOS transistor MP3, the drain of the PMOS transistor MP2 is connected to one end of the resistor R2 and the drain of the PMOS transistor MP4; the source of the PMOS transistor MP3 is connected to the power supply VDD, the gate of the PMOS transistor MP3 is connected to the output terminal VCMFB of the common mode feedback module CMFB, and the PMOS transistor The drain of MP3 is connected to the source of PMOS transistors MP1 and MP2; the gate of PMOS transistor MP4, the upper plate of capacitor C8 and one end of switch I12 are connected to form the inverting output terminal AT2ON of positive feedback active-passive integrator APINT2, the source of PMOS transistor MP4 is linked to the source of PMOS transistor MP5 and the drain of PMOS transistor MP6, the drain of PMOS transistor MP4 is connected to one end of resistor R2, the drain of PMOS transistor MP2 and one end of switch I9; the gate of PMOS transistor MP5, the upper plate of capacitor C7 and one end of switch I11 are connected After that, the in-phase output terminal AT2OP of the positive feedback active-passive integrator APINT2 is formed, the source of the PMOS transistor MP5 is connected to the source of the PMOS transistor MP4 and the drain of the PMOS transistor MP6, the drain of the PMOS transistor MP5 is connected to one end of the resistor R1, the drain of the PMOS transistor MP1 and one end of the switch I10; the source of the PMOS transistor MP6 is connected to the power supply VDD, the gate of the PMOS transistor MP6 is connected to the output terminal VCMFB of the common mode feedback module CMFB, and the drain of the PMOS transistor MP6 is connected to the sources of the PMOS transistors MP4 and MP5; The control ends of switches I9 and I10 form a first-order integration clock input terminal Φ1 of a positive feedback active-passive integrator APINT2; the control ends of switches I11 and I12 form a second-order integration clock input terminal Φ2 of the positive feedback active-passive integrator APINT2; the other end of switch I9 is ​​connected to the upper plate of capacitor C5 and the other end of switch I11; the other end of switch I10 is connected to the upper plate of capacitor C6 and the other end of switch I12; the other ends of resistors R1 and R2 and the lower plates of capacitors C5-C8 are grounded GND; The signal input in-phase terminal VINP is connected to the signal input terminal SGI1 of the DAC capacitor array DAC1, and the signal input inverting terminal VINN is connected to the signal input terminal SGI2 of the DAC capacitor array DAC2; the output terminal DO1 of the DAC capacitor array DAC1 is connected to the in-phase input terminal RESP of the passive integrator PINT1 and the first in-phase input terminal P1 of the six-input comparator COMP; the output terminal DO2 of the DAC capacitor array DAC2 is connected to the inverting input terminal RESN of the passive integrator PINT1 and the first inverting input terminal N1 of the six-input comparator COMP; The inverting output terminal PT1ON of the passive integrator PINT1 is connected to the inverting input terminal G2IN of the positive feedback active-passive integrator APINT2 and the second inverting input terminal N2 of the six-input comparator COMP; The non-inverting output terminal PT1OP of the passive integrator PINT1 is connected to the non-inverting input terminal G2IP of the positive feedback active-passive integrator APINT2 and the second non-inverting input terminal P2 of the six-input comparator COMP; the non-inverting output terminal AT2OP of the positive feedback active-passive integrator APINT2 is connected to the third non-inverting input terminal P3 of the six-input comparator COMP; the inverting output terminal AT2ON of the positive feedback active-passive integrator APINT2 is connected to the third inverting input terminal N3 of the six-input comparator COMP; the output terminal of the six-input comparator COMP is connected to the input terminal of the successive approximation logic module SAR, the non-inverting output terminal SARP of the successive approximation logic module SAR is connected back to the feedback input terminal FBI1 of the DAC capacitor array DAC1, and the inverting output terminal SARN of the successive approximation logic module SAR is connected back to the feedback input terminal FBI2 of the DAC capacitor array DAC2; the digital output bus DOUT is derived from the successive approximation logic module SAR; the global clock signal CLK is connected to the input terminal CK of the clock generation module CKG; The output terminal KFS of the clock generation module CKG is connected to the sampling clock input terminal FS of the DAC capacitor array DAC1 and the DAC capacitor array DAC2; the output terminal KRES of the clock generation module CKG is connected to the residual sampling clock input terminal Φ of the passive integrator PINT1 RES ; The output terminal K1 of the clock generation module CKG is respectively connected to the first-order integration clock input terminal Φ1 of the passive integrator PINT1 and the first-order integration clock input terminal Φ1 of the positive feedback active-passive integrator APINT2; the output terminal K2 of the clock generation module CKG is connected to the second-order integration clock input terminal Φ2 of the positive feedback active-passive integrator APINT2; the output terminal KCMP of the clock generation module CKG is connected to the clock input terminal COMPCLK of the six-input comparator COMP; the output terminal BGVCM of the reference voltage generation module BGVG is connected to the common mode voltage input terminal VCM of the passive integrator PINT1; the output terminal BGVB of the reference voltage generation module BGVG is connected to the bias voltage input terminal VB of the positive feedback active-passive integrator APINT2.

2. The active-passive noise shaping successive approximation ADC according to claim 1, characterized in that: Passive integrator PINT1 consists of switches I1~I8 and capacitors C1~C4; One end of the switch I1 forms the in-phase input terminal RESP of the passive integrator PINT1, and the other end of the switch I1 is connected to the upper plate of the capacitor C1 and one end of the switch I3; one end of the switch I2 forms the inverting input terminal RESP of the passive integrator PINT1, and the other end of the switch I2 is connected to the upper plate of the capacitor C2 and one end of the switch I4; one end of the switches I5 and I7 are connected to the lower plate of the capacitor C1; one end of the switches I6 and I8 are connected to the lower plate of the capacitor C2; the other end of the switch I7 is connected to the upper plate of the capacitor C3 to form the inverting output terminal PT1ON of the passive integrator PINT1; the other end of the switch I8 is connected to the upper plate of the capacitor C4 to form the in-phase output terminal PT1OP of the passive integrator PINT1; the other ends of the switches I3, I4, I5 and I6 form the common mode voltage input terminal VCM of the passive integrator PINT1; the control ends of the switches I1, I2, I5 and I6 form the residual sampling clock Φ of the passive integrator PINT1 RES The control terminals of switches I3, I4, I7 and I8 form the first-order integration clock input terminal Φ1 of the passive integrator PINT1; the lower plates of capacitors C3 and C4 are grounded GND.

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