Apparatus for improving DPLL stabilization and temperature compensation algorithms using a second open-loop oscillator tuning field

Abstract

A digital phase locked loop has a digitally controlled oscillator having a first coarse tuning field for coarse tuning of an oscillator frequency, a second coarse tuning field for tuning the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected in parallel with the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at startup based on interpolated frequency values ​​obtained prior to startup. A faster settling arrangement has a less complex algorithm.

Description

Technical Field

[0001] The present disclosure relates generally to methods and phase locked loop apparatus, and more particularly to methods and apparatus for frequency stabilization or temperature coverage in a phase locked loop. Background Art

[0002] For phase-locked loop (PLL) circuits, including digital phase-locked loop (DPLL) circuits used in cellular communication systems and connectivity applications, short settling times and wide temperature coverage are preferred.

[0003] A PLL is an electronic circuit that tunes an oscillator so that the oscillator adjusts its output to match a desired frequency and can be used, for example, to demodulate, modulate, or recover a signal. Some currently used digitally controlled oscillators (DCOs) have a coarse tuning (CT) field and a fine tuning (FT) field for tuning the oscillator to a target frequency. The coarse tuning (CT) field is used for coarse frequency setting of the oscillator and can be used for temperature compensation. The coarse tuning field consists of binary switched capacitors, each of which provides a tuning characteristic defined by its integral nonlinearity (INL) 1 / sqrt(LC). The coarse tuning field operates using open-loop operation, which means that the control loop is open. Due to process variations, the capacitors are not perfectly matched. Any mismatch between the capacitors results in discontinuity in the overall tuning characteristics of the coarse tuning field. In order to avoid gaps in the operating frequency, the coarse tuning field is designed to have an overlap in the tuning characteristics of the capacitors to provide a margin for any mismatch caused by process variations. The size of the overlap is different. Due to the overlap in the tuning characteristics, the coarse tuning field can be described as nonlinear.

[0004] The fine tuning (FT) field provides fine adjustment of the oscillator frequency to which the PLL is locked. The fine tuning field is used in closed loop operation, which means that the fine tuning field is driven by the loop filter. The fine tuning field has a more linear tuning characteristic than the coarse tuning field because the fine tuning field has smaller discontinuities in the tuning characteristic. The fine tuning field is thermometer encoded or arranged in an array to achieve linear behavior.

[0005] When applied to oscillators, the term stabilization refers to the time required for the PLL circuit to lock onto a frequency. Two ways in which stabilization has been achieved include a first method that uses a binary successive approximation algorithm that uses a coarse tuning (CT) field in the oscillator for initial DCO (digitally controlled oscillator) frequency setting. The first method requires several frequency measurements during PLL power-up to be effective. The second method uses a fast band selection algorithm that utilizes interpolation in conjunction with up to two frequency measurements during PLL power-up. Both methods have disadvantages because both methods require two or more frequency measurements during PLL power-up, which increases the lock time of the PLL. In other words, the oscillator takes longer to stabilize to the desired frequency.

[0006] Using a phase locked loop device over a certain temperature range can cause other problems. Changes in temperature can cause changes in the operating point of the oscillator. Temperature drifts that occur in the oscillator can be compensated by a FT (fine tuning) field that automatically changes the operating point of the oscillator as the temperature changes. However, the FT (fine tuning) field has a limited range within which the FT can compensate for temperature changes. The range over which the fine tuning field can change the operating point may not be large enough to provide temperature compensation over the entire temperature range over which the device may need to operate.

[0007] To provide an extended temperature range, a so-called temperature extension algorithm is used to switch the CT (coarse tuning) field open loop in such a way that the FT (fine tuning) field is re-centered. The disadvantage of this method is that the algorithm to achieve temperature compensation is very complex due to discontinuities in the CT (coarse tuning) field, requires a lot of memory to operate, and requires laboratory evaluation, which delays chip bring-up. Chip bring-up refers to the process that includes assembly, testing, verification, and debugging in order to achieve manufacturing readiness. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a functional block diagram of a conventional phase-locked loop device;

[0009] Figure 2 is a functional block diagram of a phase-locked loop device according to the method and apparatus of the present invention;

[0010] Figure 3 is a graph showing the variation of the operating point of the fine tuning (FT) field as a result of temperature variation;

[0011] Figure 4 is a graph showing changes in operating characteristics as a result of temperature changes and temperature-induced changes in the corrected operating point as a result of using a complex algorithm or adding a second coarse tuning (CT) field;

[0012] Figure 5 is a graph showing typical CT characteristics, where conventional temperature expansion is used and a complex CT switching algorithm is used to re-center the operating point of the fine-tuned field;

[0013] Figure 6 is a graph showing correction of changes caused by temperature in the absence of discontinuities;

[0014] Figure 7 is a process diagram illustrating the operation of a conventional fast band selection algorithm;

[0015] Figure 8 is a graph showing the steps of the fast band selection process not required by the PLL using the new linear CT field;

[0016] Fig. 9 is a signal diagram showing gate signals and clock signals;

[0017] Fig.10a is a functional block diagram of a counter circuit, and Fig.10b It is a signal diagram of gate signal and latch signal;

[0018] Fig.11 is a circuit diagram of a phase-locked loop circuit including a coarse tuning field and a fine tuning field; and

[0019] Fig.12 is a graph of the tuning characteristics of the coarse tuning field. DETAILED DESCRIPTION

[0020] The method and apparatus of the present invention provide a digital phase-locked loop (DPLL) apparatus that can have a fast settling time for stabilizing an oscillator at a desired frequency. The phase-locked loop apparatus uses two coarse tuning fields and one fine tuning field. Specifically, a nonlinear first coarse tuning (CT1) field and a linear second open-loop coarse tuning (CT2) field connected in parallel with the first coarse tuning (CT1) field are provided. Both tuning fields can be concentrated in one CT field containing a linear portion and a nonlinear portion.

[0021] The second open loop coarse tuning (CT2) field can be used to achieve very fast DPLL settling time by performing a pre-characterization of the CT field before the PLL device is powered on. In some aspects, the pre-characterization can include an interpolation function before the PLL device is powered on. Pre-measurement is performed with a frequency counter. The counter counts oscillator edges within a precisely defined gating period. The gating period is defined, for example, in terms of a reference clock period:

[0022] Tgate=gate / fref

[0023] Resulting in the counter result:

[0024] Cnt_result=fdco*Tgate

[0025] A frequency measurement is performed only once at power-up of the PLL device to determine the frequency error between the frequencies determined by interpolating between the determined measurements used for pre-characterization and the current measurements of the frequency of the received signal obtained during PLL power-up. A second linear open-loop tuning (CT2) field is used to compensate for the error as a result of the measurement.

[0026] Temperature drift compensation is provided in DPLL devices when the FT (fine tuning) field is at its limit due to temperature drift. Temperature compensation is provided by using a second linear open loop tuning (CT2) field for temperature drift compensation after large temperature changes and by re-centering the FT (fine tuning) field after temperature drift compensation by the CT2 field.

[0027] The method and apparatus of the present invention provide a phase locked loop with a much faster lock time and a less complex process to compensate for temperature drift in the oscillator as a result of temperature changes. Only one frequency measurement is required during the DPLL stabilization sequence, which reduces the stabilization time required for the PLL. Providing a second more linear coarse tuning field (in addition to the conventional nonlinear CT field) for temperature compensation and use during stabilization can produce advantages. Compared to conventionally designed DPLLs, the method and apparatus of the present invention enable the use of less complex FW (firmware) algorithms, require less memory usage, require less verification, utilize more robust FW (firmware) algorithms, and require less debugging and allow faster chip startup.

[0028] Referring to the drawings, a conventional digital PLL generally has two tuning fields, a fine tuning (FT) field and a coarse tuning (CT) field. An example of a digital phase-locked loop device 10 is shown in FIG. Figure 1 The reference frequency f REF is provided to a TDC (time-to-digital converter) 12, the output of which is provided to a loop filter 14. The loop filter 14 provides its output to a fine tuning field 16 as part of a digitally controlled oscillator 18. The output of the fine tuning field 16 fine tunes the oscillator to a target frequency and generates an output signal that provides the output of the digitally controlled oscillator (DCO) 18. The output of the DCO is provided as the output of the DPLL 10. The output of the DPLL 10 is provided to the input of an alignment algorithm unit 20. The alignment algorithm unit 20 can include one or more algorithms for processing signals, including, for example, a temperature expansion algorithm, a binary search algorithm, and an interpolation algorithm. The output of the alignment algorithm unit 20 is provided to a coarse tuning field 22 of the digitally controlled oscillator 18. The coarse tuning field 22 provides coarse tuning of the oscillator to the desired frequency. The output of the digitally controlled oscillator 18 is provided to a PLL feedback path 24, the output of which is provided to a second input of the TDC 12.

[0029] The coarse tuning (CT) field 22 is used to center the DCO 18 frequency as well as possible to the desired target frequency in coarse tuning. This is done in a conventional DPLL as an open loop operation in the alignment algorithm unit 20 by performing a binary search algorithm or by performing interpolation between support points predetermined by chip internal measurements (e.g., during the chip boot process). The second tuning field or fine tuning (FT) field 16 is used for closed loop operation and is used to fine tune the oscillator frequency to lock (stabilize) the oscillator at the desired frequency and for controlling the PLL 10.

[0030] A disadvantage of conventional open loop alignment / centering methods is the high nonlinearity of the CT (coarse tuning) field 22. The nonlinearity results in a difference between the target frequency and the DCO 18 output frequency after open loop adjustment. The frequency difference needs to be compensated by the FT field 16. Using the fine tuning (FT) field to compensate for the frequency difference can result in longer PLL lock times. The frequency mismatch and the need to use the fine tuning field to address the frequency mismatch reduces the available adjustment range for other factors that the FT field 16 can address. For example, the fine tuning (FT) field has less available adjustment range for compensating for closed loop temperature drift and for compensating for frequency errors introduced by other algorithms.

[0031] Compared with conventional DPLL, Figure 2 2 shows a digital phase locked loop device 28 according to the method and apparatus of the present invention. The DPLL combines a third tuning field (CT2) 30 with a digitally controlled oscillator 32. The third tuning field is a coarse tuning field, more specifically a second coarse tuning field added to the oscillator, which also includes a fine tuning field 34 and a first coarse tuning field 36. The third tuning field 30 can be used to improve (reduce) the locking time of the DPLL, can be used to extend the temperature compensation, and thus can maximize the usable operating range of the FT field. The DPLL 28 is otherwise similar to Figure 1 A conventional DPLL 10 is shown, and the same description applies to like numbered components. The DPLL device can be implemented using hardware, software, firmware, or a combination thereof. Reference to a DPLL device or DPLL apparatus does not limit the DPLL to hardware implementations.

[0032] In certain aspects, the numerically controlled oscillator 32 has two coarse tuning (CT) fields 30 and 36 that can have the following characteristics:

[0033] The first coarse tuning (CT1) field 36 may be a non-linear field operable to cover the total frequency range of the DCO (digitally controlled oscillator) 32 with a coarse step size.

[0034] The second coarse tuning (CT2) field can be a linear field that can operate to eliminate residual frequency errors during initial alignment and compensate for extended temperature drift. The second coarse tuning (CT2) field can have a much smaller tuning range than the first coarse tuning (CT1) field because it can operate to compensate for small frequency deviations during the locking process and compensate for temperature drift.

[0035] In some examples, the first coarse tuning field can have a range of 1 GHz, the second coarse tuning field can have a range of 300 MHz, and the fine tuning field can have a range of 40 MHz. In some examples, the fineness of the steps of CT2 is between the coarse steps of CT1 and the fine steps of FT.

[0036] Go to Figure 3 , a graph 40 of frequency of a digitally controlled oscillator (DCO) as a function of fine tuning (FT) field operation shows a first operating curve 42 at a first operating temperature. The DCO operates at a frequency as indicated by horizontal line 44. The intersection of the DCO frequency with the operating curve 42 at the first operating temperature produces a first operating point 46. In this example, the operating temperature changes, such as as a result of a change in the ambient temperature of the DPLL device or as a result of a change in heating of the device components providing the DPLL device. The new temperature produces a new operating curve 48. In order to maintain the same DCO frequency, the FT value is shifted to the new operating point 50.

[0037] The fine tuning (FT) field has an operating range that can compensate for temperature changes. Figure 3 , the operating range of the fine tuning field is indicated by limit lines 52 and 54. The temperature change indicated by the operating curve 48 has resulted in a new operating point 50 very close to the limit 54 of the range of the fine tuning field. At 54, further temperature changes or other compensations in the right hand direction of the reference graph will risk causing the fine tuning field to exceed its operating range. For temperature drifts greater than the limits 52 and 54, the PLL will not lock.

[0038] Figure 4A graph 58 of DCO frequency versus fine tuning field is shown. The graph shows a shift in the operating point which can be caused by using a complex algorithm as used in conventional systems, or can be caused by the second coarse tuning field CT2. The DPLL operates at a first temperature according to an operating curve 42. Temperature changes that would cause the operating curve to shift to the operating curve 48 in a conventional DPLL instead cause the operating curve to shift to an adjusted operating curve 60. The adjusted operating curve 60 provides an adjusted operating point 62 at the DCO frequency on the horizontal line 44. The CT switching can be the result of a complex algorithm by switching CT1. However, a simpler solution is to provide the CT switching as a result of switching the second coarse tuning field CT2. The adjusted operating curve 60 and the resulting adjusted operating point 62 are the result of coarse tuning switching (CT switching) using the second coarse tuning (CT2) field. The adjusted operating point 62 is at a position further away from the limits 52 and 54 of the fine tuning field. The fine tuning field has a greater ability to compensate for temperature changes and other factors than if the operating point were at an operating point 50 close to the operating limit 54 .

[0039] For temperature coverage, changes in temperature cause the DCO characteristics to drift. To compensate for this effect in conventional DPLLs, when the PLL is stable, it will be re-centered to a new operating point via a second DCO tuning field (FT) in closed-loop mode. The PLL automatically sets a new operating point when it is locked. Using only a fine-tuned FT field to cover a wide temperature range will result in a large fine tuning range for the oscillator, which will make the DCO design requirements more stringent.

[0040] In practice, the actual solution used in conventional DPLL devices is to provide tracking of the fine tuning field. If the tuning value reaches a certain threshold, a complex algorithm is triggered which changes the coarse tuning (CT) value in such a way that the fine tuning value is re-centered again. The disadvantage of using this algorithm is that the coarse tuning field is very non-linear, having several discontinuities in the characteristics. Furthermore, the discontinuities can vary throughout the process. This leads to a complex algorithm, since the algorithm for CT correction must take into account all non-linearities and discontinuities.

[0041] exist Figure 5The handling of discontinuities during the re-centering process is shown in the graph 80 in . The figure shows the change in frequency with coarse tuning (CT). The discontinuity in the tuning field operation is apparent from the discontinuity from line 82 to line 84. For example, as the coarse tuning changes along line 84 until it reaches operating point 86, it jumps to operating point 90 as shown by arrow 88. Since the DCO frequency will decrease and not increase as expected, operating point 90 is disabled and the target operating point will be 94. The correction algorithm assumes a linear CT characteristic to define a certain number of CT values. For example, the algorithm requires 10 CT values ​​to re-center the FT field. In a linear CT field, 10 CT values ​​will result in an increase in frequency. If there is overlap, these 10 CT steps can result in a decrease in frequency, so no correction is made and the problem becomes worse.

[0042] Definition: ΔCT = CT_actual + CT_step - CT_overlap. An example of a correction algorithm that can be used to change the coarse tuning value is described in US Patent No. 8,890,635. Adjustments are performed during gaps in transmit operations.

[0043] According to the method and device of the present invention, a third tuning field (CT2) is provided as a linear second open-loop tuning field. With the second open-loop tuning field, the complexity of the correction algorithm can be significantly reduced, because the temperature compensation algorithm does not have to take into account nonlinear effects. A linear correction of temperature changes is also linear, which is possible with low complexity.

[0044] For example, Figure 6 A graph 100 of frequency versus CT2 is shown with an operating curve 102. The change from operating point 104 to operating point 106 according to arrow 108 follows the same operating curve 102. The re-centering of operating point 104 to point 106 occurs without discontinuities. Simplified processing is provided during the re-centering process.

[0045] The gradient of the third linear tuning field (CT2) can be determined by pre-measurement before the PLL is powered on.

[0046] exist Fig. 9 , a frequency diagram of a gate signal 140 is shown, which defines a defined gating period within which reference clock periods 142 are counted. Fig.10a As shown, a numerically controlled oscillator 144 has an output that provides a clock signal to a gate 146 and then to an asynchronous counter 148 that provides a count value. The counter result is proportional to the frequency. Pre-measurement is performed using a frequency counter 148. Counter 148 counts oscillator edges 142 within a precisely defined gating period 140. The gating period 140 is defined based on a reference clock period:

[0047] Tgate=gate / fref

[0048] Resulting in a counter result proportional to the oscillator frequency

[0049] Cnt_result = fdco*gate / fref

[0050] exist Fig.10b In FIG. 1 , the gate signal 150 has a reference duration, at the end of which the latch signal 152 is generated.

[0051] Similar to the FT field, the second CT field can be characterized by Fig.10a The asynchronous counter structure shown in performs a certain number of frequency measurements (eg, 3 measurements taking into account quadratic nonlinearity).

[0052] The method and apparatus of the present invention also provide an improvement in fast frequency band selection (FBS). A solution for fast frequency band selection in a conventional device is shown in the patent application number US 2016 / 0182065 A1 published in the United States.

[0053] The FBS (Fast Band Selection) algorithm is based on two steps

[0054] 1) In the first FW (firmware) or HW (hardware) intensive step, a certain number of DCO frequency measurements are made for different CT values ​​to characterize the DCO CT behavior. This is done for each DCO core individually. During PLL configuration, the FW uses those CT measurements to solve the inverse problem of finding the CT value at which the DCO operates as close to the target frequency as possible by interpolation. To reduce PLL lock time, the characterization step is performed during the chip boot phase.

[0055] 2) In a second HW (hardware) intensive step performed during the PLL locking process (i.e., PLL power-up), the residual frequency error is further reduced by performing up to two frequency measurements in open loop. The measured frequency is compared to the target frequency, and a CT step is calculated starting from the delta frequency, which is used to reduce the initial frequency error. For the CT step calculation, a suitable approximation of the CT gradient in the lab (on a chip sample) is required. The measured frequency difference is then used to improve the CT setting starting from step 1. A suitable approximation of the CT gradient in the lab (on a chip sample) is required so that the correction step can reduce the residual error.

[0056] Mainly depending on the CT step size, but also on the CT overlap, temperature variations and measurement uncertainties as well as the signal processing itself, the residual frequency error after step 2 can still be in the range of several MHz, resulting in a frequency stabilization process when closing the control loop.

[0057] According to the method and apparatus of the present invention, by introducing a third (small) tuning field (CT2) having better integral and differential nonlinearity than that provided by the CT1 field, a more accurate adjustment of the DCO frequency in step 2, now acting on the third tuning field, can be achieved.

[0058] Therefore, the following advantages are obtained:

[0059] 1) The CT2 field can be characterized in the same way as the FT field (the gain of the field is determined from two frequency measurements).

[0060] 2) Since the CT2 field shows no overlap, the method and apparatus avoids a possible second frequency measurement in step 2, such as Figure 7 This reduces the timing budget considered by the FBS during the locking process and reduces the complexity of the step 2 algorithm since overlap does not have to be considered.

[0061] 3) The gradient of the linear third tuning field can also be characterized on-chip and applied to the HW (hardware) algorithm to improve the correction accuracy.

[0062] 4) Lower residual error will result in lower control loop stability after closing the loop, thus reducing lock time.

[0063] Go to Figure 7 , a flowchart 100 of a fast band selection algorithm as described in, for example, US 2016 / 0182065A1, published in the United States, begins at the start of fast band selection 102. At 104, the digitally controlled oscillator is powered on with an initial coarse tuning value. At 106, a frequency divider (which can be an adjustment divider or an asynchronous frequency divider (ADIV)) performs a frequency measurement with a gate time FBS_GATE1. At 108, the measured frequency value is compared with the target frequency value. At 110, a correction value calculation is performed. As indicated at 112, a firmware (FW) algorithm is used. The corrected CT value is set at 114. At 116, it is determined whether the set value and the mask value are different from the initial CT value and the mask value. If not, the fast band selection ends at 118. For example, a mask is used to detect overlaps, and the mask gives the number of bits considered: for example, for a 14-bit CT vector using the 5MSBs, this would give: FBS_MASK = '11111000000000'.

[0064] If the determination at 116 finds that the set values ​​are different, then at 120, a frequency measurement is made with the gate time FBS_GATE2. At 122, the measured value is compared to the target value to find the offset. At 124, a second correction value is calculated, and at 126, it is determined whether the second correction value is different compared to the initial CT value and the first correction value. If the second correction value is different, then at 128 the CT value is set to the second correction value, and the process ends at 118. If not, the process ends at 118.

[0065] Figure 8 1 is a graph 130 showing an algorithm branch that can be removed in the absence of CT overlap. Specifically, graph 130 shows the change in frequency stepping with CT. In the absence of overlap, a transition from the CT value shown at 132 to the next CT value at 134 occurs, as indicated by arrow 136.

[0066] Fig.11 An example of a conventional oscillator 160 having a single weighted fine tuning field 164 and a binary weighted coarse tuning field 166 is provided. Fig.12 Shows Fig.11 Graph of tuning characteristic 162 of a coarsely tuned CT field. The discontinuity is apparent in characteristic 162. By incorporating a second CT field with a smaller tuning range but a more linear characteristic, the algorithmic overhead and problems that arise when temperature compensation is performed by CT words near the region of the discontinuity can be avoided.

[0067] The tuning of the CT1, CT2 and FT fields can be considered to act on the DCO frequency alone. Fig.11 It is apparent that both the CT field and the FT field are connected to the same electrical node in the resonant circuit.

[0068] The methods and apparatus of the present invention provide various aspects. In a first aspect, an oscillator for a phase-locked loop, the oscillator comprising: a nonlinear first coarse tuner, the nonlinear first coarse tuner being configured to receive an input signal having frequency information, provide a coarse frequency setting, and be capable of operating in an open-loop operation; a second coarse tuner, the second coarse tuner being coupled in parallel with the first coarse tuner, and being configured to receive the input signal, and perform a change to an operating point of the oscillator or compensate for a frequency offset; a fine tuner, the fine tuner being configured to receive the input signal, provide a fine adjustment of the frequency of the oscillator, and be capable of operating in a closed-loop operation; and an oscillator output terminal, the oscillator output terminal being configured to output a signal having a frequency determined by the first coarse tuner, the second coarse tuner, and the fine tuner.

[0069] In a second aspect, according to the oscillator of the first aspect, the first coarse tuner comprises a first tuning range, the second coarse tuner comprises a second tuning range, and the second tuning range is smaller than the first tuning range.

[0070] In a third aspect, an oscillator according to the first aspect, wherein the first coarse tuner is configured to set the frequency of the oscillator at a first frequency interval, and wherein the second coarse tuner is configured to set the frequency of the oscillator at a second frequency interval, and the second frequency interval is smaller than the first frequency interval.

[0071] In a fourth aspect, an oscillator according to the first aspect, wherein the fine tuner is configured to compensate for temperature drift of the oscillator within a first temperature range; and wherein the second coarse tuner is configured to re-center the operating point of the fine tuner within a second temperature range, and the second temperature range is wider than the first temperature range.

[0072] In a fifth aspect, according to the oscillator of the first aspect, the second coarse tuner is configured to re-center the tuning frequency of the fine tuner.

[0073] In a sixth aspect, according to the oscillator of the first aspect, the first coarse tuner and the second coarse tuner are separate tuning fields.

[0074] In a seventh aspect, according to the oscillator of the first aspect, the first coarse tuner and the second coarse tuner are corresponding nonlinear and linear parts in a single coarse tuning field.

[0075] In an eighth aspect, according to the oscillator of the first aspect, the second coarse tuner is configured to perform a pre-characterization before the phase locked loop is powered on.

[0076] In a ninth aspect, according to the oscillator of the eighth aspect, the pre-characterization includes interpolation.

[0077] In a tenth aspect, the oscillator according to the eighth aspect further includes: a frequency counter, wherein the frequency counter is configured to count the reference clock signal within a gate period.

[0078] In an eleventh aspect, according to the oscillator of the tenth aspect, the frequency counter is configured to receive a gate signal defining the gate period.

[0079] In a twelfth aspect, according to the oscillator of the eighth aspect, the first coarse tuner, the second coarse tuner and the fine tuner are configured to output the signal at the oscillator output terminal due to a single frequency measurement after power-on of the phase-locked loop.

[0080] In a thirteenth aspect, according to the oscillator of the first aspect, the oscillator is configured to output a signal based on an alignment algorithm.

[0081] In a fourteenth aspect, according to the oscillator of the thirteenth aspect, the alignment algorithm includes at least one of a temperature expansion algorithm, a binary search algorithm, and an interpolation algorithm.

[0082] In a fifteenth aspect, a phase-locked loop device, the phase-locked loop device comprising: a time-to-digital converter, the time-to-digital converter having a first input terminal, the first input terminal being configured to receive an input signal and generate a time-to-digital converter output signal; a loop filter, the loop filter being configured to generate a filtered output signal based on the time-to-digital converter output signal; a digitally controlled oscillator, the digitally controlled oscillator being configured to generate a phase-locked loop output signal based on the filtered output signal; a feedback path, the feedback path being coupled between the output terminal of the digitally controlled oscillator and the second input terminal of the time-to-digital converter; wherein the digitally controlled oscillator comprises: a first coarse adjustment a coarse tuner configured to provide a coarse frequency setting of the oscillator and capable of operating in an open-loop operation, wherein the first coarse tuner is nonlinear; a second coarse tuner coupled in parallel with the first coarse tuner and configured to perform a change to an operating point of the oscillator or compensate for a frequency offset, wherein the second coarse tuner is linear; a fine tuner configured to provide a fine adjustment of the frequency of the oscillator and capable of operating in a closed-loop operation; and an oscillator output terminal configured to output a signal having a frequency determined by the first coarse tuner, the second coarse tuner and the fine tuner.

[0083] In the sixteenth aspect, the phase-locked loop device according to the fifteenth aspect further includes: a frequency measurer, which is configured to perform a single open-loop frequency measurement after the phase-locked loop is powered on to compensate for any frequency mismatch using the second coarse tuner; wherein the oscillator is also configured to stabilize at a frequency after the single frequency measurement after the phase-locked loop is powered on.

[0084] In the seventeenth aspect, a method for setting the frequency of an oscillator, the method comprising: setting a first coarse frequency of the oscillator based on the frequency of a reference signal by a nonlinear open-loop first coarse tuner; determining a first error between the first coarse frequency and the frequency of the reference signal by a linear second coarse tuner; changing an operating point of the oscillator based on the first error; measuring a second error by a closed-loop fine tuner; and setting the frequency of the oscillator based on the second error.

[0085] In an eighteenth aspect, the method according to the seventeenth aspect further includes: compensating for temperature changes of the oscillator by the second coarse tuner.

[0086] In a nineteenth aspect, the method according to aspect seventeen further includes: interpolating the frequency value before the phase-locked loop is powered on to obtain an interpolated frequency; powering on the phase-locked loop; determining the frequency measurement of the reference signal when the phase-locked loop is powered on to obtain a measured frequency; determining a measurement error between the interpolated frequency and the measured frequency; and compensating for the measurement error by the second coarse tuner.

[0087] In a twentieth aspect, a method according to aspect seventeen is provided, wherein the first coarse tuner determines the first coarse frequency setting at a first frequency interval; wherein the second coarse tuner determines the second coarse frequency setting at a second frequency interval smaller than the first frequency interval; and wherein the fine tuner determines the fine frequency setting at a third frequency interval smaller than the second frequency interval.

[0088] Although the foregoing has been described in conjunction with exemplary aspects, it should be understood that the term "exemplary" is intended only as an example, rather than the best or optimal. Therefore, the present invention is intended to cover alternatives, modifications, and equivalents that can be included within the scope of the present invention.

[0089] Although specific aspects are illustrated and described herein, it will be understood by those skilled in the art that the specific aspects shown and described may be replaced with a variety of alternative and / or equivalent implementations without departing from the scope of the present application. This patent application is intended to cover any modified or variant forms of the specific aspects discussed herein.

Claims

1. An oscillator for a phase-locked loop, the oscillator include: a non-linear first coarse tuner configured to receive an input signal having frequency information, provide a coarse frequency setting, and be operable in an open loop operation; a second coarse tuner coupled in parallel with the first coarse tuner and configured to receive the input signal and perform a change in an operating point of an oscillator or compensate for a frequency offset, wherein the first coarse tuner and the second coarse tuner are respective nonlinear and linear portions of a single coarse tuning field; a fine tuner configured to receive the input signal, provide fine adjustment of the frequency of the oscillator, and be operable in a closed loop operation; and An oscillator output configured to output a signal having a frequency determined by the first coarse tuner, the second coarse tuner, and the fine tuner.

2. The oscillator of claim 1, wherein the first coarse tuner has a first tuning range and the second coarse tuner has a second tuning range, the second tuning range being smaller than the first tuning range.

3. The oscillator of claim 1 , wherein the first coarse tuner is configured to set the frequency of the oscillator at a first frequency interval, and wherein the second coarse tuner is configured to set the frequency of the oscillator at a second frequency interval, the second frequency interval being smaller than the first frequency interval.

4. An oscillator according to claim 1, wherein the fine tuner is configured to compensate for temperature drift of the oscillator in a first temperature range; and wherein the second coarse tuner is configured to re-center the operating point of the fine tuner in a second temperature range, the second temperature range being wider than the first temperature range.

5. The oscillator of claim 1, wherein the second coarse tuner is configured to re-center the tuning frequency of the fine tuner.

6. The oscillator of claim 1, wherein the first coarse tuner and the second coarse tuner are separate tuning fields.

7. The oscillator of claim 1, wherein the second coarse tuner is configured to perform a pre-characterization before the phase locked loop is powered on.

8. The oscillator of claim 7, wherein the pre-characterization comprises interpolation.

9. The oscillator according to claim 7, further comprising: include: A frequency counter is configured to count the reference clock signal in gate cycles.

10. The oscillator of claim 9, wherein the frequency counter is configured to receive a gate signal defining the gate period.

11. The oscillator of claim 7, wherein the first and second coarse tuners and the fine tuner are configured to output the signal at the oscillator output as a result of a single frequency measurement after power-up of a phase locked loop.

12. The oscillator of claim 1, wherein the oscillator is configured to output a signal based on an alignment algorithm.

13. The oscillator of claim 12, wherein the alignment algorithm comprises at least one of a temperature expansion algorithm, a binary search algorithm, and an interpolation algorithm.

14. A phase-locked loop device, the phase-locked loop device include: a time-to-digital converter having a first input configured to receive an input signal and to generate a time-to-digital converter output signal; a loop filter configured to generate a filtered output signal based on the time-to-digital converter output signal; a numerically controlled oscillator configured to generate a phase-locked loop output signal based on the filtered output signal; a feedback path coupled between an output of the digitally controlled oscillator and a second input of the time-to-digital converter; The digital controlled oscillator comprises: a first coarse tuner configured to provide a coarse frequency setting of the oscillator and operable in an open loop operation, wherein the first coarse tuner is non-linear; a second coarse tuner coupled in parallel with the first coarse tuner and configured to perform a change in an operating point of the oscillator or to compensate for a frequency offset, wherein the second coarse tuner is linear, wherein the first coarse tuner and the second coarse tuner are respective nonlinear and linear portions of a single coarse tuning field; a fine tuner configured to provide fine adjustment of the frequency of the oscillator and operable in a closed loop operation; and An oscillator output configured to output a signal having a frequency determined by the first coarse tuner, the second coarse tuner, and the fine tuner.

15. The phase-locked loop device according to claim 14, wherein the phase-locked loop device further comprises: include: a frequency measurer configured to perform a single open-loop frequency measurement after the phase-locked loop is powered up to compensate for any frequency mismatch using the second coarse tuner; The oscillator is further configured to stabilize at a frequency after a single frequency measurement after powering up the phase-locked loop.

16. A method for setting the frequency of an oscillator, the method include: setting a first coarse frequency of the oscillator based on the frequency of a reference signal by a nonlinear open-loop first coarse tuner; determining, by a linear second coarse tuner, a first error between the first coarse frequency and a frequency of the reference signal; changing an operating point of the oscillator based on the first error; as well as setting, by a closed-loop fine tuner, a frequency of the oscillator based on a second error indicating a frequency difference between the operating point and a target frequency, Wherein, the first coarse tuner and the second coarse tuner are respective nonlinear and linear parts of a single coarse tuning field.

17. The method according to claim 16, further comprising: include: Temperature variations of the oscillator are compensated by the second coarse tuner.

18. The method according to claim 16, further comprising: include: interpolating the frequency value before the phase-locked loop is powered on to obtain an interpolated frequency; Powering on the phase-locked loop; determining a frequency measurement of the reference signal when the phase locked loop is powered on to obtain a measured frequency; determining a measured error between the interpolated frequency and the measured frequency; and The measured error is compensated by the second coarse tuner.

19. The method according to claim 16, wherein the first coarse tuner determines the first coarse frequency setting at a first frequency interval; wherein the second coarse tuner determines a second coarse frequency setting at a second frequency interval that is smaller than the first frequency interval; and Wherein the fine tuner determines a fine frequency setting at a third frequency interval that is smaller than the second frequency interval.

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