Control method and system for preventing current reversal in a rectifier of a switching converter

Abstract

Embodiments of this disclosure relate to a control method and system for preventing reverse current in the rectifier of a switching converter. A method for controlling synchronous rectifier transistors in a switching converter includes: sensing the drain-to-source voltage across each synchronous rectifier transistor during each switching half-cycle of the switching converter; calculating, for each synchronous rectifier transistor, an average of the sensed drain-to-source voltages over N previous switching half-cycles; and sensing a load current transient in the switching converter based on the sensed drain-to-source voltage for each synchronous rectifier transistor and the calculated average of the sensed drain-to-source voltages for each synchronous rectifier transistor over N previous switching half-cycles.

Description

Technical Field

[0001] This disclosure generally relates to control methods for rectifiers in switching converters, and more specifically to preventing or reducing current reversal in synchronous rectifiers of synchronous switching converters. Background Technology

[0002] Resonant converters are a large class of forced-switching converters characterized by the presence of a half-bridge or full-bridge circuit topology. For example, in a half-bridge version, the switching elements include a high-side transistor and a low-side transistor connected in series between the input voltage and ground. By conveniently switching the two transistors, a square wave with a high value corresponding to the supply voltage and a low value corresponding to ground can be generated.

[0003] A square wave generated by the half-bridge is applied to the primary winding of a transformer via a resonant circuit, which includes at least one capacitor and an inductor. The secondary winding of the transformer is connected to a rectifier circuit and a filter to provide an output DC voltage according to the frequency of the square wave.

[0004] Currently, one of the most widely used resonant converters is the LLC resonant converter. This name comes from the fact that this resonant circuit uses two inductors (L) and one capacitor (C). A schematic circuit of an LLC resonant converter is shown in... Figure 1 As shown, the LLC resonant converter includes a half-bridge of MOSFET transistors M1 and M2 coupled between the input voltage Vin and ground GND. M1 and M2 have corresponding body diodes Db1 and Db2, and the half-bridge is driven by driver circuit 3. A common terminal between transistors M1 and M2 is connected to a resonant network 2, which includes a series of first inductors Lr, second inductors Lm, and capacitors Cr. Inductor Lm is connected in parallel with transformer 10, which includes a secondary winding connected to the parallel capacitor Co and to resistor Rout through rectifier diodes D1 and D2. The output voltage Vo of the resonant converter is the voltage across the parallel capacitor Co and resistor Rout, while the output or load current Io / Iload flows through resistor Rout.

[0005] These resonant converters are characterized by high conversion efficiency (>95% is easily achievable), the ability to operate at high frequencies, and low EMI (electromagnetic interference) generation.

[0006] In existing types of converter circuits, such as in the case of AC-DC adapters for laptop computers, high conversion efficiency and high energy density are desired. LCC resonant converters are currently the best converters to meet these expectations. However, the maximum achievable efficiency is limited by losses in the rectifier on the secondary side of the converter, which account for more than 60% of the total losses.

[0007] To significantly reduce losses connected to the secondary rectifier, "synchronous rectification" technology is used, in which rectifier diodes (e.g., Figure 1 D1 and D2 are replaced by power MOSFETs. Power MOSFETs have a suitably low on-resistance R. dson This results in a voltage drop across each MOSFET that is significantly lower than the voltage drop across each rectifier diode D1, D2. These power MOSFETs are driven in a manner functionally equivalent to rectifier diodes D1, D2. This synchronous rectification technique is widely used in conventional converters (especially flyback and forward converters), and commercially available dedicated integrated control circuits exist for this technique. This synchronous rectification technique is also utilized in resonant converters (especially LLC converters) to improve the efficiency of such converters.

[0008] Figure 2 It shows Figure 1 The converter, except that the rectifier diodes D1 and D2 have been replaced by a synchronous rectification circuit. In this case, two synchronous rectifier transistors SR1 and SR2 are present in place of the rectifier diodes D1 and D2, and are appropriately driven by two signals G1 and G2 generated by the synchronous rectifier driver 80. In this specification, transistors SR1 and SR2 are referred to as synchronous rectifier transistors or synchronous rectifier transistors. Transistors SR1 and SR2 are connected between the center tap terminal of the center-tapped secondary winding and ground GND, while a parallel capacitor Co and a resistor Rout are provided between the rectifier output node OUTN and ground GND, and the output node OUTN is coupled to the other terminal of the center-tapped secondary winding. From a high-level functional point of view, Figure 2 Synchronous rectifier circuit system and in Figure 1 There is no difference between the rectifier circuit systems formed by rectifier diodes D1 and D2.

[0009] Transistors SR1 and SR2 have corresponding body diodes Dbr1 and Dbr2, both of which are driven by synchronous rectifier driver 80. The output voltage Vo of the resonant converter is the voltage across the parallel capacitor Co and resistor Rout, while the output current Io / Iload flows through resistor Rout. In this specification, when multiple given components exist, components are generally referred to by a letter followed by a number, such as transistors SR1 and SR2 and body diodes Dbr1 and Dbr2. Furthermore, when referring to a specific component in this specification, both the letter and the number (e.g., SR1, SR2) will be used, while when referring to all or any components, only the letter (e.g., SR and Dbr) will be used.

[0010] In operation, transistors SR1 and SR2 are driven in such a way that they are alternately switched on by the synchronous rectifier driver 80 at a certain frequency. When the body diodes Dbr1 and Dbr2 of one of the transistors SR1 and SR2 begin to conduct, the corresponding transistor is switched on, and when the current approaches zero, the transistor is switched off. In this way, using transistors SR1 and SR2 results in a lower voltage drop compared to using diodes D1 and D2, thereby reducing the power dissipation of the rectifier circuit system.

[0011] In particular, such as in Figure 3 As shown, the operation is divided into three phases, labeled in the accompanying figures by letters enclosed in circles: Phase A, Phase B, and Phase C. Phase A is activated when the drain-to-source voltage Vdvs between the drain and source terminals of one of the transistors SR1 and SR2 (e.g., transistor SR1) falls below the threshold voltage VTH1, and the associated body diode Dbr1 begins to conduct. Phase A is activated when the voltage Vdvs drops to the turn-on threshold voltage VTH1. TH_on Below or below the turn-on threshold voltage V TH_on At that time, during a fixed delay period T PD_on Then, assume that the voltage Vdvs is maintained at the on-threshold voltage V TH_on Below, transistor SR1 is turned on by synchronous rectifier driver 80.

[0012] After transistor SR1 is turned on, operation in stage B begins, and the voltage Vdvs has a value of Vdvs = -Rdson × Isr, where R... dson This is the on-resistance of transistors SR1 and SR2, and Isr is the synchronous rectifier current flowing through the electrical path between the center tap CT of the transformer secondary winding and ground GND. In this specification, this on-resistance may alternatively be referred to as R. dson and R DS(on) (That is, Rdson = R) DS(on) ).

[0013] When the voltage Vdvs is higher than the second threshold voltage V TH-OFF At this time, the current Isr through the transistor approaches zero, operation in stage C begins, and transistor SR1 is turned off by the synchronous rectifier driver 80. Then, as in Figure 3As shown in the diagram, the corresponding body diode Dbr1 turns on again, and the voltage Vdvs across transistor SR1 becomes further negative. Because the positive ISR1 is still flowing, but now flowing through the body diode Dbr1, in response to transistor SR1 turning off, the voltage Vdvs becomes further negative, and when the transistor is on, there is a voltage drop across the body diode that is larger than the voltage drop across the source and drain (Rdson × Isr). Then, the voltage Vdvs... Figure 3 The voltage Vdvs changes as shown and begins to increase, and stage C ends when the voltage Vdvs reaches the threshold voltage VTH2. Once the voltage Vdvs reaches the threshold voltage V... TH_ON The synchronous rectifier driver 80 turns on transistor SR2, and the operations in stages A, B, and C, as just described for transistor SR1, occur on transistor SR2.

[0014] The actual voltage Vdvs depends on the parasitic elements on the source and drain terminals of transistors SR1 and SR2, as well as the parasitic elements of the conductive traces or paths on the printed circuit board (PCB) from the drain terminals of transistors SR1 and SR2 to the corresponding drain terminals of transformer 10. Specifically, the voltage Vdvs depends on the parasitic inductances Lsource and Ldrain associated with the source and drain terminals of transistors SR1 and SR2, and the parasitic inductance Ltrace of the conductive path from the PCB from transistors SR1 and SR2 to the corresponding drain terminals of the secondary winding of transformer 10. Therefore, due to these parasitic inductances, the actual drain-to-source voltage for each transistor SR1 and SR2 is... Therefore, this parasitic or stray inductance Lstray or L SR (LSR = Lsource + Ldrain + Ltrace) makes the actual sensed voltages Vdvs1 and Vdvs2 across each transistor SR1 and SR2 different from the transresistance R presented by the transistor. dson The ideal voltage drop, which is denoted as Vdvs-ideal in the following description.

[0015] As in Figure 4 The parasitic inductance L shown in the figure SR The presence of this causes transistors SR1 and SR2 to turn off undesirably and prematurely, as illustrated by the stray inductance L. SR The actual drain-to-source voltage Vdvs is taken into account, along with the ideal drain-to-source voltage Vdvs. This results in the remaining on-time T of the body diode Dbr1 or Dbr2. diode The increase caused such as Figure 4The efficiency loss indicated by time LE is due to the higher voltage drop across the body diodes Dbr1 or Dbr2 during the longer duration of time LE. Transistor SR1 is turned off at time t1 instead of time t2, where (t2-t1) = LE, resulting in a remaining on-time T of the body diode Dbr1. diode This undesirable increase. For example, the typical actual remaining conduction time T of body diodes Dbr1 and Dbr2. diode It can be on the order of 1 microsecond, while the typical expected remaining conduction time T diode Approximately 60 nanoseconds.

[0016] There are known techniques to prevent transistors SR1 and SR2 from turning off prematurely, thereby improving converter efficiency. One approach is to use a method between the synchronous rectifier driver 80 and transistors SR1 and SR2, and in... Figure 5 An RC filter is added before the transformer 10 shown to compensate for the time delay caused by the parasitic inductance LSR. This compensation for the parasitic inductance LSR... SR The RC filter approach offers a simple architecture with low cost in terms of silicon area and good performance. Furthermore, the efficiency of this solution depends on the remaining on-time T of the body diodes Dbr1 and Dbr2. diode The remaining conduction time T diode It also depends on the on-resistance of transistors SR1 and SR2, the parasitic elements (Lsource, Ldrain) of the transistors and the parasitic elements (Ltrace) of the printed circuit board to which the transistors are connected, the temperature, and the slew rate of the current flowing through the transistors.

[0017] Another approach already used to compensate for parasitic inductance LSR is called adaptive turn-off control algorithms. In this approach, the idea is to utilize the anticipation or leading nature of the actually measured or sensed drain-to-source voltage Vdvs, which is caused by the parasitic inductance LSR relative to the ideal drain-to-source voltage. This is in... Figure 5 As seen in the previous text, the actual induced voltage, as defined above, is... Where LSR = (Ldrain + Lsource + Ltrace). The effect of parasitic inductance LSR is, for example, in... Figure 4As illustrated in the diagram, the actual sensed voltage Vdvs does not correspond to the ideal drain-source voltage Vdvs of the transistor SR. This actual sensed voltage Vdvs leads or precedes the ideal drain-source voltage Vdvs-ideal, meaning that, in time, the zero-crossing of the actual sensed voltage occurs earlier than the actual zero-crossing of the ideal drain-source voltage. The adaptive turn-off control algorithm utilizes the actual voltage Vdvs and detects its zero-crossing, measuring the remaining on-time of the body diode Dbr for the transistor SR. The algorithm then increases the programmable turn-off delay cycle-by-cycle relative to the detected zero-crossing to minimize the remaining on-time T of the body diode Dbr. diode This reduces the power losses of the resulting diodes, thereby improving the converter's efficiency. An adaptive turn-off control algorithm is described in more detail in U.S. Patent No. 9,356,535, which is incorporated herein in its entirety unless inconsistent with the specific teachings and definitions set forth herein. However, regardless of whether control is achieved through an adaptive turn-off control algorithm or other types of control algorithms, there is a need for improved control of the synchronous rectifier switches in synchronous resonant switching converters. Summary of the Invention

[0018] One aspect of this disclosure is a control device for a rectifier in a switching converter, which prevents the reversal or "current reversal" of the current through the synchronous rectifier transistors of the rectifier when the resonant converter experiences transients in the load current supplied by the resonant converter. Attached Figure Description

[0019] To better understand this disclosure, preferred embodiments of the disclosure will now be described by way of non-limiting example and with reference to the accompanying drawings, in which:

[0020] Figure 1 It is a diagram of an LLC-type resonant converter with a center-tapped secondary winding based on existing technology, and the rectification of the output current by means of a diode;

[0021] Figure 2 It is a diagram of an LLC-type resonant converter with a center-tapped secondary winding based on existing technology, and the rectification of the output current by means of a synchronous rectifier.

[0022] Figure 3 It shows the flow through Figure 2 The current waveform of the transistor in the rectifier, and the drain-to-source voltage of the transistor;

[0023] Figure 4 It shows the flow through Figure 2 The waveform of the current of a transistor in the rectifier, where the transistor is turned off prematurely;

[0024] Figure 5 This illustrates a filter with parasitic elements, an RC compensation filter, and a bypass diode. Figure 2 The transistors of the rectifier;

[0025] Figure 6 This is a block diagram of a switching converter according to a preferred embodiment of the present disclosure, the switching converter including control devices for a rectifier of the switching converter;

[0026] Figure 7 It is a time-varying waveform of the drain-source voltage of a transistor in a prior art synchronous rectifier.

[0027] Figure 8 Is Figure 6 A schematic representation of a synchronous rectifier transistor in a rectifier, including a stray inductance associated with the transistor.

[0028] Figure 9 This shows the stray inductance pair Figure 8 Signal timing diagram showing the effect of the turn-off time of the synchronous rectifier transistor;

[0029] Figure 10 The diagram illustrates the generation control. Figure 8 Functional block diagram of the adaptive turn-off control algorithm in the gate drive signal of the synchronous rectifier transistor.

[0030] Figure 11A and Figure 11B It is a signal timing diagram, and the map it is drawn on shows the reference. Figures 8 to 10 The operation of the described adaptive shutdown control algorithm;

[0031] Figures 12A to 12C This is a signal timing diagram illustrating the operation of the adaptive shutdown control algorithm over multiple consecutive switching half-cycles.

[0032] Figure 13A and Figure 13B The diagram shows the reverse current of the synchronous rectified current through the synchronous rectifier transistor, where the switching converter experiences a current transient from full load to zero load.

[0033] Figure 14 It shows plots of three different values ​​of the lead time as a function of the switching frequency of the switching converter, along with a signal timing diagram of the actual lead time.

[0034] Figure 15 Is Figure 14 Signal timing diagram showing the difference between the actual advance time as a function of the switching frequency and its linear approximation;

[0035] Figures 16A to 16CThis is a signal timing diagram illustrating how changes in advance time caused by changes in switching frequency lead to current reversal in the context of an adaptive shutdown control algorithm.

[0036] Figures 17A to 17F This is a signal timing and function diagram according to an embodiment of the present disclosure, illustrating a method for controlling... Figure 6 The current reverse prevention control algorithm for the operation of the rectifier of the switching converter is used to prevent current reverse even in the presence of load current transients.

[0037] Figure 18 This is a functional block diagram illustrating a threshold calculation circuit for a current reverse prevention control algorithm according to an embodiment of the present disclosure; and

[0038] Figure 19 This is a functional block diagram of an embodiment of the compensator of FIG17 according to an embodiment of the present disclosure. Detailed Implementation

[0039] Embodiments of this disclosure relate to current reverse prevention control algorithms for rectifiers in resonant converters (such as LLC resonant converters), which, as will be described in more detail below, prevent current reversal or "current inversion" through the synchronous rectifier transistors of the resonant converter when the resonant converter experiences a high-to-low transient in the load current. Embodiments of this disclosure can be used in conjunction with adaptive turn-off control algorithms, but may also be used in conjunction with other methods for controlling the synchronous rectifier transistors of the resonant converter. These embodiments utilize the actual drain-to-source voltage Vdvs(t) across each synchronous rectifier transistor SR, as discussed above, which will affect the associated stray inductance L SR This is taken into account, where the actual voltage Vdvs(t) is compared to a threshold, as will be described in more detail below, which is calculated periodically based on the sensed values ​​of the voltage Vdvs(t) over N previous cycles. This approach compensates for the switching frequency ω of the switching converter. sw The change in the actual drain-to-source voltage Vdvs(t) as a function of the actual drain-to-source voltage. Recall the drain-to-source voltage... And therefore due to the stray inductance L SR The component of the resulting drain-to-source voltage Vdvs(t) As the switching frequency ω sw The value of the drain-to-source voltage Vdvs(t) varies as a function of the switching frequency, as will be described in more detail below, and further makes the value of the drain-to-source voltage Vdvs(t) a function of the switching frequency. In the equations contained herein, the stray inductance L... SR It can be represented as LSR.

[0040] As described above, the embodiments of this disclosure are not limited to those used in conjunction with adaptive shutdown control algorithms. However, the embodiments described herein are to be described in conjunction with adaptive shutdown control algorithms to provide a better understanding of the embodiments of this disclosure and exemplary implementations. Therefore, a brief description of the adaptive shutdown control algorithm will be provided first before discussing the embodiments of this disclosure in more detail. As mentioned above, the adaptive shutdown control algorithm is described in detail in U.S. Patent No. 9,356,535, and that patent is incorporated herein by and through in its entirety, without any inconsistency with the specific teachings and definitions set forth herein.

[0041] Reference Figure 6 According to one embodiment of the present disclosure, the control circuit 7 of the rectifier 5 of a switching converter 100 is shown. The switching converter 100 includes a power switching circuit system comprising a power switching circuit block 1 powered by a DC voltage, and the power switching circuit block 1 is configured to generate a square wave with a certain frequency under the control of a first driver 20. For example, the power switching circuit block 1 may have a half-bridge or full-bridge circuit topology (typically MOSFET transistors), but other power switching circuit blocks may be equivalently applicable. The power switching circuit system of the switching converter 100 also includes an impedance 30 connected to the primary winding of a transformer 4, wherein the converter is adapted to provide an output or load current Io / Iload to a load (in Figure 6 (Not shown in the image). In Figure 6 In the embodiment, the switching converter 100 is an LLC resonant converter, and the impedance 30 is a resonant circuit. Although this document will describe the control circuit 7 as executing a current reverse prevention control algorithm combined with an adaptive turn-off control algorithm to control the turn-off of synchronous rectifier transistors SR1 and SR2, the control circuit can also implement other turn-off control methods combined with current reverse prevention control algorithms to control the turn-off of transistors SR1 and SR2.

[0042] The square wave generated by the power switching circuit block 1 is applied to the resonant circuit 30, which is tuned to the fundamental frequency of the square wave. In this manner, due to the selective frequency characteristics of the resonant circuit 30, the resonant circuit primarily responds to the fundamental frequency component and responds to higher harmonics to a negligible degree. Therefore, the cyclic power can be modulated by changing the frequency of the square wave while maintaining a constant duty cycle of 50%, and, depending on the configuration of the resonant circuit 30, the current and / or voltage associated with the power flow will have a sinusoidal pattern, or a sinusoidal pattern at intervals.

[0043] A resonant circuit 30 is coupled to a transformer 4, which includes a primary winding L1 and a center-tapped secondary winding L2. A rectifier 5, comprising at least transistors SR1 and SR2, is coupled to the center-tapped secondary winding L2 of the transformer 4. Preferably, the rectifier 5 includes a pair of transistors SR1 and SR2, each having a drain terminal connected to corresponding terminals of two portions of the center-tapped secondary winding L2, and a source terminal connected to a ground reference GND. The center-tapped CT of the secondary winding L2 is then connected to a filter 6, which supplies the output or load current Io / Iload and the output voltage Vo to a load (not shown) coupled to the filter. The filter 6 can be a typical parallel connection of capacitors and resistors. Similar to... Figure 1 The prior art rectifier configuration shown preferably comprises two MOSFET transistors SR1, SR2 having corresponding body diodes Dbr1, Dbr2 and having an appropriate low on-resistance Ron, such that the drain-to-source voltage drop across each transistor is significantly lower than the voltage drop across the diode.

[0044] Control circuit 7 controls rectifier 5 by synchronously driving transistors SR1 and SR2 using two control signals GD1 and GD2. Control signals GD1 and GD2 are applied to the control terminals of transistors SR1 and SR2, respectively, to control their switching. Control circuit 7 receives the drain-to-source voltages Vdvs1 and Vdvs2 of transistors SR1 and SR2 as inputs, and generates two control signals GD1 and GD2 for transistors SR1 and SR2 based on these voltages. Currents ISR1 and ISR2 are... Figure 6 The direction shown (i.e., the flow to the output node OUTN of converter 100) is defined as positive. A set of additional signals and other timing parameters used by control circuit 7 are described below.

[0045] The control circuit 7 includes a drive circuit 11 that provides control signals GD1 and GD2 to transistors SR1 and SR2, and preferably includes a prediction comparator circuit 10. The drive circuit 11 receives the output signal of the detection circuit 103, which receives the drain-to-source voltage Vdvs1 or Vdvs2 of transistors SR1 and SR2.

[0046] The detection circuit 103 is configured to detect when the drain-to-source voltages Vdvs1 and Vdvs2 exceed a voltage threshold Vth_on, and to provide an output signal ON_COMP in response to the drain-to-source voltages Vdvs1 and Vdvs2 reaching the Vth_on threshold. The voltage threshold Vth_on has a value related to the threshold voltages of the body diodes Dbr1 and Dbr2 of transistors SR1 and SR2. In one embodiment, the detection circuit 103 includes a first comparator circuit configured to provide the output signal ON_COMP as an output pulse signal that begins in response to the drain-to-source voltages Vdvs1 and Vdvs2 becoming less than a fixed voltage threshold Vth_on, and ends in response to the drain-to-source voltages Vdvs1 and Vdvs2 increasing and reaching the same fixed voltage threshold Vth_on. The detection circuit 103 is also configured to detect zero-crossing events of the drain-source voltages Vdvs1 and Vdvs2 of transistors SR1 and SR2, and to provide an output signal ZCD in response to the detection of such zero-crossing events. To provide the ZCD signal, in one embodiment, the detection circuit 103 includes a second comparator circuit configured to provide an output pulse as the zero-crossing signal ZCD in response to the drain-source voltages Vdvs1 and Vdvs2 crossing a zero voltage level (i.e., a reference level grounded GND in one embodiment).

[0047] The switching cycle SW of the switching converter 100 consists of two switching half-cycles SC1 and SC2. For example, in... Figure 7 As seen in the signal diagram, each switching half-cycle SC1, SC2 of the switching converter 100 alternately involves one transistor of transistors SR1, SR2, and specifically, each half-cycle SC1, SC2 begins when the drain-to-source voltages Vdvs1, Vdvs2 are equal to the threshold VTH1, and ends when the drain-to-source voltages Vdvs1, Vdvs2 reach the threshold VTH2. Now refer to Figure 6 and Figure 7 Transistor SR1 operates (i.e., is turned on) during the first half-cycle SC1 of the switching cycle SW, while transistor SR2 operates (i.e., is turned on) during the second half-cycle SC2 of the switching cycle SW. For example, in Figure 7As shown, for these voltages and currents, the drain-to-source voltages Vdvs1, Vdvs2 and the currents ISR1, ISR2 of MOSFET transistors SR1 and SR2 vary over time, as will be described in more detail below with reference to Figures 11 and 12. The correlation between current ISR2 and voltage Vdvs2 during half-cycle SC2 is the same as the correlation between current ISR1 and voltage Vdvs1 during half-cycle SC1. Each switching cycle SW includes a first half-cycle and a second half-cycle SC1, SC2 of converter 100, and therefore includes the alternating switching on and off of transistors SR1, SR2. Thus, each switching half-cycle SC1, SC2 of converter 100 involves activating one of transistors SR1, SR2, and specifically each half-cycle SC1, SC2 begins in response to the drain-to-source voltages Vdvs1, Vdvs2 becoming equal to a first threshold VTH1, and ends in response to the same drain voltage Vdvs1, Vdvs2 reaching a second threshold Vth2. For example, in one application, where the switching cycle corresponds to a switching frequency of 100 kHz, each half-cycle of half-cycles SC1 and SC2 is equal to 5 microseconds (i.e., a 10-microsecond switching cycle).

[0048] As mentioned above, these are collectively referred to as stray inductance L. SR The presence of parasitic inductances Ldrain, Lsource, and Ltrace determines the undesirable premature turn-off T of transistors SR1 and SR2. off It occurs in, for example Figure 4 The actual drain-to-source voltage Vdvs (i.e., Vdvs1 or Vdvs2) and the desired or ideal voltage Vdvs-ideal are shown at time t1. Due to the high voltage drop across the body diodes Dbr1 and Dbr2, this increases the remaining conduction time T of the body diodes Dbr1 and Dbr2. diode This leads to a loss of efficiency, which is in Figure 4 The duration LE is indicated in the figure. For example, the remaining on-time T of a typical startup diode. diode It can be on the order of 1 microsecond (i.e., duration LE), while for an ideal drain-to-source voltage Vdvs-ideal, the typical expected residual conduction time of the body diode is on the order of 60 nanoseconds.

[0049] In embodiments of this disclosure, at the beginning of the switching cycle SW, and particularly at the beginning of the switching half-cycles SC1, SC2, wherein as previously referenced Figure 6 As discussed, transistors SR1 and SR2 are turned on, and the control circuit 7 according to an embodiment of the present disclosure is configured to set a new turn-off time T for transistors SR1 and SR2 at the beginning of the switching half-cycle SC1 and SC2. off1As described in more detail in U.S. Patent No. 9,356,535, which is previously incorporated herein, the new turn-off time T off1 It is configured such that the turn-off time immediately precedes a large time interval T1 of the zero-crossing event with respect to the drain-to-source voltage Vdvs1. The new turn-off time T... off1 It has a fixed value, preferably a percentage of half-cycles SC1 and SC2. The new turn-off time T off1 The appropriate turn-off time T should be selected to take into account the gate drive discharge time of transistors SR1 and SR2 before they are fully turned off, as well as other additional factors. off1 It can be equal to 70% of the switching half-cycles SC1 and SC2, but other suitable percentages can also be used to set the turn-off time T. off1 .

[0050] Adaptive turn-off control and alternating control algorithms for controlling the rectifier circuitry in synchronous switching converters provide sufficient control over the converter. However, in many applications, transients in the load current Iload can lead to inadequate control. Transients in the load current Iload can occur, for example, when a load is connected to or disconnected from the switching converter during operation, such as when the switching converter is part of the power supply for electronic devices (e.g., laptops or smartphones). Large or high load current transients cause changes in the regulated output voltage Vo, which are then compensated for by the switching converter's control circuitry to maintain the desired value of the output voltage Vo. The control circuitry adjusts the switching frequency of the switching converter in response to transients in the load current Iload and the resulting changes in the output voltage Vo. As the switching frequency increases or decreases depending on whether the transient causes an increase or decrease in the load current Iload, the adaptive turn-off control algorithm continues to turn off the synchronous rectifier transistor SR using the last value of a programmable turn-off delay.

[0051] This operation of the adaptive turn-off control algorithm, responding to transients in the load current Iload, may cause the synchronous rectifier transistor SR to be turned off after the current Isr crosses zero, potentially leading to current inversion in the switching converter. Current inversion occurs when the synchronous rectifier current Isr through the synchronous rectifier transistor SR reverses direction or "reverses" before the synchronous rectifier controller turns it off. Current inversion should be avoided because when the current Isr reverses direction, i.e., becomes negative, and is in direct contact with... Figure 2When the current flows in the opposite direction to the positive direction shown in the diagram, the negative current Isr flows from the rectifier output node OUTN to ground GND, thereby discharging the rectifier output node. This discharge of the output node OUTN wastes the charge supplied to the rectifier output node and reduces the efficiency of the converter. As those skilled in the art will understand, in addition to reducing the efficiency of the switching converter, current reversal can also lead to the failure or malfunction of the switching converter, and should therefore be avoided for these additional reasons.

[0052] In operation, the adaptive shutdown control algorithm advantageously employs stray inductance L SR The advance effect, namely the stray inductance Ltrace associated with the printed circuit board (PCB) trace coupled to the transistor SR, and the stray inductances Lsource and Ldrain of the transistor SR package, will now be referred to Figure 8 and Figure 9 Let's discuss this in more detail. Figure 8 It is the transistor SR and the associated stray inductance L SR A schematic representation. Ideal drain-to-source voltage Vdvs-ideal (see...) Figure 4 ) is in Figure 8 The voltage at node d is given by the equation, while the actual drain-to-source voltage Vdvs(t) is the voltage at node d', i.e., the ideal voltage Vdvs-ideal(-R). dson x I SR Adding stray inductance L SR voltage Figure 9 The diagram illustrates the ideal voltage Vdvs-ideal and the actual voltage Vdvs(t). Figure 9 In the diagram, the vertical axis represents voltage, and the horizontal axis represents time. Parasitic inductance L SR The impact in Figure 9 The diagram shows that the actual or practical voltage Vdvs(t) is advanced or ahead of the ideal voltage Vdvs-ideal in time. This causes the zero-crossing of the actual voltage Vdvs(t) to occur before the zero-crossing of the ideal voltage Vdvs-ideal. In the context of this specification, the term "zero-crossing" is used to mean a point indicating that the voltage Vdvs-ideal or Vdvs(t) is close to zero, and therefore corresponds to... Figure 9 The image shown by the horizontal dashed line, and as previously referenced Figure 4 The threshold V discussed TH-OFF Actual voltage V DVS This advance or lead characteristic of (t) is achieved by using a zero-crossing comparator (see...). Figure 6 The detector 103 is utilized in the adaptive shutdown algorithm. In this way, the adaptive shutdown control algorithm controls the current I passing through the transistor.SR It functions to turn off transistor SR before it reaches zero or becomes negative (i.e., before the current reverses).

[0053] In operation, during each switching half-cycle SC, the adaptive turn-off control algorithm initially sets the estimated turn-off time Toff for the corresponding transistor SR that is active during that half-cycle. The remaining on-time T of the body diode Dbr of transistor SR is also considered. diode It is then measured to determine whether the conduction time is less than a time threshold T. th1 As long as the remaining conduction time T of the body diode Dbr... diode Greater than the time threshold T th1 The algorithm then progressively increases the programmable delay PD of the turn-off time Toff of transistor SR cycle by cycle, and measures the on-time Tdiode of transistor body diode Dbr again. As the programmable delay PD progressively increases, in Figure 9 The zero-crossing of the actual voltage signal Vdvs(t) shifts from time t1 towards time t2, corresponding to the zero-crossing of the ideal voltage Vdvs-ideal. This shift in the zero-crossing point of the actual voltage Vdvs(t) is progressively increased with the programmable delay PD. Figure 9 This is illustrated by arrow 900. Therefore, the adaptive turn-off control algorithm progressively increases the programmable delay PD of the turn-off time Toff of transistor SR until the measured on-time T of the transistor's body diode Dbr is reached. diode It is approximately equal to the conduction time T of the body diode Dbr for the ideal voltage Vdvs-ideal. diode-ideal Therefore, the time threshold T th1 Corresponding to the conduction time T diode-ideal The programmable delay PD is progressively adjusted to delay the turn-off of the transistor SR until the actual turn-on time T. diode Approximately equal to the ideal conduction time T diode-ideal , which corresponds to in Figure 9 The zero-crossing of the actual voltage Vdvs(t) occurs at time t2. In this way, the adaptive turn-off control algorithm uses the stray inductance time T... LSTRAY To adjust the actual turn-off time Toff of transistor SR, such as in Figure 9 The stray inductance time T shown in the figure is... LSTRAY This corresponds to the time interval from time t1 to time t2.

[0054] As just referenced Figure 8 and Figure 9 The operation of the described adaptive shutdown control algorithm is in Figure 10The functional diagram is shown. The actual voltage Vdvs(t) is compared with a threshold VTH-OFF, which is represented as a comparator in the diagram, and an initial gate drive signal GD' is generated when Vdvs(t) = VTH-OFF is detected. The initial gate drive signal GD' is then delayed using a programmable delay PD as described above to generate a delayed gate drive signal GD', which is then provided by the driver DRV as the actual gate drive signal GD, which is used to control the switching of the synchronous rectifier transistor SR. The programmable delay PD is progressively adjusted (i.e., increased or decreased) to delay the turn-off of the transistor SR until the actual on-time T of the body diode Dbr of the transistor SR. diode Approximately equal to the ideal conduction time, as mentioned above, the body diode Dbr in the absence of stray inductance L SR (L SR In the case of (Lsource + Ldrain + Ltrace), the ideal on-time will be achieved.

[0055] Figure 11A and Figure 11B It is a signal timing diagram, and its plot is shown in the reference above. Figures 8 to 10 The operation of the aforementioned adaptive shutdown control algorithm. In Figure 11A The diagram shows the voltage Vdvs and current ISR of one of the synchronous rectifier transistors SR during a half-cycle SC, during which the transistor is turned on and then off. Figure 11B The gate drive signal GD is shown, which is controlled by the control circuit 7 ( Figure 6 An application is made to turn on transistor SR at time t1' to begin half-cycle SC, and to initially turn it off at time t1, and then turn it off at progressively delayed times relative to time t1 until the turn-off of transistor SR occurs at time t2. Time t2 corresponds to the desired turn-off time of transistor SR, meaning it is the turn-on time T of the body diode Dbr of transistor SR. diode It is equal to as in Figure 11A The ideal conduction time T indicated in the figure diode-ideal The time. In Figure 11A In the diagram, the vertical axis represents voltage or current (V / I), i.e., voltage Vdvs and current I. SR The horizontal axis represents time t. Similarly, in Figure 11B In the diagram, the vertical axis represents voltage V, while the horizontal axis represents time t.

[0056] As in Figure 11BAs seen, the gate drive signal GD initially goes low at time t1 to turn off transistor SR. Then, the adaptive turn-off control algorithm compares the voltage Vdvs(t) with the threshold V... TH-OFF The on-time of the body diode Dbr is measured, as described in more detail in U.S. Patent No. 9,356,535. The algorithm measures the on-time T after the initial turn-off at time t1. diode At that time, the algorithm determines the conduction time T. diode Is it greater than time T? diode-ideal (T diode >T diode-ideal If so, the algorithm adds a progressive delay T to the initial shutdown time at time t1. step Therefore, the new shutdown time Toff = (Toff1 + T step The algorithm uses a progressive delay T for each half-cycle SC of the switching converter 100. step The off-time Toff is continuously increased. This algorithm performs this operation for each half-cycle SC1, SC2, wherein the off-time Toff of transistor SR1 is controlled, measured, and adjusted in the first half-cycle SC1, and the off-time Toff of transistor SR1 is controlled, measured, and adjusted in the second half-cycle SC2. This specification describes the operation of the adaptive turn-off control algorithm for one half-cycle SC, and is applicable to the control of each transistor in transistors SR1 and SR2 during half-cycles SC1 and SC2, respectively.

[0057] Figure 11B The diagram illustrates the operation of an adaptive turn-off control algorithm that progressively delays the gate drive signal GD from time t1 to time t2, at which time the on-time T... diode Approximately equal to the ideal conduction time T diode-ideal (T diode =T diode-ideal Each vertical dashed line represents the position at the corresponding time step T. step Add the turn-off time Toff to the previous turn-off time Toff, where the algorithm adds a progressive delay D to each half-cycle SC. step To provide a new shutdown time Toff. In other words, programmable delay PD ( Figure 10 The progressive delay D is achieved through each half-cycle SC. step Adjust progressively to reduce the conduction time T. diode The programmable delay PD in Figure 11B This is represented by an arrow PD pointing to the right between times t1 and t2. For example, in... Figure 11B As shown in the diagram, reducing the on-time T of the body diode Dbr of transistor SR. diode To minimize the conduction time T diodeUntil (T) diode =T diode-ideal This also corresponds to maximizing the on-time of the SC transistor SR in each half-cycle.

[0058] The above reference Figures 8 to 1 The description of the adaptive turn-off control algorithm in section 1 neglects the gate discharge time of the transistor SR, as well as additional factors associated with the actual operation of the transistor. In short, each transistor SR requires a finite amount of time to turn off and therefore will not immediately turn off completely in response to the gate drive signal GD. Therefore, the actual deactivation of the gate drive signal GD occurs before the desired turn-off time of the transistor SR to compensate for the gate discharge time and other factors to ensure that the transistor is fully turned off at the desired turn-off time, as described in more detail in U.S. Patent No. 9,356,535.

[0059] Figures 12A to 12C These are signal timing diagrams illustrating the operation of the adaptive shutdown control algorithm over multiple consecutive switching half-cycles (SC). In each of these diagrams, the horizontal axis represents time t, and the vertical axis represents current I and voltage V, where current I... SR The voltage Vdvs signal is shown in each signal diagram. Each switching half-cycle SC is labeled separately: in Figure 12A The initial half-cycle CYCLE[0] shown in the figure, in Figure 12B The second half of the cycle CYCLE[1] is shown, and in Figure 12C The nth half-cycle CYCLE[n] is shown in the figure. The ideal voltage V of the controlled transistor SR is... dvs-ideal exist Figures 12A to 12C The middle part is shown as a dashed line. Figure 12A During the half-cycle CYCLE[0], the zero-crossing of the actual voltage Vdvs(t) is detected, and in response to the detection of the zero-crossing of the actual voltage Vdvs(t), the zero-crossing detection signal ZCD is activated at time t1. In response to the ZCD signal becoming active at time t1, the control circuit 7( Figure 6 This deactivates the gate drive signal GD of the corresponding transistor SR, which is controlled during half-cycle CYCLE[0], as also shown in the figure. The case of half-cycle CYCLE[0] corresponds to the control circuit 7 controlling the rectifier 5 ( Figure 6 The initial operation of transistor SR in the adaptive turn-off control algorithm begins by delaying the gate drive signal GD to reduce the on-time T of the body diode Dbr of transistor SR. diode Before.

[0060] exist Figure 12BDuring half-cycle CYCLE[1], the adaptive turn-off control algorithm delays the gate drive signal GD by a first delay T relative to the gate drive signal in cycle CYCLE[0]. DEL_OFF Therefore, delay T DEL_OFF This is the first incremental or step delay added to the gate drive signal GD to reduce the on-time T of the body diode Dbr of transistor SR as described above. diode Therefore, during the initial half-cycle CYCLE[0], the programmable delay PD = 0, and during the second half-cycle CYCLE[1], the programmable delay PD = T. DEL_OFF Among them Figure 12B In this context, the progressive delay is denoted as T. DEL_OFF1 The adaptive turn-off control algorithm continues to operate in this manner in each of the following half-cycles CYCLE[2]-CYCLE[n-1], that is, an incremental delay T is added to the programmable delay PD of the gate drive signal GD in each half-cycle. DEL-OFF And the conduction time T of the body diode Dbr of transistor SR was measured. diode Finally, in the nth half-cycle CYCLE[n], the programmable delay PD = T DEL_OFF1 +T DEL_OFF2 +T DEL_OFF3 +T DEL_OFF4 ...+T DEL_OFFn The delay T DEL_OFF2 The progressive delay, T, is added during the half-cycle CYCLE[1]. DEL_OFF3 The progressive delay, T, is added during the half-cycle CYCLE[2]. DEL_OFF4 The progressive delay, T, is added during the half-cycle CYCLE[3]. DEL_OFFn This is the incremental delay added during half a cycle CYCLE[n]. During cycle CYCLE[n], the conduction time T of the body diode Dbr of transistor SR is... diode Approximately equal to the ideal conduction time T diode-ideal Therefore, during the period CYCLE[n] and subsequent periods, the gate drive signal GD utilizes this programmable delay PD to control the deactivation of transistor SR. In this way, the adaptive turn-off control algorithm takes into account the stray inductance L associated with transistor SR. SR To turn off the transistor at an appropriate time during each half-cycle, thereby minimizing the on-time T of the body diode Dbr. diode Furthermore, the efficiency of the switching converter 100 is improved. With the actual on-time T... diode Approximately ideal conduction time T diode-idealAs described in more detail in U.S. Patent No. 9,356,535, the adaptive shutdown control algorithm can control the programmable delay by increasing the incremental delay T compared to the initial increment used to increase the programmable delay. DEL-OFF Smaller or finer incremental delays are used to increment or decrement the programmable delay PD to provide a final programmable delay PD, which results in an actual on-time T. diode Closer to the ideal conduction time T diode-ideal .

[0061] The adaptive shutdown control algorithm described above assumes that the stray inductance L... STRAY =L SR The advance effect relative to the switching frequency ω of the switching converter 100 sw It is constant. However, under this assumption, the load current I of the switching converter 100... O / I LOAD After the transient, the converter's output voltage V O Decreasing or increasing causes the primary control loop of the switching converter to operate at a new switching frequency ω. SW Drive resonant circuit 30 ( Figure 6 Although not described in detail herein, as those skilled in the art will understand, the primary control loop of the resonant switching converter 100 will regulate the output voltage V. O Compare with the expected value and adjust the switching frequency ω of the switching converter. sw To maintain the regulated output voltage at the desired value, the new switching frequency ω of the switching converter 100... sw This leads to stray inductance L SR Different advance effects on the voltage Vdvs(t) across the synchronous rectifier transistor SR. When this is the case, the load current I of the switching converter 100... O / I LOAD This transient, and the subsequent load switching frequency ω sw Following the change, the adaptive shutdown control algorithm continues to use the last value of the programmable delay PD determined before the transient in the load current.

[0062] Typically, this operation causes the adaptive shutdown control algorithm to continue operating beyond the current I through transistor SR. SR The zero-crossing turns off the transistor SR earlier and avoids current reversal, as described in more detail above. However, when the switching converter 100 experiences the load current I... O / I LOAD During the high-to-low transient, the regulated output voltage V O It may experience some kind of "overshoot," meaning that the regulated output voltage becomes larger than the expected regulated output voltage. As a result, the primary control loop increases the switching frequency ω.SW To reduce the output voltage V toward the desired value O .

[0063] In the first approximation, the stray inductance L SR The advance effect can be considered a constant parameter, but in some specific cases, this approximation is insufficient to describe the true phenomenon of stray inductance. In these cases, when the current from the maximum or full load I... O / I LOAD After the zero-load current transient, because the primary control loop is not fast enough to control the switching converter to balance the transient, the regulated output voltage V... O The increase exceeds the expected value. As a result, the primary control loop increases the switching frequency ω. SW To compensate for the regulated output voltage V O This change in the process reduces the stray inductance L. SR The premature turn-off effect. This means that if the adaptive turn-off control algorithm continues to use the last adaptive turn-off delay value, i.e., programs the delay of the last value of PD, then the transistor SR will be turned off later, which may lead to an increase in current I. SR The current is reversed.

[0064] Figure 13A and 13B The diagram illustrates the current I that can occur in the above scenario. SR The current reversal is for the current from the maximum or full load current I. O / I LOAD The transient to zero load current is also referred to in this description as the "full load to zero load current transient". Figure 13A The diagram illustrates the operation of the switching converter 100 prior to the full-load to zero-load current transient, and corresponds to the following operating conditions described above: when the programmable delay PD (PD = T) DEL_OFF1 +T DEL_OFF2 …+T DEL_OFFn The conduction time T has been adjusted to make the conduction time T diode =T diode-ideal hour, Figure 12C The period CYCLE[n] and the subsequent half-cycle.

[0065] Figure 13B The diagram illustrates the operation in half-cycle CYCLE[n+1], where the full-load to zero-load current transient has occurred and the switching frequency ω... SW Increased to compensate for the regulated output voltage V O After the overshoot. As seen in 13B, the stray inductance L SRThe advance effect decreases in the period CYCLE[n+1], resulting in a zero-crossing of the voltage Vdvs(t) at time t1', which is later than time t1. Figure 13B The actual voltage Vdvs(t) in the equation is relative to Figure 13A Delayed (i.e., stray inductance L) SR The advance effect is smaller), and the resulting Vdvs(t) voltage is closer to the ideal voltage Vdvs-ideal shown in the dashed line. As a result, when the zero-crossing of voltage Vdvs(t) is detected at time t1′, and the deactivation of the gate drive signal GD is delayed from this point by the programmable delay PD, the gate drive signal does not deactivate transistor SR until a later time t2′ relative to time t2. Figure 13B The programmable delay PD period in (i.e., from in Figure 13B During time t1' to time t2', transistor SR remains on and current I... SR The current reverses. Current I SR This current is reversed in Figure 13B The middle is marked, and corresponds to the current becoming negative, and therefore as previously mentioned (refer to...). Figure 6 The aforementioned current I SR From the output node OUTN ( Figure 6 The current flows to ground, thus undesirably discharging the output node OUTN.

[0066] To better describe this phenomenon, it is necessary to consider the stray inductance L. SR The closed-form expression for the advance effect. To obtain such a closed-form expression, the current I is assumed to be based on the following equation. SR It has a near-sinusoidal shape in the last part of the switching cycle:

[0067] I SR (t)=I PK ·sin(ω SW Equation 1 (t)

[0068] Under these conditions, the actual or true voltage V DVS (t) is given by the following equation:

[0069]

[0070] This expression can be rewritten to separate the time component and the phase-shift component as follows:

[0071]

[0072] in It is caused by stray inductance L SRThe resulting lead time. The lead time in Equation 3. In the following description, it is referred to as T. LSR (Right now, By making equations 2 and 3 equal, we can obtain the following expression for the phase shift:

[0073]

[0074]

[0075] As mentioned above, resistor R DS(on) It is the on-resistance of the synchronous rectifier transistor SR, and is also referred to as R in the description above. dson .

[0076] The last approximation in Equation 5 is for the lead time T. LSR And only when Only then is it established, and in this case, the advance time T LSR It is based on the switching frequency f SW When ω is constant SW =2π·f SW This is a linear approximation of the arctangent function and applies to the independent variable (L). SR / R DS(on) ·ω SW ) is much smaller than 1((L) SR / R DS(on) ·ω SW The case where ) << 1). Figure 14 It shows the advance time T LSR and regarding the advance time T LSR A plot of three distinct values ​​of the linear approximation, where the advance time T is... LSR Equation 5 gives the switching frequency f as the three values ​​for this approximation. sw The function. In Figure 14 In the middle, line 1400 is the following advance time T LSR The linear approximation, where the stray inductance L SR = 4nH, and resistor R is connected. DS(on) = 4mΩ, therefore T LSR = (4nH / 4mΩ) = 1μs = 1000ns. Line 1402 shows a plot of Equation 5, where L SR / R DS(on) =1000ns. Similarly, line 1404 has the following advance time T. LSR The linear approximation, where the stray inductance L SR =8nH, with resistor R connected DS(on) =4mΩ, therefore the advance time T LSR= (8nH / 4mΩ) = 2μs = 2000ns, line 1406 shows the plot of equation 5. Where L SR / R DS(on) =2000ns. Finally, line 1408 has the following advance time T. LSR The linear approximation, where the stray inductance L SR =16nH, with resistor R connected DS(on) =4mΩ, therefore the advance time T LSR = (16nH / 4mΩ) = 4μs = 4000ns, line 1410 shows a plot of equation 5, where L SR / R DS(on) = 4000ns.

[0077] Figure 14 The actual or true lead time T is shown. LSR As the switching frequency f SW It varies as a function of the time advance. The adaptive shutdown control algorithm assumes that it is for the time advance T LSR A linear approximation is made, and accordingly it is assumed that the value of the lead time is not taken as the switching frequency f. SW It changes as a function, which is in Figure 14 The switching frequency range shown is inaccurate. Following the high-to-low transient in the load current Iload, the primary control loop of the resonant switching converter 100 ( Figure 6 Increase the switching frequency f SW This compensates for variations in the output voltage Vout, thereby providing the desired regulation of that output voltage. Switching frequency f SW This change (Δf) SW / f SW This can be on the order of 10% to 15%, which leads to a lead time T LSR The change or variation ΔT is on the order of 50 ns, which is related to the turn-off time of the transistor SR or the on-time T of the target body diode. diode-ideal quite.

[0078] In this scenario, where the load current changes rapidly from high to low, the change ΔT is more specifically the advance time T. LSR The reduction. If the advance time T LSR The change ΔT reaches or exceeds the target or desired conduction time T of the body diode Dbr. diode-ideal (For example, 50 ns), the current reverses, as described above, where the synchronous rectifier current Isr through transistor SR reverses direction.

[0079] Figure 15 It is used as the switching frequency f SW advance time T of the function LSR A graph showing the change in ΔT. Lead time T LSRThe change ΔT in the value represents the switching frequency f. SW The function, in advance time T LSR The error or variation between the ideal constant linear approximation and the true or actual value of the advance time. Line 1500 shows the error or variation as the switching frequency f. SW The function of T LSR = (4nH / 4mΩ) = 1μs = 1000ns advance time T LSR The linear approximation of the change ΔT. Line 1502 shows the change as the switching frequency f. SW The function of T LSR = (8nH / 4mΩ) = 2μs = 2000ns advance time T LSR The linear approximation of the change ΔT, while line 1504 shows the change from T as a function of the switching frequency. LSR The advance time T is (16nH / 4mΩ) = 4μs = 4000ns. LSR The linear approximation of the change ΔT.

[0080] Figures 16A to 16C This is a signal timing diagram that illustrates the switching frequency f within the context of an adaptive shutdown control algorithm. SW The advance time T caused by the change from half-cycle n to the next half-cycle n+1 LSR How does the change ΔT cause the current to reverse? Figures 16A to 16C In the example, the switching converter 100 experiences a high-to-low current transient. If the advance time T... LSR If the change in current ΔT is greater than the target turn-off time Toff according to the adaptive turn-off algorithm, then the current I caused by the delayed turn-off Toff will be... SR Reverse current flow may occur, and this delayed turn-off Toff is provided by an adaptive turn-off control algorithm. Figure 16A In the diagram, the vertical axis represents the voltage of the Vdvs signal, and the horizontal axis represents time t. Figure 16B and 16C In the diagram, the vertical axis represents the voltage of the output signal ZCD, which indicates the voltage across the transistor SR (…). Figure 6 The zero-crossing event of the drain-to-source voltage Vdvs, with the horizontal axis being time t.

[0081] Figures 16A to 16CThe ideal voltage signal Vdvs-ideal 1600 for the first half-cycle n is shown, as well as the real or actual signal Vdvs 1602 for the same first half-cycle n. Cycle n is the period preceding the load transient. Similarly, for the second half-cycle n+1, the ideal voltage signal Vdvs-ideal 1604 and the real or actual signal Vdvs 1606 are shown, where the load transient occurs between cycle n and cycle n+1. The ideal signals Vdvs1600 and 1604 are not affected by stray inductance L. SR The influence of, and therefore these signals and current I SR Directly proportional. Conversely, the real or actual signal Vdvs 1602, 1606 is subject to stray inductance L. SR and advance time T LSR The effect of the change ΔT, which is due to the switching frequency f SW The change from half-cycle n to half-cycle n+1.

[0082] Figure 16A The diagram illustrates various ideal and real signal DVSs during half-cycles n and n+1, where time t along the horizontal axis is extended or amplified near the zero-crossing of the load current Iload associated with the signal in the figure. Load current Iload ( Figure 6 The current (ISR1 + ISR2) is equal to the current, where in each half-cycle SC, one of these currents ISR1 and ISR2 is equal to zero, such that in each half-cycle, the load current Iload is equal to either ISR1 or ISR2. Figure 16 illustrates the advance time T. LSR The effect of the change ΔT between the half-cycle n before the load transient and the half-cycle n+1 after the load transient. In the figure, the advance time T of the half-cycle n. LSR Designated as T LSR [n], and the advance time T of half-cycle n+1. LSR Designated as T LSR [n+1].

[0083] As in Figures 16A to 16C As seen in the diagram, due to the switching frequency f SW The period increases from period n to period n+1, so the advance time T LSR [n+1]( Figure 16C Less than the lead time T LSR [n]( Figure 16BFor each half-cycle, n and n+1, the zero-crossing of the voltage Vdvs occurs at time t1. In half-cycle n, the programmable delay PD, provided by the adaptive turn-off control algorithm, is the time from the detection of the zero-crossing of the voltage Vdvs at time t1 until the turn-off time Toff at time t2. In the figure, the duration of this programmable delay PD is also specified as the time interval T from time t1 to t2. DEL_OFF For example, in Figure 16A and 16B As seen in the diagram, in half a cycle n, prior to the load transient, the programmable delay PD provided by the adaptive turn-off control algorithm turns off the transistor SR at time Toff = t2, thereby providing the ideal on-time T for the body diode Dbr of the transistor. diode-ideal .

[0084] refer to Figure 16C In the half-cycle n+1 following the load transient, the adaptive turn-off control algorithm again provides a programmable delay PD to turn off transistor SR at Toff = t2. When this is done, the switching frequency f due to the load transient... SW The changes, and the resulting advance time T LSR The change in [n+1] implies that the zero-crossing of the ideal signal Vdvs-ideal occurs earlier, as seen in the figure, and the transistor SR should cross at T' OFF The area was shut down earlier, T' OFF exist Figures 16A to 16C At time t2' in the time table. Advance time T LSR [n+1] corresponds to the time from time t1 to t2'. However, the adaptive shutdown control algorithm does not work at T'. OFF Instead of turning off transistor SR, it turns off T again. off The transistor is turned off at time t2′. As a result, the zero-crossing of the signal Vdvs occurs at time t2′ in half a cycle n+1, but the transistor SR is not turned off until time t2, causing the current ISR to reverse before the transistor is turned off (i.e., ISR becomes negative). As mentioned earlier, this current reversal is undesirable.

[0085] From reference Figures 16A to 16C As can be seen from the description of the adaptive shutdown control algorithm, the programmable delay PD evaluated during half-cycle n is used for half-cycle n+1. This programmable delay PD is updated only at the end of half-cycle n+1, and this updated delay is subsequently used for the next half-cycle n+2. When the advance time T... LSR When the value is constant, this operation of the adaptive shutdown control algorithm will not cause problems. However, when due to the reference... Figures 16A to 16C The high-to-low load current transient has a lead time T. LSRWhen the switching frequency f changes, SW As mentioned earlier, changes in current, such as those in 16B, can lead to a reversal of current. (See figure 16B and...) Figure 16C As shown in the diagram, in this situation, T LSR [n+1] <T LSR [n], and this reduction in the advance time ΔT (i.e., from t3 to t2') causes the transistor SR to turn off with a delay, resulting in a current I SR The unwanted current reverses.

[0086] Figures 17A to 17F This is a signal timing and function diagram illustrating the operation of a current reverse prevention control algorithm according to an embodiment of the present disclosure, for controlling... Figure 6 The operation of the rectifier 5 of the switching converter 100 is designed to prevent current reversal even in the presence of load current transients. Figure 17A This is a signal timing diagram showing the drain-to-source voltage signal Vdvs of activated transistors SR1 and SR2. More specifically, the first half-cycle CYCLE[n] in which transistor SR1 is activated (i.e., turned on) is shown. The current and voltage associated with transistor SR1 are labeled I, respectively. SR1 and V DVS1 The second half-cycle CYCLE[n+1] in which transistor SR2 is activated is shown, where the current and voltage associated with transistor SR2 are labeled I, respectively. SR2 and V DVS2 Finally, the third half-cycle CYCLE[n+2] in which transistor SR1 is activated again is shown, and for this half-cycle, the current I... SR1 and voltage V DVS1 It is shown.

[0087] Figure 17B and 17C This is a signal timing diagram showing gate drive signals GD1 and GD2, which are applied to control, respectively, the gate drive signals GD1 and GD2. Figure 6 The activation and deactivation (i.e., turning on and off) of transistors SR1 and SR2 are shown in the figure. Figure 17D The amplitude of the voltage Vdvs across the activated transistor SR1 or SR2 is shown, which is related to the threshold TH = (α·V) for each half-cycle in half-cycles CYCLE[n], CYCLE[n+1], and CYCLE[n+2]. dvs_PK In comparison, this comparison is conducted through... Figure 17F The comparator 1700 shown is used as an example, which will be described in more detail below. The parameter α is the threshold adjustment factor, which will be discussed in detail below. Figure 17EThe output signal COMP generated by comparator 1700 is shown, which will also be described in more detail below. Figures 17A to 17E Each figure shows the voltage, or voltage and current, along the vertical axis, and the time t along the horizontal axis.

[0088] Figure 6 The control circuit 7 is configured to execute the current reverse prevention control algorithm, wherein the control circuit can be formed by a suitable circuit system as understood by those skilled in the art, such as hardware, software, or firmware executed on a suitable processing circuit system, or a combination of these types of circuits. In operation, the current reverse prevention control algorithm detects the voltage signal Vdvs of the transistor SR and controls the transistor to avoid current I before the transistor is turned off in each half-cycle. SR The current is reversed; now refer to Figure 17 to... Figure 19 To explain this in more detail. As mentioned above, in this application, the current reverse prevention control algorithm is described in the context of the adaptive turn-off control algorithm, or is described as being used in conjunction with the adaptive turn-off control algorithm, but the current reverse prevention control algorithm can also be used in conjunction with other control algorithms for controlling transistors SR in the rectifier circuit of a switching converter.

[0089] In operation, the current reverse prevention control algorithm compares the actual voltage signal Vdvs detected by SC in each half-cycle with a peak voltage reference threshold TH, which is calculated cycle-by-cycle from the voltage signal Vdvs sensed in each half-cycle. Cycle-by-cycle means that the voltage signals Vdvs of the transistors SR1 and SR2 activated in each half-cycle SC are sensed, and these voltage signals Vdvs are used in the calculation of the threshold TH. Then, if a high-to-low load current transient occurs in each half-cycle SC, the result of this comparison is used to prevent current I... SR The current is reversed, and this comparison is represented by comparator 1700 in Figure 17, which will now be explained in more detail. (Refer to the following...) Figure 18 In more detail, the peak voltage reference threshold TH actually includes a first peak voltage reference threshold for the voltage signal Vdvs of transistor SR1 and a second peak voltage reference threshold for transistor SR2.

[0090] The current reverse prevention control algorithm evaluates the voltage signal V during the on-time TSW of transistor SR in N previous half-cycles SC. DVS Average voltage V DVS_AVG The average voltage signal V DVS_AVG Unaffected by stray inductance L SR The effect is proportional to the load current Iload. Recall that the load current Iload = ISR1 + ISR2 (see... Figure 6 If, during the final portion of the switching half-cycle SC, the current ISR approximates a near-sinusoidal shape, then the average V of the voltage signal Vdvs is... DVS_AVG and peak V DVS_PK It is related through the following equation:

[0091]

[0092] This means that it is possible to obtain the average value V DVS_AVG Calculate the peak value V of the Vdvs signal. DVS_PK Therefore, the current reverse prevention control algorithm is based on the peak V. DVS_PK Determine the peak voltage reference threshold TH, where the threshold TH is, for example, set to the peak voltage V. DVS_PK 75%. Therefore, the peak voltage reference threshold TH = (α·V) DVS_PK ), where α is the threshold adjustment factor, and in the example α = 0.75. Then, the current reverse prevention control algorithm compares this peak voltage reference threshold TH with the actual voltage signal Vdvs during the on-time TSW of the transistor SR.

[0093] During operation, during the half-cycle SC in which no load current transient occurs, comparator 1700 generates an output signal COMP, which becomes active for a certain percentage of the on-time TSW of transistor SR during this half-cycle SC. Figures 17A to 17E In the example, for instance, when no load current transient occurs, comparator 1700 activates the COMP signal for 75% of the on-time TSW. This percentage of the on-time is defined by multiplying the on-time TSW by an on-time adjustment factor β, where β = 0.75 in the example embodiment. The COMP signal generated by comparator 1700 in… Figure 17E As shown in the diagram. During the first half-cycle CYCLE[n], comparator 1700 will activate the voltage signal V of transistor SR1. DVS1 With threshold TH=(α·V DVS_PK The threshold TH is compared with the average V of the voltage signal Vdvs described above by Equation 6. DVS_AVG The average value V DVS_AVG exist Figure 17D As shown in the diagram. No load current transient occurs in CYCLE[n], and therefore at time t1, comparator 1700 detects voltage V. DVS1 The threshold TH has been reached and the COMP signal is activated. The same operation occurs in the second half-cycle CYCLE[n+1] illustrated, where comparator 1700 activates the voltage signal V of transistor SR2. DVS2 With threshold TH=(α·V DVS_PKThe comparison is performed. At time t2, comparator 1700 detects the voltage signal V. DVS2 The threshold TH has been reached and the COMP signal has been activated.

[0094] The operation of comparator 1700 in generating COMP signals in CYCLE[n] and CYCLE[n+1] illustrates the sensed voltage signal V during the half-cycle SC in which no load current transient occurs. DVS1 V DVS2 The threshold is reached within a certain percentage of the conduction time TSW of the activated transistors SR1 and SR2 (defined by the adjustment parameter β). Conversely, as will now be referred to... Figures 17A to 17F To explain this in more detail using CYCLE[n+2] in the diagram, in the event of a load current transient, comparator 1700 does not activate the COMP signal for a certain percentage of the conduction time TSW. In this example, as shown by... Figure 17A Arrow 1702 indicates that a high-to-low load current transient (such as from maximum load current to zero load current Iload) occurs between CYCLE[n+1] and CYCLE[n+2]. As a result of this load current transient, the voltage V sensed by comparator 1700 in CYCLE[n+2] is... DVS1 The threshold TH = (α·V) was not reached within a certain percentage of the conduction time TSW. DVS_PK In fact, in the example illustrated, the voltage V DVS1 The threshold TH is never reached in CYCLE[n+2]. As will now be explained in more detail, comparator 1700 therefore does not activate the COMP signal in CYCLE[n+2], which can be used to indicate the detection of load current transients, as well as the switching converter 100 ( Figure 6 The corresponding adjustment of the control is made to prevent current I. SR The current is reversed.

[0095] Before describing this operation in detail, it should be noted that the operation of comparator 1700 to detect load current transients via the COMP signal in CYCLE[n+2] occurs before the end of the conduction time TSW of CYCLE[n+2]. Therefore, this approach supports the detection of load current transients in the half-cycle SC in which the load current transient occurs, corresponding to the time when the load current Iload is at its maximum level. This rapid detection of load current transients via comparator 1700 enables the detection of load current transients in the half-cycle SC in which the load current transient is detected (i.e., during...). Figures 17A to 17F In the example CYCLE[n+2], the current can be prevented from reversing.

[0096] From the above description of the operation of comparator 1700 for CYCLE[n], CYCLE[n+1], and CYCLE[n+2], it can be seen that there are two scenarios regarding the output signal COMP generated by the comparator. The first scenario is the one illustrated and described above for CYCLE[n] and CYCLE[n+1], where no load current transient occurs from one half-cycle to the next. In this scenario, comparator 1700 will activate the COMP signal within a certain percentage of the conduction time TSW (i.e., within β·TSW). When this scenario occurs, no measures are needed to prevent the current I through the synchronous rectifier transistors SR1 and SR2. SR1 I SR2 The current is reversed, and these transistors can continue to be controlled via adaptive shutdown control algorithms, or used for control. Figure 6 The synchronous rectifier transistors in rectifier 5 can be controlled by any other suitable turn-off control algorithm.

[0097] The second scenario is the one illustrated and described above for CYCLE[n+2], where a load current transient causes a reduction in the high load current Iload, such as a transient from maximum or full load current to zero load current. In this scenario, comparator 1700 will not activate the COMP signal within a certain percentage of the conduction time TSW (i.e., within β·TSW). When using an adaptive shutdown control algorithm to control transistors SR1 and SR2, the detection of the load current transient indicated by the COMP signal (i.e., the COMP signal is not activated within the time limit β·TSW of the conduction time TSW), and the programmable delay PD being reset to zero, the programmable delay PD in... Figure 16B and Figure 16C The middle is also indicated as a delay T DEL_OFF This zero latency will result in a response as previously referred to above. Figure 11A , 11B The earlier zero-crossing of the voltage signal Vdvs causes transistor SR to turn off. This turn-off of the transistor may not result in the ideal on-time T of the body diode Dbr of transistor SR. diode-ideal However, this will prevent current reversal. Furthermore, after the programmable delay PD is reset to zero in response to the COMP signal indicating a transient load current, the adaptive shutdown control algorithm will proceed as described above. Figure 11A and Figure 11B The operation described above is used to readjust the programmable delay in the continuous half-cycle SC until the actual on-time T of the body diode Dbr is reached. diode Approximately equal to the ideal conduction time T diode-ideal .

[0098] As mentioned several times in the above description, the current reverse prevention control algorithm described herein is not limited to use in conjunction with the adaptive turn-off control algorithm. It is used to control rectifier circuits (such as...) Figure 6 Other control methods for turning off the synchronous rectifier transistor SR in the rectifier 5) can be combined with a current reverse prevention control algorithm. In another embodiment, the controlled circuit system (such as, ) that detects load current transients indicated by the COMP signal Figure 6 The control circuit 7) in the middle is used to switch the converter 100 ( Figure 6 The transistors are placed in a "safe state" to turn off transistors SR1 and SR2, thereby preventing reverse current flow.

[0099] Figure 18 This is a functional block diagram illustrating a threshold calculation circuit 1800 of a current reverse prevention control algorithm according to an embodiment of the present disclosure, which is used to generate a threshold TH. In this embodiment, the averaging calculation circuit 1801 senses the voltage signals V from transistors SR1, SR2 of N previous half-cycles SC of the switching converter 100. DVS1 V DVS2 More specifically, the averaging circuit 1801 senses the voltage signal V during the on-time TSW of each of the transistors SR1 and SR2 in N previous half-cycles SC. DVS1 V DVS2 And calculate the average voltage signal V for each of these sensed voltage signals. DVS1_AVG V DVS2_AVG Therefore, the averaging circuit 1801 generates the average voltage signal V. DVS1_AVG Its indicator voltage signal V DVS1 The average is calculated over N previous half-cycles SC, and the averaging circuit 1801 also generates an average voltage signal V. DVS2_AVG Its indicator voltage signal V DVS2 The average over N previous half-cycles of SC.

[0100] Peak calculation circuit 1802 receives average voltage signal V DVS1_AVG and V DVS2_AVG and from the average voltage signal V DVS1_AVG and V DVS2_AVG A threshold TH is generated, which includes the individual peak voltage reference thresholds for each of transistors SR1 and SR2 as mentioned above. Therefore, the peak voltage reference threshold TH includes a first peak voltage reference threshold TH1 = (α·V) DVS1_PK ) and the second peak voltage reference threshold TH2=(α·V DVS2_PK It is used by comparator 1700 to sense voltage signal V DVS1 and VDVS2 Therefore, although in Figure 17F Not shown in the diagram, comparator 1700 converts the voltage signal V... DVS1 The first peak voltage reference threshold TH1 = (α·V) DVS1_PK Compare and convert the voltage signal V DVS2 The second peak voltage reference threshold TH2 = (α·V) DVS2_PK The comparison is performed for use by comparator 1700 on the sensed voltage signal V. DVS1 and V DVS2 Used in.

[0101] Figure 19 This is a functional block diagram of one embodiment of the comparator 1700 in Figure 17. Figure 19 In one embodiment, comparator 1700 includes a first comparator circuit 1900-1, which receives a first peak voltage reference threshold TH1 = (α·V) DVS1_PK The voltage signal V of transistor SR1 and transistor SR1 DVS1 And based on the comparison of the two received signals, a first comparison output signal COMP1 is generated. Comparator 1700 includes a second comparator circuit 1900-2, which receives a second peak voltage reference threshold TH2 = (α·V) DVS2_PK The voltage signal V of transistor SR2 and transistor SR2 DVS2 And based on the comparison of the two received signals, a second comparison output signal COMP2 is generated. Therefore, the first comparator circuit 1900-1 generates the COMP1 signal to indicate whether a load current transient related to the switching of transistor SR1 is detected, and the second comparator circuit 1900-2 generates the COMP2 signal to indicate whether a load current transient related to the switching of transistor SR2 is detected. (Figure 17 and...) Figure 19 Comparator 1700 and Figure 18 The threshold calculation circuit 1800 is Figure 6 It is part of the control circuit 7, and as those skilled in the art will understand, it can be implemented by a suitable circuit system including hardware, software, firmware or a combination thereof.

[0102] The embodiments described above in this disclosure are in the context of a resonant switching converter, which includes a synchronous rectification circuit system comprising a first synchronous rectifier transistor and a second synchronous rectifier transistor, wherein the first and second synchronous rectifier transistors are MOSFETs. The embodiments of this disclosure are not limited to this particular type of switching converter, synchronous rectification circuit system, or synchronous rectifier transistor. In other embodiments of this disclosure, the synchronous rectification circuit system includes at least one synchronous rectifier transistor. Furthermore, in other embodiments of this disclosure, the synchronous rectifier transistor is a bipolar transistor or an insulated-gate bipolar junction transistor.

[0103] The various embodiments described above can be combined to provide other embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to which these claims are entitled. Therefore, the claims are not limited to this disclosure.

Claims

1. A method of controlling synchronous rectifier transistors in a switching converter, the method comprising: sensing a drain-to-source voltage across each synchronous rectifier transistor during each switching half-cycle of the switching converter; calculating, for each synchronous rectifier transistor, an average of the sensed drain-to-source voltage over N previous switching half-cycles, where N is an integer greater than 0; and controlling the synchronous rectifier transistors by an adaptive turn-off control algorithm.

2. The method of claim 1, comprising: detecting a load current transient in the switching converter based on the sensed drain-to-source voltage of each synchronous rectifier transistor and the calculated average of the sensed drain-to-source voltage over the N previous switching half-cycles for each synchronous rectifier transistor, detecting the load current transient comprising: calculating a peak voltage reference threshold for each synchronous rectifier transistor having a value based on the calculated average of the sensed drain-to-source voltage for the synchronous rectifier transistor; and comparing the sensed drain-to-source voltage of each synchronous rectifier transistor to the corresponding peak voltage reference threshold for the synchronous rectifier transistor.

3. The method of claim 2, wherein calculating the peak voltage reference threshold for each synchronous rectifier transistor comprises: calculating a peak sensed drain-to-source voltage from the calculated average of the sensed drain-to-source voltage for the synchronous rectifier transistor; and multiplying the peak sensed drain-to-source voltage by a threshold adjustment factor to generate the peak voltage reference threshold. for each synchronous rectifier transistor:

4. The method of claim 2, wherein detecting the load current transient further comprises: during a turn-on time of the synchronous rectifier transistor, comparing the sensed drain-to-source voltage to the peak voltage reference threshold; determining whether the sensed drain-to-source voltage reaches the peak voltage reference threshold within a certain percentage of the turn-on time; and in response to the sensed drain-to-source voltage not reaching the peak voltage reference threshold within the certain percentage of the turn-on time, detecting the load current transient. multiplying the turn-on time by a turn-on time adjustment factor to determine the certain percentage of the turn-on time.

5. The method of claim 4, further comprising: calculating the average of the sensed drain-to-source voltage during the turn-on time of the synchronous rectifier transistor.

6. The method of claim 5, wherein calculating the average of the sensed drain-to-source voltage over the N previous switching half cycles for each synchronous rectification transistor comprises: in response to detecting a load current transient in the switching converter, resetting the programmable delay to zero.

7. The method of claim 1, wherein the adaptive shutdown control algorithm generates a programmable delay that is utilized in controlling each synchronous rectification transistor, and wherein the method further comprises:

8. The method of claim 1, wherein the switching half-cycle of each synchronous rectifier transistor begins in response to the sensed drain-to-source voltage of the synchronous rectifier transistor reaching a first threshold and ends in response to the drain-to-source voltage reaching a second threshold.

9. The method of claim 8, wherein the first threshold is less than the second threshold. ​ 10. A control circuit configured to be coupled to synchronous rectification circuitry of a switching converter, the control circuit configured to generate control signals to control switching of at least one synchronous rectification transistor in the synchronous rectification circuitry, each at least one synchronous rectification transistor including a control node and a signal node, and the control circuit configured to sense a voltage across the signal node of each at least one synchronous rectification transistor for a portion of each switching cycle of the switching converter in which the at least one synchronous rectification transistor is activated, and the control circuit configured to determine, for each at least one synchronous rectification transistor, an average of the sensed voltage across the signal node of the at least one synchronous rectification transistor over N previous portions of a switching cycle in which the at least one synchronous rectification transistor is activated, N being an integer greater than 0, wherein the control circuit is further configured to implement an adaptive turn-off control algorithm to control the at least one synchronous rectification transistor.

11. The control circuit of claim 10, wherein the control circuit is configured to generate first and second control signals to control switching of first and second synchronous rectification transistors, respectively, and wherein the portion of each switching cycle of the switching converter includes a first and second switching half-cycle in which the first and second synchronous rectification transistors are activated, respectively.

12. The control circuit of claim 11, wherein the control circuit includes: an average calculation circuit coupled to at least one of the signal nodes of each of the first and second synchronous rectification transistors, the average calculation circuit configured to sense the voltage across the signal nodes of the first and second synchronous rectification transistors during on-time of the first and second synchronous rectification transistors, and the average calculation circuit configured to calculate, for the first and second synchronous rectification transistors, a first and second average voltage, respectively, of the sensed voltage over N previous first and second switching half-cycles; and a peak calculation circuit coupled to the average calculation circuit to receive the calculated first and second average voltages, and the peak calculation circuit configured to generate first and second peak voltage reference thresholds based on the calculated first and second average voltages, respectively.

13. The control circuit of claim 12, wherein the peak calculation circuit is configured to multiply the calculated first and second average voltages by a threshold adjustment factor to generate the first and second peak voltage reference thresholds.

14. The control circuit of claim 13, wherein the control circuit further comprises a first comparator and a second comparator, the first and second comparators each comprising a first input coupled to one of the signal nodes of the first and second synchronous rectification transistors, respectively, and the first and second comparators each comprising a second input coupled to receive one of the first and second peak voltage reference thresholds generated for the first and second synchronous rectification transistors, and wherein the first and second comparators are configured to generate a first and second comparison output signal, respectively, each of the first and second comparison output signals indicating whether a load transient has occurred in a current first and second switching half-cycle, respectively.

15. A switching converter comprising: switching circuitry comprising at least one switching element; synchronous rectification circuitry coupled to the switching circuitry, the synchronous rectification circuitry comprising at least one synchronous rectification transistor, each at least one synchronous rectification transistor comprising a control node and a signal node; and a control circuit coupled to each at least one synchronous rectification transistor, the control circuit configured to: sense a voltage across the signal node of each at least one synchronous rectification transistor during each portion of a switching cycle of the switching converter in which the at least one synchronous rectification transistor is activated; calculate an average of the sensed voltage across each at least one synchronous rectification transistor over N previous portions of the switching cycle in which the at least one synchronous rectification transistor is activated, N being an integer greater than 0; and implement an adaptive turn-off control algorithm to control the at least one synchronous rectification transistor.

16. The switching converter of claim 15, wherein the control circuit is configured to detect a load current transient in the switching converter based on a comparison of: the sensed voltage of each at least one synchronous rectification transistor during the portion of the switching cycle in which the at least one synchronous rectification transistor is activated; and the calculated average of the sensed voltage across the at least one synchronous rectification transistor over the N previous portions of the switching cycle in which the at least one synchronous rectification transistor is activated.

17. The switching converter of claim 15, wherein each at least one synchronous rectification transistor comprises a MOSFET, and the synchronous rectification circuitry comprises a first and second MOSFET.

18. The switching converter of claim 17, wherein the control circuit is further configured to implement an adaptive turn-off control algorithm to control switching of the first and second MOSFETs. ​ 19. The switched converter of claim 15, wherein the switching circuitry comprises LLC resonant converter circuitry.

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