Non-volatile memory device and operating method thereof and storage system

Abstract

A method of operating a non-volatile memory device, wherein the non-volatile memory device includes a cell string, wherein the cell string includes a plurality of cell transistors stacked in a direction perpendicular to a substrate in series between a bit line and a common source line, the method comprising: programming an erase control transistor in the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground select transistor in the plurality of cell transistors and the common source line or between a string select transistor in the plurality of cell transistors and the bit line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0054546, filed with the Korean Intellectual Property Office on May 9, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to a semiconductor memory, and more specifically, to a non-volatile memory device and a method of operating the same, as well as a storage device including the non-volatile memory device. Background Technology

[0004] Semiconductor memory devices can be classified as volatile or non-volatile. Semiconductor memory devices are volatile because the stored data is lost when power is off. Examples of volatile memory devices include Static Random Access Memory (SRAM) or Dynamic RAM (DRAM). Semiconductor memory devices are non-volatile because the stored data is retained when power is off. Examples of non-volatile memory devices include flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0005] Flash memory is widely used as a high-capacity storage medium in non-volatile memory devices. Currently, three-dimensional flash memory devices are being developed to provide increased integration. Therefore, various technologies are being developed for controlling highly integrated flash memory devices. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a method of operating a non-volatile memory device includes a cell string, wherein the cell string includes a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate. The method includes: programming an erase control transistor among the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line, and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than an erase voltage and greater than a ground voltage, and wherein the erase control transistor is located between a ground selection transistor and the common source line among the plurality of cell transistors, or between a string selection transistor and the bit line among the plurality of cell transistors.

[0007] According to an exemplary embodiment of the present invention, a non-volatile memory device includes: a memory cell array, wherein the memory cell array includes a cell string, wherein the cell string includes a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate; a row decoder configured to control the common source line and an erase control line connected to an erase control transistor among the plurality of cell transistors; an input / output circuit configured to control the bit line; and control logic circuitry, wherein, in an erase operation associated with the cell string, the control logic circuitry controls the row decoder and the input / output circuitry such that the erase control transistor is programmed, and then controls the row decoder and the input / output circuitry such that an erase voltage is applied to the common source line or the bit line and an erase control voltage is applied to the erase control line, wherein the erase control voltage is less than the erase voltage and greater than the ground voltage, and wherein the erase control transistor is located between a ground selection transistor among the plurality of cell transistors and the common source line, or between a string selection transistor among the plurality of cell transistors and the bit line.

[0008] According to an exemplary embodiment of the present invention, a memory system includes: a non-volatile memory device, wherein the non-volatile memory device includes a cell string, wherein the cell string includes a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate; and a memory controller configured to provide a first command and a second command to the non-volatile memory device, wherein, after programming an erase control transistor among the plurality of cell transistors in response to the first command, the non-volatile memory device is configured to, in response to the second command, apply an erase voltage to the common source line or the bit line and apply an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is located between a ground selection transistor and the common source line among the plurality of cell transistors, or between a string selection transistor and the bit line among the plurality of cell transistors. Attached Figure Description

[0009] The above and other features of the present invention will become apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating an exemplary storage system according to a concept of the present invention.

[0011] Figure 2 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 1 A block diagram of a non-volatile memory device.

[0012] Figure 3A , Figure 3B and Figure 3C The exemplary embodiments shown are included in the present invention. Figure 2 The circuit diagram of the memory block in the memory cell array.

[0013] Figure 4 This illustrates exemplary embodiments of the invention and includes [the following]. Figure 2 A flowchart illustrating the erase operations associated with a string of cells in a memory cell array.

[0014] Figure 5 This is a timing diagram illustrating the voltage applied to program the erase control transistor according to an exemplary embodiment of the present invention.

[0015] Figure 6 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 3A The diagram shows a view of the structure of the cell strings in the first memory block.

[0016] Figure 7 This is a view illustrating the structure of an erase control transistor according to an exemplary embodiment of the present invention.

[0017] Figure 8 This is a diagram illustrating the threshold voltage distribution of an erase control transistor that is altered by programming operations according to an exemplary embodiment of the present invention.

[0018] Figure 9A , Figure 9B and Figure 9C This is a diagram illustrating an erasure bias for performing an erasure operation according to an exemplary embodiment of the present invention.

[0019] Figure 10 This is a timing diagram illustrating the voltage applied for an erasure operation according to an exemplary embodiment of the present invention.

[0020] Figure 11This is a diagram illustrating the threshold voltage distribution of a memory cell altered by an erase operation according to an exemplary embodiment of the present invention.

[0021] Figure 12 This is a block diagram illustrating an exemplary embodiment of a storage system including a non-volatile memory device according to a concept of the present invention. Detailed Implementation

[0022] Figure 1 This is a block diagram illustrating an exemplary storage system according to a concept of the present invention. (Reference) Figure 1 The storage system 1000 may include a non-volatile memory device 100 and a memory controller 200. The non-volatile memory device 100 may receive commands CMD and addresses ADDR from the memory controller 200, and may perform various operations in response to commands CMD and addresses ADDR, such as programming operations, reading operations, and erasing operations.

[0023] For example, the non-volatile memory device 100 may include a flash memory device. However, the inventive concept is not limited thereto. For example, the non-volatile memory device 100 may include non-volatile memory devices such as read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM).

[0024] The memory controller 200 can provide commands CMD and addresses ADDR to the non-volatile memory device 100 to control the operation of the non-volatile memory device 100. For example, the memory controller 200 can provide data "DATA" to the non-volatile memory device 100 for storage in the non-volatile memory device 100, or it can read data "DATA" stored in the non-volatile memory device 100. Alternatively, the memory controller 200 can erase data "DATA" stored in the non-volatile memory device 100.

[0025] In an exemplary embodiment of the present invention, the non-volatile memory device 100 can perform an erase operation using gate-induced drain leakage (GIDL) current. The memory controller 200 can program a portion of a specific memory region of the non-volatile memory device 100 to improve GIDL efficiency (e.g., increase the GIDL current) during an erase operation associated with that specific memory region. The memory controller 200 can provide the non-volatile memory device 100 with a command CMD and an address ADDR to program the portion of the specific memory region. In this case, the address ADDR can indicate a portion of the specific memory region in which data “DATA” is to be programmed. After the data “DATA” is programmed, the memory controller 200 can provide the non-volatile memory device 100 with a command CMD and an address ADDR for an erase operation. In this case, the address ADDR can indicate a specific memory region. Thus, an erase operation can be performed on a specific memory region of the non-volatile memory device 100.

[0026] The configuration and operation of the non-volatile memory device 100 for improving GIDL efficiency (e.g., increasing GIDL current) will now be described more fully with reference to the accompanying drawings.

[0027] Figure 2 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 1 A block diagram of a non-volatile memory device. (See reference) Figure 2 The non-volatile memory device 100 may include a memory cell array 110 and peripheral circuitry 120. For ease of description, the following description will assume that the non-volatile memory device 100 is a NAND flash memory device, but the inventive concept is not limited thereto.

[0028] The memory cell array 110 may include multiple memory blocks. Each memory block may include multiple cell strings. Each of the multiple cell strings may include multiple cell transistors connected in series, wherein the multiple cell transistors connected in series are connected to the string select line SSL, the word line WL, the ground select line GSL, the erase control line ECL, and the common source line CSL.

[0029] In an exemplary embodiment of the present invention, the cell transistors of the memory cell array 110 can be stacked in a direction perpendicular to the semiconductor substrate. In other words, the memory cell array 110 may include a three-dimensional memory block.

[0030] The peripheral circuitry 120 may include a line decoder 121, a voltage generator 122, control logic circuitry 123, and input / output (I / O) circuitry 124. In an exemplary embodiment of the inventive concept, a memory cell array 110 may be formed in a cell region of a semiconductor substrate, and the peripheral circuitry 120 may be formed in a peripheral region of the semiconductor substrate, wherein the peripheral region is physically separated from the cell region. Alternatively, the peripheral circuitry 120 may be formed on the semiconductor substrate, and the memory cell array 110 may be stacked on the peripheral circuitry 120. In other words, the non-volatile memory device 100 may have a cell-on-peripheral (COP) structure. However, the inventive concept is not limited thereto. For example, the non-volatile memory device 100 may be implemented in various shapes.

[0031] The row decoder 121 can be connected to the memory cell array 110 via the serial select line SSL, word line WL, ground select line GSL, erase control line ECL, and common source line CSL. The row decoder 121 can be connected from external devices (e.g., Figure 1 The memory controller 200 or host device receives the address ADDR. In an exemplary embodiment of the present invention, the address ADDR may include various address information such as block address, row address, and column address. The row decoder 121 can decode the received address ADDR to control the string select line SSL, word line WL, ground select line GSL, erase control line ECL, and common source line CSL.

[0032] Voltage generator 122 can be configured to generate various voltages (e.g., programming voltage, verification voltage, pass voltage, and erase voltage) used during operation of non-volatile memory device 100. The voltages generated by voltage generator 122 can be provided to line decoder 121 and input / output circuitry 124.

[0033] The control logic circuit 123 can be controlled from external devices (e.g., Figure 1 The memory controller 200 or host device receives the command CMD and can control the line decoder 121, voltage generator 122 and input / output circuit 124 in response to the command CMD.

[0034] Input / output circuitry 124 can be connected to memory cell array 110 via multiple bit lines BL. Input / output circuitry 124 can read data “DATA” stored in memory cell array 110 via multiple bit lines BL, and can output the read data “DATA” to an external device. Alternatively, input / output circuitry 124 can receive data “DATA” from an external device and store the received data “DATA” in memory cell array 110 via multiple bit lines BL.

[0035] In an exemplary embodiment of the present invention, the non-volatile memory device 100 can use a GIDL current for an erase operation associated with a cell string of memory cell array 110. The GIDL current can be generated by a cell transistor connected to the erase control line ECL among the cell transistors of the cell string. In other words, the GIDL current can be generated when the erase control line ECL is controlled by the row decoder 121, and the erase operation can be performed on the cell string based on the GIDL current.

[0036] In an exemplary embodiment of the present invention, for an erase operation associated with a cell string, the non-volatile memory device 100 may receive a programming command PGM for programming a specific cell transistor (e.g., a first cell transistor) of the cell string and an erase command ERS for erasing the cell transistor. In response to the programming command PGM, control logic circuitry 123 may control the row decoder 121, the voltage generator 122, and the input / output circuitry 124 such that the first cell transistor is programmed. Thus, the row decoder 121 and the input / output circuitry 124 may control the string select line SSL, the word line WL, the ground select line GSL, the erase control line ECL, and the common-source line CSL to program the first cell transistor. In response to the erase command ERS, control logic circuitry 123 may control the row decoder 121, the voltage generator 122, and the input / output circuitry 124 such that the cell transistors of the cell string are erased. In this way, the line decoder 121 and the input / output circuit 124 can control the serial select line SSL, word line WL, ground select line GSL, erase control line ECL and common source line CSL to erase the unit transistors.

[0037] In an erase operation associated with a cell string, the GIDL current can be increased by programming the first cell transistor before the erase operation. In this case, a GIDL current of the desired magnitude can be generated, and the erase operation can be performed normally on the cell transistor.

[0038] Figures 3A to 3C The exemplary embodiments shown are included in the present invention. Figure 2 The circuit diagram of the memory block in the memory cell array. Figures 3A to 3C The structures of the first memory block BLK1, the second memory block BLK2, and the third memory block BLK3 are exemplary structures of a three-dimensional memory block, and the inventive concept is not limited thereto.

[0039] refer to Figure 3A The first memory block BLK1 may include multiple cell strings CS11, CS12, CS21, and CS22. Cell strings CS11, CS12, CS21, and CS22 can be arranged in both row and column directions. For simplicity, in... Figure 3A The diagram shows four unit strings CS11, CS12, CS21, and CS22, but the inventive concept is not limited thereto. For example, the number of unit strings can be increased or decreased in the row or column direction.

[0040] Cell strings belonging to the same column can be connected to the same bit line. For example, cell strings CS11 and CS21 can be connected to the first bit line BL1, and cell strings CS12 and CS22 can be connected to the second bit line BL2.

[0041] Each of the multiple cell strings CS11, CS12, CS21, and CS22 may include multiple cell transistors, each of which includes a charge-trap flash (CTF) memory cell. Multiple cell transistors may be stacked in a height direction, wherein the height direction is perpendicular to a plane (e.g., a semiconductor substrate) defined by row and column directions.

[0042] In each cell string, multiple cell transistors can be connected in series between a corresponding bit line (e.g., BL1 or BL2) and the common-source line CSL. For example, in each cell string, the multiple cell transistors may include string select transistors SST1 and SST2, memory cells MC1, MC2, MC3, and MC4, a ground select transistor GST, and an erase control transistor ECT. The series-connected string select transistors SST1 and SST2 can be positioned between the series-connected memory cells MC1 to MC4 and their corresponding bit lines (e.g., BL1 or BL2). The ground select transistor GST can be positioned between the series-connected memory cells MC1 to MC4 and the erase control transistor ECT. The erase control transistor ECT can be positioned between the ground select transistor GST and the common-source line CSL.

[0043] In multiple cell strings CS11, CS12, CS21, and CS22, memory cells located at the same height from memory cells MC1 through MC4 can share the same word line. For example, the first memory cell MC1 of the multiple cell strings CS11, CS12, CS21, and CS22 can be located at the same height from the substrate and can share the first word line WL1. The second memory cell MC2 of the multiple cell strings CS11, CS12, CS21, and CS22 can be located at the same height from the substrate and can share the second word line WL2. Similarly, the third memory cell MC3 of the multiple cell strings CS11, CS12, CS21, and CS22 can be located at the same height from the substrate and can share the third word line WL3, and the fourth memory cell MC4 of the multiple cell strings CS11, CS12, CS21, and CS22 can be located at the same height from the substrate and can share the fourth word line WL4.

[0044] In multiple cell strings CS11, CS12, CS21, and CS22, string select transistors located at the same height and belonging to the same row can share the same string select line. For example, string select transistor SST1 of cell strings CS11 and CS12 can share string select line SSL1a, and string select transistor SST2 of cell strings CS11 and CS12 can share string select line SSL2a. Similarly, string select transistor SST1 of cell strings CS21 and CS22 can share string select line SSL1b, and string select transistor SST2 of cell strings CS21 and CS22 can share string select line SSL2b.

[0045] In multiple cell strings CS11, CS12, CS21, and CS22, ground selection transistors belonging to the same row from the ground selection transistor GST can share the same ground selection line. For example, the ground selection transistors GST of cell strings CS11 and CS12 can be connected to the ground selection line GSLa, and the ground selection transistors GST of cell strings CS21 and CS22 can share the ground selection line GSLb. Furthermore, the ground selection transistors GST of multiple cell strings CS11, CS12, CS21, and CS22 can share the same ground selection line.

[0046] The erase control transistors (ECTs) of multiple cell strings CS11, CS12, CS21, and CS22 can share the same erase control line (ECL). In an exemplary embodiment of the present invention, the erase control transistors (ECTs) can be configured to generate a GIDL current during an erase operation associated with the first memory block BLK1.

[0047] Figure 3AThe first memory block BLK1 shown is merely exemplary. For example, the number of cell strings can be increased or decreased, and the number of rows and columns of cell strings can be increased or decreased depending on the number of cell strings. Additionally, the number of cell transistors (e.g., SST, MC, GST, and / or ECT) in the first memory block BLK1 can be increased or decreased. For example, cell string CS11 may include two or more erase control transistors ECT between the ground select transistor GST and the common-source line CSL. The height of the first memory block BLK1 can be increased or decreased depending on the number of cell transistors. Furthermore, when the number of cell transistors increases or decreases, the number of lines connected to the cell transistors (e.g., GSL, WL, DWL, and / or SSL) can be increased or decreased.

[0048] refer to Figure 3B The second memory block BLK2 may include multiple cell strings CS11, CS12, CS21, and CS22. These cell strings can be arranged in both row and column directions. Cell strings belonging to the same column can be connected to the same bit line. For example, cell strings CS11 and CS21 can be connected to the first bit line BL1, and cell strings CS12 and CS22 can be connected to the second bit line BL2.

[0049] Each of the multiple cell strings CS11, CS12, CS21, and CS22 may include multiple cell transistors. In each cell string, the multiple cell transistors may be connected in series between a corresponding bit line and a common-source line CSL. In an exemplary embodiment of the inventive concept, in each cell string, the multiple cell transistors may include an erase control transistor ECT, string select transistors SST1 and SST2, memory cells MC1 to MC4, and a ground select transistor GST. The cell transistors in each cell string may be connected to corresponding lines (e.g., ECL, SSL1a, SSL1b, SSL2a, SSL2b, WL1 to WL4, GSLa, and GSLb).

[0050] and Figure 3A The first memory block BLK1 is different. Figure 3BThe second memory block BLK2 may include an erase control transistor ECT disposed between series-connected string select transistors SST1 and SST2 and corresponding bit lines (e.g., BL1 or BL2). In each cell string, the string select transistors SST1 and SST2 may be disposed between the erase control transistor ECT and the series-connected memory cells MC1 to MC4. A ground select transistor GST may be disposed between the series-connected memory cells MC1 to MC4 and the common-source line CSL. In an exemplary embodiment of the inventive concept, the erase control transistor ECT may be configured to generate a GIDL current during an erase operation associated with the second memory block BLK2.

[0051] refer to Figure 3C The third memory block BLK3 may include multiple cell strings CS11, CS12, CS21, and CS22. Multiple cell strings CS11, CS12, CS21, and CS22 can be arranged in both row and column directions. Cell strings belonging to the same column can be connected to the same bit line. For example, cell strings CS11 and CS21 can be connected to the first bit line BL1, and cell strings CS12 and CS22 can be connected to the second bit line BL2.

[0052] Each of the multiple cell strings CS11, CS12, CS21, and CS22 may include multiple cell transistors. In each cell string, the multiple cell transistors may be connected in series between a corresponding bit line and a common-source line CSL. In an exemplary embodiment of the inventive concept, in each cell string, the multiple cell transistors may include erase control transistors ECT1 and ECT2, string select transistors SST1 and SST2, memory cells MC1 to MC4, and a ground select transistor GST. The cell transistors in each cell string may be connected to corresponding lines (e.g., ECL1, ECL2, SSL1a, SSL1b, SSL2a, SSL2b, WL1 to WL4, GSLa, and GSLb).

[0053] and Figure 3A The first memory block BLKl and Figure 3B The second memory block BLK2 is different. Figure 3CThe third memory block BLK3 may include erase control transistors ECT1 and ECT2 positioned at different heights. In each cell string, erase control transistor ECT2 may be positioned between a corresponding bit line (e.g., BL1 or BL2) and series-connected string select transistors SST1 and SST2. String select transistors SST1 and SST2 may be positioned between erase control transistor ECT2 and series-connected memory cells MC1 to MC4. Ground select transistor GST may be positioned between series-connected memory cells MC1 to MC4 and erase control transistor ECT1. Erase control transistor ECT1 may be positioned between ground select transistor GST and the common-source line CSL. In other words, erase control transistor ECT1 may be placed closer to the common-source line CSL than erase control transistor ECT2. In an exemplary embodiment of the inventive concept, erase control transistors ECT1 and ECT2 may generate GIDL current during an erase operation associated with the third memory block BLK3.

[0054] As mentioned above, included Figure 2 The cell strings in the memory cell array 110 may include at least one erase control transistor ECT. The erase control transistor ECT may be positioned between the ground select transistor GST and the common source line CSL, or it may be positioned between the string select transistor SST and the bit line BL. However, the inventive concept is not limited thereto.

[0055] Figure 4 This illustrates exemplary embodiments of the invention and includes [the following]. Figure 2 A flowchart illustrating the erase operations associated with a string of cells in a memory cell array. (Reference) Figures 2 to 4 In operation S101, the non-volatile memory device 100 can program the erase control transistor ECT. For example, the non-volatile memory device 100 can program the erase control transistor ECT based on data "DATA" provided from an external source, or it can program the erase control transistor ECT based on data with a given value (e.g., dummy data).

[0056] For example, non-volatile memory device 100 can receive a command CMD, an address ADDR, and data “DATA” to program the erase control transistor ECT. Control logic circuitry 123 can control line decoder 121, voltage generator 122, and input / output circuitry 124 in response to the command CMD. Voltage generator 122 can provide various voltages for programming operations to line decoder 121 and input / output circuitry 124. Line decoder 121 can apply relevant voltages to lines (e.g., SSL, WL, GSL, ECL, and CSL) to program the erase control transistor ECT corresponding to address ADDR. Additionally, input / output circuitry 124 can apply voltages to relevant bit lines BL. Based on these bias conditions, the erase control transistor ECT can be programmed.

[0057] For example, such as Figure 3C As shown, when each of the multiple cell strings CS11, CS12, CS21, and CS22 includes multiple erase control transistors ECT1 and ECT2, the non-volatile memory device 100 can program at least one of the multiple erase control transistors ECT1 and ECT2. For example, the non-volatile memory device 100 can program only the erase control transistor ECT1 based on the command CMD and the address ADDR. Alternatively, the non-volatile memory device 100 can program only the erase control transistor ECT2 based on the command CMD and the address ADDR. Alternatively, the non-volatile memory device 100 can program both the erase control transistors ECT1 and ECT2 based on the command CMD and the address ADDR.

[0058] After the erase control transistor ECT is programmed, in operation S102, the non-volatile memory device 100 can perform an erase operation on the cell string including the erase control transistor ECT. For example, the non-volatile memory device 100 can erase memory cells included in the cell string. For example, when the erase control transistor ECT of cell string CS11 is programmed, the non-volatile memory device 100 can erase memory cells MC1 to MC4 included in cell string CS11. The erase operation can be performed on a memory block including cell strings, but the inventive concept is not limited thereto.

[0059] For example, non-volatile memory device 100 can receive a command CMD and an address ADDR to erase memory cells of a cell string. When the erase operation is performed on a block-by-block basis, the address ADDR can correspond to a memory block that includes the cell string. Control logic circuitry 123 can control row decoder 121, voltage generator 122, and input / output circuitry 124 in response to command CMD. Voltage generator 122 can provide various voltages for the erase operation to row decoder 121 and input / output circuitry 124. Row decoder 121 can apply relevant voltages to lines (e.g., SSL, WL, GSL, ECL, and CSL) to erase the memory block containing the cell string. Additionally, input / output circuitry 124 can apply voltages to the bit lines of the memory block. Based on the above bias conditions, memory cells of a cell string can be erased.

[0060] Reference Figures 5 to 8 A more detailed description of the operation of programming the erase control transistor ECT, in other words, Figure 4 Operation S101. For ease of description, it will be described as follows: Figure 3A The erase control transistor ECT shown is configured to describe the programming operation with the ground selection transistor GST and the common source line CSL between them, but the inventive concept is not limited thereto.

[0061] Figure 5 This is a timing diagram illustrating the voltage applied to program the erase control transistor according to an exemplary embodiment of the present invention. (Reference) Figure 5 The non-volatile memory device 100 can Figure 5 A voltage is applied to lines BL, SSL, WL, GSL, ECL, and CSL to program the erase control transistor ECT.

[0062] For example, refer to Figure 2 and Figure 5 The bit line BL, ground select line GSL, and common source line CSL can be maintained at the level of the ground voltage Vss. At the first time t1, the row decoder 121 can apply the power supply voltage Vcc to the serial select line SSL. The power supply voltage Vcc can be a high voltage used to turn on the serial select transistor connected to the serial select line SSL. When the serial select transistor is turned on, the channel connected to the serial select line SSL can be initialized. In other words, the channel voltage of the cell string can be set to the voltage level corresponding to the ground voltage Vss.

[0063] At the second time t2, the line decoder 121 can apply the pass voltage Vpass to all word lines WL and the erase control line ECL. At the third time t3, the line decoder 121 can apply the programming voltage Vpgm to the erase control line ECL. Figure 5As shown, the programming voltage Vpgm can be greater than the pass voltage Vpass. Based on the above bias conditions, the erase control transistor ECT connected to the erase control line ECL can be programmed. At the fourth time t4, the programming voltage Vpgm applied to the erase control line ECL can be restored. At the fifth time t5, all applied voltages can be restored.

[0064] Figure 6 This illustrates an exemplary embodiment of the concept according to the present invention. Figure 3A The image shows a view of the structure of the cell strings in the first memory block. (Reference) Figure 3A and Figure 6 The cell string CS may include a post PL extending in a direction perpendicular to the substrate SUB and in contact with the substrate SUB. Each of the erase control line ECL, ground select line GSL, word line WL, and string select line SSL may be formed of a conductive material (e.g., a metallic material). The erase control line ECL, ground select line GSL, word line WL, and string select line SSL may be arranged parallel to the substrate SUB. The post PL may be in contact with the substrate SUB through the conductive material forming the string select line SSL, word line WL, ground select line GSL, and erase control line ECL. In an exemplary embodiment of the inventive concept, the width of the post PL or the cross-sectional area of ​​the post PL parallel to the upper surface of the substrate SUB may be reduced as the distance from the substrate SUB decreases. In other words, the width of the post PL near the string select line SSL is greater than the width of the post PL near the substrate SUB.

[0065] Figure 7 This is a view illustrating the structure of an erase control transistor according to an exemplary embodiment of the concept of the present invention. For example, Figure 7 It is along Figure 6 A cross-sectional view of the erase control transistor ECT, taken along line A-A', corresponding to an erase control line ECL. The pillar PL may include a cylindrical body BD. An air gap AG may be disposed within the body BD. The body BD may include P-type silicon and may be the region in which a channel will be formed. The pillar PL may also include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge-harvesting layer CT surrounding the tunnel insulating layer TI. A blocking insulating layer BI may be disposed between the erase control line ECL and the pillar PL. The body BD, tunnel insulating layer TI, charge-harvesting layer CT, blocking insulating layer BI, and erase control line ECL may constitute a charge-harvesting transistor formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB. The string select transistors SST1 and SST2 of the cell string CS, the memory cells MC1 to MC4, and the ground select transistor GST may have the same structure as the erase control transistor ECT.

[0066] In an exemplary embodiment of the present invention, when the erase control transistor ECT is programmed, the number of electrons captured in the charge-collecting layer CT can be increased. In this case, during the erase operation, the captured electrons can allow an increase in the electric field of the tunnel insulating layer TI, and band-to-band tunneling (BTBT) can be activated. This increases the number of holes supplied to the channel formed in the body BD, and increases the GIDL current generated at the erase control transistor ECT. Therefore, the body (BD) voltage of the cell string CS can be increased.

[0067] Figure 8 This is a diagram illustrating the threshold voltage distribution of an erase control transistor, which is altered by programming operations according to an exemplary embodiment of the present invention. (Reference) Figure 8 Before the erase control transistor is programmed, the erase control transistor connected to the erase control line ECL can have a first threshold voltage distribution Vth1. When the erase control transistor is programmed according to the reference... Figures 4 to 7 During the programming operation described, the erase control transistor may have a second threshold voltage distribution Vth2. In this case, the second threshold voltage distribution Vth2 may be at a higher level than the first threshold voltage distribution Vth1.

[0068] The erase control transistor ECT can be programmed according to an exemplary embodiment of the present invention, such that the second threshold voltage distribution Vth2 is a reference voltage Vr or greater. The reference voltage Vr can be a voltage that allows the GIDL current flowing at the erase control transistor ECT to be a reference current or greater. In other words, when the threshold voltage of the erase control transistor ECT is the reference voltage Vr or greater, the GIDL current flowing at the erase control transistor ECT can be increased to the reference current or greater. In an exemplary embodiment of the present invention, after the erase control transistor ECT is programmed, the threshold voltage of the erase control transistor ECT can be verified based on the reference voltage Vr.

[0069] As described above, the non-volatile memory device 100 according to an exemplary embodiment of the present invention can program the erase control transistor(s) of the cell string to be erased. When the erase control transistor is programmed, the number of holes supplied to the channel of the cell string can be increased, and the GIDL current generated at the erase control transistor ECT can be increased. Therefore, a channel voltage with an amplitude sufficient to implement the erase operation can be provided.

[0070] Below, we will refer to Figures 9A to 11 A more comprehensive description of the erase operation associated with the cell string, in other words, Figure 4 Operation S102.

[0071] Figures 9A to 9C This is a diagram illustrating an erasure bias for performing an erasure operation according to an exemplary embodiment of the concept of the present invention. For example, Figure 9A It shows the method for having Figure 3A An example of an erase bias for performing an erase operation on a string of cells in a structure. Figure 9B It shows the method for having Figure 3B An example of an erase bias for performing an erase operation on a string of cells in a structure. Figure 9C It shows the method for having Figure 3C An example of an erase bias for performing an erase operation on a string of cells in a structure.

[0072] refer to Figure 2 , Figure 3A and Figure 9A After the erase control transistor ECT, which is located between the ground selection transistor GST and the common source line CSL, is programmed, the non-volatile memory device 100 can bias lines BL1, BL2, SSL1, SSL2, WL1 to WL4, GSL, ECL and CSL to perform an erase operation on a string of cells (e.g., a memory block) including the erase control transistor ECT.

[0073] For example, bit lines BL1 or BL2 connected to the cell string, string select lines SSL1 and SSL2 connected to string select transistors SST1 and SST2, and ground select line GSL connected to ground select transistor GST can be floated. The row decoder 121 can apply a ground voltage Vss to word lines WL1 to WL4 connected to memory cells MC1 to MC4. The row decoder 121 can apply an erase voltage Vers to the common-source line CSL connected to the cell string. The row decoder 121 can apply a GIDL voltage Vgidl to the erase control line ECL connected to the erase control transistor ECT. Here, the GIDL voltage Vgidl can be less than the erase voltage Vers and greater than the ground voltage Vss.

[0074] Based on the erase bias described above, the channels of the cell string can be charged, and holes can be supplied from the charged channels to the charge-collecting layers of memory cells MC1 to MC4 through the tunnel insulating layer. The supplied holes can be combined with electrons in the charge-collecting layers of memory cells MC1 to MC4. In this case, the charge in the charge-collecting layers can be reduced, thus erasing the memory cells MC1 to MC4 of the cell string.

[0075] The GIDL voltage Vgidl applied to the erase control line ECL can be a specified voltage. When the GIDL voltage Vgidl is greater than the specified voltage, it can be increased. Figure 7The electric field of the blocking insulating layer BI is increased. In this case, back-tunneling can be increased, thus reducing the time-dependent dielectric breakdown (TDDB) of the erase control transistor ECT. Therefore, according to an exemplary embodiment of the present invention, the GIDL voltage Vgidl applied to the erase control line ECL can be a voltage that minimizes the increase in the electric field of the blocking insulating layer BI of the erase control transistor ECT. Therefore, the TDDB of the erase control transistor ECT can be improved.

[0076] refer to Figure 2 , Figure 3B and Figure 9B After the erase control transistor ECT, which is set between the string select transistors SST1 and SST2 and the bit line BL1 or BL2, is programmed, the non-volatile memory device 100 can bias the lines BL1, BL2, ECL, SSL1, SSL2, WL1 to WL4, GSL and CSL to perform an erase operation on the cell string including the erase control transistor ECT.

[0077] For example, the string select lines SSL1 and SSL2 connected to string select transistors SST1 and SST2, and the ground select line GSL connected to the ground select transistor GST, can be floated. The row decoder 121 can apply a ground voltage Vss to the word lines WL1 to WL4 connected to memory cells MC1 to MC4. The common-source line CSL connected to the cell string can be floated. The row decoder 121 can apply the GIDL voltage Vgidl to the erase control line ECL connected to the erase control transistor ECT. Figure 9B The GIDL voltage Vgidl is similar to Figure 9A The GIDL voltage Vgidl is used, therefore additional descriptions will be omitted to avoid redundancy. Input / output circuitry 124 can apply the erase voltage Vers to bit lines BL1 or BL2 connected to the cell string. See reference... Figure 9A As described, it can be found Figure 9B The memory cells MC1 to MC4 of the cell string are erased under the erase bias.

[0078] refer to Figure 2 , Figure 3C and Figure 9CAfter the erase control transistor ECT1, which is located between the ground selection transistor GST and the common source line CSL, and the erase control transistor ECT2, which is located between the string selection transistors SST1 and SST2 and the bit line BL1 or BL2, are programmed, the non-volatile memory device 100 can bias the lines BL1, BL2, ECL2, SSL1, SSL2, WL1 to WL4, GSL, ECL1, and CSL to perform an erase operation on the cell string including the erase control transistor ECT.

[0079] For example, the string select lines SSL1 and SSL2 connected to string select transistors SST1 and SST2, and the ground select line GSL connected to the ground select transistor GST, can be floated. The row decoder 121 can apply a ground voltage Vss to the word lines WL1 to WL4 connected to memory cells MC1 to MC4. The row decoder 121 can apply an erase voltage Vers to the common-source line CSL connected to the cell string. The row decoder 121 can apply the GIDL voltage Vgidl to the erase control lines ECL1 and ECL2 connected to erase control transistors ECT1 and ECT2. Figure 9C The GIDL voltage Vgidl is similar to Figure 9A The GIDL voltage Vgidl is used, therefore additional descriptions will be omitted to avoid redundancy. Input / output circuitry 124 can apply the erase voltage Vers to bit lines BL1 or BL2 connected to the cell string. See reference... Figure 9A As described, it can be found Figure 9C The memory cells MC1 to MC4 of the cell string are erased under the erase bias.

[0080] refer to Figure 9C The example described applies an erase voltage Vers to Figure 3C Both bit lines BL1 or BL2 and the common-source line CSL in the cell string. However, as referenced... Figure 9A or Figure 9B As described, about Figure 3C The cell string allows an erase voltage Vers to be applied to either bit line BL1 or BL2 and the common-source line CSL, while the other bit can be floated. For example, the erase voltage Vers can be applied to bit line BL1, and the common-source line CSL can be floated.

[0081] Figure 10 This is a timing diagram illustrating the voltage applied for an erase operation according to an exemplary embodiment of the invention. For ease of description, in Figure 10 Only the erase voltage Vers and the GIDL voltage Vgidl are shown in the figure, but the concept of the present invention is not limited thereto.

[0082] refer to Figure 10At the first time t1, an erase voltage Vers can be applied to at least one of the bit line BL and the common-source line CSL. After applying the erase voltage Vers, at the second time t2, a GIDL voltage Vgidl can be applied to the erase control line ECL. In other words, the GIDL voltage Vgidl can be applied after the erase voltage Vers has been applied and a specified time has elapsed. At the third time t3, the applied voltages Vers and Vgidl can be restored. See reference... Figures 9A to 9C As described, when the erase voltage Vers and the GIDL voltage Vgidl are applied, the memory cells MC1 to MC4 of the cell string can be erased.

[0083] Figure 11 This is a diagram illustrating the threshold voltage distribution of a memory cell altered by an erase operation, according to an exemplary embodiment of the present invention. (Reference) Figure 11 When the erase control transistor is not programmed, the memory cell connected to the word line may have a first threshold voltage distribution VV1. According to an exemplary embodiment of the present invention, when the erase control transistor is programmed, the memory cell connected to the word line may have a second threshold voltage distribution VV2.

[0084] like Figure 11 As shown, because the first threshold voltage distribution VV1 is wider than the second threshold voltage distribution VV2, the first threshold voltage distribution VV1 can include a relatively higher threshold voltage (e.g., Vth). In other words, when the erase control transistor is not programmed, there may be memory cells that have not been correctly erased. Conversely, because the second threshold voltage distribution VV2 is narrower than the first threshold voltage distribution VV1, the first threshold voltage distribution VV1 can include a relatively lower threshold voltage (e.g., Vth). In other words, when the erase control transistor is programmed, the reliability of the erase operation can be improved.

[0085] As described above, the non-volatile memory device 100 according to an exemplary embodiment of the present invention can perform an erase operation by using a GIDL current. The non-volatile memory device 100 can program the erase control transistor before performing the erase operation, thus increasing the GIDL current. Therefore, the reliability of the erase operation can be improved.

[0086] Figure 12 This is a block diagram illustrating a storage system including a non-volatile memory device according to an exemplary embodiment of the present invention. (Reference) Figure 12 The storage system 2000 may include a host 2100 and a storage device 2200.

[0087] Storage device 2200 exchanges signals SIG with host 2100 via signal connector 2201 and is supplied with power PWR via power connector 2202. Storage device 2200 includes a Solid State Drive (SSD) controller 2210, a plurality of non-volatile memories 2221 to 222n, an auxiliary power supply 2230, and a buffer memory 2240. In an exemplary embodiment of the present invention, each of the non-volatile memories 2221 to 222n may include a reference... Figures 1 to 10 Any of the non-volatile memory devices described.

[0088] SSD controller 2210 can control non-volatile memories 2221 to 222n in response to a signal SIG received from host 2100. Non-volatile memories 2221 to 222n can operate under the control of SSD controller 2210. In an exemplary embodiment of the inventive concept, SSD controller 2210 may be a reference... Figure 1 The memory controller is described. An auxiliary power supply 2230 is connected to the host 2100 via a power connector 2202. The auxiliary power supply 2230 can be charged by power supplied from the host 2100 via a power PWR. When power is not being supplied smoothly from the host 2100, the auxiliary power supply 2230 can supply power to the storage device 2200.

[0089] A non-volatile memory device according to an exemplary embodiment of the present invention can perform an erase operation using a GIDL current. In this case, the GIDL current generated for the erase operation can be increased, thereby improving GIDL efficiency. Therefore, the threshold voltage distribution of the memory cells formed by the erase operation can be improved, and the reliability of the erase operation can be enhanced.

[0090] Furthermore, the non-volatile memory device according to an exemplary embodiment of the present invention can reduce the TDDB of the erase control transistor used to generate the GIDL current.

[0091] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A method of operating a non-volatile memory device, wherein the non-volatile memory device includes a cell string, wherein the cell string includes a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method comprising: Program the erase control transistor in the plurality of unit transistors; as well as After the erase control transistor is programmed, an erase voltage is applied to the common source line or the bit line, and an erase control voltage is applied to the erase control line connected to the erase control transistor. Wherein, the erasure control voltage is less than the erasure voltage but greater than the ground voltage, and The erase control transistor is located between the ground selection transistor and the common source line in the plurality of unit transistors, or between the string selection transistor and the bit line in the plurality of unit transistors.

2. The method according to claim 1, wherein, Programming the erase control transistor includes: The ground voltage is applied to the bit line and the common source line, and the programming voltage is applied to the erase control line.

3. The method according to claim 1, wherein, The erase control transistor is programmed to increase the threshold voltage of the erase control transistor.

4. The method according to claim 3, wherein, The increased threshold voltage of the erase control transistor causes an increase in the gate-induced drain leakage (GIDL) current from the erase control transistor.

5. The method according to claim 1, further comprising: When the erase control transistor is between the ground select transistor and the common source line, after the erase control transistor is programmed, the erase voltage is applied to the common source line and the bit line is floated.

6. The method according to claim 1, further comprising: When the erase control transistor is between the string select transistor and the bit line, after the erase control transistor is programmed, the erase voltage is applied to the bit line and the common source line is floated.

7. The method according to claim 1, further comprising: After the erase control transistor is programmed, the ground select line connected to the ground select transistor and the string select line connected to the string select transistor are floated.

8. A non-volatile memory device, comprising: A memory cell array includes a cell string, wherein the cell string includes a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to the substrate. The line decoder is configured to control the common source line and the erase control line connected to the erase control transistor in the plurality of unit transistors; Input / output circuitry is configured to control the bit lines; as well as Control logic circuit, In the erase operation associated with the cell string, the control logic circuit controls the row decoder and the input / output circuit to program the erase control transistor, and then controls the row decoder and the input / output circuit to apply an erase voltage to the common-source line or the bit line and an erase control voltage to the erase control line. Wherein, the erasure control voltage is less than the erasure voltage but greater than the ground voltage, and The erase control transistor is located between the ground selection transistor and the common source line in the plurality of unit transistors, or between the string selection transistor and the bit line in the plurality of unit transistors.

9. The non-volatile memory device according to claim 8, wherein, In the programming operation associated with the erase control transistor, the line decoder applies the ground voltage to the common source line and the programming voltage to the erase control line, and the input / output circuit applies the ground voltage to the bit line.

10. The non-volatile memory device according to claim 8, wherein, The erase control transistor is programmed such that its threshold voltage is increased to at least the reference voltage.

11. The non-volatile memory device according to claim 10, wherein, The reference voltage is the voltage that allows the gate-induced drain leakage (GIDL) current from the erase control transistor to increase.

12. The non-volatile memory device according to claim 8, wherein, After the erase control transistor is programmed during the erase operation, the control logic circuit controls the line decoder such that the ground select line connected to the ground select transistor and the string select line connected to the string select transistor are floated.

13. A storage system, comprising: A non-volatile memory device includes a cell string, wherein the cell string includes a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate. as well as The memory controller is configured to provide a first command and a second command to the non-volatile memory device. Wherein, after programming the erase control transistor among the plurality of cell transistors in response to the first command, the non-volatile memory device is configured to, in response to the second command, apply an erase voltage to the common-source line or the bit line and apply an erase control voltage to the erase control line connected to the erase control transistor. Wherein, the erasure control voltage is less than the erasure voltage but greater than the ground voltage, and The erase control transistor is located between the ground selection transistor and the common source line in the plurality of unit transistors, or between the string selection transistor and the bit line in the plurality of unit transistors.

14. The storage system according to claim 13, wherein, In response to the first command, the non-volatile memory device applies the ground voltage to the common source line and the bit line, and applies the programming voltage to the erase control line.

15. The storage system according to claim 13, wherein, The erase control transistor is programmed such that its threshold voltage is increased to a reference voltage or greater.

16. The storage system according to claim 15, wherein, The reference voltage is a voltage that allows the gate-induced drain leakage (GIDL) current from the erase control transistor to become a reference current or a larger voltage.

17. The storage system according to claim 13, wherein, When the erase control transistor is between the ground select transistor and the common source line, in response to the second command, the non-volatile memory device applies the erase voltage to the common source line and floats the bit line.

18. The storage system according to claim 13, wherein, When the erase control transistor is between the string select transistor and the bit line, in response to the second command, the non-volatile memory device applies the erase voltage to the bit line and floats the common source line.

19. The storage system according to claim 13, wherein, In response to the second command, the non-volatile memory device floats the ground select line connected to the ground select transistor and the string select line connected to the string select transistor.

20. The storage system according to claim 13, wherein, Another erase control transistor, which includes the memory block of the cell string, is connected to the erase control line.

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