Semiconductor integrated circuits

Abstract

The invention comprises: a phase synchronization circuit, which is synchronized with a reference clock signal and generates a synchronization clock signal obtained by multiplying the reference clock signal; an edge detection circuit, which detects the edge at which the signal waveform of the reference clock signal changes at the timing of the synchronization clock signal and outputs an edge detection signal indicating the timing at which the edge is detected; and a clock frequency division circuit, which is reset at a timing corresponding to the edge detection signal and generates a divided clock signal obtained by dividing the synchronization clock signal.

Description

Technical Field

[0001] The present invention relates to semiconductor integrated circuits. Background Art

[0002] There is a device that is equipped with a large-scale semiconductor integrated circuit such as ASIC (Application Specific Integrated Circuit) that activates various circuit elements formed on a semiconductor substrate to achieve predetermined functions. In such a device, various structural elements (digital circuits, analog circuits, etc.) including the above-mentioned semiconductor integrated circuits such as ASIC are installed on a system substrate used to constitute the device, and each structural element installed on the system substrate shares a power supply. In addition, among the structural elements constituting such a device, there are also structural elements that operate based on a clock signal of a predetermined frequency. Therefore, on the system substrate of the device, a clock supply circuit that supplies a clock signal of a predetermined frequency oscillated by a quartz resonator or a quartz oscillator to each structural element is also installed. Moreover, in such a device, the clock supply circuit installed on the system substrate also shares a power supply like other structural elements.

[0003] However, in semiconductor integrated circuits such as ASICs, when the output signal output by the circuit elements formed on the semiconductor substrate according to the input signal changes from one state (level) to another state (level), currents such as the through current and the charge and discharge current for the load flow between the power supply and the ground line. Moreover, the more the number of circuit elements that simultaneously output the output signal, the more current flows between the power supply and the ground line in the semiconductor integrated circuit. The current flowing between the power supply and the ground line in such a semiconductor integrated circuit becomes the power supply noise (self-noise) generated by the semiconductor integrated circuit, which affects the power supply of each structural element mounted on the system substrate.

[0004] In particular, the power supply noise generated when the circuit elements that operate based on the input clock signal, that is, the circuit elements that operate synchronously with the clock signal, among the circuit elements formed on the semiconductor substrate, operate, flows at a timing synchronized with the clock signal. Therefore, the power supply noise synchronized with the clock signal generated by the semiconductor integrated circuit increases the variation (jitter) of the clock signal supplied (distributed) to each structural element and circuit element by the clock supply circuit of the shared power supply and the clock buffer circuit formed in the semiconductor substrate. This is because, for example, in the clock buffer circuit, if power supply noise is generated when the input clock signal changes from the "Low" level to the "High" level, the threshold voltage of the gate terminal (the so-called gate threshold voltage Vth) specified in the transistor constituting the clock buffer circuit changes due to the influence of the power supply noise, and the delay time when the clock signal passes through the clock buffer circuit changes.

[0005] Furthermore, in the system of the device, the variation (jitter) of the clock signal caused by the power supply noise generated by the semiconductor integrated circuit has a significant influence on the operation of each component in the system substrate on which the semiconductor integrated circuit is mounted, and becomes a cause of the overall performance of the system of the device to be degraded. Therefore, in the system of the device, in the semiconductor integrated circuit such as ASIC, it is desirable to suppress the generation of power supply noise that causes the increase of the variation (jitter) of the clock signal, or to operate at a timing that does not vary the clock signal (does not cause jitter).

[0006] Therefore, for example, Patent Document 1 discloses a technology for reducing the generation of jitter of a clock signal caused by power supply noise by adjusting the phase of the clock signal. The technology disclosed in Patent Document 1 includes a delay measurement circuit for measuring the delay time of the clock signal, a time measurement circuit for measuring the variation time of the power supply voltage, a delay adjustment circuit for delaying the clock signal, a phase difference measurement circuit for measuring the phase difference of the clock signal, and a phase control circuit for controlling the phase of the clock signal. Furthermore, in the technology disclosed in Patent Document 1, the phase control circuit calculates the phase difference of the clock signal that optimizes the jitter based on the period, variation time, and delay time of the clock signal, and adjusts the delay amount of the delay adjustment circuit so that the phase difference of the clock signal measured by the phase difference measurement circuit becomes the calculated phase difference.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2011-004248 Summary of the invention

[0010] Problem that the invention aims to solve

[0011] However, the technology disclosed in Patent Document 1 is a technology for adjusting the phase difference between two clock signals, and is not a technology for reducing the generation of fluctuations (jitters) of the clock signal that serves as the reference for operation. Moreover, since the technology disclosed in Patent Document 1 is provided with a plurality of measurement circuits for measuring various states in each clock signal, even if it is applied to reduce the generation of fluctuations (jitters) of the clock signal that serves as the reference, the structure becomes complicated. In addition, in the technology disclosed in Patent Document 1, the clock signal needs to be measured, the phase difference needs to be calculated and adjusted each time the system of the device is restored from the reset state, and the startup of the device may be slow.

[0012] The present invention has been made based on the above-mentioned problem recognition, and an object of the present invention is to provide a semiconductor integrated circuit capable of suppressing the variation of a clock signal caused by power supply noise generated in the semiconductor integrated circuit.

[0013] Means used to solve problems

[0014] According to the first scheme of the present invention, the semiconductor integrated circuit comprises: a phase synchronization circuit, which is synchronized with a reference clock signal and generates a synchronization clock signal obtained by multiplying the reference clock signal; an edge detection circuit, which detects an edge at which a signal waveform of the reference clock signal changes at a timing of the synchronization clock signal and outputs an edge detection signal indicating the timing at which the edge is detected; and a clock division circuit, which is reset at a timing corresponding to the edge detection signal and generates a divided clock signal obtained by dividing the synchronization clock signal.

[0015] According to a second aspect of the present invention, in the semiconductor integrated circuit of the first aspect, the edge detection circuit may output the edge detection signal corresponding to one cycle of the synchronous clock signal.

[0016] According to a third aspect of the present invention, the semiconductor integrated circuit of the second aspect may further include a delay adjustment unit that delays the edge detection signal in units of a period of the synchronization clock signal.

[0017] According to the fourth scheme of the present invention, on the basis of the semiconductor integrated circuit of the above-mentioned third scheme, it can also be provided with: a delay unit, which simulates the propagation delay of the path of the divided clock signal to delay the divided clock signal by a time corresponding to the propagation delay; and a phase comparison unit, which compares the phase of the reference clock signal with the divided clock signal after being delayed by the delay unit.

[0018] According to a fifth aspect of the present invention, in the semiconductor integrated circuit of the fourth aspect, the delay adjustment unit may delay the edge detection signal by a period of the synchronous clock signal set based on a phase comparison result of the phase comparison unit.

[0019] According to the sixth scheme of the present invention, on the basis of the semiconductor integrated circuit of the above-mentioned fifth scheme, it can also be that there is also a delay fine-adjustment unit, which delays the divided clock signal by a time within one cycle of the synchronous clock signal, and the delay unit further delays the divided clock signal delayed by the delay fine-adjustment unit by a time corresponding to the propagation delay.

[0020] According to a seventh aspect of the present invention, in the semiconductor integrated circuit of the sixth aspect, the delay fine adjustment section may delay the divided clock signal by a time period set based on a phase comparison result of the phase comparison section.

[0021] According to an eighth aspect of the present invention, the semiconductor integrated circuit of any one of the first to seventh aspects may further include a control unit that causes the edge detection circuit to start detecting the edge.

[0022] According to the 9th scheme of the present invention, on the basis of the semiconductor integrated circuit of any one of the above-mentioned schemes 3 to 7, it can also be provided with a control unit, which enables the edge detection circuit to start detecting the edge and sets the time for delaying the edge detection signal to the delay adjustment unit.

[0023] According to the 10th scheme of the present invention, on the basis of any one of the above-mentioned schemes 4 to 7, the semiconductor integrated circuit may also include a control unit, which enables the edge detection circuit to start detecting the edge, and sets the time for delaying the edge detection signal to the delay adjustment unit based on the phase comparison result of the phase comparison unit.

[0024] According to the 11th scheme of the present invention, on the basis of the semiconductor integrated circuit of the above-mentioned 6th scheme or the above-mentioned 7th scheme, it can also be that there is also a control unit, which enables the edge detection circuit to start detecting the edge, and based on the phase comparison result of the phase comparison unit, sets the time for delaying the edge detection signal for the delay adjustment unit, and sets the time for delaying the divided clock signal for the delay fine adjustment unit.

[0025] Effects of the Invention

[0026] According to the above-described aspects, there is provided an effect that a semiconductor integrated circuit capable of suppressing a variation in a clock signal due to power supply noise generated in the semiconductor integrated circuit can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a diagram for explaining a method of considering phase adjustment of a clock signal in a semiconductor integrated circuit according to the present invention.

[0028] Figure 2 This is a block diagram showing a schematic configuration of a semiconductor integrated circuit in the first embodiment of the present invention.

[0029] Figure 3 This is a timing chart showing the phase adjustment operation in the semiconductor integrated circuit according to the first embodiment of the present invention.

[0030] Figure 4 This is a block diagram showing a schematic configuration of a semiconductor integrated circuit in a second embodiment of the present invention.

[0031] Figure 5This is a block diagram showing an example of a schematic configuration of a delay adjustment unit included in a semiconductor integrated circuit according to a second embodiment of the present invention.

[0032] Figure 6 This is a timing chart showing the phase adjustment operation in the semiconductor integrated circuit according to the second embodiment of the present invention.

[0033] Figure 7 This is a block diagram showing a schematic configuration of a semiconductor integrated circuit in a third embodiment of the present invention.

[0034] Figure 8 This is a diagram showing an example of a schematic configuration of a phase comparison section included in a semiconductor integrated circuit according to a third embodiment of the present invention and an example of the operation of the phase comparison section.

[0035] Fig. 9 This is a block diagram showing a schematic configuration of a semiconductor integrated circuit in a fourth embodiment of the present invention.

[0036] Fig.10 This is a block diagram showing an example of a schematic configuration of a delay fine adjustment unit included in a semiconductor integrated circuit according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the semiconductor integrated circuit of the present invention, by shifting the timing of the level change (transition) of the output signal output by the semiconductor integrated circuit from the timing of the signal waveform change (transition) of the clock signal input to the semiconductor integrated circuit, the variation (jitter) generated in the signal waveform of each clock signal is reduced, and this is taken as a basic consideration method. That is, in the semiconductor integrated circuit of the present invention, the timing generated by the power supply noise (self-noise) that causes the power supply variation in the system substrate of the device (system) equipped with the semiconductor integrated circuit is shifted from the timing of the level change (transition) of the clock signal input to the semiconductor integrated circuit, and this is taken as a basic consideration method. Therefore, in the semiconductor integrated circuit of the present invention, the following adjustment is made: the phase of the clock signal used in the semiconductor integrated circuit generated based on the input clock signal is shifted from the phase of the clock signal input to the semiconductor integrated circuit. That is, in the semiconductor integrated circuit of the present invention, the following adjustment is made: the action timing of the circuit element that acts synchronously with the clock signal is shifted from the timing of the level change (transition) of the clock signal input to the semiconductor integrated circuit.

[0038] First, a basic conception of phase adjustment of a clock signal in a semiconductor integrated circuit of the present invention will be described. Figure 1 FIG. 1 is a diagram for explaining a method for considering phase adjustment of a clock signal in a semiconductor integrated circuit of the present invention. Figure 1In FIG. 1 , the timing of each of the following signals is shown: a clock signal input to a semiconductor integrated circuit as a reference clock signal in a device (system) equipped with the semiconductor integrated circuit of the present invention (hereinafter referred to as a “reference clock signal”), a multi-bit parallel output signal output by the semiconductor integrated circuit, and a clock signal generated from the reference clock signal in the semiconductor integrated circuit and used within the semiconductor integrated circuit (hereinafter referred to as an “internal clock signal”). In addition, in FIG. Figure 1 , the timing of power supply noise (self-noise) of the semiconductor integrated circuit generated along with the change (transition) of the level of the output signal is shown. Figure 1 In (a), the timing of transient current generated as power supply noise is shown when the method of considering phase adjustment in the semiconductor integrated circuit of the present invention is not applied. Figure 1 (b) shows the timing of transient current generated as power supply noise when the method of considering phase adjustment in a semiconductor integrated circuit of the present invention is applied.

[0039] First, use Figure 1 (a) of the present invention is used to describe power supply noise generated by a semiconductor integrated circuit when the method for considering phase adjustment in a semiconductor integrated circuit of the present invention is not applied. Figure 1 As shown in (a), the semiconductor integrated circuit uses the timing of the rising edge (time t01 and time t03) at which the level of the reference clock signal changes (transitions) as a reference, multiplies the reference clock signal, and generates an internal clock signal. Therefore, in a semiconductor integrated circuit that does not apply the method of considering phase adjustment in a semiconductor integrated circuit of the present invention, Figure 1 As shown in (a), the output signal changes in synchronization with each rising edge of the internal clock signal, for example, at time t01, time t02, time t03, etc.

[0040] Therefore, in a semiconductor integrated circuit to which the method of considering phase adjustment in a semiconductor integrated circuit of the present invention is not applied, as Figure 1 As shown in (a), a large amount of transient current flows at the timings (e.g., time t01, time t02, time t03, etc.) synchronized with the rising edges of the internal clock signal. Therefore, a semiconductor integrated circuit to which the method of considering phase adjustment in the semiconductor integrated circuit of the present invention is not applied has a large amount of transient current flowing at the timings (e.g., time t01, time t02, time t03, etc.) synchronized with the rising edges of the internal clock signal. Figure 1 The timings at which the rising edges of the internal clock signals shown in (a) are synchronized (eg, time t01, time t02, time t03, etc.) generate much power supply noise.

[0041] Thus, in a device (system) equipped with a semiconductor integrated circuit to which the method for considering phase adjustment in a semiconductor integrated circuit of the present invention is not applied, due to the influence of power supply noise generated at time t01 and time t03 which are references of the internal clock signal, as shown in FIG. Figure 1 As shown in the transition period J of the reference clock signal in (a), the reference clock signal varies greatly. That is, in a device (system) equipped with a semiconductor integrated circuit to which the phase adjustment method in the semiconductor integrated circuit of the present invention is not applied, jitter occurs at the rising edge of the reference clock signal that serves as the reference of the internal clock signal.

[0042] Next, use Figure 1 (b) describes power supply noise generated in a semiconductor integrated circuit when the method of considering phase adjustment in a semiconductor integrated circuit of the present invention is applied. Figure 1 The timing shown in (b) is also consistent with Figure 1 Similarly, the semiconductor integrated circuit uses the timing of the rising edge (time t01 and time t03) at which the level of the reference clock signal changes (transitions) as a reference to generate an internal clock signal obtained by multiplying the reference clock signal. However, in a semiconductor integrated circuit to which the method of considering phase adjustment in a semiconductor integrated circuit of the present invention is applied, as Figure 1 As shown in (b), the timing of the rising edge of the generated internal clock signal is set to time t11 and time t13, thereby offsetting the timing of the rising edge of the reference clock signal. In other words, in a semiconductor integrated circuit to which the method for considering phase adjustment in a semiconductor integrated circuit of the present invention is applied, the phase of the generated internal clock signal is offset from the phase of the reference clock signal. Therefore, in a semiconductor integrated circuit to which the method for considering phase adjustment in a semiconductor integrated circuit of the present invention is applied, as Figure 1 As shown in (b), the output signal changes in synchronization with each rising edge of the internal clock signal, for example, at time t11, time t12, time t13, etc.

[0043] Furthermore, in a semiconductor integrated circuit to which the method of considering phase adjustment in a semiconductor integrated circuit of the present invention is applied, as Figure 1 As shown in (b), a large amount of transient current also flows at the timings (e.g., time t11, time t12, time t13, etc.) synchronized with each rising edge of the internal clock signal. That is, in the semiconductor integrated circuit to which the phase adjustment consideration method in the semiconductor integrated circuit of the present invention is applied, a large amount of power supply noise is generated at the timings (e.g., time t11, time t12, time t13, etc.) synchronized with each rising edge of the internal clock signal, similarly to the semiconductor integrated circuit to which the phase adjustment consideration method in the semiconductor integrated circuit of the present invention is not applied.

[0044] However, in the semiconductor integrated circuit to which the phase adjustment consideration method in the semiconductor integrated circuit of the present invention is applied, as described above, the timing of the rising edge of the generated internal clock signal is shifted from the timing of the rising edge of the reference clock signal. Therefore, in the semiconductor integrated circuit to which the phase adjustment consideration method in the semiconductor integrated circuit of the present invention is applied, although a large amount of power supply noise is generated at the timing synchronized with each rising edge of the internal clock signal, by setting the timing of generating the power supply noise to the time t11 and the time t13, it becomes the timing that deviates from the timing of the rising edge of the reference clock signal that is the reference of the internal clock signal. That is, in the semiconductor integrated circuit to which the phase adjustment consideration method in the semiconductor integrated circuit of the present invention is applied, unlike the semiconductor integrated circuit to which the phase adjustment consideration method in the semiconductor integrated circuit of the present invention is not applied, the power supply noise is generated during the period when the level of the reference clock signal is stabilized at an arbitrary level, avoiding the rising period when the level of the reference clock signal changes (transitions). Therefore, in the semiconductor integrated circuit to which the phase adjustment consideration method in the semiconductor integrated circuit of the present invention is applied, the influence of the generated power supply noise on the reference clock signal becomes smaller.

[0045] Therefore, in a device (system) equipped with a semiconductor integrated circuit to which the phase adjustment method of the present invention is applied, power supply noise is not generated at time t01 and time t03, which are references of the internal clock signal. Figure 1 As shown in the transition period N of the reference clock signal in (b), the reference clock signal does not vary significantly due to the influence of power supply noise. That is, in a device (system) equipped with a semiconductor integrated circuit to which the phase adjustment consideration method in a semiconductor integrated circuit of the present invention is applied, jitter does not occur at the rising edge of the reference clock signal that serves as a reference for the internal clock signal.

[0046] In this way, in a semiconductor integrated circuit to which the method for considering phase adjustment in a semiconductor integrated circuit of the present invention is applied, the power supply noise (self-noise) that causes fluctuations (jitter) in the rising edge of the reference clock signal is eliminated by shifting the timing of the rising edge of the internal clock signal generated based on the reference clock signal from the timing of the rising edge of the reference clock signal.

[0047] (First embodiment)

[0048] Next, a semiconductor integrated circuit according to a first embodiment of the present invention will be described. Figure 2 This is a block diagram showing a schematic configuration of a semiconductor integrated circuit in the first embodiment of the present invention. Figure 2The semiconductor integrated circuit 1 shown includes a comparator 10, a control unit 20, a system PLL (Phase Locked Loop) 30, a clock frequency division circuit 31, an edge detection circuit 310, a large-scale circuit block 32, and an output buffer 33. In addition, the semiconductor integrated circuit 1 includes a PLL 40, a large-scale circuit block 41, a PLL 50, and an analog circuit 51. In addition, Figure 2 The PLL 40 , large-scale circuit block 41 , PLL 50 , and analog circuit 51 shown use the reference clock signal as a common source, and are shown as an example of a circuit that is affected by the jitter performance of the reference clock signal degraded by fluctuations in power supply noise.

[0049] The semiconductor integrated circuit 1 is a large-scale semiconductor integrated circuit implemented by, for example, an ASIC (Application Specific Integrated Circuit). The semiconductor integrated circuit 1 implements a predetermined function in a device (system) equipped with the semiconductor integrated circuit 1. The semiconductor integrated circuit 1 is mounted on a system substrate for constituting a system of the device, and performs an operation for implementing a predetermined function in the system of the device based on a clock signal of a predetermined frequency output from a clock supply circuit mounted on the same system substrate. Here, as a clock supply circuit mounted on the system substrate, for example, a clock oscillation circuit such as a quartz crystal resonator or a quartz oscillator is considered. In the following description, the case where the clock supply circuit mounted on the system substrate of the device is a quartz crystal resonator and the semiconductor integrated circuit 1 operates based on a clock signal oscillated by the quartz crystal resonator (hereinafter referred to as "original oscillation clock signal Xtal").

[0050] The comparator 10 is a clock buffer circuit that shapes the waveform of the original oscillation clock signal Xtal output by the clock supply circuit (quartz oscillator) and supplies it to the components of the semiconductor integrated circuit 1. The comparator 10 shapes the waveform of the original oscillation clock signal Xtal of a sine wave into a rectangular wave, for example. The comparator 10 supplies the original oscillation clock signal Xtal (hereinafter referred to as the "reference clock signal RCK") after the waveform shaping to the system PLL 30, the edge detection circuit 310, the PLL 40 and the PLL 50 respectively.

[0051] The control unit 20 controls the phase adjustment of the clock signal for operating each component included in the semiconductor integrated circuit 1. The control unit 20 outputs a phase adjustment enable signal EN to the edge detection circuit 310 when performing the phase adjustment of the clock signal.

[0052] In addition, the control unit 20 is also a control unit that controls the overall functions of the semiconductor integrated circuit 1 in order to realize the predetermined functions in the system of the device. The control unit 20 is, for example, a processing device such as a CPU (Central Processing Unit). The control unit 20 controls the overall functions of the semiconductor integrated circuit 1 according to the program and data used to control the various structural elements of the semiconductor integrated circuit 1. In addition, the control unit 20 can also control other structural elements of the system of the device installed on the same system substrate. The program and data used by the control unit 20 to control the various functions of the semiconductor integrated circuit 1 or the various structural elements of the system of the device can also be stored in a storage device such as a memory that is not shown. In this case, the control unit 20 controls the overall functions of the semiconductor integrated circuit 1 and the various structural elements of the system of the device by reading and executing the program and data stored in the memory. In addition, the control unit 20 is not limited to a structure provided in the semiconductor integrated circuit 1, and can also be a structure provided outside the semiconductor integrated circuit 1, that is, installed on the same system substrate.

[0053] The system PLL 30 is a phase synchronization circuit that generates a synchronous clock signal PLLOUT synchronized with the reference clock signal RCK output from the comparator 10. The system PLL 30 generates a synchronous clock signal PLLOUT obtained by multiplying the reference clock signal RCK by an integer multiple, that is, a synchronous clock signal PLLOUT having a frequency higher than that of the reference clock signal RCK. Then, the system PLL 30 outputs the generated synchronous clock signal PLLOUT to the clock frequency division circuit 31 and the edge detection circuit 310.

[0054] The edge detection circuit 310 detects the rising edge of the reference clock signal RCK output from the comparator 10 according to the control from the control unit 20. The edge detection circuit 310 outputs a signal indicating the timing of detecting the rising edge of the reference clock signal RCK to the clock frequency division circuit 31. More specifically, when the phase adjustment enable signal EN is output from the control unit 20, the edge detection circuit 310 detects the first rising edge in the reference clock signal RCK at the timing of the rising edge of the synchronous clock signal PLLOUT. Then, the edge detection circuit 310 outputs a signal indicating the timing of detecting the rising edge of the reference clock signal RCK to the clock frequency division circuit 31 as a synchronous reset signal SR, and the synchronous reset signal SR is used to reset the clock frequency division circuit 31 synchronously with the rising edge of the reference clock signal RCK.

[0055] The clock frequency dividing circuit 31 is a clock frequency dividing circuit that divides the synchronous clock signal PLLOUT output from the system PLL 30 and generates an internal clock signal ICK for operating each circuit element in the corresponding large-scale circuit block 32. The clock frequency dividing circuit 31 generates the internal clock signal ICK obtained by dividing the synchronous clock signal PLLOUT by a predetermined frequency division ratio. Then, the clock frequency dividing circuit 31 outputs the generated internal clock signal ICK to each circuit element in the large-scale circuit block 32.

[0056] In addition, the frequency division operation of the synchronous clock signal PLLOUT in the clock frequency division circuit 31 is reset by the synchronous reset signal SR output from the edge detection circuit 310. In other words, the clock frequency division circuit 31 starts to generate the internal clock signal ICK from the timing when the synchronous reset signal SR is released. Therefore, the internal clock signal ICK generated by the clock frequency division circuit 31 becomes a clock signal synchronized with the timing of the first rising edge of the reference clock signal RCK detected by the edge detection circuit 310 after the control unit 20 outputs the phase adjustment enable signal EN to the edge detection circuit 310.

[0057] The large-scale circuit block 32 is a group of digital circuit elements that realizes a predetermined function in the semiconductor integrated circuit 1 based on the timing of the clock of the internal clock signal ICK output by the clock frequency dividing circuit 31. Each circuit element of the large-scale circuit block 32 realizes the predetermined function at a timing synchronized with the internal clock signal ICK. Moreover, the large-scale circuit block 32 outputs a signal indicating the result of realizing the predetermined function to the output buffer 33 at a timing synchronized with the internal clock signal ICK. In addition, Figure 2 , a structure is shown in which the large-scale circuit block 32 outputs a multi-bit parallel signal indicating a result of realizing a predetermined function to the output buffer 33.

[0058] The output buffer 33 is a buffer circuit that outputs a signal indicating the result of the large-scale circuit block 32 realizing a predetermined function as an output signal OUT in the semiconductor integrated circuit 1 to the outside of the semiconductor integrated circuit 1. As described above, the large-scale circuit block 32 outputs a multi-bit parallel signal indicating the result of realizing the predetermined function to the output buffer 33 at a timing synchronized with the internal clock signal ICK. Therefore, the output buffer 33 also outputs the multi-bit parallel output signal OUT to the outside of the semiconductor integrated circuit 1. Therefore, in the semiconductor integrated circuit 1, the change (transition) in the level of the output signal OUT output by the output buffer 33 may become a cause of power supply noise (self-noise) generated in the semiconductor integrated circuit 1. However, in the semiconductor integrated circuit 1, as described above, phase adjustment is performed to shift the phase of the internal clock signal ICK generated by the clock frequency dividing circuit 31 from the phase of the reference clock signal RCK. Therefore, in the semiconductor integrated circuit 1, the power supply noise (self-noise) generated by the change (transition) in the level of the output signal OUT does not become a cause of jitter in the rising edge of the original oscillation clock signal Xtal oscillating in the clock supply circuit (quartz oscillator) or the reference clock signal RCK output by the comparator 10. Note that detailed description of the phase adjustment operation of the internal clock signal ICK in the semiconductor integrated circuit 1 will be given later.

[0059] The PLL 40 is a phase synchronization circuit that generates a PLL clock signal synchronized with the reference clock signal RCK output from the comparator 10, similarly to the system PLL 30. However, the PLL 40 outputs the generated PLL clock signal to the large-scale circuit block 41. That is, the PLL 40 is a phase synchronization circuit corresponding to a clock path different from that of the system PLL 30.

[0060] The large-scale circuit block 41 is a group of digital circuit elements that realize predetermined functions in the semiconductor integrated circuit 1 at the timing of the clock signal based on the PLL clock signal output by the PLL 40. Each circuit element included in the large-scale circuit block 41 realizes a predetermined function at the timing synchronized with the PLL clock signal output by the PLL 40.

[0061] In addition, Figure 2In order to facilitate the description, the path (signal line) for outputting the result of the large-scale circuit block 41 realizing the predetermined function is omitted. However, the semiconductor integrated circuit 1 may also be configured as follows: similarly to the large-scale circuit block 32, the result of the large-scale circuit block 41 realizing the predetermined function is also output as an output signal to the outside of the semiconductor integrated circuit 1. In this case, the large-scale circuit block 41 outputs a signal indicating the result of realizing the predetermined function to the corresponding output buffer not shown. Thus, the output signal indicating the result of the large-scale circuit block 41 realizing the predetermined function is output from the output buffer not shown. In this way, the level change (transition) of the output signal output to the outside of the semiconductor integrated circuit 1 by the output buffer not shown corresponding to the large-scale circuit block 41 also becomes a cause of the power supply noise (self-noise) generated in the semiconductor integrated circuit 1. In this case, the semiconductor integrated circuit 1 may also include the following structural element, which, similarly to the internal clock signal ICK based on the synchronous clock signal PLLOUT output by the system PLL30, also performs phase adjustment on the clock signal for operating the circuit element of the large-scale circuit block 41, that is, the clock signal based on the PLL clock signal output by the PLL40. That is, the semiconductor integrated circuit 1 may also include a component that performs the same operation as the edge detection circuit 310 and the clock frequency dividing circuit 31 to generate a clock signal based on the PLL clock signal output by the PLL 40. Thus, in the semiconductor integrated circuit 1, power supply noise (self-noise) generated by a change (transition) in the level of an output signal output at a timing based on the PLL clock signal output by the PLL 40 will not cause jitter on the rising edge of the original oscillation clock signal Xtal oscillating in the clock supply circuit (quartz crystal oscillator) or the reference clock signal RCK output by the comparator 10.

[0062] PLL50 is a phase synchronization circuit that generates a PLL clock signal synchronized with the reference clock signal RCK output from the comparator 10, similarly to the system PLL30. However, PLL50 outputs the generated PLL clock signal to the analog circuit 51. That is, PLL50 is a phase synchronization circuit corresponding to a clock path different from that of the system PLL30 or PLL40.

[0063] The analog circuit 51 is a group of analog circuit elements that implement predetermined functions in the semiconductor integrated circuit 1 at the timing of a clock signal based on the PLL clock signal output by the PLL 50. Each circuit element included in the analog circuit 51 implements a predetermined function at a timing synchronized with the PLL clock signal output by the PLL 50.

[0064] In addition, Figure 2In the figure, for ease of explanation, the path (signal line) for outputting the result of the analog circuit 51 realizing the predetermined function is omitted, similarly to the clock path of the large-scale circuit block 41. However, the semiconductor integrated circuit 1 may also be configured as follows: similarly to the large-scale circuit block 32 or the large-scale circuit block 41, the result of the analog circuit 51 realizing the predetermined function is also output as an output signal to the outside of the semiconductor integrated circuit 1. In this case, the analog circuit 51 outputs a signal indicating the result of realizing the predetermined function to a corresponding output buffer not shown. Thus, the output signal indicating the result of the analog circuit 51 realizing the predetermined function is output from the output buffer not shown. In this way, the level change (transition) of the output signal output to the outside of the semiconductor integrated circuit 1 by the output buffer not shown corresponding to the analog circuit 51 also becomes a cause of the power supply noise (self-noise) generated in the semiconductor integrated circuit 1. In this case, the semiconductor integrated circuit 1 may also include a component that performs phase adjustment on a clock signal for operating a circuit element of the analog circuit 51, that is, a clock signal based on the PLL clock signal output by the PLL50, similarly to the internal clock signal ICK based on the synchronous clock signal PLLOUT output by the system PLL30. That is, the semiconductor integrated circuit 1 may also include a component that performs the same operation as the edge detection circuit 310 or the clock frequency division circuit 31 to generate a clock signal based on the PLL clock signal output by the PLL50. Thus, in the semiconductor integrated circuit 1, power supply noise (self-noise) generated by a level change (transition) of an output signal output at a timing of a clock signal based on the PLL clock signal output by the PLL50 will not become a cause of jitter at the rising edge of the original oscillation clock signal Xtal oscillating in the clock supply circuit (quartz oscillator) or the reference clock signal RCK output by the comparator 10.

[0065] Here, the operation of phase adjustment for the internal clock signal ICK for operating each circuit element in the large-scale circuit block 32 included in the semiconductor integrated circuit 1 will be described. Figure 3 1 is a timing chart showing the phase adjustment operation in the semiconductor integrated circuit 1 according to the first embodiment of the present invention. Figure 3 , the timing of the signals output by each structural element of the clock path of the internal clock signal ICK in the semiconductor integrated circuit 1 is shown. More specifically, the timing of the original oscillation clock signal Xtal, the synchronous clock signal PLLOUT, the phase adjustment enable signal EN, the synchronous reset signal SR, and the internal clock signal ICK are shown. In addition, Figure 3The timing of the original oscillation clock signal Xtal shown is also the timing of the reference clock signal RCK detecting the rising edge by the edge detection circuit 310. In the following description, the case where the edge detection circuit 310 detects the rising edge of the original oscillation clock signal Xtal is described. Figure 3 , the timing of the transient current is shown as the timing of power supply noise (self-noise) generated at the timing based on the internal clock signal ICK in the semiconductor integrated circuit 1.

[0066] In the semiconductor integrated circuit 1, when the power of the system substrate of the device is turned on and the control unit 20 is started, the phase adjustment operation starts. At this time, first, the control unit 20 sets the phase adjustment enable signal EN to the "High" level. As a result, the edge detection circuit 310 detects the rising edge of the original oscillation clock signal Xtal according to the "High" level of the phase adjustment enable signal EN. Figure 3 , the operation of the edge detection circuit 310 when the rising edge of the original oscillation clock signal Xtal is detected at time t01 is shown.

[0067] When the edge detection circuit 310 detects the rising edge of the original oscillation clock signal Xtal at time t01, it outputs the synchronization reset signal SR of one cycle of the synchronization clock signal PLLOUT to the clock division circuit 31. That is, the edge detection circuit 310 sets the synchronization reset signal SR to the "High" level at time t01, and then sets the synchronization reset signal SR to the "Low" level at time t11. Thus, the clock division circuit 31 resets the division action by the "High" level of the synchronization reset signal SR output from the edge detection circuit 310, and the synchronization reset signal SR becomes the "Low" level, that is, from the time t11 when the reset is released, it starts to output the internal clock signal ICK obtained by dividing the synchronization clock signal PLLOUT. Thus, the internal clock signal ICK output by the clock division circuit 31 becomes a clock signal whose phase is offset by one cycle of the synchronization clock signal PLLOUT from the timing of the rising edge of the original oscillation clock signal Xtal detected by the edge detection circuit 310. In addition, Figure 3 The internal clock signal ICK shown is an example of a case where the synchronous clock signal PLLOUT is divided by 5. That is, Figure 3 The frequency of the internal clock signal ICK shown is 1 / 5 times the frequency of the synchronous clock signal PLLOUT.

[0068] Furthermore, in the semiconductor integrated circuit 1, the large-scale circuit block 32 performs a predetermined function and the signal output to the outside by the output buffer 33 also becomes a signal whose level changes (transitions) at, for example, time t11, time t12, time t13, etc., in accordance with the change (transition) in the level of the output signal OUT output synchronously with each rising edge of the internal clock signal ICK output by the semiconductor integrated circuit 1, for example, at time t11, time t12, time t13, etc., in the system substrate of the device. Figure 3 That is, in the system substrate of the device, when the timing of the rising edge of the original oscillation clock signal Xtal deviates from the phase of one cycle of the synchronous clock signal PLLOUT, power supply noise synchronized with the output signal OUT output by the semiconductor integrated circuit 1 is generated.

[0069] In other words, in the system substrate of the device, the power supply noise generated by the semiconductor integrated circuit 1 avoids the timing of the time t01 or the time t03 in the middle of the change (transition) of the level of the original oscillation clock signal Xtal or the reference clock signal RCK, and is generated during the period when the level of the original oscillation clock signal Xtal or the reference clock signal RCK is stabilized at an arbitrary level. Therefore, the power supply noise generated by the semiconductor integrated circuit 1 in the system substrate of the device has little influence on the original oscillation clock signal Xtal or the reference clock signal RCK, and will not become a cause of jitter at the rising edge of the original oscillation clock signal Xtal or the reference clock signal RCK.

[0070] Thus, in the semiconductor integrated circuit 1, the edge detection circuit 310 detects the rising edge of the reference clock signal RCK and resets the clock frequency division circuit 31. Thus, in the semiconductor integrated circuit 1, the timing of the rising edge of the internal clock signal ICK generated based on the reference clock signal RCK (original oscillation clock signal Xtal) is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Thus, in the semiconductor integrated circuit 1, the timing of the power supply noise (self-noise) generated by the system substrate of the device due to the change (transition) of the level of the output signal OUT output to the outside is deviated from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Therefore, in the semiconductor integrated circuit 1, even if the power supply noise (self-noise) is generated, the power supply noise will not become the cause of the variation (causing jitter) of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). In other words, in the semiconductor integrated circuit 1, the power supply noise (self-noise) that causes the variation (jitter) in the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) is eliminated.

[0071] According to the first embodiment, a semiconductor integrated circuit (semiconductor integrated circuit 1) is constructed, and the semiconductor integrated circuit (semiconductor integrated circuit 1) includes: a phase synchronization circuit (system PLL30), which generates a synchronization clock signal (synchronous clock signal PLLOUT) obtained by multiplying the reference clock signal RCK in synchronization with a reference clock signal (which can also be a reference clock signal RCK or an original oscillation clock signal Xtal); an edge detection circuit (edge ​​detection circuit 310), which detects the edge (a rising edge in the first embodiment) at which the signal waveform of the reference clock signal RCK changes at the timing of the synchronization clock signal PLLOUT, and outputs an edge detection signal (edge ​​detection signal ED) indicating the timing at which the rising edge is detected; and a clock division circuit (clock division circuit 31), which is reset at a timing corresponding to the edge detection signal ED, and generates a divided clock signal (internal clock signal ICK) obtained by dividing the synchronization clock signal PLLOUT.

[0072] Furthermore, according to the first embodiment, the semiconductor integrated circuit 1 is configured in which the edge detection circuit 310 outputs the edge detection signal ED corresponding to one cycle of the synchronous clock signal PLLOUT.

[0073] Furthermore, according to the first embodiment, the semiconductor integrated circuit 1 is configured which further includes a control unit (control unit 20 ) that causes the edge detection circuit 310 to start detecting a rising edge.

[0074] As described above, in the semiconductor integrated circuit 1 of the first embodiment, the edge detection circuit 310 detects the rising edge of the reference clock signal RCK and resets the clock frequency division circuit 31, thereby shifting the timing of the rising edge of the internal clock signal ICK generated by the clock frequency division circuit 31 from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Therefore, in the semiconductor integrated circuit 1 of the first embodiment, even if the system substrate of the device (system) equipped with the semiconductor integrated circuit 1 of the first embodiment generates power supply noise (self-noise) due to the change (transition) of the level of the output signal OUT output to the outside, the timing of generating the power supply noise (self-noise) is also shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Therefore, in the semiconductor integrated circuit 1 of the first embodiment, the generated power supply noise (self-noise) does not become a cause of the rising edge variation (causing jitter) of the reference clock signal RCK (original oscillation clock signal Xtal). That is, in the semiconductor integrated circuit 1 of the first embodiment, the generation of timing variation (jitter) caused by power supply noise (self-noise) at the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) is eliminated.

[0075] Thus, in a device (system) equipped with the semiconductor integrated circuit 1 according to the first embodiment, it is possible to suppress degradation in the performance of the entire system due to power supply noise (self-noise) generated by the semiconductor integrated circuit 1 according to the first embodiment.

[0076] In addition, in the semiconductor integrated circuit 1 of the first embodiment, the following structure is described: the internal clock signal ICK generated by the clock frequency division circuit 31 is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) by the phase of one cycle of the synchronous clock signal PLLOUT by the synchronous reset signal SR output by the edge detection circuit 310. However, in the semiconductor integrated circuit 1 of the first embodiment, the amount by which the timing of the rising edge of the internal clock signal ICK generated by the clock frequency division circuit 31 is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal), that is, the phase adjustment amount of the internal clock signal ICK is not limited to one cycle of the synchronous clock signal PLLOUT. For example, in the semiconductor integrated circuit 1 of the first embodiment, it is considered that there is a propagation delay in the clock path of the internal clock signal ICK. More specifically, in the semiconductor integrated circuit 1 of the first embodiment, it is considered that when the signal line of the internal clock signal ICK output by the clock frequency division circuit 31 is routed to each circuit element possessed by the large-scale circuit block 32, there is a corresponding propagation delay configured for each circuit element. Therefore, in the semiconductor integrated circuit 1 according to the first embodiment, the phase of the internal clock signal ICK may be adjusted at a timing corresponding to the propagation delay of the internal clock signal ICK.

[0077] (Second embodiment)

[0078] Next, a semiconductor integrated circuit according to a second embodiment of the present invention is described. The semiconductor integrated circuit according to the second embodiment of the present invention is as follows: considering that there is a propagation delay in the clock path of the internal clock signal ICK, the phase of the internal clock signal ICK is adjusted at a timing corresponding to the propagation delay of the internal clock signal ICK.

[0079] Figure 4 1 is a block diagram showing a schematic structure of a semiconductor integrated circuit in a second embodiment of the present invention. Figure 4 The structure of the semiconductor integrated circuit of the second embodiment shown in FIG. 1 includes Figure 2 Therefore, among the components of the semiconductor integrated circuit of the second embodiment, the same reference numerals are used for the components that are the same as those of the semiconductor integrated circuit 1 of the first embodiment, and detailed descriptions of the components are omitted.

[0080] Figure 4The semiconductor integrated circuit 2 shown in the figure includes a comparator 10, a control unit 20, a system PLL 30, a clock frequency division circuit 31, an edge detection circuit 310, a delay adjustment unit 320, a large-scale circuit block 32, and an output buffer 33. In the semiconductor integrated circuit 2, a delay adjustment unit 320 is added between the edge detection circuit 310 and the clock frequency division circuit 31 in the semiconductor integrated circuit 1 of the first embodiment. Figure 4 The structure of the semiconductor integrated circuit 2 shown schematically shows the propagation delay of the clock path of the internal clock signal ICK as a propagation delay 34 of a structure obtained by connecting a plurality of buffer circuits in series. The semiconductor integrated circuit 2 also includes a PLL 40, a large-scale circuit block 41, a PLL 50, and an analog circuit 51.

[0081] Semiconductor integrated circuits 2 and Figure 2 The semiconductor integrated circuit 1 of the first embodiment shown is a large-scale semiconductor integrated circuit implemented by, for example, an ASIC. The semiconductor integrated circuit 2 is also similar to the semiconductor integrated circuit 1 of the first embodiment, and implements a predetermined function in a device (system) equipped with the semiconductor integrated circuit 2. The semiconductor integrated circuit 2 is also similar to the semiconductor integrated circuit 1 of the first embodiment, and is mounted on a system substrate for constituting a system of the device, and performs operations for implementing predetermined functions in the system of the device based on a clock signal of a predetermined frequency output from a clock supply circuit mounted on the same system substrate. In the following description, similar to the first embodiment, the case where the clock supply circuit mounted on the system substrate of the device is a quartz crystal resonator and the semiconductor integrated circuit 2 operates based on the original oscillation clock signal Xtal oscillated by the quartz crystal resonator is described.

[0082] In the semiconductor integrated circuit 2 , the system PLL 30 outputs the generated synchronous clock signal PLLOUT to the clock frequency dividing circuit 31 and the edge detection circuit 310 , and also to the delay adjustment section 320 .

[0083] Furthermore, in the semiconductor integrated circuit 2, the edge detection circuit 310 outputs a signal indicating the timing of detecting the rising edge of the reference clock signal RCK as the edge detection signal ED to the delay adjustment section 320. In addition, the edge detection signal ED output by the edge detection circuit 310 to the delay adjustment section 320 is the same signal as the synchronous reset signal SR in the first embodiment. That is, the edge detection circuit 310 outputs the synchronous reset signal SR to the delay adjustment section 320 as the edge detection signal ED.

[0084] The delay adjustment unit 320 delays the edge detection signal ED output from the edge detection circuit 310 by a predetermined time. More specifically, when the period of the internal clock signal ICK is set to TICK and the delay time of the propagation delay 34 of the clock path is set to TDICK, the delay adjustment unit 320 delays the edge detection signal ED by a time of (TICK-TDICK). The delay adjustment unit 320 outputs the delayed edge detection signal ED as a synchronous reset signal SR to the clock frequency division circuit 31. More specifically, the delay adjustment unit 320 delays the edge detection signal ED output from the edge detection circuit 310 by a period unit of the synchronous clock signal PLLOUT, and outputs the synchronous reset signal SR to the clock frequency division circuit 31 as the same signal as the synchronous reset signal SR in the first embodiment. Thus, in the semiconductor integrated circuit 2, the reset timing of the clock dividing circuit 31 according to the synchronous reset signal SR is delayed by the time delayed by the delay adjustment unit 320, that is, the time (TICK-TDICK), compared with the clock dividing circuit 31 included in the semiconductor integrated circuit 1 of the first embodiment.

[0085] In addition, the delay adjustment unit 320 is not limited to a structure that delays a time equivalent to the above-mentioned (TICK-TDICK) time, that is, it is not limited to a structure that outputs a synchronous reset signal SR obtained by delaying the edge detection signal ED by a fixed delay time. For example, the delay adjustment unit 320 can also be configured to change the time when the edge detection signal ED is delayed and output as the synchronous reset signal SR according to the control from the control unit 20. That is, the delay adjustment unit 320 can also adopt a structure that can change the phase adjustment amount of the internal clock signal ICK. Thereby, the phase adjustment amount of the internal clock signal ICK can be changed by taking into account the timing generated by the power supply noise (self-noise) that may vary according to the configuration position of each structural element in the system substrate of the device equipped with the semiconductor integrated circuit 2.

[0086] In addition, in the semiconductor integrated circuit 2, the internal clock signal ICK generated by the clock dividing circuit 31 is also a clock signal that is synchronized with the timing of the first rising edge of the reference clock signal RCK detected by the edge detection circuit 310 after the control unit 20 outputs the phase adjustment enable signal EN to the edge detection circuit 310. However, in the semiconductor integrated circuit 2, as described above, the delay adjustment unit 320 delays the timing of the synchronous reset signal SR, and therefore, the internal clock signal ICK generated by the clock dividing circuit 31 is a clock signal that is phase-shifted by multiple cycles of the synchronous clock signal PLLOUT.

[0087] Therefore, in the semiconductor integrated circuit 2, the level of the output signal OUT output by the output buffer 33 also changes (transitions) at a timing delayed by a plurality of cycles of the synchronous clock signal PLLOUT delayed by the delay adjustment unit 320. In addition, in the semiconductor integrated circuit 2, as in the semiconductor integrated circuit 1 of the first embodiment, the power supply noise (self-noise) generated by the level change (transition) of the output signal OUT does not cause jitter at the rising edge of the original oscillation clock signal Xtal oscillating the clock supply circuit (quartz oscillator) or the reference clock signal RCK output by the comparator 10. On the contrary, in the semiconductor integrated circuit 2, since the level of the output signal OUT changes (transitions) at a timing further reflecting the propagation delay of the clock path of the internal clock signal ICK in the large-scale circuit block 32, the jitter that may be caused at the rising edge of the original oscillation clock signal Xtal or the reference clock signal RCK can be more appropriately suppressed. In addition, a detailed description of the operation of phase adjustment for the internal clock signal ICK in the semiconductor integrated circuit 2 will be described later.

[0088] Here, an example of the configuration of the delay adjustment unit 320 will be described. Figure 5 This is a block diagram showing an example of a schematic configuration of a delay adjustment unit 320 included in the semiconductor integrated circuit 2 according to the second embodiment of the present invention. Figure 5 The example of the configuration of the delay adjustment unit 320 shown is an example of a configuration that can change the time for delaying the edge detection signal ED, that is, can change the phase adjustment amount of the internal clock signal ICK.

[0089] The delay adjustment section 320 includes four D-type flip-flops (D-FF) 3201 to D-FF3204, and a selector 3205. In the delay adjustment section 320, the edge detection signal ED input to the delay adjustment section 320 and the output signal of each D-type flip-flop are connected in sequence in the order of D-FF3201, D-FF3202, D-FF3203, and D-FF3204, and are connected as input signals of the selector 3205. Furthermore, in the delay adjustment section 320, the input signal selected by the selector 3205 is output as a synchronous reset signal SR.

[0090] In the delay adjustment section 320, each D-type flip-flop takes in and holds the input edge detection signal ED or the output signal of the previous D-type flip-flop in each cycle of the synchronous clock signal PLLOUT. In the delay adjustment section 320, the selector 3205 selects the edge detection signal ED or any one of the output signals of the four D-type flip-flops, for example, based on the control from the control section 20, and outputs the selected signal as the synchronous reset signal SR.

[0091] With such a structure, the delay adjustment unit 320 directly outputs the edge detection signal ED output from the edge detection circuit 310 as the synchronous reset signal SR to the clock frequency division circuit 31, or delays the edge detection signal ED by 1 cycle to 4 cycles of the synchronous clock signal PLLOUT and outputs it as the synchronous reset signal SR to the clock frequency division circuit 31, according to the control from the control unit 20. As a result, the semiconductor integrated circuit 2 has the following structure: the internal clock signal ICK generated by the clock frequency division circuit 31 is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) by the phase of 1 cycle to 5 cycles of the synchronous clock signal PLLOUT through the synchronous reset signal SR output by the delay adjustment unit 320.

[0092] In addition, Figure 5 , the structure of the delay adjustment unit 320 is shown, which delays the edge detection signal ED by 0 to 4 cycles of the synchronous clock signal PLLOUT and outputs the delay signal ED. However, the structure of the delay adjustment unit 320 is not limited to Figure 5 The structure shown. For example, the delay adjustment unit 320 can also be configured to have a number of D-type flip-flops equivalent to one cycle of the reference clock signal RCK, that is, one cycle of the original oscillation clock signal Xtal. In the case of this structure, the delay adjustment unit 320 can delay the edge detection signal ED to any timing of one cycle of the reference clock signal RCK according to the control from the control unit 20, and output it as the synchronous reset signal SR. As a result, in the semiconductor integrated circuit 2, even when it is mounted on various different devices, the phase adjustment amount of the internal clock signal ICK can be appropriately changed. In addition, the structure of the delay adjustment unit 320 can be any structure as long as it adopts a structure that delays the edge detection signal ED and outputs it as the synchronous reset signal SR.

[0093] In addition, when the delay adjustment unit 320 is not configured to change the time for delaying the edge detection signal ED, that is, when the phase adjustment amount of the internal clock signal ICK is fixed, the final stage D-type flip-flop ( Figure 5 The output signal of D-FF3204) is output to the clock dividing circuit 31 as a synchronous reset signal SR.

[0094] Here, the operation of phase adjustment for the internal clock signal ICK for operating each circuit element in the large-scale circuit block 32 included in the semiconductor integrated circuit 2 will be described. Figure 6 2 is a timing chart showing the phase adjustment operation in the semiconductor integrated circuit 2 according to the second embodiment of the present invention. Figure 6 In, with Figure 3The phase adjustment operation in the semiconductor integrated circuit 1 of the first embodiment shown in the figure is similar to the timing of the signals output by each structural element of the clock path of the internal clock signal ICK in the semiconductor integrated circuit 2. More specifically, the timing of the original oscillation clock signal Xtal, the synchronous clock signal PLLOUT, the phase adjustment enable signal EN, the edge detection signal ED, the synchronous reset signal SR and the internal clock signal ICK is shown. In addition, Figure 6 The timing of the original oscillation clock signal Xtal shown is also the same as the timing of the original oscillation clock signal Xtal in the semiconductor integrated circuit 1 of the first embodiment, and is also the timing of the reference clock signal RCK detected by the edge detection circuit 310. In the following description, the edge detection circuit 310 detects the rising edge of the original oscillation clock signal Xtal, which is the same as the phase adjustment operation in the semiconductor integrated circuit 1 of the first embodiment. In addition, Figure 6 In, with Figure 3 Similarly, the phase adjustment operation in the semiconductor integrated circuit 1 of the first embodiment shown shows the timing of the transient current as the timing of the power supply noise (self-noise) generated at the timing of the internal clock signal ICK in the semiconductor integrated circuit 2 .

[0095] In addition, the semiconductor integrated circuit 2 is configured to adjust the phase of the internal clock signal ICK in consideration of the delay of the internal clock signal ICK generated by the clock frequency dividing circuit 31 due to the propagation delay 34. Figure 6 , as the timing of the internal clock signal ICK, two aspects are shown: the internal clock signal ICK (before adjustment) when the delay adjustment unit 320 does not adjust the timing of the synchronous reset signal SR, and the internal clock signal ICK (after adjustment) when the delay adjustment unit 320 adjusts the timing of the synchronous reset signal SR. In addition, Figure 6 The timing of the internal clock signal ICK (after adjustment) shown in FIG. 1 is an example of a case where the delay adjustment unit 320 delays the edge detection signal ED by two cycles of the synchronous clock signal PLLOUT and outputs the delayed edge detection signal ED to the clock frequency division circuit 31 as the synchronous reset signal SR. Figure 6 , the timing of the internal clock signal ICK (before adjustment) when the phase of the internal clock signal ICK generated by the clock frequency division circuit 31 is shifted by one cycle of the synchronous clock signal PLLOUT in the same manner as the semiconductor integrated circuit 1 of the first embodiment, and the timing of the internal clock signal ICK (after adjustment) when the phase of the internal clock signal ICK generated by the clock frequency division circuit 31 is shifted by three cycles of the synchronous clock signal PLLOUT. In addition, Figure 6 The internal clock signal ICK is shown as Figure 3The phase adjustment operation in the semiconductor integrated circuit 1 of the first embodiment shown in FIG. 1 is an example of a case where the synchronization clock signal PLLOUT is divided by 5. That is, Figure 6 The frequency of the internal clock signal ICK is shown as Figure 3 The phase adjustment operation in the semiconductor integrated circuit 1 of the first embodiment shown is similarly performed at a frequency 1 / 5 times that of the synchronous clock signal PLLOUT.

[0096] In the semiconductor integrated circuit 2, similarly to the semiconductor integrated circuit 1 of the first embodiment, when the power of the system substrate of the device is turned on and the control unit 20 is started, the phase adjustment operation begins. At this time, first, the control unit 20 sets the phase adjustment enable signal EN to the "High" level similarly to the semiconductor integrated circuit 1 of the first embodiment. Thus, the edge detection circuit 310 detects the rising edge of the original oscillation clock signal Xtal based on the "High" level of the phase adjustment enable signal EN. Figure 6 In, also with Figure 3 The phase adjustment operation in the semiconductor integrated circuit 1 according to the first embodiment shown in the figure similarly shows the operation when the edge detection circuit 310 detects the rising edge of the original oscillation clock signal Xtal at time t01.

[0097] When the edge detection circuit 310 detects the rising edge of the original oscillation clock signal Xtal at time t01, it outputs the edge detection signal ED corresponding to one cycle of the synchronous clock signal PLLOUT to the delay adjustment unit 320. That is, the edge detection circuit 310 sets the edge detection signal ED to a "High" level at time t01, and then sets the edge detection signal ED to a "Low" level at time t11.

[0098] Here, consider the case where the delay adjustment unit 320 does not delay the edge detection signal ED output from the edge detection circuit 310 and outputs it to the clock frequency division circuit 31 as the synchronous reset signal SR. In this case, the internal clock signal ICK generated by the clock frequency division circuit 31 is delayed by the propagation delay 34 and is output to each circuit element in the large-scale circuit block 32 at the timing of the internal clock signal ICK (before adjustment). As shown in the transition period B of the internal clock signal ICK, the timing of the rising edge of the internal clock signal ICK (before adjustment) is close to the timing of the rising edge of the original oscillation clock signal Xtal. Therefore, the power supply noise (self-noise) generated by the change (transition) of the level of the output signal OUT of the semiconductor integrated circuit 2 may become a cause of jitter in the rising edge of the original oscillation clock signal Xtal oscillating in the clock supply circuit (quartz oscillator) or the reference clock signal RCK output by the comparator 10.

[0099] More specifically, in Figure 6The timing of the internal clock signal ICK (before adjustment) shown in FIG. 1 is that the timing of the rising edge of the internal clock signal ICK at time t13 is close to the timing of the rising edge of the original oscillation clock signal Xtal at time t03. Therefore, Figure 6 The power supply noise (self-noise) generated by the transient current (before adjustment) that flows more synchronously with each rising edge of the internal clock signal ICK (before adjustment), shown by the middle dotted line, may become the cause of jitter on the rising edge of the original oscillation clock signal Xtal (reference clock signal RCK) at time t03.

[0100] Therefore, in the semiconductor integrated circuit 2, the delay adjustment unit 320 delays the edge detection signal ED output from the edge detection circuit 310 by the period unit of the synchronous clock signal PLLOUT, and outputs it to the clock frequency dividing circuit 31 as the synchronous reset signal SR. Figure 6 In the embodiment, the delay adjustment unit 320 delays the edge detection signal ED by two cycles of the synchronous clock signal PLLOUT and outputs it to the clock frequency division circuit 31 as the synchronous reset signal SR. Therefore, the delay adjustment unit 320 sets the synchronous reset signal SR to the "High" level at time t21, and then sets the synchronous reset signal SR to the "Low" level at time t22. As a result, the clock frequency division circuit 31 resets the frequency division operation by the "High" level of the synchronous reset signal SR output from the delay adjustment unit 320, and starts to output the internal clock signal ICK after dividing the synchronous clock signal PLLOUT from the time t22 when the synchronous reset signal SR becomes the "Low" level, that is, the reset is released. In addition, the internal clock signal ICK output by the clock frequency division circuit 31 from time t22 is also delayed by the propagation delay 34. Therefore, the internal clock signal ICK outputted from the clock frequency dividing circuit 31 from time t22 is outputted to each circuit element in the large-scale circuit block 32 at the timing of the internal clock signal ICK (after adjustment) from time t23 after being delayed by the propagation delay 34. As shown in the transition period A of the internal clock signal ICK, the timing of the rising edge of the internal clock signal ICK (after adjustment) is away from the timing of the rising edge of the original oscillation clock signal Xtal. That is, the internal clock signal ICK (after adjustment) outputted from the clock frequency dividing circuit 31 becomes a clock signal whose phase is more appropriately shifted from the timing of the rising edge of the original oscillation clock signal Xtal detected by the edge detection circuit 310. Therefore, the power supply noise (self-noise) generated by the change (transition) of the level of the output signal OUT of the semiconductor integrated circuit 2 does not become a cause of jitter in the rising edge of the original oscillation clock signal Xtal oscillating in the clock supply circuit (quartz oscillator) or the reference clock signal RCK outputted from the comparator 10.

[0101] More specifically, in Figure 6The timing of the internal clock signal ICK (adjusted) shown in FIG. 1 is that the timing of the rising edge of the internal clock signal ICK at time t24 is far away from the timing of the rising edge of the original oscillation clock signal Xtal at time t03. Therefore, Figure 6 The power supply noise (self-noise) generated by the transient current (after adjustment) that flows more synchronously with each rising edge of the internal clock signal ICK (after adjustment) shown by the solid line will not cause jitter on the rising edge of the original oscillation clock signal Xtal (reference clock signal RCK) at time t03.

[0102] Thus, in the semiconductor integrated circuit 2, after the edge detection circuit 310 detects the rising edge of the reference clock signal RCK, the delay adjustment unit 320 delays the timing of resetting the clock frequency division circuit 31. Thus, in the semiconductor integrated circuit 2, even if there is a propagation delay in the clock path of the internal clock signal ICK, the timing of the rising edge of the internal clock signal ICK is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Thus, in the semiconductor integrated circuit 2, as in the semiconductor integrated circuit 1 of the first embodiment, the timing of the power supply noise (self-noise) generated in the system substrate of the device due to the change (transition) of the level of the output signal OUT output to the outside is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Therefore, in the semiconductor integrated circuit 2, as in the semiconductor integrated circuit 1 of the first embodiment, even if the power supply noise (self-noise) is generated, the power supply noise will not become a cause of the variation (causing jitter) of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). In other words, in the semiconductor integrated circuit 2 as well, like the semiconductor integrated circuit 1 of the first embodiment, the power supply noise (self-noise) causing the variation (jitter) at the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) is eliminated.

[0103] According to the second embodiment, a semiconductor integrated circuit (semiconductor integrated circuit 2) is constituted, and the semiconductor integrated circuit (semiconductor integrated circuit 2) also has a delay adjustment unit (delay adjustment unit 320), which delays the edge detection signal (edge ​​detection signal ED) by a period unit of a synchronous clock signal (synchronous clock signal PLLOUT).

[0104] In addition, according to the second embodiment, a semiconductor integrated circuit 2 is constituted, which also has a control unit (control unit 20), which enables the edge detection circuit (edge ​​detection circuit 310) to start edge (rising edge in the first embodiment) detection, and sets the time for delaying the edge detection signal (edge ​​detection signal ED) in the delay adjustment unit 320.

[0105] As described above, in the semiconductor integrated circuit 2 of the second embodiment, the edge detection circuit 310 detects the rising edge of the reference clock signal RCK, similarly to the semiconductor integrated circuit 1 of the first embodiment. In addition, in the semiconductor integrated circuit 2 of the second embodiment, the delay adjustment unit 320 delays the timing and resets the clock frequency division circuit 31. Thus, in the semiconductor integrated circuit 2 of the second embodiment, even if there is a propagation delay in the clock path of the internal clock signal ICK, the timing of the rising edge of the internal clock signal ICK generated by the clock frequency division circuit 31 is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal), similarly to the semiconductor integrated circuit 1 of the first embodiment. Thus, in the semiconductor integrated circuit 2 of the second embodiment, also like the semiconductor integrated circuit 1 of the first embodiment, even if power supply noise (self-noise) is generated on the system substrate of the device (system) on which the semiconductor integrated circuit 2 of the second embodiment is mounted due to the change (transition) of the level of the output signal OUT output to the outside, the timing of the generation of the power supply noise (self-noise) is also shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Thus, in the semiconductor integrated circuit 2 of the second embodiment, as in the semiconductor integrated circuit 1 of the first embodiment, the generated power supply noise (self-noise) does not become a cause of variation (causing jitter) in the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). That is, in the semiconductor integrated circuit 2 of the second embodiment, as in the semiconductor integrated circuit 1 of the first embodiment, the power supply noise (self-noise) generated at the timing causing variation (jitter) in the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) is eliminated.

[0106] Therefore, even a device (system) equipped with the semiconductor integrated circuit 2 of the second embodiment can suppress the degradation of the overall system performance caused by the power supply noise (self-noise) generated by the semiconductor integrated circuit 2 of the second embodiment, just like a device (system) equipped with the semiconductor integrated circuit 1 of the first embodiment.

[0107] In addition, in the semiconductor integrated circuit 2 of the second embodiment, the following structure is described: the synchronous reset signal SR is obtained by delaying the edge detection signal ED by the delay adjustment unit 320 by a fixed delay time equivalent to the time (TICK-TDICK), so that the internal clock signal ICK generated by the clock frequency division circuit 31 is phase-shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) by the period unit of the synchronous clock signal PLLOUT. Moreover, in the semiconductor integrated circuit 2 of the second embodiment, the structure in which the delay adjustment unit 320 can change the period of the synchronous clock signal PLLOUT that delays the edge detection signal ED according to the control from the control unit 20 is also described. However, in the semiconductor integrated circuit 2 of the second embodiment, a method for changing the period of the synchronous clock signal PLLOUT that delays the edge detection signal ED by the delay adjustment unit 320 through the control unit 20 is not described. For example, in the semiconductor integrated circuit 2 of the second embodiment, the control unit 20 can also be configured to change the period of the synchronous clock signal PLLOUT in which the delay adjustment unit 320 delays the edge detection signal ED based on the deviation between the timing of the rising edge of the reference clock signal RCK and the timing of the rising edge of the internal clock signal ICK, that is, the deviation between the phases of the reference clock signal RCK and the internal clock signal ICK.

[0108] (Third embodiment)

[0109] Next, a semiconductor integrated circuit according to a third embodiment of the present invention is described. The semiconductor integrated circuit according to the third embodiment of the present invention has a structure in which the phase of the internal clock signal ICK is adjusted based on the phase deviation between the reference clock signal RCK and the internal clock signal ICK, taking into account the timing of the propagation delay in the clock path of the internal clock signal ICK.

[0110] Figure 7 1 is a block diagram showing a schematic structure of a semiconductor integrated circuit in a third embodiment of the present invention. Figure 7 The structure of the semiconductor integrated circuit of the third embodiment shown in FIG. Figure 2 The semiconductor integrated circuit 1 of the first embodiment shown or Figure 4 Therefore, among the components of the semiconductor integrated circuit of the third embodiment, the components that are the same as the components of the semiconductor integrated circuit 1 of the first embodiment or the semiconductor integrated circuit 2 of the second embodiment are denoted by the same reference numerals, and detailed descriptions of the components are omitted.

[0111] Figure 7The semiconductor integrated circuit 3 shown in the figure includes a comparator 10, a control unit 20, a system PLL 30, a clock frequency division circuit 31, an edge detection circuit 310, a delay adjustment unit 320, a phase comparison unit 330, a dummy delay unit 331, a large-scale circuit block 32, and an output buffer 33. In the semiconductor integrated circuit 3, a phase comparison unit 330 and a dummy delay unit 331 are added to the semiconductor integrated circuit 2 of the second embodiment. Figure 7 In the structure of the semiconductor integrated circuit 3 shown in FIG. Figure 4 Similarly, the semiconductor integrated circuit 2 of the second embodiment shown schematically shows the propagation delay of the clock path of the internal clock signal ICK by the propagation delay 34. The semiconductor integrated circuit 3 also includes a PLL 40, a large-scale circuit block 41, a PLL 50, and an analog circuit 51.

[0112] The semiconductor integrated circuit 3 is also Figure 2 The semiconductor integrated circuit 1 of the first embodiment shown or Figure 4 The semiconductor integrated circuit 2 of the second embodiment shown is a large-scale semiconductor integrated circuit implemented by, for example, an ASIC. The semiconductor integrated circuit 3, like the semiconductor integrated circuit 1 of the first embodiment or the semiconductor integrated circuit 2 of the second embodiment, implements a predetermined function in a device (system) equipped with the semiconductor integrated circuit 3. The semiconductor integrated circuit 3, like the semiconductor integrated circuit 1 of the first embodiment or the semiconductor integrated circuit 2 of the second embodiment, is mounted on a system substrate for constituting a system of a device, and performs an operation for implementing a predetermined function in the system of the device based on a clock signal of a predetermined frequency output from a clock supply circuit mounted on the same system substrate. In the following description, like the semiconductor integrated circuit 1 of the first embodiment or the semiconductor integrated circuit 2 of the second embodiment, the clock supply circuit mounted on the system substrate of the device is a quartz crystal oscillator and the semiconductor integrated circuit 3 operates based on the original oscillation clock signal Xtal oscillated by the quartz crystal oscillator.

[0113] In the semiconductor integrated circuit 3 , the comparator 10 supplies the original oscillation clock signal Xtal after waveform shaping to the system PLL 30 , the edge detection circuit 310 , the PLL 40 , and the PLL 50 , and also to the phase comparison unit 330 .

[0114] Furthermore, in the semiconductor integrated circuit 3 , the clock frequency dividing circuit 31 outputs the generated internal clock signal ICK to the dummy delay section 331 in addition to outputting it to each circuit element in the large-scale circuit block 32 .

[0115] In addition, in the semiconductor integrated circuit 3, the control unit 20 determines the phase adjustment amount of the internal clock signal ICK and sets it to the delay adjustment unit 320. More specifically, the control unit 20 determines the time for delaying the edge detection signal ED in the delay adjustment unit 320, that is, the number of stages of the D-type flip-flops, and outputs the delay adjustment signal DA for setting (selecting) the determined number of stages of the D-type flip-flops to the delay adjustment unit 320. In addition, the structure of the delay adjustment unit 320 provided in the semiconductor integrated circuit 3 is Figure 5 Therefore, the selector 3205 of the delay adjustment unit 320 selects the edge detection signal ED or any one of the output signals of the four D-type flip-flops according to the delay adjustment signal DA output from the control unit 20, and outputs the selected signal as the synchronous reset signal SR.

[0116] The dummy delay section 331 is a circuit that simulates a delay amount equivalent to the propagation delay of the clock path of the internal clock signal ICK. More specifically, the dummy delay section 331 is a delay circuit that simulates a propagation delay corresponding to the configuration of each circuit element when the signal line of the internal clock signal ICK output by the clock frequency dividing circuit 31 is routed to each circuit element of the large-scale circuit block 32. That is, the dummy delay section 331 simulates the same simulated delay amount as the propagation delay 34. Figure 7 In the structure of the semiconductor integrated circuit 3 shown in FIG. 1 , a dummy delay section 331 is shown that simulates the same delay amount as the propagation delay 34 by connecting a plurality of buffer circuits in series. The structure in which the dummy delay section 331 simulates the same delay amount as the propagation delay 34 is not limited to Figure 7 The dummy delay unit 331 shown may have any structure as long as it can simulate the same delay amount as the propagation delay 34. The dummy delay unit 331 delays the internal clock signal ICK output from the clock frequency dividing circuit 31 by the same delay time as the propagation delay 34 and outputs it to the phase comparison unit 330.

[0117] The phase comparison unit 330 compares the phase of the reference clock signal RCK output from the comparator 10 with the phase of the internal clock signal ICK delayed by the dummy delay unit 331. The phase comparison unit 330 uses the reference clock signal RCK as a reference clock signal and the internal clock signal ICK delayed by the dummy delay unit 331 (hereinafter referred to as "delayed internal clock signal DICK") as a clock signal to be compared, and compares the phases of the clock signals. The phase comparison unit 330 outputs a phase comparison result signal PD indicating the result of comparing the phases of the reference clock signal RCK and the delayed internal clock signal DICK to the control unit 20. In addition, the phase comparison result signal PD output by the phase comparison unit 330 includes information indicating whether the phase of the rising edge of the delayed internal clock signal DICK is ahead of or behind the phase of the rising edge of the reference clock signal RCK.

[0118] In the semiconductor integrated circuit 3, the control unit 20 determines the time for delaying the edge detection signal ED in the delay adjustment unit 320 based on the phase comparison result signal PD output from the phase comparison unit 330, and sets the phase adjustment amount of the internal clock signal ICK to the delay adjustment unit 320 according to the result of the determination. More specifically, in the semiconductor integrated circuit 3, the control unit 20 determines the number of stages of the edge detection signal ED delayed by the D-type flip-flop included in the delay adjustment unit 320, and outputs information indicating the determined number of stages as the delay adjustment signal DA to the selector 3205 included in the delay adjustment unit 320. Then, in the semiconductor integrated circuit 3, the selector 3205 included in the delay adjustment unit 320 selects the output signal output from the D-type flip-flop of the number of stages indicated by the delay adjustment signal DA, and outputs the selected signal to the clock frequency division circuit 31 as the synchronous reset signal SR. Thus, in the semiconductor integrated circuit 3, the phase of the internal clock signal ICK generated by the clock frequency dividing circuit 31 is changed according to the phase difference between the reference clock signal RCK and the delayed internal clock signal DICK compared by the phase comparison unit 330, that is, the phase adjustment amount of the internal clock signal ICK is changed.

[0119] In addition, in the semiconductor integrated circuit 3, the internal clock signal ICK generated by the clock frequency division circuit 31 is also a clock signal synchronized with the timing of the first rising edge of the reference clock signal RCK detected by the edge detection circuit 310 after the control unit 20 outputs the phase adjustment enable signal EN to the edge detection circuit 310. However, in the semiconductor integrated circuit 3, as in the semiconductor integrated circuit 2 of the second embodiment, the delay adjustment unit 320 delays the timing of the synchronous reset signal SR, and therefore, the internal clock signal ICK generated by the clock frequency division circuit 31 is a clock signal whose phase is shifted by multiple cycles of the synchronous clock signal PLLOUT.

[0120] Therefore, in the semiconductor integrated circuit 3, similarly to the semiconductor integrated circuit 2 of the second embodiment, the level of the output signal OUT outputted by the output buffer 33 changes (transitions) at a timing delayed by a plurality of cycles of the synchronous clock signal PLLOUT delayed by the delay adjustment unit 320. In addition, in the semiconductor integrated circuit 3, similarly to the semiconductor integrated circuit 1 of the first embodiment or the semiconductor integrated circuit 2 of the second embodiment, the power supply noise (self-noise) generated by the level change (transition) of the output signal OUT does not cause jitter at the rising edge of the original oscillation clock signal Xtal oscillating from the clock supply circuit (quartz crystal oscillator) or the reference clock signal RCK outputted from the comparator 10. On the contrary, in the semiconductor integrated circuit 3, since the level of the output signal OUT changes (transitions) at a timing corresponding to the phase difference between the reference clock signal RCK and the delayed internal clock signal DICK, the jitter that may be caused at the rising edge of the original oscillation clock signal Xtal or the reference clock signal RCK can be more appropriately suppressed.

[0121] In addition, in the semiconductor integrated circuit 3, the phase adjustment amount of the internal clock signal ICK is different from that of the semiconductor integrated circuit 2 of the second embodiment, but the operation of the phase adjustment for the internal clock signal ICK in the semiconductor integrated circuit 3 is the same as that of the semiconductor integrated circuit 2 of the second embodiment. Therefore, the detailed description of the operation of the phase adjustment for the internal clock signal ICK in the semiconductor integrated circuit 3 is omitted.

[0122] Here, an example of the configuration of the phase comparison unit 330 and the phase comparison operation will be described. Figure 8 1 is a diagram showing an example of a schematic configuration of a phase comparison unit 330 included in the semiconductor integrated circuit 3 according to the third embodiment of the present invention and an example of the operation of the phase comparison unit 330. Figure 8 An example of the structure of the phase comparison unit 330 is shown in (a). Figure 8 (b)~ Figure 8 (d) shows Figure 8 An example of a phase comparison operation in the phase comparison unit 330 of the structure shown in (a). Figure 8 (e) schematically shows an example of a range of time (delay adjustment value) for delaying the edge detection signal ED in the delay adjustment section 320 , which is determined by the control section 20 based on the phase comparison result signal PD output from the phase comparison section 330 .

[0123] First of all, Figure 8The structure of the phase comparison unit 330 shown in (a) is described. In addition, in the semiconductor integrated circuit 3, as in the semiconductor integrated circuit 1 of the first embodiment or the semiconductor integrated circuit 2 of the second embodiment, the reference clock signal RCK is the same clock signal as the original oscillation clock signal Xtal. In the following description, the case where the phase comparison unit 330 compares the phase of the delayed internal clock signal DICK with the original oscillation clock signal Xtal is described.

[0124] In the phase comparison unit 330, the original oscillation clock signal Xtal is used as a reference clock signal for phase comparison, and the delayed internal clock signal DICK is used as a clock signal for the object of phase comparison. The phase comparison unit 330 includes a D-type flip-flop (D-FF) 3301 and a counter 3302. In the phase comparison unit 330, the delayed internal clock signal DICK is input as a data input of the D-FF 3301, and the original oscillation clock signal Xtal is input as a clock input of the D-FF 3301. In addition, in the phase comparison unit 330, the output signal FFOUT output from the D-FF 3301 is input to the counter 3302. In addition, in the phase comparison unit 330, the original oscillation clock signal Xtal is input as a clock input of the counter 3302. In addition, in the phase comparison unit 330, the output signal of the counter 3302 is output as a phase comparison result signal PD.

[0125] In the phase comparison unit 330, D-FF3301 takes in and holds the level of the delayed internal clock signal DICK at the timing of the rising edge of the original oscillation clock signal Xtal. In addition, in the phase comparison unit 330, the counter 3302 counts the level of the output signal FFOUT output from D-FF3301, that is, the level of the held delayed internal clock signal DICK, at the timing of the rising edge of the original oscillation clock signal Xtal. In addition, the counter 3302 counts the predetermined number of times when the output signal FFOUT output from D-FF3301 is at the "High" level, that is, during the predetermined cycle in the original oscillation clock signal Xtal. Moreover, in the phase comparison unit 330, the value (count value) of the result obtained by the counter 3302 counting the predetermined number of times is output as the phase comparison result signal PD. That is, the phase comparison unit 330 outputs the number of times the delayed internal clock signal DICK is at a "High" level, counted by the counter 3302 at the rising edge of the original oscillation clock signal Xtal, as information (phase comparison result signal PD) indicating whether the phase of the rising edge of the delayed internal clock signal DICK is ahead of or behind the phase of the rising edge of the original oscillation clock signal Xtal.

[0126] Next, use Figure 8(b)~ Figure 8 (d), yes Figure 8 An example of the phase comparison operation in the phase comparison unit 330 shown in (a) is described. If the period of the original oscillation clock signal Xtal for which the counter 3302 of the phase comparison unit 330 counts the "High" level of the output signal FFOUT output from the D-FF3301 is a period that can be counted multiple times, its length, that is, the number of times counted, is not specifically specified. In the following description, as an example, the counter 3302 of the phase comparison unit 330 counts the "High" level of the output signal FFOUT output from the D-FF3301 only during 32 cycles of the original oscillation clock signal Xtal.

[0127] First, the operation in the case where the phase of the rising edge of the delayed internal clock signal DICK is always delayed compared to the phase of the rising edge of the original oscillation clock signal Xtal is described. That is, the case where the phase of the rising edge of the delayed internal clock signal DICK is delayed compared to the phase of the rising edge of the original oscillation clock signal Xtal and stabilizes is described. In this case, Figure 8 As shown in (b), D-FF3301 takes in and holds the "High" level of the delayed internal clock signal DICK at the timing of the rising edge of the original oscillation clock signal Xtal, i.e., at time t31 and time t32. Then, D-FF3301 outputs the held "High" level output signal FFOUT to the counter 3302. Therefore, the counter 3302 counts the "High" level of the output signal FFOUT output by D-FF3301 at the timing of the rising edge of the original oscillation clock signal Xtal 32 times, and outputs the phase comparison result signal PD with a count value = 32.

[0128] Next, the operation will be described in the case where the phase of the rising edge of the delayed internal clock signal DICK always leads the phase of the rising edge of the original oscillation clock signal Xtal. That is, the case where the phase of the rising edge of the delayed internal clock signal DICK leads the phase of the rising edge of the original oscillation clock signal Xtal and stabilizes will be described. In this case, Figure 8As shown in (c), D-FF3301 takes in and holds the "Low" level of the delayed internal clock signal DICK at the timing of the rising edge of the original oscillation clock signal Xtal, i.e., at time t31 and time t32. Then, D-FF3301 outputs the output signal FFOUT of the "Low" level held to the counter 3302. Therefore, the counter 3302 does not count the "High" level of the output signal FFOUT output by D-FF3301 at the timing of the rising edge of the original oscillation clock signal Xtal 32 times, but outputs the phase comparison result signal PD with the count value = 0.

[0129] Next, the operation will be described for the case where the phase of the rising edge of the delayed internal clock signal DICK is delayed or advanced compared to the phase of the rising edge of the original oscillation clock signal Xtal. That is, since the phase of the rising edge of the delayed internal clock signal DICK is consistent with the phase of the rising edge of the original oscillation clock signal Xtal, the case where the state is not stable on one side will be described. In this case, Figure 8 As shown in (d), D-FF3301 takes in and maintains the "High" level or "Low" level of the delayed internal clock signal DICK at the timing of the rising edge of the original oscillation clock signal Xtal, i.e., time t31 and time t32. Then, D-FF3301 outputs the maintained "High" level or "Low" level output signal FFOUT to the counter 3302. Therefore, the counter 3302 only counts the "High" level of the output signal FFOUT output by D-FF3301 at the timing of the rising edge of the original oscillation clock signal Xtal, and outputs a phase comparison result signal PD with a count value between 31 and 1. Figure 8 (d) shows an example in which the counter 3302 outputs the phase comparison result signal PD having a count value ≈15 (a plurality of values ​​in a range close to the count value=15).

[0130] According to such a structure and operation, the phase comparison unit 330 outputs the phase comparison result signal PD indicating the result of comparing the phases of the delayed internal clock signal DICK and the original oscillation clock signal Xtal to the control unit 20. That is, the phase comparison unit 330 outputs the phase comparison result signal PD of the count value that is different according to the state of the phase of the rising edge of the original oscillation clock signal Xtal relative to the phase of the rising edge of the delayed internal clock signal DICK to the control unit 20. Thus, in the semiconductor integrated circuit 3, the control unit 20 determines the time for delaying the edge detection signal ED in the delay adjustment unit 320 as the phase adjustment amount of the internal clock signal ICK based on the count value indicated by the phase comparison result signal PD output from the phase comparison unit 330.

[0131] In addition, Figure 8 (a)~ Figure 8 (d) shows a phase comparison unit 330 that counts the number of times the level of the delayed internal clock signal DICK is at a "High" level during a predetermined period of the original oscillation clock signal Xtal. However, the phase comparison unit 330 is not limited to Figure 8 (a)~ Figure 8 More specifically, the phase comparison unit 330 of the semiconductor integrated circuit 3 can be a phase comparison unit of any structure and operation as long as it can compare the phases of the delayed internal clock signal DICK and the original oscillation clock signal Xtal, and at least output a phase comparison result signal PD indicating whether the phase of the rising edge of the delayed internal clock signal DICK is consistent with the phase of the rising edge of the reference clock signal RCK.

[0132] Next, use Figure 8 (e) of FIG. 2 illustrates an example of an operation in which the control unit 20 determines the time (delay adjustment value) for delaying the edge detection signal ED in the delay adjustment unit 320. The control unit 20 determines the time (delay adjustment value) for delaying the edge detection signal ED in the delay adjustment unit 320 within a range in which the count value represented by the phase comparison result signal PD output from the phase comparison unit 330 indicates that the phases of the delayed internal clock signal DICK and the original oscillation clock signal Xtal are stable in a delayed state or an advanced state. In other words, the control unit 20 determines the number of stages of the D-type flip-flops included in the delay adjustment unit 320 within a range in which the count value represented by the phase comparison result signal PD output from the phase comparison unit 330 indicates that the phases of the rising edge of the delayed internal clock signal DICK and the rising edge of the original oscillation clock signal Xtal are inconsistent.

[0133] As described above, when the phase of the rising edge of the delayed internal clock signal DICK is delayed from the phase of the rising edge of the original oscillation clock signal Xtal, the phase comparison unit 330 outputs the phase comparison result signal PD with a count value of 32. In addition, when the phase of the rising edge of the delayed internal clock signal DICK is ahead of the phase of the rising edge of the original oscillation clock signal Xtal, the phase comparison unit 330 outputs the phase comparison result signal PD with a count value of 0. In addition, when the phase of the rising edge of the delayed internal clock signal DICK is consistent with the phase of the rising edge of the original oscillation clock signal Xtal, the phase comparison unit 330 outputs the phase comparison result signal PD with a count value between 31 and 1.

[0134] Therefore, the control unit 20 determines the range in which the count value represented by the phase comparison result signal PD outputted from the phase comparison unit 330 indicates whether the phase of the delayed internal clock signal DICK and the original oscillation clock signal Xtal is delayed or advanced as the delay adjustment value. That is, the control unit 20 determines the count value represented by the phase comparison result signal PD outputted from the phase comparison unit 330 to be within the range of count value = 32 or count value = 0 ( Figure 8 The delay adjustment value is a range other than the "phase = consistent" shown in (e) and the delay adjustment signal DA for setting (selecting) the number of D-type flip-flops that become the delay adjustment value is output to the delay adjustment unit 320.

[0135] In addition, in the semiconductor integrated circuit 3, similarly to the semiconductor integrated circuit 1 of the first embodiment or the semiconductor integrated circuit 2 of the second embodiment, when the power of the system substrate of the device is turned on and the control unit 20 is started, the phase adjustment operation is started and the phase adjustment enable signal EN is set to the "High" level. However, in the semiconductor integrated circuit 3, the delay adjustment signal DA output to the delay adjustment unit 320 in the phase adjustment operation when the control unit 20 is started is not necessarily a delay adjustment value in the range indicating that the phase of the delayed internal clock signal DICK and the original oscillation clock signal Xtal is in a delayed state or an advanced state. That is, it is also considered that the phase comparison result of the phase comparison unit 330 after the operation is performed with the number of stages of the D-type flip-flop set in the delay adjustment unit 320 when the control unit 20 is started is a state where the phase of the rising edge of the delayed internal clock signal DICK is consistent with the phase of the rising edge of the original oscillation clock signal Xtal. In this case, the control unit 20 temporarily sets the phase adjustment enable signal EN to the "Low" level, outputs the delay adjustment signal DA which becomes a different delay adjustment value to the delay adjustment unit 320, and sets the phase adjustment enable signal EN to the "High" level again. That is, when the phase comparison result signal PD indicating that the phase of the rising edge of the delayed internal clock signal DICK is consistent with the phase of the rising edge of the original oscillation clock signal Xtal is output from the phase comparison unit 330, the control unit 20 re-performs the phase adjustment operation in the same way as at the start. As a result, the delay adjustment unit 320 outputs the synchronous reset signal SR obtained by selecting the output signal output from the D-type flip-flop of different stages by the selector 3205 to the clock frequency division circuit 31, and the clock frequency division circuit 31 regenerates the internal clock signal ICK of different phases and outputs it to each circuit element in the large-scale circuit block 32.

[0136] In addition, when the phase comparison result signal PD indicating that the phase of the rising edge of the delayed internal clock signal DICK is consistent with the phase of the rising edge of the original oscillation clock signal Xtal is further outputted from the phase comparison unit 330, the control unit 20 similarly re-performs the phase adjustment operation, thereby changing the phase of the internal clock signal ICK generated by the clock frequency division circuit 31. That is, the control unit 20 repeatedly performs the phase adjustment operation based on the phase comparison result signal PD outputted from the phase comparison unit 330, thereby changing the phase adjustment amount of the internal clock signal ICK generated by the clock frequency division circuit 31.

[0137] In addition, the control unit 20 may be configured to pre-store a final delay adjustment value for changing the phase adjustment amount of the internal clock signal ICK generated by the clock frequency dividing circuit 31. In this case, in a device (system) equipped with the semiconductor integrated circuit 3, when returning to a normal operation mode from a low power consumption mode such as a standby mode or a sleep mode in which the power consumption is reduced without disconnecting the power supply of the system substrate, i.e., the operation of other components is stopped while the reference clock signal RCK is continuously generated, the phase adjustment amount of the internal clock signal ICK generated by the clock frequency dividing circuit 31 can be changed based on the stored delay adjustment value. As a result, in the device (system) equipped with the semiconductor integrated circuit 3, the normal operation mode can be returned to more quickly than when the control unit 20 repeatedly performs the phase adjustment based on the phase comparison result signal PD output from the phase comparison unit 330. That is, in a device (system) equipped with a semiconductor integrated circuit 3, if there is no change in the phase relationship between the original oscillation clock signal Xtal and the internal clock signal ICK, the phase adjustment action for changing the phase adjustment amount of the internal clock signal ICK generated by the clock division circuit 31 is not performed, and the previous delay adjustment value can be used.

[0138] In addition, Figure 8(e) of FIG. 3 illustrates the following operation: the count value represented by the phase comparison result signal PD output from the phase comparison unit 330 is set to the range of "phase = consistent" when the count value is outside the range of count value = 32 or count value = 0, and only the case where the count value represented by the phase comparison result signal PD is outside the range of "phase = consistent", that is, the case where the count value represented by the phase comparison result signal PD is count value = 32 or count value = 0 is set as the delay adjustment value to be determined. However, for example, it is also considered that there is an allowable range in the fluctuation (jitter) of the rising edge of the original oscillation clock signal Xtal oscillated by the clock supply circuit (quartz oscillator) or the reference clock signal RCK output by the comparator 10 caused by the power supply noise (self-noise) generated by the semiconductor integrated circuit 3. In this case, the control unit 20 can also expand the range of "phase = delay" or "phase = advance", and set the case where the count value represented by the phase comparison result signal PD is, for example, between count value = 3 and count value = 30 to the range of "phase = consistent".

[0139] In this way, in the semiconductor integrated circuit 3, the delay of the internal clock signal ICK input to each circuit element of the large-scale circuit block 32 is simulated by the propagation delay (propagation delay 34) of the clock path of the internal clock signal ICK through the dummy delay section 331. In addition, in the semiconductor integrated circuit 3, the phase comparison section 330 compares the phase of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) with the phase of the rising edge of the internal clock signal ICK (delayed internal clock signal DICK) delayed by the dummy delay section 331. Moreover, in the semiconductor integrated circuit 3, the control section 20 sets the time for delaying the edge detection signal ED in the delay adjustment section 320, that is, the phase adjustment amount of the internal clock signal ICK generated by the clock frequency division circuit 31, based on the phase comparison result signal PD output from the phase comparison section 330. Thus, in the semiconductor integrated circuit 3, even when there is a propagation delay in the clock path of the internal clock signal ICK, the timing of the rising edge of the internal clock signal ICK is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Thus, in the semiconductor integrated circuit 3, as in the semiconductor integrated circuit 1 of the first embodiment or the semiconductor integrated circuit 2 of the second embodiment, the timing of the power supply noise (self-noise) generated in the system substrate of the device due to the change (transition) of the level of the output signal OUT output to the outside is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Therefore, in the semiconductor integrated circuit 3, as in the semiconductor integrated circuit 1 of the first embodiment or the semiconductor integrated circuit 2 of the second embodiment, even if the power supply noise (self-noise) is generated, the power supply noise will not become a cause of the rising edge variation (causing jitter) of the reference clock signal RCK (original oscillation clock signal Xtal). In other words, in the semiconductor integrated circuit 3, as in the semiconductor integrated circuit 1 of the first embodiment or the semiconductor integrated circuit 2 of the second embodiment, the power supply noise (self-noise) that causes the variation (jitter) on the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) is eliminated.

[0140] According to the third embodiment, a semiconductor integrated circuit (semiconductor integrated circuit 3) is constructed, and the semiconductor integrated circuit (semiconductor integrated circuit 3) also includes: a delay unit (dummy delay unit 331) which simulates the propagation delay (propagation delay 34) of the path of the divided clock signal (internal clock signal ICK) to delay the internal clock signal ICK by a time corresponding to the propagation delay; and a phase comparison unit (phase comparison unit 330) which compares the phase of the reference clock signal (which may also be the reference clock signal RCK, the original oscillation clock signal Xtal) with the phase of the internal clock signal ICK after being delayed by the dummy delay unit 331.

[0141] In addition, according to the third embodiment, a semiconductor integrated circuit 3 is constituted, in which a delay adjustment unit (delay adjustment unit 320) delays an edge detection signal (edge ​​detection signal ED) by a period of a synchronous clock signal (synchronous clock signal PLLOUT) set based on a phase comparison result of a phase comparison unit 330.

[0142] In addition, according to the third embodiment, a semiconductor integrated circuit 3 is constituted, which also has a control unit (control unit 20), which enables the edge detection circuit (edge ​​detection circuit 310) to start detecting the edge (the rising edge in the first embodiment), and based on the phase comparison result of the phase comparison unit 330, sets the delay adjustment unit 320 to delay the edge detection signal ED.

[0143] As described above, in the semiconductor integrated circuit 3 of the third embodiment, the edge detection circuit 310 detects the rising edge of the reference clock signal RCK, similarly to the semiconductor integrated circuit of the first embodiment or the second embodiment. In addition, in the semiconductor integrated circuit 3 of the third embodiment, similarly to the semiconductor integrated circuit 2 of the second embodiment, the delay adjustment unit 320 delays the timing and resets the clock frequency division circuit 31. At this time, in the semiconductor integrated circuit 3 of the third embodiment, the control unit 20 sets the time for the delay adjustment unit 320 to delay the timing for resetting the clock frequency division circuit 31 based on the phase comparison result signal PD obtained by the phase comparison unit 330 comparing the phase of the rising edge of the reference clock signal RCK with the phase of the rising edge of the internal clock signal ICK (delayed internal clock signal DICK) delayed by the dummy delay unit 331. Thus, in the semiconductor integrated circuit 3 of the third embodiment, even if there is a propagation delay in the clock path of the internal clock signal ICK, the timing of the rising edge of the internal clock signal ICK generated by the clock frequency dividing circuit 31 is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal), as in the semiconductor integrated circuit of the first embodiment or the second embodiment. Thus, in the semiconductor integrated circuit 3 of the third embodiment, also in the same manner as the semiconductor integrated circuit of the first embodiment or the second embodiment, even if power supply noise (self-noise) is generated in the system substrate of the device (system) on which the semiconductor integrated circuit 3 of the third embodiment is mounted due to the change (transition) of the level of the output signal OUT output to the outside, the timing of generating the power supply noise (self-noise) is also shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Thus, in the semiconductor integrated circuit 3 of the third embodiment, also in the same manner as the semiconductor integrated circuit of the first embodiment or the second embodiment, the generated power supply noise (self-noise) does not become a cause of the variation (causing jitter) of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). That is, in the semiconductor integrated circuit 3 of the third embodiment, as in the semiconductor integrated circuit of the first embodiment or the second embodiment, the timing-generated power supply noise (self-noise) that causes variations (jitter) on the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) is eliminated.

[0144] Therefore, even a device (system) equipped with the semiconductor integrated circuit 3 of the third embodiment can suppress the degradation of the overall performance of the system caused by the power supply noise (self-noise) generated by the semiconductor integrated circuit 3 of the third embodiment, just like a device (system) equipped with the semiconductor integrated circuit of the first embodiment or the second embodiment.

[0145] In addition, in the semiconductor integrated circuit 3 of the third embodiment, the following structure is described: the control unit 20 repeatedly performs the phase adjustment operation based on the phase comparison result signal PD output from the phase comparison unit 330, thereby sequentially changing the phase adjustment amount of the internal clock signal ICK generated by the clock frequency division circuit 31. This is based on the structure that the phase comparison unit 330 outputs the phase comparison result signal PD indicating whether the phase of the rising edge of the delayed internal clock signal DICK is advanced or delayed compared to the phase of the rising edge of the reference clock signal RCK. However, as described above, the phase comparison unit 330 provided in the semiconductor integrated circuit 3 can be a phase comparison unit of any structure and operation as long as it can compare the phase of the delayed internal clock signal DICK with the original oscillation clock signal Xtal. Therefore, the phase comparison unit 330 provided in the semiconductor integrated circuit 3 can also be a structure as follows: for example, the phase of the rising edge of the delayed internal clock signal DICK is compared with the phase of the rising edge of the reference clock signal RCK, and the phase comparison result signal PD including information indicating the magnitude of the phase deviation is output. In this case, the control unit 20 can immediately determine the time to delay the edge detection signal ED in the delay adjustment unit 320 based on the phase comparison result signal PD output from the phase comparison unit 330 without repeatedly performing the phase adjustment operation. In this case, the control unit 20 can also perform the following operation: according to the result of the determination, the phase adjustment amount of the internal clock signal ICK generated by the clock frequency dividing circuit 31 is set only once in the delay adjustment unit 320.

[0146] In addition, the following structure is described in the semiconductor integrated circuit of the second embodiment or the third embodiment: the synchronous reset signal SR obtained by delaying the edge detection signal ED by the delay adjustment unit 320 by the period unit of the synchronous clock signal PLLOUT causes the timing of the rising edge of the internal clock signal ICK generated by the clock frequency division circuit 31 to be phase-shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) by the period unit of the synchronous clock signal PLLOUT. However, in the semiconductor integrated circuit of the second embodiment or the third embodiment, the delay amount of the propagation delay (propagation delay 34) of the clock path of the internal clock signal ICK is not necessarily limited to being expressed by the period unit of the synchronous clock signal PLLOUT. That is, in the semiconductor integrated circuit of the second embodiment or the third embodiment, the delay time of the internal clock signal ICK input to each circuit element possessed by the large-scale circuit block 32 is also considered to be the time between the periods of the synchronous clock signal PLLOUT. Even in this case, in the semiconductor integrated circuit of the second embodiment or the third embodiment, the phase of the internal clock signal ICK generated by the clock frequency division circuit 31 is shifted by the period unit of the synchronous clock signal PLLOUT, so the generated power supply noise (self-noise) does not become a cause of the rising edge variation (causing jitter) of the reference clock signal RCK (original oscillation clock signal Xtal). However, in the semiconductor integrated circuit of the second embodiment or the third embodiment, the amount by which the timing of the rising edge of the internal clock signal ICK generated by the clock frequency division circuit 31 is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) (the phase adjustment amount of the internal clock signal ICK) is not limited to the period unit of the synchronous clock signal PLLOUT. For example, in the semiconductor integrated circuit of the second embodiment or the third embodiment, it is also possible to configure the timing of the rising edge of the internal clock signal ICK generated by the clock frequency division circuit 31 to be shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) in coordination with the propagation delay in the clock path of the internal clock signal ICK.

[0147] (Fourth embodiment)

[0148] Next, a semiconductor integrated circuit according to a fourth embodiment of the present invention is described. The semiconductor integrated circuit according to the fourth embodiment of the present invention is configured to adjust the phase of the internal clock signal ICK to a timing corresponding to the propagation delay of the internal clock signal ICK, taking into account the presence of a propagation delay of a time unit that is not a period unit of the synchronous clock signal PLLOUT in the clock path of the internal clock signal ICK.

[0149] Fig. 9 1 is a block diagram showing a schematic structure of a semiconductor integrated circuit in a fourth embodiment of the present invention. Fig. 9 The structure of the semiconductor integrated circuit of the fourth embodiment shown in FIG. 1 includes Figure 2 The semiconductor integrated circuit 1 of the first embodiment shown in FIG. Figure 4 The semiconductor integrated circuit 2 of the second embodiment shown in FIG. Figure 7 Therefore, among the structural elements of the semiconductor integrated circuit of the fourth embodiment, the structural elements that are the same as the structural elements of the semiconductor integrated circuit 1 of the first embodiment, the semiconductor integrated circuit 2 of the second embodiment, and the semiconductor integrated circuit 3 of the third embodiment are denoted by the same reference numerals, and detailed descriptions of the respective structural elements are omitted.

[0150] Fig. 9 The semiconductor integrated circuit 4 shown in the figure includes a comparator 10, a control unit 20, a system PLL 30, a clock frequency division circuit 31, an edge detection circuit 310, a delay adjustment unit 320, a phase comparison unit 330, a dummy delay unit 331, a delay fine adjustment unit 340, a large-scale circuit block 32, and an output buffer 33. In the semiconductor integrated circuit 4, the delay fine adjustment unit 340 is added to the semiconductor integrated circuit 3 of the third embodiment. Fig. 9 The structure of the semiconductor integrated circuit 4 shown in FIG. Figure 4 The semiconductor integrated circuit 2 of the second embodiment shown in FIG. Figure 7 The semiconductor integrated circuit 3 of the third embodiment shown schematically shows the propagation delay of the clock path of the internal clock signal ICK by the propagation delay 34. The semiconductor integrated circuit 4 includes a PLL 40, a large-scale circuit block 41, a PLL 50, and an analog circuit 51.

[0151] The semiconductor integrated circuit 4 is also Figure 2 The semiconductor integrated circuit 1 of the first embodiment shown in FIG. Figure 4 The semiconductor integrated circuit 2 of the second embodiment shown in FIG. Figure 7The semiconductor integrated circuit 3 of the third embodiment shown is a large-scale semiconductor integrated circuit implemented by, for example, ASIC. The semiconductor integrated circuit 4, like the semiconductor integrated circuit 1 of the first embodiment, the semiconductor integrated circuit 2 of the second embodiment, and the semiconductor integrated circuit 3 of the third embodiment, realizes a predetermined function in a device (system) equipped with the semiconductor integrated circuit 4. The semiconductor integrated circuit 4, like the semiconductor integrated circuit 1 of the first embodiment, the semiconductor integrated circuit 2 of the second embodiment, and the semiconductor integrated circuit 3 of the third embodiment, is mounted on a system substrate for constituting a system of a device, and performs an operation for realizing a predetermined function in the system of the device based on a clock signal of a predetermined frequency output from a clock supply circuit mounted on the same system substrate. In the following description, like the semiconductor integrated circuit 1 of the first embodiment, the semiconductor integrated circuit 2 of the second embodiment, and the semiconductor integrated circuit 3 of the third embodiment, the clock supply circuit mounted on the system substrate of the device is a quartz crystal oscillator and the semiconductor integrated circuit 4 operates based on the original oscillation clock signal Xtal oscillated by the quartz crystal oscillator.

[0152] In the semiconductor integrated circuit 4, the internal clock signal ICK generated by the clock frequency dividing circuit 31 is output to the delay fine adjustment section 340, and the internal clock signal ICKD output from the delay fine adjustment section 340 is output to each circuit element in the large-scale circuit block 32. In addition, in the semiconductor integrated circuit 4, the internal clock signal ICK input to the dummy delay section 331 is replaced by the internal clock signal ICKD output from the delay fine adjustment section 340. That is, the internal clock signal ICK output to each component in the semiconductor integrated circuit 3 of the third embodiment is replaced by the internal clock signal ICKD output from the delay fine adjustment section 340 in the semiconductor integrated circuit 4.

[0153] The delay fine adjustment unit 340 delays the internal clock signal ICK output from the clock frequency dividing circuit 31 by a period of one cycle of the synchronous clock signal PLLOUT according to the control from the control unit 20. That is, the delay fine adjustment unit 340 finely adjusts the timing of the rising edge of the internal clock signal ICK so as to be more consistent with the propagation delay 34 in the clock path of the internal clock signal ICK. The delay fine adjustment unit 340 outputs the delayed internal clock signal ICK as the internal clock signal ICKD to each circuit element in the large-scale circuit block 32 and the dummy delay unit 331.

[0154] Here, an example of the configuration of the delay fine adjustment unit 340 will be described. Fig.101 is a block diagram showing an example of a schematic structure of a delay fine adjustment section 340 provided in a semiconductor integrated circuit 4 according to a fourth embodiment of the present invention. The delay fine adjustment section 340 includes four buffer circuits 3401 to 3404, and a selector 3405. In the delay fine adjustment section 340, the buffer circuit 3401, the buffer circuit 3402, the buffer circuit 3403, and the buffer circuit 3404 are sequentially connected in this order, and the internal clock signal ICK input to the delay fine adjustment section 340 and the output signal of each buffer circuit are connected as the input signal of the selector 3405. In addition, in the delay fine adjustment section 340, the input signal selected by the selector 3405 is output as the internal clock signal ICKD.

[0155] In the delay fine adjustment section 340, each buffer circuit delays the input internal clock signal ICK or the output signal of the buffer circuit at the previous stage by the delay time of the element in the buffer circuit and outputs it. In addition, in the delay fine adjustment section 340, the selector 3405 selects the internal clock signal ICK or any one of the output signals of the four buffer circuits according to the control from the control section 20, and outputs the selected signal as the internal clock signal ICKD.

[0156] With such a structure, the delay fine adjustment unit 340 directly outputs the internal clock signal ICK output from the clock frequency dividing circuit 31 as the internal clock signal ICKD to each circuit element in the large-scale circuit block 32, or delays the internal clock signal ICK by 1 to 4 times of the buffer circuit, and outputs it as the internal clock signal ICKD to each circuit element in the large-scale circuit block 32, according to the control from the control unit 20. Thus, in the semiconductor integrated circuit 4, as in the semiconductor integrated circuit 3 of the third embodiment, the internal clock signal ICKD for each circuit element in the large-scale circuit block 32 is shifted in phase by 1 to 5 cycles of the synchronous clock signal PLLOUT, and further shifted in phase by 1 to 4 times of the buffer circuit.

[0157] In addition, Fig.10 FIG. 4 shows a structure of the delay fine adjustment unit 340 that directly outputs the internal clock signal ICK or delays the internal clock signal ICK by 1 to 4 steps of the buffer circuit. However, the structure of the delay fine adjustment unit 340 is not limited to Fig.10The structure shown. For example, the delay fine adjustment unit 340 can also be configured as a buffer circuit having a number of delay times that can set the amount of one cycle of the synchronous clock signal PLLOUT. In the case of this structure, the delay fine adjustment unit 340 can delay the internal clock signal ICK to any timing of one cycle of the synchronous clock signal PLLOUT according to the control from the control unit 20, and output it as the internal clock signal ICKD. As a result, in the semiconductor integrated circuit 2, even when it is mounted on various different devices, the phase adjustment amount of the internal clock signal ICKD can be appropriately changed. In addition, the structure of the delay fine adjustment unit 340 can be any structure as long as it is a structure that delays the internal clock signal ICK and outputs it as the internal clock signal ICKD.

[0158] In addition, the delay fine adjustment unit 340 may not be configured to change the time for delaying the internal clock signal ICK, that is, the delay fine adjustment unit 340 may be configured to have a fixed phase adjustment amount for the internal clock signal ICK. In this case, the delay fine adjustment unit 340 is configured to have no selector 3405, and the final buffer circuit (at Fig.10 The output signal of the buffer circuit 3404 (in the figure) is output as the internal clock signal ICKD to each circuit element in the large-scale circuit block 32 and the dummy delay unit 331.

[0159] The dummy delay section 331 delays the internal clock signal ICKD outputted from the delay fine adjustment section 340 by the same delay time as the propagation delay 34 , and outputs the delayed internal clock signal ICKD to the phase comparison section 330 as the delayed internal clock signal DICK.

[0160] In addition, in the semiconductor integrated circuit 4, when the control unit 20 fine-adjusts the phase of the internal clock signal ICK based on the same consideration method as the phase adjustment of the internal clock signal ICK in the semiconductor integrated circuit 3 of the third embodiment, the time for the internal clock signal ICK to be delayed by the delay fine-adjustment unit 340 is determined, and the phase adjustment amount of the internal clock signal ICK is set for the delay fine-adjustment unit 340 based on the determined result. At this time, the signal used by the control unit 20 to set the phase adjustment amount of the internal clock signal ICK for the delay fine-adjustment unit 340 may also be the same signal as the delay adjustment signal DA used by the control unit 20 to set the phase adjustment amount of the internal clock signal ICK for the delay adjustment unit 320. Fig. 9In the semiconductor integrated circuit 4 shown in the figure, the control unit 20 also outputs the delay adjustment signal DA to the delay fine adjustment unit 340. That is, the control unit 20 sets the time for delaying the signals corresponding to the delay adjustment unit 320 and the delay fine adjustment unit 340 respectively by the delay adjustment signal DA. In this case, in the semiconductor integrated circuit 4, the control unit 20 determines the number of stages of the internal clock signal ICK delayed by the buffer circuit provided in the delay fine adjustment unit 340, and outputs information indicating the determined number of stages to the selector 3405 provided in the delay fine adjustment unit 340 as the delay adjustment signal DA. In addition, in the semiconductor integrated circuit 4, the selector 3405 provided in the delay fine adjustment unit 340 selects the output signal output from the buffer circuit of the number of stages indicated by the delay adjustment signal DA, and outputs the selected signal as the internal clock signal ICKD to each circuit element in the large circuit block 32 and the dummy delay unit 331. Therefore, in the semiconductor integrated circuit 4, the phase of the internal clock signal ICK generated by the clock division circuit 31 is changed according to the phase difference between the reference clock signal RCK compared by the phase comparison unit 330 and the delayed internal clock signal DICK including the delay time adjusted by the delay fine adjustment unit 340, that is, the phase adjustment amount of the internal clock signal ICK before the delay by the delay fine adjustment unit 340 is changed.

[0161] Therefore, in the semiconductor integrated circuit 4, the level of the output signal OUT outputted from the output buffer 33 changes (transitions) at a timing delayed by the time within one cycle of the synchronous clock signal PLLOUT delayed by the delay fine adjustment section 340, compared to the semiconductor integrated circuit 3 of the third embodiment. In addition, in the semiconductor integrated circuit 4, as in the semiconductor integrated circuit 1 of the first embodiment, the semiconductor integrated circuit 2 of the second embodiment, and the semiconductor integrated circuit 3 of the third embodiment, the power supply noise (self-noise) generated by the level change (transition) of the output signal OUT does not cause jitter at the rising edge of the original oscillation clock signal Xtal oscillating from the clock supply circuit (quartz crystal resonator) or the reference clock signal RCK outputted from the comparator 10. On the contrary, in the semiconductor integrated circuit 4, the level of the output signal OUT changes (transitions) at a timing corresponding to the phase difference between the reference clock signal RCK and the delayed internal clock signal DICK including the delay time adjusted by the delay fine adjustment section 340, so that the jitter that may be caused at the rising edge of the original oscillation clock signal Xtal or the reference clock signal RCK can be more appropriately suppressed than in the semiconductor integrated circuit 3 of the third embodiment.

[0162] In addition, in the semiconductor integrated circuit 4, the phase adjustment amount of the internal clock signal ICK is different from that of the semiconductor integrated circuit 2 of the second embodiment or the semiconductor integrated circuit 3 of the third embodiment, but the operation of the phase adjustment for the internal clock signal ICK in the semiconductor integrated circuit 4 is the same as that of the semiconductor integrated circuit 2 of the second embodiment or the semiconductor integrated circuit 3 of the third embodiment. Therefore, detailed description of the operation of the phase adjustment for the internal clock signal ICK in the semiconductor integrated circuit 4 is omitted.

[0163] Thus, in the semiconductor integrated circuit 4, the delay fine adjustment section 340 delays the internal clock signal ICK generated by the clock frequency dividing circuit 31 by the time within one cycle of the synchronization clock signal PLLOUT. In addition, in the semiconductor integrated circuit 4, similarly to the semiconductor integrated circuit 3 of the third embodiment, the phase comparison section 330 compares the phase of the rising edge of the reference clock signal RCK (the original oscillation clock signal Xtal) with the phase of the rising edge of the internal clock signal ICK delayed by the dummy delay section 331 (the delayed internal clock signal DICK including the delay time adjusted by the extended delay fine adjustment section 340). In addition, in the semiconductor integrated circuit 4, the control section 20 sets the time for delaying the edge detection signal ED in the delay adjustment section 320 and the time for delaying the internal clock signal ICK in the delay fine adjustment section 340, that is, the phase adjustment amount of the internal clock signal ICK generated by the clock frequency dividing circuit 31, to the delay adjustment section 320 and the delay fine adjustment section 340, respectively, based on the phase comparison result signal PD output from the phase comparison section 330. Thus, in the semiconductor integrated circuit 4, even when there is a propagation delay in the clock path of the internal clock signal ICK, the timing of the rising edge of the internal clock signal ICK is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Thus, in the semiconductor integrated circuit 4, as in the semiconductor integrated circuit 1 of the first embodiment, the semiconductor integrated circuit 2 of the second embodiment, and the semiconductor integrated circuit 3 of the third embodiment, the timing of the power supply noise (self-noise) generated in the system substrate of the device due to the change (transition) of the level of the output signal OUT output to the outside is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). Therefore, in the semiconductor integrated circuit 4, as in the semiconductor integrated circuit 1 of the first embodiment, the semiconductor integrated circuit 2 of the second embodiment, and the semiconductor integrated circuit 3 of the third embodiment, even if the power supply noise (self-noise) is generated, the power supply noise will not become a cause of the rising edge variation (causing jitter) of the reference clock signal RCK (original oscillation clock signal Xtal). In other words, in the semiconductor integrated circuit 4, as in the semiconductor integrated circuit 1 of the first embodiment, the semiconductor integrated circuit 2 of the second embodiment, and the semiconductor integrated circuit 3 of the third embodiment, the power supply noise (self-noise) that causes the variation (jitter) on the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) is eliminated.

[0164] According to the fourth embodiment, a semiconductor integrated circuit (semiconductor integrated circuit 4) is constituted, and the semiconductor integrated circuit (semiconductor integrated circuit 4) also has a delay fine-adjustment unit (delay fine-adjustment unit 340), and the delay fine-adjustment unit (delay fine-adjustment unit 340) delays the divided clock signal (internal clock signal ICK) by a time within one cycle of the synchronous clock signal (synchronous clock signal PLLOUT), and the delay unit (virtual delay unit 331) further delays the internal clock signal ICK delayed by the delay fine-adjustment unit 340 by a time corresponding to the propagation delay (propagation delay 34).

[0165] According to the fourth embodiment, a semiconductor integrated circuit 4 is configured in which the delay fine adjustment section 340 delays the internal clock signal ICK by the time set based on the phase comparison result of the phase comparison section (phase comparison section 330 ).

[0166] In addition, according to the fourth embodiment, a semiconductor integrated circuit 4 is constituted, which also has a control unit (control unit 20), which enables the edge detection circuit (edge ​​detection circuit 310) to start edge (rising edge in the first embodiment) detection, and, based on the phase comparison result of the phase comparison unit 330, sets the time for delaying the edge detection signal (edge ​​detection signal ED) for the delay adjustment unit (delay adjustment unit 320), and sets the time for delaying the internal clock signal ICK for the delay fine adjustment unit 340.

[0167] As described above, in the semiconductor integrated circuit 4 of the fourth embodiment, the edge detection circuit 310 detects the rising edge of the reference clock signal RCK, similarly to the semiconductor integrated circuits of the first to third embodiments. In addition, in the semiconductor integrated circuit 4 of the fourth embodiment, the delay adjustment unit 320 delays the timing and resets the clock frequency division circuit 31, similarly to the semiconductor integrated circuits of the second and third embodiments. At this time, in the semiconductor integrated circuit 4 of the fourth embodiment, the control unit 20 sets the time for the delay adjustment unit 320 to delay the timing for resetting the clock frequency division circuit 31, based on the phase comparison result signal PD obtained by the phase comparison unit 330 comparing the phase of the rising edge of the reference clock signal RCK with the phase of the rising edge of the internal clock signal ICK (the delayed internal clock signal DICK including the delay time adjusted by the delay fine adjustment unit 340) delayed by the dummy delay unit 331. In addition, in the semiconductor integrated circuit 4 of the fourth embodiment, the control unit 20 sets the delay fine adjustment unit 340 to a time within one cycle of the synchronization clock signal PLLOUT, which is a time within one cycle of the synchronization clock signal PLLOUT, by which the internal clock signal ICK generated by the clock frequency dividing circuit 31 is delayed by the delay fine adjustment unit 340. Thus, in the semiconductor integrated circuit 4 of the fourth embodiment, even when there is a propagation delay in the clock path of the internal clock signal ICK, the timing of the rising edge of the internal clock signal ICK generated by the clock frequency dividing circuit 31 is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal), as in the semiconductor integrated circuits of the first to third embodiments. Thus, in the semiconductor integrated circuit 4 of the fourth embodiment, even when power supply noise (self-noise) is generated in the system substrate of the device (system) on which the semiconductor integrated circuit 4 of the fourth embodiment is mounted due to a change (transition) in the level of the output signal OUT output to the outside, the timing of the generation of the power supply noise (self-noise) is shifted from the timing of the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal), as in the semiconductor integrated circuits of the first to third embodiments. Thus, in the semiconductor integrated circuit 4 of the fourth embodiment, as in the semiconductor integrated circuits of the first to third embodiments, the generated power supply noise (self-noise) does not become a cause of variation (causing jitter) in the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal). That is, in the semiconductor integrated circuit 4 of the fourth embodiment, as in the semiconductor integrated circuits of the first to third embodiments, the power supply noise (self-noise) generated at the timing causing variation (jitter) in the rising edge of the reference clock signal RCK (original oscillation clock signal Xtal) is eliminated.

[0168] Therefore, in a device (system) equipped with the semiconductor integrated circuit 4 of the fourth embodiment, the degradation of the overall system performance caused by the power supply noise (self-noise) generated by the semiconductor integrated circuit 4 of the fourth embodiment can be suppressed, just like the device (system) equipped with the semiconductor integrated circuit of the first to third embodiments.

[0169] In the semiconductor integrated circuit 4 of the fourth embodiment, similarly to the semiconductor integrated circuit 3 of the third embodiment, the control unit 20 may be configured to repeatedly perform the phase adjustment operation based on the phase comparison result signal PD output from the phase comparison unit 330, thereby sequentially changing the phase adjustment amount of the internal clock signal ICK generated by the clock frequency division circuit 31. However, in the semiconductor integrated circuit 4 of the fourth embodiment, similarly to the semiconductor integrated circuit 3 of the third embodiment, the phase comparison unit 330 may be configured to output the phase comparison result signal PD including information indicating the magnitude of the phase deviation amount, and the control unit 20 may not repeatedly perform the phase adjustment operation. That is, in the semiconductor integrated circuit 4 of the fourth embodiment, similarly to the semiconductor integrated circuit 3 of the third embodiment, the control unit 20 may be configured to set the phase adjustment amount of the internal clock signal ICK generated by the clock frequency division circuit 31 only once to each of the delay adjustment unit 320 and the delay fine adjustment unit 340 based on the phase comparison result signal PD output once from the phase comparison unit 330.

[0170] In addition, in the semiconductor integrated circuit 4 of the fourth embodiment, as in the semiconductor integrated circuit 3 of the third embodiment, the control unit 20 may be configured to pre-store the final delay adjustment value in which the phase adjustment amount of the internal clock signal ICK generated by the clock frequency dividing circuit 31 is changed. In this case, in the device (system) equipped with the semiconductor integrated circuit 4 of the fourth embodiment, as in the device (system) equipped with the semiconductor integrated circuit 3 of the third embodiment, for example, when returning to the normal operation mode from a low power consumption mode such as a standby mode or a sleep mode, the control unit 20 can use the previous delay adjustment value to change the phase adjustment amount of the internal clock signal ICK generated by the clock frequency dividing circuit 31.

[0171] As described above, according to each embodiment of the present invention, an edge detection circuit is provided in a semiconductor integrated circuit, and the edge detection circuit detects the rising edge of a reference clock signal (original oscillation clock signal), and resets the clock frequency division circuit that generates an internal clock signal at the timing of the detected reference clock signal. Thus, in each embodiment of the present invention, in the semiconductor integrated circuit, the timing of the rising edge of the internal clock signal generated by the clock frequency division circuit is shifted from the timing of the rising edge of the reference clock signal. That is, in each embodiment of the present invention, in the semiconductor integrated circuit, the phase of the internal clock signal generated by the clock frequency division circuit is shifted from the phase of the reference clock signal. Thus, in each embodiment of the present invention, the timing of the level change (transition) of the output signal output to the outside by the semiconductor integrated circuit is deviated from the timing of the rising edge of the reference clock signal. Thus, in each embodiment of the present invention, the power supply noise (self-noise) generated in the system substrate of the device (system) equipped with the semiconductor integrated circuit due to the change (transition) of the level of the output signal output to the outside by the semiconductor integrated circuit does not become the cause of the change (causing jitter) of the rising edge of the reference clock signal.

[0172] In addition, according to various embodiments of the present invention, a delay adjustment unit is provided in the semiconductor integrated circuit, and the delay adjustment unit delays the timing of resetting the clock frequency division circuit by the edge detection circuit in units of the period of the original clock signal (PLL clock signal) of the internal clock signal generated by frequency division by the clock frequency division circuit. In addition, in various embodiments of the present invention, the control unit sets the time for the delay adjustment unit to delay the timing of resetting the clock frequency division circuit. Therefore, in various embodiments of the present invention, even if there is a propagation delay in the clock path of the internal clock signal in the semiconductor integrated circuit, the phase of the internal clock signal is shifted from the phase of the reference clock signal, and the power supply noise (self-noise) generated in the system substrate of the device (system) equipped with the semiconductor integrated circuit will not become the cause of the rising edge variation of the reference clock signal (causing jitter).

[0173] In addition, according to various embodiments of the present invention, a semiconductor integrated circuit is provided with: a dummy delay section simulating the delay amount of the propagation delay of the clock path of the internal clock signal; and a phase comparison section comparing the phase of the reference clock signal and the internal clock signal delayed by the dummy delay section. In addition, in various embodiments of the present invention, a delay fine adjustment section is provided in the semiconductor integrated circuit, which delays the internal clock signal generated by the clock frequency division circuit by a time within one cycle of the original clock signal (PLL clock signal) used to generate the internal clock signal. Moreover, in various embodiments of the present invention, the control section changes (adjusts) the timing of resetting the clock frequency division circuit, that is, the phase of the internal clock signal, according to the phase difference between the reference clock signal and the internal clock signal delayed by the dummy delay section. Thus, in various embodiments of the present invention, in the semiconductor integrated circuit, the phase of the internal clock signal is shifted from the phase of the reference clock signal according to the phase difference between the reference clock signal and the delayed internal clock signal, and the power supply noise (self-noise) generated in the system substrate of the device (system) equipped with the semiconductor integrated circuit does not become a cause of the rising edge variation (causing jitter) of the reference clock signal.

[0174] Thus, in each embodiment of the present invention, in the semiconductor integrated circuit, the timing power supply noise (self-noise) that causes the variation (jitter) of the rising edge of the reference clock signal can be eliminated. That is, in each embodiment of the present invention, in the device (system) equipped with the semiconductor integrated circuit, the variation (jitter) of the rising edge of the reference clock signal caused by the power supply noise generated by the semiconductor integrated circuit can be suppressed. Thus, in each embodiment of the present invention, in the device (system) equipped with the semiconductor integrated circuit, the degradation of the overall performance of the system caused by the power supply noise (self-noise) generated by the semiconductor integrated circuit can be suppressed.

[0175] In addition, in each embodiment of the present invention, the semiconductor integrated circuit of the present invention is described for the case where the structure of eliminating the timing of power supply noise (self-noise) that causes the rising edge of the reference clock signal to change (cause jitter). However, in the semiconductor integrated circuit, the power supply noise (self-noise) associated with the phase of the reference clock signal and the internal clock signal is considered to be generated in the relationship between other edges. For example, in the case where the semiconductor integrated circuit operates based on the falling edge of the reference clock signal, it is considered that the power supply noise (self-noise) is generated based on the relationship between the falling edge of the reference clock signal and the falling edge or rising edge of the internal clock signal. In this case, regardless of the relationship between the edges of each clock signal, the consideration method in the semiconductor integrated circuit of the present invention can be easily applied, that is, the consideration method of shifting the timing of the rising edge of the internal clock signal from the timing of the rising edge of the reference clock signal. Moreover, by applying the consideration method in the semiconductor integrated circuit of the present invention, the same effect can be obtained.

[0176] Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments and their modifications, and additions, omissions, substitutions, and other changes to the structure can be made without departing from the gist of the present invention.

[0177] It should be noted that the present invention is not limited by the above description, but is limited only by the appended claims.

[0178] Industrial applicability

[0179] According to the above-described embodiments, it is possible to suppress the variation of the clock signal due to the power supply noise generated in the semiconductor integrated circuit.

[0180] Description of symbols

[0181] 1, 2, 3, 4 semiconductor integrated circuits;

[0182] 10. Comparator;

[0183] 20. Control Department;

[0184] 30 System PLL (phase synchronization circuit);

[0185] 31 clock frequency division circuit;

[0186] 310 edge detection circuit;

[0187] 320 Delay Adjustment Department;

[0188] 3201, 3202, 3203, 3204 D-type flip-flops (delay adjustment unit);

[0189] 3205 selector (delay adjustment unit);

[0190] 330 phase comparison unit;

[0191] 3301 D-type flip-flop (phase comparison unit);

[0192] 3302 counter (phase comparison unit);

[0193] 331 dummy delay unit (delay unit);

[0194] 340 Delay fine adjustment unit;

[0195] 3401, 3402, 3403, 3404 buffer circuit (delay fine adjustment unit);

[0196] 3405 selector (delay fine adjustment unit);

[0197] 32 large-scale circuit blocks;

[0198] 33 output buffer;

[0199] 34 Propagation delay;

[0200] 40 PLL (Phase synchronization circuit);

[0201] 41 large-scale circuit blocks;

[0202] 50 PLL (Phase-synchronous loop);

[0203] 51 Analog circuits.

Claims

1. A semiconductor integrated circuit, wherein: The semiconductor integrated circuit comprises: A phase synchronization circuit synchronized with a reference clock signal and generating a synchronization clock signal obtained by multiplying the reference clock signal; an edge detection circuit that detects an edge at which the signal waveform of the reference clock signal changes at the timing of the synchronization clock signal, and outputs an edge detection signal indicating the timing at which the edge is detected; as well as The clock frequency dividing circuit is reset at a timing corresponding to the edge detection signal, and generates a divided clock signal obtained by dividing the synchronous clock signal so that the timing of the rising edge of the divided clock signal is offset from the timing of the rising edge of the reference clock signal.

2. The semiconductor integrated circuit according to claim 1, wherein: The edge detection circuit outputs the edge detection signal corresponding to one cycle of the synchronous clock signal.

3. The semiconductor integrated circuit according to claim 2, wherein: The semiconductor integrated circuit further includes a delay adjustment unit that delays the edge detection signal in units of a period of the synchronization clock signal.

4. The semiconductor integrated circuit according to claim 3, wherein: The semiconductor integrated circuit further comprises: a delay unit for simulating a propagation delay of a path of the divided-frequency clock signal to delay the divided-frequency clock signal by a time corresponding to the propagation delay; as well as A phase comparison section compares the phase of the reference clock signal with the phase of the divided clock signal delayed by the delay section.

5. The semiconductor integrated circuit according to claim 4, wherein: The delay adjustment unit delays the edge detection signal by a period of the synchronous clock signal set based on a phase comparison result of the phase comparison unit.

6. The semiconductor integrated circuit according to claim 5, wherein: The semiconductor integrated circuit further includes a delay fine adjustment unit that delays the frequency-divided clock signal by a time within one cycle of the synchronization clock signal. The delay section further delays the divided clock signal delayed by the fine delay adjustment section by a time corresponding to the propagation delay.

7. The semiconductor integrated circuit according to claim 6, wherein: The delay fine adjustment section delays the divided clock signal by a time period set based on a phase comparison result of the phase comparison section.

8. The semiconductor integrated circuit according to any one of claims 1 to 7, wherein: The semiconductor integrated circuit further includes a control unit that causes the edge detection circuit to start detecting the edge.

9. The semiconductor integrated circuit according to any one of claims 3 to 7, wherein: The semiconductor integrated circuit further includes a control unit that causes the edge detection circuit to start detecting the edge and sets a time for delaying the edge detection signal in the delay adjustment unit.

10. The semiconductor integrated circuit according to any one of claims 4 to 7, wherein: The semiconductor integrated circuit further includes a control unit that causes the edge detection circuit to start detecting the edge and sets a time for delaying the edge detection signal in the delay adjustment unit based on a phase comparison result of the phase comparison unit.

11. The semiconductor integrated circuit according to claim 6 or 7, wherein: The semiconductor integrated circuit also has a control unit, which enables the edge detection circuit to start detecting the edge, and based on the phase comparison result of the phase comparison unit, sets the time for delaying the edge detection signal for the delay adjustment unit, and sets the time for delaying the divided clock signal for the delay fine adjustment unit.

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