Semiconductor device, method for manufacturing the semiconductor device, or display device including the semiconductor device

Abstract

In a transistor comprising an oxide semiconductor film, variations in electrical characteristics are suppressed. The transistor includes a first gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, a second insulating film, a second gate electrode, and a third insulating film. The oxide semiconductor film includes a first oxide semiconductor film on one side of the first gate electrode and a second oxide semiconductor film on the first oxide semiconductor film. Both the first and second oxide semiconductor films contain In, M, and Zn (M is Al, Ga, Y, or Sn). In a region of the second oxide semiconductor film, the number of In atoms is less than that of the first oxide semiconductor film. The second gate electrode contains at least one of the metal elements in the oxide semiconductor film.

Description

[0001] This application is a divisional application of the patent application filed on February 23, 2016, with application number 201680012805.5 and entitled "Semiconductor device, method of manufacturing the semiconductor device or display device including the semiconductor device". Technical Field

[0002] One aspect of the present invention relates to a semiconductor device comprising an oxide semiconductor film and a display device comprising the semiconductor device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device comprising an oxide semiconductor film.

[0003] Note that one aspect of the present invention is not limited to the aforementioned technical fields. The technical field of one aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Furthermore, the present invention relates to a process, machine, manufacture, or composition of matter. In particular, the present invention relates to a semiconductor device, display device, light-emitting device, energy storage device, memory device, and methods for driving or manufacturing thereof.

[0004] Note that in this specification, etc., a semiconductor device generally refers to all devices that can operate by utilizing the properties of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, or storage devices are also types of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells or organic thin-film solar cells, etc.), and electronic devices sometimes include semiconductor devices. Background Technology

[0005] The technology of constructing transistors (also known as field-effect transistors (FETs) or thin-film transistors (TFTs)) using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is a well-known semiconductor material that can be used in transistors. In addition, oxide semiconductors have also garnered attention as other materials.

[0006] A highly reliable semiconductor device has been disclosed, wherein stable electrical characteristics are imparted to transistors using oxide semiconductors (for example, see Patent Document 1). In this semiconductor device, different oxide semiconductor films are stacked, thereby using an oxide semiconductor film containing a large amount of In on the channel side and an oxide semiconductor film containing a large amount of stabilizers such as Ga on the back channel side.

[0007] [References]

[0008] [Patent Literature]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2013-175715 Summary of the Invention

[0010] Oxide semiconductor films containing a large amount of In sometimes have a small band gap (Eg) (e.g., Eg less than 3.0 eV). In this case, oxide semiconductor films with a smaller Eg are more susceptible to light than oxide semiconductor films with a larger Eg (e.g., Eg above 3.0 eV and below 3.5 eV). For example, as a result of performing illumination light and applying negative bias stress testing (optical negative GBT stress testing), the reliability of transistors including oxide semiconductor films with a smaller Eg can sometimes be reduced.

[0011] Furthermore, photo-negative GBT stress testing is an accelerated test that can evaluate the changes in transistor characteristics caused by long-term use under light irradiation in a short time. In particular, the change in the transistor's threshold voltage (ΔVth) before and after photo-negative GBT stress testing is an important indicator for checking reliability. The smaller the change in threshold voltage (ΔVth) before and after photo-negative GBT stress testing, the higher the transistor's reliability.

[0012] In view of the above problems, one objective of the present invention is to suppress variations in electrical characteristics and improve reliability in transistors comprising oxide semiconductor films. In particular, one objective of the present invention is to suppress variations in electrical characteristics and improve reliability in transistors comprising oxide semiconductor films containing a large amount of In. Another objective of the present invention is to provide a semiconductor device with reduced power consumption. Another objective of the present invention is to provide a novel semiconductor device. Another objective of the present invention is to provide a method for manufacturing a novel semiconductor device. Another objective of the present invention is to provide a novel display device.

[0013] Note that the description of the above objectives does not preclude the existence of other objectives. One aspect of the present invention does not need to achieve all of the above objectives. Objectives other than those described above are obvious from the description in the specification, etc., and can be extracted from the specification, etc.

[0014] One aspect of the present invention is a semiconductor device including a transistor, the transistor comprising a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, and a third insulating film on the second gate electrode. The oxide semiconductor film includes a first oxide semiconductor film on one side of the first gate electrode and a second oxide semiconductor film on the first oxide semiconductor film. The first and second oxide semiconductor films contain In, M, and Zn (M is Al, Ga, Y, or Sn). In a region of the second oxide semiconductor film, the number of In atoms is less than that of the first oxide semiconductor film. The second gate electrode contains at least one of the metal elements in the oxide semiconductor film.

[0015] Another aspect of the present invention is a semiconductor device including a transistor, the transistor comprising a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a source electrode electrically connected to the oxide semiconductor film, a drain electrode electrically connected to the oxide semiconductor film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, and a third insulating film on the second gate electrode. The second gate electrode is electrically connected to the first gate electrode through openings provided in the first and second insulating films. The oxide semiconductor film includes a first oxide semiconductor film on one side of the first gate electrode and a second oxide semiconductor film on the first oxide semiconductor film. The first and second oxide semiconductor films contain In, M (M is Al, Ga, Y, or Sn), and Zn. In a region of the second oxide semiconductor film, the number of In atoms is less than that of the first oxide semiconductor film, and the second gate electrode contains at least one of the metal elements in the oxide semiconductor film.

[0016] In the above manner, preferably, the first oxide semiconductor film includes a region satisfying In > M (M is Al, Ga, Y or Sn), and the second oxide semiconductor film includes a region satisfying In ≤ M (M is Al, Ga, Y or Sn).

[0017] In the above-described manner, preferably, the second gate electrode includes a third oxide semiconductor film and a fourth oxide semiconductor film on the third oxide semiconductor film, the third oxide semiconductor film including a region satisfying In≤M (M is Al, Ga, Y or Sn), and the fourth oxide semiconductor film including a region satisfying In≥M (M is Al, Ga, Y or Sn).

[0018] Furthermore, in the above-described manner, it is preferable that the oxide semiconductor film has a crystalline portion having a c-axis orientation.

[0019] In addition, in the above-described manner, it is preferred that the third insulating film contains one or both of hydrogen and nitrogen.

[0020] Another aspect of the present invention is a display device comprising a semiconductor device and a display element according to any of the above-described embodiments. Additionally, another aspect of the present invention is a display module comprising the display device and a touch sensor. Furthermore, another aspect of the present invention is an electronic device comprising: a semiconductor device according to any of the above-described embodiments, the aforementioned display device or the aforementioned display module; and operation keys or a battery.

[0021] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first gate electrode; forming a first insulating film on the first gate electrode; forming a first oxide semiconductor film on the first insulating film; forming a second oxide semiconductor film on the first oxide semiconductor film; forming a source electrode and a drain electrode on the second oxide semiconductor film; forming a second insulating film on the second oxide semiconductor film, the source electrode, and the drain electrode; forming a third oxide semiconductor film on the second insulating film to serve as a second gate electrode; and forming a third insulating film containing hydrogen on the third oxide semiconductor film. In the step of forming the first oxide semiconductor film, the first oxide semiconductor film is formed in an atmosphere containing a first oxygen gas, and the first oxygen gas is added to the first insulating film. In the step of forming the second oxide semiconductor film, the second oxide semiconductor film is formed in an atmosphere containing a second oxygen gas. In the step of forming the third oxide semiconductor film, the third oxide semiconductor film is formed in an atmosphere containing a third oxygen gas, and the third oxygen gas is added to the second insulating film. In the step of forming the third insulating film or after the step of forming the third insulating film, hydrogen is added from the third insulating film to the third oxide semiconductor film.

[0022] In the above-described manner, it is preferable to use sputtering to form the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film.

[0023] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first gate electrode; forming a first insulating film on the first gate electrode; forming a first oxide semiconductor film on the first insulating film; forming a second oxide semiconductor film on the first oxide semiconductor film; forming a source electrode and a drain electrode on the second oxide semiconductor film; forming a second insulating film on the second oxide semiconductor film, the source electrode, and the drain electrode; forming a third oxide semiconductor film used as a second gate electrode on the second insulating film; forming a fourth oxide semiconductor film used as a second gate electrode on the third oxide semiconductor film; and forming a third insulating film containing hydrogen on the fourth oxide semiconductor film. In the step of forming the first oxide semiconductor film, the first oxide semiconductor film is formed in an atmosphere containing a first oxygen gas, and the first oxygen gas is added to the first insulating film. In the step of forming the second oxide semiconductor film, the second oxide semiconductor film is formed in an atmosphere containing a second oxygen gas. In the step of forming the third oxide semiconductor film, the third oxide semiconductor film is formed in an atmosphere containing a third oxygen gas, and the third oxygen gas is added to the second insulating film. In the step of forming the fourth oxide semiconductor film, the fourth oxide semiconductor film is formed in an atmosphere containing a fourth oxygen gas. During or after the step of forming the third insulating film, hydrogen is added from the third insulating film to the fourth oxide semiconductor film.

[0024] In the above-described manner, it is preferable to use sputtering to form the first oxide semiconductor film, the second oxide semiconductor film, the third oxide semiconductor film, and the fourth oxide semiconductor film.

[0025] Furthermore, in the above method, the flow rate of the third oxygen gas is preferably greater than that of the fourth oxygen gas.

[0026] According to one aspect of the present invention, variations in electrical characteristics can be suppressed and reliability improved in transistors comprising oxide semiconductor films. In particular, according to one aspect of the present invention, variations in electrical characteristics can be suppressed and reliability improved in transistors comprising oxide semiconductor films containing a large amount of In. Furthermore, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. Furthermore, according to one aspect of the present invention, a novel semiconductor device can be provided. Furthermore, according to one aspect of the present invention, a novel method for manufacturing a semiconductor device can be provided. Furthermore, according to one aspect of the present invention, a novel display device can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the invention does not necessarily require all of the aforementioned effects. Additionally, effects other than these are evident from the description, drawings, claims, etc., and thus, effects other than these can be extracted from the description, drawings, claims, etc. Attached Figure Description

[0028] Figures 1A to 1C This is a top view and a cross-sectional view showing one configuration of a semiconductor device;

[0029] Figures 2A to 2C This is a top view and a cross-sectional view showing one configuration of a semiconductor device;

[0030] Figures 3A to 3C This is a top view and a cross-sectional view showing one configuration of a semiconductor device;

[0031] Figures 4A to 4C This is a top view and a cross-sectional view showing one configuration of a semiconductor device;

[0032] Figures 5A to 5D This is a cross-sectional view showing one way a semiconductor device is constructed;

[0033] Figure 6A and Figure 6B It is a diagram illustrating the band structure;

[0034] Figures 7A to 7D This is a cross-sectional view showing one way a semiconductor device is constructed;

[0035] Figures 8A to 8F This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device;

[0036] Figures 9A to 9F This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device;

[0037] Figures 10A to 10F This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device;

[0038] Figures 11A to 11F This is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device;

[0039] Figure 12A and Figure 12B This is a model diagram illustrating oxygen moving in an oxide semiconductor film;

[0040] Figure 13 This is a graph illustrating the TDS measurement results;

[0041] Figure 14A and Figure 14B This is a graph illustrating the TDS measurement results;

[0042] Figure 15A and Figure 15B This is a graph illustrating the TDS measurement results;

[0043] Figure 16 This is a graph illustrating the temperature dependence of the oxide conductive film.

[0044] Figures 17A to 17D This is a Cs-corrected high-resolution TEM image of the CAAC-OS cross section and a schematic diagram of the CAAC-OS cross section;

[0045] Figures 18A to 18D It is a Cs-corrected high-resolution TEM image on the plane of CAAC-OS;

[0046] Figures 19A to 19C This is a diagram illustrating the structural analysis of CAAC-OS and single-crystal oxide semiconductors obtained by XRD;

[0047] Figure 20A and Figure 20B This is a diagram showing the electron diffraction pattern of CAAC-OS;

[0048] Figure 21 This is a diagram showing the changes in the crystal structure of In-Ga-Zn oxide caused by electron irradiation;

[0049] Figure 22 This is a diagram illustrating the deposition method of CAAC-OS;

[0050] Figures 23A to 23C This is a diagram illustrating the crystallization of InMZnO4;

[0051] Figures 24A to 24F This is a diagram illustrating the deposition method of CAAC-OS;

[0052] Figures 25A to 25G It is a diagram illustrating the location where particles attach to the granules;

[0053] Figures 26A to 26G It is a diagram illustrating the location where particles attach to the granules;

[0054] Figure 27A and Figure 27B It is a top view showing one configuration of the display device and a circuit diagram showing one configuration of the pixels;

[0055] Figure 28 It is a top view showing one way the pixels are displayed;

[0056] Figure 29 It is a cross-sectional view showing one way of displaying pixels;

[0057] Figure 30 It is a cross-sectional view showing one way of displaying pixels;

[0058] Figure 31 It is a top view showing one way the pixels are displayed;

[0059] Figure 32 It is a cross-sectional view showing one way of displaying pixels;

[0060] Figure 33 It is a cross-sectional view showing one way of displaying pixels;

[0061] Figure 34 It is a top view showing one way the pixels are displayed;

[0062] Figure 35 It is a cross-sectional view showing one way of displaying pixels;

[0063] Figure 36 It is a cross-sectional view showing one way of displaying pixels;

[0064] Figure 37 It is a top view showing one way the pixels are displayed;

[0065] Figure 38 It is a cross-sectional view showing one way of displaying pixels;

[0066] Figure 39 It is a cross-sectional view showing one way of displaying pixels;

[0067] Figure 40 It is a cross-sectional view showing one way of displaying pixels;

[0068] Figure 41 It is a top view showing one way the pixels are displayed;

[0069] Figure 42 It is a cross-sectional view showing one way of displaying pixels;

[0070] Figure 43 It is a top view showing one way the pixels are displayed;

[0071] Figure 44 It is a cross-sectional view showing one way of displaying pixels;

[0072] Figure 45 It is a circuit diagram showing one way of displaying pixels;

[0073] Figure 46A and Figure 46B These are block diagrams and circuit diagrams illustrating the display device;

[0074] Figure 47A and Figure 47B These are top views and cross-sectional views illustrating the display device;

[0075] Figure 48A and Figure 48B This is a perspective view showing an example of a touch panel;

[0076] Figure 49A and Figure 49B This is a cross-sectional view showing an example of a display device;

[0077] Figure 50 This is a cross-sectional view showing an example of a touch sensor;

[0078] Figure 51A and Figure 51B This is a cross-sectional view showing an example of a touch panel;

[0079] Figure 52A and Figure 52B This is a block diagram and timing diagram of the touch sensor;

[0080] Figure 53 This is the circuit diagram of the touch sensor;

[0081] Figure 54A and Figure 54B This is a diagram illustrating the display of a display device according to one aspect of the present invention;

[0082] Figure 55A and Figure 55B This is a diagram illustrating the display of a display device according to one aspect of the present invention;

[0083] Figures 56A to 56E This is a diagram illustrating an example of a display method on a display device according to an embodiment;

[0084] Figures 57A to 57E This is a diagram illustrating an example of a display method on a display device according to an embodiment;

[0085] Figure 58 This is a diagram illustrating the display module;

[0086] Figures 59A to 59G It is a diagram illustrating an electronic device;

[0087] Figure 60A and Figure 60B It is a perspective view of the display device;

[0088] Figure 61 It is a diagram illustrating the structure of the deposition apparatus;

[0089] Figure 62A and Figure 62B This is a diagram illustrating the Id-Vg characteristics of a transistor;

[0090] Figure 63 This is a diagram illustrating the Id-Vg characteristics of a transistor;

[0091] Figure 64A and Figure 64B This is a graph illustrating the GBT test results of transistors and the results of repeated GBT tests on transistors;

[0092] Figure 65 This is a cross-sectional STEM image illustrating a transistor;

[0093] Figure 66A and Figure 66B It is a graph illustrating the structure used for the calculation and the calculation results of the current density distribution;

[0094] Figure 67A and Figure 67B This is a diagram illustrating the structure used for calculation and the Id-Vg characteristics of the transistor;

[0095] Figure 68A and Figure 68B This is a graph illustrating the calculation results of the Id-Vg characteristics of a transistor;

[0096] Figure 69A and Figure 69B It is a graph illustrating the probability distribution of the threshold voltage of a transistor;

[0097] Figure 70A and Figure 70B It is a graph illustrating the probability distribution of the threshold voltage of a transistor;

[0098] Figure 71A and Figure 71B This is a graph illustrating the non-uniformity of the Id-Vg characteristics in the subthreshold region of a transistor.

[0099] Figure 72A and Figure 72B It is a diagram illustrating the structure used for calculation;

[0100] Figure 73A and Figure 73B This is a diagram illustrating the potential distribution along the thickness direction when NBTS is applied;

[0101] Figures 74A to 74C It is a diagram illustrating the top surface and cross-section of a transistor;

[0102] Figures 75A to 75C It is a diagram illustrating the top surface and cross-section of a transistor;

[0103] Figure 76A and Figure 76B This is a diagram illustrating the Id-Vg characteristics of a transistor;

[0104] Figure 77A and Figure 77B This is a diagram illustrating the Id-Vg characteristics of a transistor;

[0105] Figure 78A and Figure 78B This is a diagram illustrating the Id-Vg characteristics of a transistor;

[0106] Figure 79A and Figure 79B This is a diagram illustrating the Id-Vg characteristics of a transistor;

[0107] Figure 80A and Figure 80B This is a diagram illustrating the Id-Vd characteristics of a transistor;

[0108] Figures 81A to 81C This is a diagram illustrating the Id-Vd characteristics of a transistor;

[0109] Figures 82A to 82C This is a diagram illustrating the Id-Vd characteristics of a transistor;

[0110] Figure 83 This is a diagram illustrating the Id-Vg characteristics of a transistor;

[0111] Figure 84A and Figure 84B It is a graph illustrating the maximum field-effect mobility of a transistor and the threshold voltage of a transistor;

[0112] Figure 85A and Figure 85B It is a diagram illustrating the distribution of the potential supplied to the transistor;

[0113] Figure 86 This is a schematic diagram illustrating the potential supplied to the transistor;

[0114] Figure 87 This is a schematic diagram illustrating the potential supplied to the transistor;

[0115] Figure 88A and Figure 88B This is a schematic diagram illustrating the potential supplied to the transistor;

[0116] Figure 89 It is a graph illustrating the probability distribution of the threshold voltage of a transistor;

[0117] Figure 90 It is a graph illustrating the probability distribution of the threshold voltage of a transistor;

[0118] Figure 91 This is a graph illustrating the calculation results of the Id-Vg characteristics of a transistor. Detailed Implementation

[0119] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the contents described in the embodiments shown below.

[0120] Furthermore, for ease of understanding, the positions, sizes, and extents of various structures shown in the accompanying drawings, etc., do not necessarily represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings, etc.

[0121] Furthermore, in this specification and other materials, ordinal numbers such as "first" and "second" are used for convenience, but these do not always indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. Additionally, the ordinal numbers used in this specification and other materials may sometimes differ from those used to specify one aspect of the invention.

[0122] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate the arrangement of components in conjunction with the accompanying drawings. Furthermore, the positional relationships of the components may vary depending on the orientation in which each component is described. Therefore, the terminology used is not limited to that described in this specification and may be appropriately replaced as needed.

[0123] Note that in this specification and the like, when the structure of the invention is described using drawings, the symbols representing the same parts are used in the same drawings.

[0124] Note that in this specification, etc., "semiconductor device" refers to all devices that can operate by utilizing the properties of semiconductors. Semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, or storage devices are all types of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells or organic thin-film solar cells, etc.), and electronic devices sometimes include semiconductor devices.

[0125] In this specification, for example, when the conductivity is sufficiently low, sometimes even when referred to as a "semiconductor," it may also possess the characteristics of an "insulator." Furthermore, the boundary between "semiconductor" and "insulator" is not always clear, and therefore, it is sometimes difficult to distinguish precisely. Therefore, sometimes "semiconductor" as described in this specification may be replaced with "insulator." Similarly, sometimes "insulator" as described in this specification may be replaced with "semiconductor." Additionally, sometimes "insulator" as described in this specification may be replaced with "semi-insulator."

[0126] In this specification, for example, when the conductivity is sufficiently high, sometimes even when referred to as a "semiconductor," it also possesses the characteristics of a "conductor." Furthermore, the boundary between "semiconductor" and "conductor" is not always clear, and therefore, it is sometimes difficult to distinguish them precisely. Therefore, sometimes the term "semiconductor" as used in this specification may be replaced with "conductor." Similarly, sometimes the term "conductor" as used in this specification may be replaced with "semiconductor."

[0127] In this specification and the like, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain region, the channel region, and the source region. Note that in this specification and the like, the channel region refers to the region through which current primarily flows.

[0128] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification and other similar documents, the terms "source" and "drain" may be interchanged.

[0129] Note that channel length, for example, refers to the distance between the overlapping region of the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor, or between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region forming the channel. Furthermore, the channel length in a transistor is not necessarily the same value in all regions. That is, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel length refers to any value, maximum value, minimum value, or average value in the region forming the channel.

[0130] Channel width, for example, refers to the length of the region where the semiconductor (or the portion in the semiconductor where current flows when the transistor is turned on) overlaps with the gate electrode, or the portion of the region where the channel is formed where the source and drain are opposite each other. Furthermore, in a transistor, the channel width is not necessarily the same value in all regions. That is, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum value, minimum value, or average value in the region forming the channel.

[0131] In this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0132] Furthermore, voltage mostly refers to the potential difference between a certain potential and a reference potential (e.g., source potential or ground potential (GND)). Therefore, voltage can be referred to as potential instead.

[0133] Note that in this specification, silicon oxynitride film refers to a film in which the oxygen content is greater than the nitrogen content. Preferably, the silicon oxynitride film contains oxygen, nitrogen, silicon, and hydrogen in concentration ranges of 55 atomic% or more and 65 atomic% or less, 1 atomic% or more and 20 atomic% or less, 25 atomic% or more and 35 atomic% or less, and 0.1 atomic% or more and 10 atomic% or less. Silicon oxynitride film refers to a film in which the nitrogen content is greater than the oxygen content. Preferably, the silicon oxynitride film contains nitrogen, oxygen, silicon, and hydrogen in concentration ranges of 55 atomic% or more and 65 atomic% or less, 1 atomic% or more and 20 atomic% or less, 25 atomic% or more and 35 atomic% or less, and 0.1 atomic% or more and 10 atomic% or less.

[0134] Additionally, in this specification and other materials, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Furthermore, "insulating film" may sometimes be replaced with "insulating layer."

[0135] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. "Approximately parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -30° and less than 30°. Furthermore, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°. "Approximately perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 60° and less than 120°.

[0136] Implementation Method 1

[0137] In this embodiment, refer to Figures 1A to 1C , Figures 2A to 2C , Figures 3A to 3C , Figures 4A to 4C , Figures 5A to 5D , Figure 6A and Figure 6B , Figures 7A to 7D , Figures 8A to 8F , Figures 9A to 9F , Figures 10A to 10F , Figures 11A to 11F , Figure 12A and Figure 12B , Figure 13 , Figure 14A and Figure 14B , Figure 15A and Figure 15B as well as Figure 16 This invention describes a semiconductor device and a method for manufacturing the semiconductor device.

[0138] <1-1. Example 1 of the structure of a semiconductor device>

[0139] Figure 1AThis is a top view of a transistor 100 of a semiconductor device as an embodiment of the present invention. Figure 1B Equivalent to along Figure 1A The cross-sectional view shown is the dotted-dash line X1-X2. Figure 1C Equivalent to along Figure 1A The cross-sectional view of the dashed line Y1-Y2 is shown. Note that in... Figure 1A For convenience, some of the constituent elements of transistor 100 (such as the insulating film used as the gate insulating film) are omitted. Furthermore, the direction of the dotted line X1-X2 is sometimes referred to as the channel length direction, and the direction of the dotted line Y1-Y2 is sometimes referred to as the channel width direction. Note that this is sometimes also used in the top view of the transistor later. Figure 1A Similarly, a portion of the constituent elements is omitted.

[0140] The transistor 100 includes a conductive film 104 on a substrate 102 serving as a first gate electrode, an insulating film 106 on the substrate 102 and the conductive film 104, an insulating film 107 on the insulating film 106, an oxide semiconductor film 108 on the insulating film 107, a conductive film 112a electrically connected to the oxide semiconductor film 108 and serving as a source electrode, a conductive film 112b electrically connected to the oxide semiconductor film 108 and serving as a drain electrode, insulating films 114 and 116 on the oxide semiconductor film 108 and the conductive films 112a and 112b, an oxide semiconductor film 120a disposed on the insulating film 116 and electrically connected to the conductive film 112b, an oxide semiconductor film 120b on the insulating film 116, and an insulating film 118 on the insulating film 116 and the oxide semiconductor films 120a and 120b.

[0141] In transistor 100, insulating films 106 and 107 are used as the first gate insulating film of transistor 100, insulating films 114 and 116 are used as the second gate insulating film of transistor 100, and insulating film 118 is used as the protective insulating film of transistor 100. Note that in this specification, etc., insulating films 106, 107, 114, 116, and 118 are sometimes referred to as the first insulating film, the second insulating film, and the third insulating film, respectively. In transistor 100, oxide semiconductor film 120a is used as the pixel electrode of the display device, and oxide semiconductor film 120b is used as the second gate electrode of transistor 100.

[0142] The oxide semiconductor film 108 includes an oxide semiconductor film 108b and an oxide semiconductor film 108c on the oxide semiconductor film 108b. The oxide semiconductor film 108b is closer to the conductive film 104, which is used as the first gate electrode, than the oxide semiconductor film 108c. In addition, both the oxide semiconductor film 108b and the oxide semiconductor film 108c contain In, M (M is Al, Ga, Y or Sn) and Zn.

[0143] For example, oxide semiconductor film 108b preferably includes a region where the atomic ratio of In is greater than the atomic ratio of M. Additionally, oxide semiconductor film 108c preferably includes a region where the number of In atoms is less than that of oxide semiconductor film 108b.

[0144] By including regions in the oxide semiconductor film 108b where the atomic ratio of In is greater than the atomic ratio of M, the field-effect mobility (sometimes simply referred to as mobility or μFE) of the transistor 100 can be improved. Specifically, the field-effect mobility of the transistor 100 can exceed 10 cm⁻¹. 2 / Vs, preferably, the field-effect mobility of transistor 100 can exceed 30 cm⁻¹. 2 / Vs.

[0145] For example, by using the aforementioned high field-effect mobility transistors as gate drivers for generating gate signals (in particular, multiplexers connected to the output terminals of shift registers included in the gate driver), semiconductor devices or display devices with narrow bezel widths can be provided.

[0146] On the other hand, when the oxide semiconductor film 108b includes a region where the atomic ratio of In is greater than the atomic ratio of M, the electrical characteristics of the transistor 100 are prone to change under light irradiation. However, in a semiconductor device according to one aspect of the present invention, an oxide semiconductor film 108c is formed on the oxide semiconductor film 108b. Furthermore, because the oxide semiconductor film 108c includes a region where the atomic ratio of In is less than that of the oxide semiconductor film 108b, the Eg of the oxide semiconductor film 108c is larger than that of the oxide semiconductor film 108b. Therefore, the tolerance of the oxide semiconductor film 108 having the stacked structure of oxide semiconductor film 108b and oxide semiconductor film 108c to optical negative bias stress testing can be improved.

[0147] Furthermore, impurities such as hydrogen or moisture, particularly in the channel region of the oxide semiconductor film 108b, negatively impact transistor characteristics, thus becoming a problem. Therefore, the fewer impurities such as hydrogen or moisture in the channel region of the oxide semiconductor film 108b, the better. Oxygen vacancies formed in the channel region of the oxide semiconductor film 108b also negatively impact transistor characteristics, thus becoming a problem. For example, when oxygen vacancies are formed in the channel region of the oxide semiconductor film 108b, these oxygen vacancies bond with hydrogen to become carrier supply sources. When carrier supply sources are formed in the channel region of the oxide semiconductor film 108b, changes occur in the electrical characteristics of the transistor 100 with the oxide semiconductor film 108b, typically resulting in threshold voltage drift. Therefore, the fewer oxygen vacancies in the channel region of the oxide semiconductor film 108b, the better.

[0148] Therefore, in one aspect of the invention, the insulating film in contact with the oxide semiconductor film 108, specifically the insulating film 107 formed under the oxide semiconductor film 108 and the insulating films 114 and 116 formed on the oxide semiconductor film 108, contains excess oxygen. By moving oxygen or excess oxygen from the insulating film 107 and the insulating films 114 and 116 to the oxide semiconductor film 108, oxygen vacancies in the oxide semiconductor film can be reduced. Therefore, variations in the electrical characteristics of the transistor 100, especially variations in the transistor 100 under light irradiation, can be suppressed.

[0149] Furthermore, in one aspect of the present invention, because insulating films 107 and 114, 116 contain excess oxygen, a manufacturing method with minimal or no additional manufacturing steps is used. Therefore, the yield of transistor 100 can be improved.

[0150] Specifically, in the process of forming the oxide semiconductor film 108b, the oxide semiconductor film 108b is formed by sputtering in an atmosphere containing oxygen gas, and oxygen or excess oxygen is added to the insulating film 107 on which the oxide semiconductor film 108b is formed.

[0151] Furthermore, in the process of forming oxide semiconductor films 120a and 120b, oxide semiconductor films 120a and 120b are formed by sputtering in an atmosphere containing oxygen gas, and oxygen or excess oxygen is added to the insulating film 116 on which oxide semiconductor films 120a and 120b are formed. Note that when oxygen or excess oxygen is added to the insulating film 116, oxygen or excess oxygen is sometimes also added to the insulating film 114 and the oxide semiconductor film 108 located below the insulating film 116.

[0152] <1-2. Oxygen released from the insulating film in Thermal Desorption Spectroscopy (TDS)>

[0153] The following describes the measurement results of the amount of oxygen released from an insulating film on which an oxide semiconductor film formed in an atmosphere containing oxygen gas is disposed.

[0154] To measure the amount of oxygen released from the insulating film, samples A1 to A20, shown below, were manufactured, and the amount of oxygen released from their TDS was evaluated.

[0155] [1-2-1. Evaluation of the amount of oxygen added to the insulating film when changing the target composition]

[0156] First, let's describe samples A1 to A5. Note that samples A1 to A5 are used to determine the amount of oxygen added to the insulating film when the target composition is changed.

[0157] (Sample A1)

[0158] As sample A1, a 400 nm thick silicon oxynitride film was formed on a glass substrate using a PECVD apparatus, followed by heat treatment. The formation conditions for the silicon oxynitride film were as follows: substrate temperature 350 °C; introduction of silane gas at a flow rate of 160 sccm and nitrous oxide gas at a flow rate of 4000 sccm into the chamber; pressure 200 Pa; and supply of 1500 W of RF power between the parallel plate electrodes positioned within the PECVD apparatus. Using an RTA apparatus, heat treatment was performed at 650 °C for 6 minutes under a nitrogen atmosphere. Due to this heat treatment, oxygen contained in the silicon oxynitride film during deposition was desorbed.

[0159] As samples A2 to A5, a silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate using a PECVD apparatus, followed by heat treatment. After heat treatment, an oxide semiconductor film with a thickness of 50 nm was formed on the silicon oxynitride film using a sputtering apparatus. The formation conditions of the oxide semiconductor film were as follows: substrate temperature 170°C; oxygen gas with a flow rate of 100 sccm was introduced into the chamber, i.e., a 100% oxygen gas atmosphere was used; pressure 0.6 Pa; and 2500 W of AC power was supplied to the target material placed in the sputtering apparatus. Note that the target material composition of the oxide semiconductor films of samples A2 to A5 is different from that of samples A5. The target material composition of the oxide semiconductor films of samples A2 to A5 will be described later. In addition, after the oxide semiconductor film was formed, it was removed to expose the surface of the silicon oxynitride film. The formation conditions of the oxide semiconductor film, the formation conditions of the silicon oxynitride film, and the heat treatment conditions were the same as those of sample A1.

[0160] (Sample A2)

[0161] The target composition of the oxide semiconductor film of sample A2 is In:Ga:Zn = 1:1:1.2 (atomic ratio).

[0162] (Sample A3)

[0163] The target composition of the oxide semiconductor film of sample A3 is In:Ga:Zn = 4:2:4.1 (atomic ratio).

[0164] (Sample A4)

[0165] The target composition of the oxide semiconductor film of sample A4 is In:Ga:Zn = 3:1:2 (atomic ratio).

[0166] (Sample A5)

[0167] The target composition of the oxide semiconductor film of sample A5 is In:Ga:Zn = 1:3:6 (atomic ratio).

[0168] Next, the amount of gas with a mass-to-charge ratio (M / z) of 32, i.e., gas equivalent to oxygen (O2), released from the silicon oxynitride films of the manufactured samples A1 to A5 was measured. A TDS (Transient Current Distribution System) device was used to measure the amount of gas released. The amount of gas equivalent to oxygen was measured in the TDS device within a film surface temperature range of 50°C to 600°C.

[0169] Figure 13 The TDS measurement results for samples A1 to A5 are shown. Figure 13 In the diagram, the vertical axis represents the amount of gas released at M / z = 32, and the horizontal axis represents the sample name, etc.

[0170] like Figure 13 The results show that the gas release amount of sample A1 with M / z = 32 is 1.82 × 10⁻⁶. 14 / cm 2 The amount of gas released from sample A2 with M / z = 32 is 1.22 × 10⁻⁶. 15 / cm 2 The amount of gas released from sample A3 at M / z = 32 was 1.14 × 10⁻⁶. 15 / cm 2 The amount of gas released from sample A4 at M / z = 32 was 1.18 × 10⁻⁶. 15 / cm 2 The amount of gas released from sample A5 at M / z = 32 was 1.20 × 10⁻⁶. 15 / cm 2 .

[0171] Thus, it can be seen that by using sputtering to form an oxide semiconductor film on an insulating film (here, a silicon oxynitride film) on which an oxide semiconductor film is formed, excess oxygen can be added to the insulating film.

[0172] Note that the amount of oxygen added to the insulating film (oxygen released from the insulating film) does not show a significant variation due to the different target composition when forming the oxide semiconductor film.

[0173] [1-2-2. Evaluation of the amount of oxygen added to the insulating film when the flow rate of the deposited gas is changed]

[0174] Next, samples A6 to A8 will be described. Note that samples A6 to A8 are used to determine the amount of oxygen added to the insulating film when the flow rate of the deposited gas is changed.

[0175] For samples A6 to A8, a silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate using a PECVD apparatus, followed by heat treatment. After heat treatment, an oxide semiconductor film with a thickness of 50 nm was formed on the silicon oxynitride film using a sputtering apparatus. Then, the oxide semiconductor film was removed, exposing the surface of the silicon oxynitride film. The formation conditions of the silicon oxynitride film and the heat treatment conditions were the same as those for samples A1 to A5. The formation conditions of the oxide semiconductor film for samples A6 to A8 were different from those for each sample.

[0176] (Sample A6)

[0177] The oxide semiconductor film formation conditions for sample A6 are as follows: substrate temperature is 170℃; argon gas with a flow rate of 90 sccm and oxygen gas with a flow rate of 10 sccm are introduced into the chamber, i.e., an atmosphere of 10% oxygen gas is used; pressure is 0.6 Pa; and 2500 W of AC power is supplied to the target (In:Ga:Zn = 4:2:4.1) placed in the sputtering device.

[0178] (Sample A7)

[0179] The oxide semiconductor film formation conditions for sample A7 are as follows: substrate temperature is 170℃; argon gas and oxygen gas with a flow rate of 50 sccm are introduced into the chamber, i.e., an atmosphere of 50% oxygen gas is used; pressure is 0.6 Pa; and 2500 W of AC power is supplied to the target (In:Ga:Zn = 4:2:4.1) placed in the sputtering device.

[0180] (Sample A8)

[0181] The oxide semiconductor film formation conditions for sample A8 are as follows: substrate temperature 170°C; oxygen gas at a flow rate of 100 sccm is introduced into the chamber, i.e., a 100% oxygen atmosphere is used; pressure is 0.6 Pa; and 2500 W of AC power is supplied to the target (In:Ga:Zn = 4:2:4.1) placed in the sputtering apparatus. Note that sample A8 is the same as sample A3.

[0182] Next, the amount of gas with a mass-to-charge ratio (M / z) of 32, i.e., gas equivalent to oxygen (O2), released from the silicon oxynitride films of the manufactured samples A6 to A8 was measured. A TDS analyzer was used to measure the amount of gas released.

[0183] Figure 14A The TDS measurement results for samples A6 to A8 are shown. Figure 14A In the diagram, the vertical axis represents the amount of gas released at M / z = 32, and the horizontal axis represents the sample name, etc.

[0184] like Figure 14AThe results show that the gas release amount of sample A6 with M / z = 32 is 1.19 × 10⁻⁶. 14 / cm 2 The amount of gas released from sample A7 at M / z = 32 was 5.02 × 10⁻⁶. 14 / cm 2 The amount of gas released from sample A8 at M / z = 32 was 1.14 × 10⁻⁶. 15 / cm 2 .

[0185] Thus, it can be understood that when forming an oxide semiconductor film on an insulating film (here, a silicon oxynitride film) on which an oxide semiconductor film is formed using a sputtering method, it is preferable to increase the oxygen gas flow rate during the formation of the oxide semiconductor film when adding excess oxygen to the insulating film.

[0186] [1-2-3. Evaluation of the amount of oxygen added to the insulating film when the deposition power is changed]

[0187] Next, samples A9 to A12 will be described. Note that samples A9 to A12 are used to determine the amount of oxygen added to the insulating film when changing the deposition power.

[0188] For samples A9 to A12, a silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate using a PECVD apparatus, followed by heat treatment. After heat treatment, an oxide semiconductor film with a thickness of 50 nm was formed on the silicon oxynitride film using a sputtering apparatus. Then, the oxide semiconductor film was removed, exposing the surface of the silicon oxynitride film. The formation conditions of the silicon oxynitride film and the heat treatment conditions were the same as those for samples A1 to A8. The formation conditions of the oxide semiconductor film for samples A9 to A12 were different from each other.

[0189] (Sample A9)

[0190] The oxide semiconductor film formation conditions for sample A9 are as follows: substrate temperature is 170℃; oxygen gas with a flow rate of 100 sccm is introduced into the chamber, i.e., a 100% oxygen gas atmosphere is used; pressure is 0.6 Pa; and 500 W of AC power is supplied to the target (In:Ga:Zn = 4:2:4.1) placed in the sputtering device.

[0191] (Sample A10)

[0192] The oxide semiconductor film formation conditions for sample A10 are as follows: substrate temperature is 170℃; oxygen gas with a flow rate of 100 sccm is introduced into the chamber, i.e., a 100% oxygen gas atmosphere is used; pressure is 0.6 Pa; 1500 W of AC power is supplied to the target (In:Ga:Zn = 4:2:4.1) placed in the sputtering device.

[0193] (Sample A11)

[0194] The oxide semiconductor film formation conditions for sample A11 were as follows: substrate temperature 170°C; oxygen gas at a flow rate of 100 sccm was introduced into the chamber, i.e., a 100% oxygen atmosphere was used; pressure 0.6 Pa; and 2500 W of AC power was supplied to the target (In:Ga:Zn = 4:2:4.1) placed in the sputtering apparatus. Note that sample A11 is the same as samples A3 and A8.

[0195] (Sample A12)

[0196] The oxide semiconductor film formation conditions for sample A12 are as follows: substrate temperature is 170℃; oxygen gas with a flow rate of 100 sccm is introduced into the chamber, i.e., a 100% oxygen gas atmosphere is used; pressure is 0.6 Pa; and 4500 W of AC power is supplied to the target (In:Ga:Zn = 4:2:4.1) placed in the sputtering device.

[0197] Next, the amount of gas with a mass-to-charge ratio (M / z) of 32, i.e., gas equivalent to oxygen (O2), released from the silicon oxynitride films of the manufactured samples A9 to A12 was measured. A TDS analyzer was used to measure the amount of gas released.

[0198] Figure 14B The TDS measurement results for samples A9 to A12 are shown. Figure 14B In the diagram, the vertical axis represents the amount of gas released at M / z = 32, and the horizontal axis represents the sample name, etc.

[0199] like Figure 14B The results show that the gas release amount of sample A9 with M / z = 32 is 9.28 × 10⁻⁶. 14 / cm 2 The amount of gas released from sample A10 at M / z = 32 was 1.07 × 10⁻⁶. 15 / cm 2 The amount of gas released from sample A11 at M / z = 32 was 1.14 × 10⁻⁶. 15 / cm 2 The amount of gas released from sample A12 at M / z = 32 was 1.24 × 10⁻⁶. 15 / cm 2 .

[0200] Thus, it can be seen that when forming an oxide semiconductor film on an insulating film (here, a silicon oxynitride film) on which an oxide semiconductor film is formed using a sputtering method, it is preferable to increase the deposition power when forming the oxide semiconductor film when adding excess oxygen to the insulating film.

[0201] [1-2-4. Evaluation of the amount of oxygen added to the insulating film when the deposition pressure is changed]

[0202] Next, samples A13 to A15 will be described. Note that samples A13 to A15 are used to confirm the amount of oxygen added to the insulating film when determining the deposition pressure.

[0203] For samples A13 to A15, a silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate using a PECVD apparatus, followed by heat treatment. After heat treatment, an oxide semiconductor film with a thickness of 50 nm was formed on the silicon oxynitride film using a sputtering apparatus. Then, the oxide semiconductor film was removed, exposing the surface of the silicon oxynitride film. The formation conditions of the silicon oxynitride film and the heat treatment conditions were the same as those for samples A1 to A12. The formation conditions of the oxide semiconductor film for samples A13 to A15 were different for each sample.

[0204] (Sample A13)

[0205] The oxide semiconductor film formation conditions for sample A13 are as follows: substrate temperature is 170℃; oxygen gas with a flow rate of 100 sccm is introduced into the chamber, i.e., a 100% oxygen gas atmosphere is used; pressure is 0.3 Pa; and 2500 W of AC power is supplied to the target (In:Ga:Zn = 4:2:4.1) placed in the sputtering device.

[0206] (Sample A14)

[0207] The oxide semiconductor film formation conditions for sample A14 were as follows: substrate temperature 170°C; oxygen gas at a flow rate of 100 sccm was introduced into the chamber, i.e., a 100% oxygen atmosphere was used; pressure 0.6 Pa; and 2500 W of AC power was supplied to the target (In:Ga:Zn = 4:2:4.1) placed in the sputtering apparatus. Note that sample A14 is the same as samples A3, A8, and A11.

[0208] (Sample A15)

[0209] The oxide semiconductor film formation conditions for sample A15 are as follows: substrate temperature is 170℃; oxygen gas with a flow rate of 100 sccm is introduced into the chamber, i.e., a 100% oxygen gas atmosphere is used; pressure is 0.8 Pa; and 2500 W of AC power is supplied to the target (In:Ga:Zn = 4:2:4.1) placed in the sputtering device.

[0210] Next, the amount of gas with a mass-to-charge ratio (M / z) of 32, i.e., gas equivalent to oxygen (O2), released from the silicon oxynitride films of the manufactured samples A13 to A15 was measured. A TDS analyzer was used to measure the amount of gas released.

[0211] Figure 15A The TDS measurement results for samples A13 to A15 are shown. Figure 15A In the diagram, the vertical axis represents the amount of gas released at M / z = 32, and the horizontal axis represents the sample name, etc.

[0212] like Figure 15A The results show that the gas release amount of sample A13 with M / z = 32 is 1.17 × 10⁻⁶. 15 / cm 2 The amount of gas released from sample A14 at M / z = 32 was 1.14 × 10⁻⁶. 15 / cm 2 The amount of gas released from sample A15 at M / z = 32 was 1.15 × 10⁻⁶. 15 / cm 2 .

[0213] Thus, no significant variation in the amount of oxygen added to the insulating film (oxygen released from the insulating film) due to different pressures during the formation of the oxide semiconductor film was observed.

[0214] [1-2-5. Evaluation of the amount of oxygen added to the insulating film when the thickness is changed]

[0215] Next, samples A16 to A20 will be described. Note that samples A16 to A20 are used to determine the amount of oxygen added to the insulating film when the thickness is changed.

[0216] For samples A16 to A20, a silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate using a PECVD apparatus, followed by heat treatment. After heat treatment, an oxide semiconductor film was formed on the silicon oxynitride film using a sputtering apparatus. Then, the oxide semiconductor film was removed, exposing the surface of the silicon oxynitride film. The formation conditions and heat treatment conditions of the silicon oxynitride film were the same as those for samples A1 to A15. The thicknesses of the oxide semiconductor films in samples A16 to A20 were different.

[0217] (Sample A16)

[0218] The oxide semiconductor film thickness of sample A16 is 0 nm. That is, sample A16 is a sample without an oxide semiconductor film. Note that sample A16 is the same as sample A1.

[0219] (Sample A17)

[0220] The oxide semiconductor film of sample A17 has a thickness of 10 nm. The formation conditions of the oxide semiconductor film of sample A17 are as follows: substrate temperature is 170 °C; oxygen gas with a flow rate of 100 sccm is introduced into the chamber, i.e., a 100% oxygen gas atmosphere is used; pressure is 0.6 Pa; and 2500 W of AC power is supplied to the target material (In:Ga:Zn = 4:2:4.1 (atomic ratio)) placed in the sputtering device.

[0221] (Sample A18)

[0222] The oxide semiconductor film of sample A18 has a thickness of 50 nm. The formation conditions of the oxide semiconductor film of sample A18 are the same as those of sample A17. Note that sample A18 is the same as samples A3, A8, A11, and A14.

[0223] (Sample A19)

[0224] The oxide semiconductor film of sample A19 has a thickness of 100 nm. The formation conditions of the oxide semiconductor film of sample A19 are the same as those of sample A17.

[0225] (Sample A20)

[0226] The oxide semiconductor film of sample A20 has a thickness of 300 nm. The formation conditions of the oxide semiconductor film of sample A20 are the same as those of sample A17.

[0227] Next, the amount of gas with a mass-to-charge ratio (M / z) of 32, i.e., gas equivalent to oxygen (O2), released from the silicon oxynitride films of the manufactured samples A16 to A20 was measured. A TDS analyzer was used to measure the amount of gas released.

[0228] Figure 15B The TDS measurement results for samples A16 to A20 are shown. Figure 15B In the diagram, the vertical axis represents the amount of gas released at M / z = 32, and the horizontal axis represents the sample name.

[0229] like Figure 15B The results show that the gas release amount of sample A16 with M / z = 32 is 1.82 × 10⁻⁶. 14 / cm 2 The amount of gas released from sample A17 at M / z = 32 was 1.08 × 10⁻⁶. 15 / cm 2 The amount of gas released from sample A18 at M / z = 32 was 1.14 × 10⁻⁶. 15 / cm 2 The amount of gas released from sample A19 at M / z = 32 was 1.11 × 10⁻⁶. 15 / cm 2The amount of gas released from sample A20 at M / z = 32 was 1.17 × 10⁻⁶. 15 / cm 2 .

[0230] Thus, it can be seen that when an oxide semiconductor film is formed on an insulating film (here, a silicon oxynitride film) on which an oxide semiconductor film is formed by sputtering with a thickness of 10 nm or more, excess oxygen can be added to the insulating film.

[0231] <1-3. Oxide Conductors>

[0232] Next, the oxide conductor will be described. In the process of forming oxide semiconductor films 120a and 120b, the oxide semiconductor films 120a and 120b are used as protective films to suppress the release of oxygen from insulating films 114 and 116. The oxide semiconductor films 120a and 120b are used as semiconductors before the process of forming insulating film 118 and as conductors after the process of forming insulating film 118. Therefore, the oxide semiconductor films 120a and 120b can be referred to as oxide conductors (OC).

[0233] To use the oxide semiconductor films 120a and 120b as conductors, oxygen vacancies are formed in the oxide semiconductor films 120a and 120b, and hydrogen is added to these oxygen vacancies from the insulating film 118, thereby forming donor levels near the conduction band. As a result, the conductivity of the oxide semiconductor films 120a and 120b increases, and the oxide semiconductor films become conductive. The conductive oxide semiconductor films 120a and 120b can be called oxide conductors. Generally, oxide semiconductors are transparent to visible light due to their large band gap. On the other hand, oxide conductors are oxide semiconductors with donor levels near the conduction band. Therefore, due to the small influence of absorption at these donor levels, they have approximately the same transparency to visible light as oxide semiconductors.

[0234] Here, use Figure 16 This section describes the temperature dependence of the resistivity of films formed using oxide conductors (hereinafter referred to as oxide conductive films).

[0235] Here, samples B1 to B4, including oxide conductive films, are fabricated. For samples B1 to B3, an oxide semiconductor film with a thickness of 100 nm is formed on a glass substrate using sputtering. Next, a silicon nitride film containing hydrogen with a thickness of 100 nm is formed on the oxide semiconductor film using PECVD. The target composition and formation conditions of the oxide semiconductor films for samples B1 to B3 are different. For sample B4, an oxide conductive film with a thickness of 100 nm is formed on a glass substrate using sputtering.

[0236] Figure 16 The sheet resistance measurements for each sample are shown. The sheet resistance was determined using the four-terminal van der Pauw method. Figure 16 In the diagram, the vertical axis represents the sheet resistance, and the horizontal axis represents the measurement temperature. The manufacturing methods for each sample are shown below.

[0237] (Sample B1)

[0238] The formation conditions for the oxide semiconductor film of sample B1 were as follows: substrate temperature 170℃; oxygen gas at a flow rate of 100 sccm was introduced into the chamber, i.e., a 100% oxygen atmosphere was used; pressure 0.6 Pa; and 2500 W of AC power was supplied to the target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) placed in the sputtering apparatus. Figure 16 In the figure, the composition of the oxide semiconductor film of sample B1 is represented as IGZO (423). Note that the values ​​in parentheses are not the composition of the target material, but the composition of the film formed. This also applies to IGZO (312) and IGZO (136).

[0239] (Sample B2)

[0240] The formation conditions for the oxide semiconductor film of sample B2 were as follows: substrate temperature 170°C; oxygen gas at a flow rate of 100 sccm was introduced into the chamber, i.e., a 100% oxygen atmosphere was used; pressure 0.6 Pa; and 2500 W of AC power was supplied to the target (In:Ga:Zn = 3:1:2 [atomic ratio]) placed in the sputtering apparatus. Additionally, in Figure 16 In this paper, the oxide semiconductor film of sample B2 is denoted as IGZO(312).

[0241] (Sample B3)

[0242] The formation conditions for the oxide semiconductor film of sample B3 were as follows: substrate temperature 170°C; oxygen gas at a flow rate of 100 sccm was introduced into the chamber, i.e., a 100% oxygen atmosphere was used; pressure 0.8 Pa; and 2500 W of AC power was supplied to the target (In:Ga:Zn = 1:3:6) placed in the sputtering apparatus. Additionally, in Figure 16 In the figure, the oxide semiconductor film of sample B3 is represented as IGZO(136).

[0243] (Sample B4)

[0244] The oxide conductive film formation conditions for sample B4 were as follows: substrate temperature was room temperature; argon gas at a flow rate of 72 sccm and oxygen gas at a flow rate of 5 sccm were introduced into the chamber; the pressure was 0.15 Pa; and 3200 W of DC power was supplied to the target (an oxide target containing indium, tin, and silicon, In₂O₃:SnO₂:SiO₂ = 85:10:5 [wt%]) placed in the sputtering apparatus. Figure 16 In the figure, NITO is used as the oxide conductive film of sample B4.

[0245] according to Figure 16 The results show that the sheet resistance of the oxide semiconductor film of samples B1 and B2 is higher than that of sample B4, at 1.0 × 10⁻⁶. 2 Ω / □ or higher and 1.0 × 10 3 Below Ω / □. Furthermore, the change in sheet resistance based on the measurement temperature is also minimal. That is to say, the oxide conductors used for samples B1 and B2 are degenerate semiconductors, and it can be inferred that their conduction band bottom level coincides with or is approximately coincident with the Fermi level. On the other hand, the sheet resistance of the oxide semiconductor film in sample B3 is very high, exceeding the upper limit of measurement (1.0 × 10⁻⁶). 6 Because the resistance is above Ω / □, it is difficult to measure the resistance of thin films.

[0246] As described above, in one aspect of the semiconductor device of the present invention, oxygen is added to the surface of the oxide semiconductor film during the process of forming the oxide semiconductor film. Both the first oxide semiconductor film used as the channel region and the second oxide semiconductor film used as the second gate electrode are oxide semiconductor films containing the same metal element. An insulating film containing hydrogen is formed on the second oxide semiconductor film, thereby making the second oxide semiconductor film an oxide conductive film. By employing this structure, a semiconductor device with suppressed variations in electrical characteristics and high reliability can be achieved.

[0247] <1-4. Components of a Semiconductor Device>

[0248] The constituent elements of the semiconductor device according to this embodiment will be described in detail below.

[0249] [Substrate]

[0250] While there are no particular restrictions on the material of substrate 102, it must at least possess heat resistance capable of withstanding subsequent heat treatments. For example, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., can be used as substrate 102. Additionally, single-crystal or polycrystalline semiconductor substrates made of silicon or silicon carbide, compound semiconductor substrates made of silicon-germanium, SOI (Silicon on Insulator) substrates, etc., can also be used. Furthermore, any of the aforementioned substrates on which semiconductor elements are disposed can be used as substrate 102. When a glass substrate is used as substrate 102, glass substrates with any of the following sizes can be used: sixth generation (1500mm × 1850mm), seventh generation (1870mm × 2200mm), eighth generation (2200mm × 2400mm), ninth generation (2400mm × 2800mm), tenth generation (2950mm × 3400mm), etc. This allows for the manufacture of large-scale display devices.

[0251] A flexible substrate can also be used as substrate 102, and transistor 100 can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between substrate 102 and transistor 100. The release layer can be used when a part or all of a semiconductor device is fabricated on the release layer, and then it is separated from substrate 102 and transferred to another substrate. In this case, transistor 100 can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0252] [The conductive film used as the first gate electrode, source electrode, and drain electrode]

[0253] The conductive film 104 used as the gate electrode, the conductive film 112a used as the source electrode, and the conductive film 112b used as the drain electrode can be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co), an alloy with any of the above metal elements as its components, or an alloy combining any of the above metal elements.

[0254] Furthermore, conductive films 104, 112a, and 112b can have a single-layer structure or a stacked structure of two or more layers. Examples include a single-layer structure of an aluminum film containing silicon, a two-layer structure of a titanium film stacked on an aluminum film, a two-layer structure of a titanium film stacked on a titanium nitride film, a two-layer structure of a tungsten film stacked on a titanium nitride film, a two-layer structure of a tantalum nitride film or a tungsten nitride film stacked on a tungsten film, and a three-layer structure of a titanium film, an aluminum film, and a titanium film stacked sequentially. Additionally, alloy films or nitride films formed by combining aluminum with one or more of titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can also be used.

[0255] Conductive films 104, 112a, and 112b can also be made of transparent conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon oxide.

[0256] Alternatively, Cu-X alloy films (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be used as conductive films 104, 112a, and 112b. By using Cu-X alloy films, processing can be performed using a wet etching process, thereby reducing manufacturing costs.

[0257] [The insulating film used as the first gate insulating film]

[0258] The insulating films 106 and 107, which are used as the gate insulating films of the transistor 100, can be one or more insulating layers selected from silicon oxide films, silicon oxynitride films, silicon oxynitride films, silicon nitride films, aluminum oxide films, hafnium oxide films, yttrium oxide films, zirconium oxide films, gallium oxide films, tantalum oxide films, magnesium oxide films, lanthanum oxide films, cerium oxide films, and neodymium oxide films, formed by plasma-enhanced chemical vapor deposition (PECVD), sputtering, etc. Note that single-layer or three-layer or more insulating films of the above materials can also be used instead of the stacked structure of insulating films 106 and 107.

[0259] The insulating film 106 functions as a barrier film that inhibits oxygen permeation. For example, when excess oxygen is supplied to the insulating films 107, 114, 116 and / or the oxide semiconductor film 108, the insulating film 106 can inhibit oxygen permeation.

[0260] The insulating film 107 that contacts the oxide semiconductor film 108 used as the channel region of the transistor 100 is preferably an oxide insulating film, and this insulating film 107 preferably includes regions where the oxygen content exceeds the stoichiometric composition (oxygen excess regions). In other words, the insulating film 107 is an insulating film capable of releasing oxygen. Furthermore, in order to provide oxygen excess regions in the insulating film 107, the insulating film 107 can be formed, for example, in an oxygen atmosphere. Alternatively, oxygen can be added to the deposited insulating film 107. The method of adding oxygen to the deposited insulating film 107 will be described later.

[0261] Furthermore, when hafnium oxide is used in the insulating film 107, the following effects occur: Hafnium oxide has a higher relative permittivity than silicon oxide or silicon oxynitride. Therefore, by using hafnium oxide, the thickness of the insulating film 107 can be increased compared to the case where silicon oxide is used, thereby reducing leakage current caused by tunneling current. That is, a transistor with a small off-state current can be realized. Moreover, hafnium oxide with a crystalline structure has a higher relative permittivity than hafnium oxide with an amorphous structure. Therefore, hafnium oxide with a crystalline structure is preferably used to form a transistor with a small off-state current. Examples of crystalline structures include monoclinic or cubic crystal systems. Note that one aspect of the invention is not limited to this.

[0262] Note that in this embodiment, a silicon nitride film is formed as insulating film 106, and a silicon oxide film is formed as insulating film 107. Compared to a silicon oxide film, a silicon nitride film has a higher relative permittivity and requires a larger thickness to obtain an electrostatic capacitance equal to that of a silicon oxide film. Therefore, by including a silicon nitride film in the gate insulating film of transistor 150, the physical thickness of the insulating film can be increased. Therefore, electrostatic discharge damage to transistor 100 can be suppressed by suppressing the drop in its dielectric withstand voltage and increasing the dielectric withstand voltage.

[0263] [Oxide semiconductor film]

[0264] The above-mentioned material can be used as the oxide semiconductor film 108.

[0265] When the oxide semiconductor film 108b is an In-M-Zn oxide, the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide preferably satisfies In > M. Examples of such atomic ratios for the metal elements in the sputtering target include In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, and In:M:Zn = 4:2:4.1.

[0266] Furthermore, when the oxide semiconductor film 108c is an In-M-Zn oxide, the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide preferably satisfies In ≤ M. Examples of such atomic ratios for the metal elements in the sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, and In:M:Zn = 1:3:6.

[0267] Furthermore, when the oxide semiconductor film 108b and oxide semiconductor film 108c are In-M-Zn oxides, a sputtering target containing polycrystalline In-M-Zn oxide is preferably used. By using a target containing polycrystalline In-M-Zn oxide, crystalline oxide semiconductor films 108b and 108c can be easily formed. Note that the atomic ratio of the formed oxide semiconductor film 108b and oxide semiconductor film 108c is within ±40% of the atomic ratio of the metal elements in the sputtering target. For example, when an atomic ratio of In:Ga:Zn = 4:2:4.1 is used as the sputtering target for oxide semiconductor film 108b, the atomic ratio of the formed oxide semiconductor film 108b is sometimes around In:Ga:Zn = 4:2:3.

[0268] The bandgap of the oxide semiconductor film 108 is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. Thus, by using an oxide semiconductor with a wider bandgap, the off-state current of the transistor 100 can be reduced. In particular, an oxide semiconductor film with a bandgap of 2 eV or more, preferably 2 eV or more and 3.0 eV or less, is used as oxide semiconductor film 108b, and an oxide semiconductor film with a bandgap of 2.5 eV or more and 3.5 eV or less is used as oxide semiconductor film 108c. Furthermore, it is preferable that the bandgap of oxide semiconductor film 108c is larger than that of oxide semiconductor film 108b.

[0269] Furthermore, the thicknesses of the oxide semiconductor film 108b and the oxide semiconductor film 108c are respectively 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0270] Furthermore, an oxide semiconductor film with a low carrier density is used as the oxide semiconductor film 108c. For example, the carrier density of the second oxide semiconductor film 108c is 1 × 10⁻⁶. 17 / cm 3 The following is preferred: 1×10 15 / cm 3 Hereinafter, 1×10 is more preferred. 13 / cm 3 Hereinafter, 1×10 is further preferred. 11 / cm 3 the following.

[0271] This invention is not limited to the above-described composition and materials; materials with appropriate compositions can be used according to the desired semiconductor and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Furthermore, it is preferable to appropriately set the carrier density, impurity concentration, defect density, ratio of metal elements to oxygen atoms, interatomic distance, and density of the oxide semiconductor film 108b and 108c to obtain the desired semiconductor characteristics of the transistor.

[0272] By using oxide semiconductor films with low impurity concentration and low defect state density as oxide semiconductor films 108b and 108c, respectively, transistors with superior electrical characteristics can be manufactured, which is therefore preferred. Here, the state of low impurity concentration and low defect state density (few oxygen vacancies) is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have fewer carrier generation sources, the carrier density can be reduced. Therefore, transistors with a channel region formed in this oxide semiconductor film rarely exhibit negative threshold voltage characteristics (also known as always-on characteristics). Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect state density, they are likely to have a low trap state density. The off-state current of high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films is significantly small, even when the channel width W is 1 × 10⁻⁶. 6 For a device with a diameter of μm and a channel length L of 10μm, when the voltage between the source and drain electrodes (drain voltage) is in the range of 1V to 10V, the off-state current can also be below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10⁻⁶. -13 Below A.

[0273] Therefore, transistors with channel regions formed in oxide semiconductor films of high intrinsic purity or substantially high intrinsic purity can be transistors with small variations in electrical characteristics and high reliability. Furthermore, the charge trapped in the trap levels of the oxide semiconductor film requires a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, transistors with channel regions formed in oxide semiconductor films with high trap state density sometimes exhibit unstable electrical characteristics. Impurities include hydrogen, nitrogen, alkali metals, or alkaline earth metals.

[0274] Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to form water, while oxygen vacancies are formed in the lattice (or the portion where oxygen desorption occurs) where oxygen desorption takes place. When hydrogen enters this oxygen vacancy, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using oxide semiconductor films containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the oxide semiconductor film 108. Specifically, the hydrogen concentration in the oxide semiconductor film 108, measured using SIMS (Secondary Ion Mass Spectrometry), is 2 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is more preferably 5×10 17 atoms / cm 3 Hereinafter, 1×10 is more preferred. 16 atoms / cm 3 the following.

[0275] Furthermore, the oxide semiconductor film 108b preferably includes a region with a hydrogen concentration lower than that of the oxide semiconductor film 108c. By including a region with a hydrogen concentration lower than that of the oxide semiconductor film 108c in the oxide semiconductor film 108b, a highly reliable semiconductor device can be provided.

[0276] Furthermore, when the oxide semiconductor film 108b contains silicon or carbon, one of the Group 14 elements, the increase in oxygen vacancies in the oxide semiconductor film 108b leads to the n-type formation of the oxide semiconductor film 108b. Therefore, the concentration of silicon or carbon in the oxide semiconductor film 108b (the concentration measured using SIMS analysis) and the concentration of silicon or carbon near the interface with the oxide semiconductor film 108b (the concentration measured using SIMS analysis) are 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 17 atoms / cm 3 the following.

[0277] Furthermore, in the oxide semiconductor film 108b, the concentration of alkali metals or alkaline earth metals, as measured by SIMS analysis, is 1 × 10⁻⁶.18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 The following applies. When alkali metals and alkaline earth metals bond with oxide semiconductors, charge carriers are sometimes generated, which increases the off-state current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor film 108b.

[0278] When nitrogen is present in the oxide semiconductor film 108b, electrons are generated as charge carriers, increasing the charge carrier density and making the oxide semiconductor film 108b more prone to n-type conversion. As a result, transistors using nitrogen-containing oxide semiconductor films tend to exhibit always-on characteristics. Therefore, it is preferable to minimize the nitrogen content in the oxide semiconductor film; for example, a nitrogen concentration measured using SIMS analysis is preferably 5 × 10⁻⁶. 18 atoms / cm 3 the following.

[0279] For example, oxide semiconductor films 108b and 108c can each have non-single-crystal structures. Non-single-crystal structures include, for example, CAAC-OS (C-axis Aligned Crystalline Oxide Semiconductor), polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, amorphous structures have the highest defect state density, while CAAC-OS has the lowest.

[0280] [Insulating film used as the second gate insulating film]

[0281] Insulating films 114 and 116 are used as the second gate insulating films of transistor 100. Furthermore, insulating films 114 and 116 function to supply oxygen to oxide semiconductor film 108. That is, insulating films 114 and 116 contain oxygen. Additionally, insulating film 114 is an insulating film that allows oxygen to permeate. Note that insulating film 114 also serves as a film to mitigate damage to oxide semiconductor film 108 during the subsequent formation of insulating film 116.

[0282] As the insulating film 114, a silicon oxide film or silicon oxynitride film with a thickness of 5 nm or more and 150 nm or less can be used, preferably 5 nm or more and 50 nm or less.

[0283] Furthermore, it is preferable to have a low amount of defects in the insulating film 114. Typically, the spin density of the signal originating from silicon dangling bonds and appearing at g = 2.001, as measured by electron spin resonance (ESR), is preferably 3 × 10⁻⁶. 17 spins / cm 3The reason is that if the defect density of the insulating film 114 is high, oxygen will bond with the defect, thereby reducing the amount of oxygen permeating the insulating film 114.

[0284] In the insulating film 114, sometimes oxygen entering from the outside does not completely migrate to the outside of the insulating film 114, but a portion of it remains inside the insulating film 114. Additionally, sometimes oxygen entering the insulating film 114 also migrates to the outside of the insulating film 114, thus causing oxygen movement within the insulating film 114. When forming an oxide insulating film 114 that allows oxygen to permeate, oxygen detached from the insulating film 116 disposed on the insulating film 114 can pass through the insulating film 114 and move into the oxide semiconductor film 108.

[0285] Furthermore, the insulating film 114 can be formed using an oxide insulating film due to the low density of states of nitrides. Note that this density of states due to nitrides can sometimes be formed at the energy (E) at the valence band top of the oxide semiconductor film. V _ OS The energy of the conduction band bottom of the oxide semiconductor film (E) C _ OS Between ), as the above-mentioned oxide insulating film, silicon oxynitride film with low nitrogen oxide emission or aluminum oxynitride film with low nitrogen oxide emission can be used.

[0286] Furthermore, in thermal desorption spectroscopy, silicon oxynitride films with low nitrogen oxide release are those with higher ammonia release than nitrogen oxide release, typically with an ammonia release of 1 × 10⁻⁶. 18 / cm 3 Above and 5×10 19 / cm 3 Note that this ammonia release amount is the amount released during heat treatment at a membrane surface temperature of 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower.

[0287] Nitrogen oxides (NO) x (where x is greater than 0 and less than 2, preferably greater than 1 and less than 2), typically NO2 or NO forms an energy level in the insulating film 114, etc. This energy level is located in the band gap of the oxide semiconductor film 108. Therefore, when nitrogen oxides diffuse to the interface between the insulating film 114 and the oxide semiconductor film 108, sometimes this energy level traps electrons on the insulating film 114 side. As a result, the trapped electrons remain near the interface between the insulating film 114 and the oxide semiconductor film 108, thereby causing the threshold voltage of the transistor to drift in the positive direction.

[0288] Furthermore, during heat treatment, nitrogen oxides react with ammonia and oxygen. During heat treatment, the nitrogen oxides contained in insulating film 114 react with the ammonia contained in insulating film 116, thereby reducing the amount of nitrogen oxides contained in insulating film 114. Therefore, electrons are less likely to be trapped at the interface between insulating film 114 and oxide semiconductor film 108.

[0289] By using the aforementioned oxide insulating film as insulating film 114, the threshold voltage drift of the transistor can be reduced, thereby reducing the variation in the electrical characteristics of the transistor.

[0290] Through heat treatment during transistor manufacturing, typically above 300°C and below 350°C, the ESR spectrum of the insulating film 114 below 100K revealed a first signal with a g value of 2.037 to 2.039, a second signal with a g value of 2.001 to 2.003, and a third signal with a g value of 1.964 to 1.966. In X-band ESR measurements, the split width between the first and second signals, and between the second and third signals, was approximately 5 mT. Furthermore, the sum of the spin densities of the first signal (g value 2.037 to 2.039), the second signal (g value 2.001 to 2.003), and the third signal (g value 1.964 to 1.966) was less than 1 × 10⁻⁶. 18 spins / cm 3 Typically 1×10 17 spins / cm 3 Above and below 1×10 18 spins / cm 3 .

[0291] In ESR spectra below 100 K, the first signal with a g value of 2.037 to 2.039, the second signal with a g value of 2.001 to 2.003, and the third signal with a g value of 1.964 to 1.966 are all attributed to nitrogen oxides (NO). x The signal has a value of x greater than 0 and less than 2, preferably greater than 1 and less than 2. Typical examples of nitrogen oxides include nitric oxide and nitrogen dioxide. That is, the lower the total number of spin densities of the first signal with a g value of 2.037 or greater and less than 2.039, the lower the second signal with a g value of 2.001 or greater and less than 2.003, and the lower the third signal with a g value of 1.964 or greater and less than 1.966, the lower the nitrogen oxide content in the oxide insulating film.

[0292] In addition, the nitrogen concentration of the aforementioned oxide insulating film, measured using SIMS, was 6 × 10⁻⁶. 20 atoms / cm3 the following.

[0293] By forming the above-mentioned oxide insulating film using PECVD with silane and nitrous oxide at a substrate temperature of 220°C or higher and 350°C or lower, a dense and hard film can be formed.

[0294] Insulating film 116 is formed using an oxide insulating film with an oxygen content exceeding its stoichiometric composition. Upon heating, a portion of the oxygen is released from the oxide insulating film with the oxygen content exceeding its stoichiometric composition. In TDS analysis, the oxygen release amount, converted to oxygen atoms, from the oxide insulating film with the oxygen content exceeding its stoichiometric composition is 1.0 × 10⁻⁶. 19 atoms / cm 3 The preferred value is 3.0 × 10⁴. 20 atoms / cm 3 That's all. Note that in the above TDS, the surface temperature of the membrane is preferably 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower.

[0295] The insulating film 116 can be a silicon oxide film or a silicon oxynitride film with a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 400 nm or less.

[0296] Furthermore, it is preferable to have a low amount of defects in the insulating film 116; typically, the spin density of the signal originating from silicon dangling bonds and appearing at g = 2.001, as measured by ESR, is less than 1.5 × 10⁻⁶. 18 spins / cm 3 More preferably 1×10 18 spins / cm 3 Therefore, since the insulating film 116 is farther away from the oxide semiconductor film 108 than the insulating film 114, the defect density of the insulating film 116 can also be higher than that of the insulating film 114.

[0297] Furthermore, since insulating films 114 and 116 can be formed using the same type of material, the boundary between insulating films 114 and 116 is sometimes not clearly observable. Therefore, in this embodiment, the boundary between insulating films 114 and 116 is shown as a dashed line. Note that although a two-layer structure of insulating films 114 and 116 is described in this embodiment, the present invention is not limited thereto; for example, a single-layer structure of insulating film 114 may also be used.

[0298] [Oxide semiconductor film used as pixel electrode and oxide semiconductor film used as second gate electrode]

[0299] The oxide semiconductor film 120a used as a pixel electrode and the oxide semiconductor film 120b used as a second gate electrode can be manufactured using the same materials and the same manufacturing method as the oxide semiconductor film 108 described above.

[0300] Alternatively, the oxide semiconductor film 120a used as a pixel electrode and the oxide semiconductor film 120b used as a second gate electrode may contain at least one of the metal elements contained in the oxide semiconductor film 108. For example, In oxide, In-Sn oxide, In-Zn oxide, In-Ga oxide, Zn oxide, Al-Zn oxide, In-Ga-Zn oxide, etc., may be used for the oxide semiconductor films 120a and 120b. In particular, it is preferable to use In-Sn oxide or In-Ga-Zn oxide for the oxide semiconductor films 120a and 120b.

[0301] Specifically, transparent conductive materials such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium zinc oxide, and indium tin silicon oxide (ITSO) can be used in oxide semiconductor films 120a and 120b.

[0302] That is, the oxide semiconductor film 120a used as a pixel electrode and the oxide semiconductor film 120b used as a second gate electrode contain at least one of the metal elements contained in the oxide semiconductor film 108 (oxide semiconductor film 108b and oxide semiconductor film 108c). For example, by making the oxide semiconductor film 120b used as a second gate electrode and the oxide semiconductor film 108 (oxide semiconductor film 108b and oxide semiconductor film 108c) contain the same metal element, manufacturing costs can be suppressed.

[0303] When the oxide semiconductor film 120a used as the pixel electrode and the oxide semiconductor film 120b used as the second gate electrode are In-M-Zn oxides, the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide preferably satisfies In ≥ M. Examples of such atomic ratios for the metal elements in the sputtering target include In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, and In:M:Zn = 4:2:4.1.

[0304] The oxide semiconductor film 120a, used as a pixel electrode, and the oxide semiconductor film 120b, used as a second gate electrode, can be a single-layer structure or a stacked structure of two or more layers. Note that when the oxide semiconductor films 120a and 120b have a stacked structure, the composition of the sputtering target is not limited to the above composition. The case where the oxide semiconductor films 120a and 120b have a stacked structure will be described later.

[0305] [The insulating film used as a protective insulating film for transistors]

[0306] Insulating film 118 is used as a protective insulating film for transistor 100.

[0307] The insulating film 118 contains one or both of hydrogen and nitrogen. Alternatively, the insulating film 118 contains nitrogen and silicon. The insulating film 118 functions to block oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the insulating film 118, it is possible to prevent oxygen from diffusing from the oxide semiconductor film 108 to the outside and to prevent the oxygen contained in the insulating films 114 and 116 from diffusing to the outside. It is also possible to inhibit hydrogen, water, etc. from entering the oxide semiconductor film 108 from the outside.

[0308] The insulating film 118 has the function of supplying one or both of hydrogen and nitrogen to the oxide semiconductor film 120a, which is used as a pixel electrode, and the oxide semiconductor film 120b, which is used as a second gate electrode. In particular, the insulating film 118 preferably contains hydrogen and has the function of supplying the hydrogen to the oxide semiconductor films 120a and 120b. When hydrogen is supplied from the insulating film 118 to the oxide semiconductor films 120a and 120b, the oxide semiconductor films 120a and 120b are used as conductors.

[0309] As the insulating film 118, a nitride insulating film can be used, for example. Examples of such nitride insulating films include silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride.

[0310] While the various films described above, such as conductive films, insulating films, and oxide semiconductor films, can be formed using sputtering or PECVD methods, other methods, such as thermal CVD (Chemical Vapor Deposition), can also be used. Examples of thermal CVD methods include MOCVD (Metal Organic Chemical Vapor Deposition) and ALD (Atomic Layer Deposition).

[0311] Since thermal CVD is a film-forming method that does not use plasma, it has the advantage of not producing defects caused by plasma damage.

[0312] The deposition using thermal CVD can be performed by simultaneously supplying source gas and oxidant into the chamber, thereby setting the pressure inside the chamber to atmospheric pressure or reducing it, and causing a reaction to occur near or on the substrate.

[0313] Alternatively, deposition using the ALD method can be performed as follows: The pressure within the chamber is set to atmospheric pressure or reduced pressure, and the source gases for the reaction are sequentially introduced into the chamber, then this process is repeated. For example, two or more source gases can be sequentially supplied into the chamber by switching various switching valves (also called high-speed valves). For example, to prevent mixing of multiple source gases, an inert gas (such as argon or nitrogen) can be introduced simultaneously with or after the introduction of the first source gas, followed by the introduction of the second source gas. Note that when the first source gas and the inert gas are introduced simultaneously, the inert gas is used as the carrier gas. Furthermore, the inert gas can be introduced simultaneously with the introduction of the second source gas. Alternatively, the first source gas can be evacuated by vacuum pumping without introducing the inert gas, followed by the introduction of the second source gas. The first source gas adheres to the substrate surface to form a first layer; then the second source gas is introduced to react with this first layer; as a result, the second layer is stacked on top of the first layer, thereby forming a thin film. By repeatedly introducing the gas in this sequence until the desired thickness is obtained, a thin film with good step coverage can be formed. Since the thickness of the thin film can be adjusted according to the number of times the gas is introduced in sequence, the ALD method can precisely control the thickness and is suitable for manufacturing micro FETs.

[0314] Various films, such as conductive films, insulating films, oxide semiconductor films, and metal oxide films, as described in the above embodiments can be formed using thermal CVD methods such as MOCVD or ALD. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. Dimethylzinc has the chemical formula Zn(CH3)2. However, not limited to the above combinations, triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc.

[0315] For example, when forming a hafnium oxide film using an ALD deposition apparatus, two gases are used: ozone (O3) as an oxidant; and a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, tetramethylammonium hafnium (TDMAH), etc.). Furthermore, the chemical formula of tetramethylammonium hafnium is Hf[N(CH3)2]4. Other materials include tetra(ethylmethylammonium)hafnium.

[0316] For example, when forming an alumina film using an ALD deposition apparatus, two gases are used: H₂O as an oxidant; and a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA)). Furthermore, the chemical formula of trimethylaluminum is Al(CH₃)₃. Other liquid materials include tris(dimethylammonium)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptadecyl)one.

[0317] For example, when forming a silicon oxide film using a deposition apparatus employing the ALD method, hexachlorosilane is attached to the surface to be film-forming, removing the chlorine contained in the attached material, and supplying free radicals of oxidizing gases (O2, nitrous oxide) to react with the attached material.

[0318] For example, when forming a tungsten film using an ALD deposition apparatus, WF6 gas and B2H6 gas are introduced sequentially and repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are used to form the final tungsten film. Note that SiH4 gas can also be used instead of B2H6 gas.

[0319] For example, when forming oxide semiconductor films such as In-Ga-ZnO films using an ALD deposition apparatus, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly to form an In-O layer, Ga(CH3)3 gas and O3 gas are used to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are used to form a ZnO layer. Note that the order of these layers is not limited to the example above. Furthermore, these gases can be mixed to form mixed compound layers such as In-Ga-O layers, In-Zn-O layers, Ga-Zn-O layers, etc. Note that although H2O gas obtained by bubbling with an inert gas such as Ar can be used instead of O3 gas, it is preferable to use O3 gas that does not contain H. Additionally, In(C2H5)3 gas can be used instead of In(CH3)3 gas. Additionally, Ga(C2H5)3 gas can be used instead of Ga(CH3)3 gas. Additionally, Zn(CH3)2 gas can also be used.

[0320] <1-5. Example 2 of the structure of a semiconductor device>

[0321] Next, use Figures 2A to 2C Explanation and Figures 1A to 1C Examples of different structures of transistor 100 are shown.

[0322] Figure 2A This is a top view of a transistor 150 of a semiconductor device as an embodiment of the present invention. Figure 2B Equivalent to along Figure 2A The cross-sectional view shown is the dotted-dash line X1-X2. Figure 2C Equivalent to along Figure 2AThe cross-sectional view of the dotted line Y1-Y2 is shown.

[0323] The difference between transistor 150 and transistor 100 is that openings 152b and 152c are formed in the channel width direction. The other structures of transistor 150 are the same as those of transistor 100, and they perform the same function. The following describes the structure that differs from transistor 100.

[0324] like Figure 2C As shown, the oxide semiconductor film 120b, which serves as the second gate electrode, is connected to the conductive film 104, which serves as the first gate electrode, through openings 152b and 152c formed in insulating films 106, 107, and 114, 116. Therefore, the conductive film 104 and the oxide semiconductor film 120b are supplied with the same potential.

[0325] Furthermore, this embodiment illustrates a structure in which openings 152b and 152c are formed to connect the conductive film 104 to the oxide semiconductor film 120b; however, the invention is not limited to this. For example, a structure in which only one of openings 152b and 152c is formed to connect the conductive film 104 to the oxide semiconductor film 120b may also be used. When using such... Figures 1A to 1C When the transistor 100 shown is configured such that the conductive film 104 is not connected to the oxide semiconductor film 120b, different potentials can be supplied to the conductive film 104 and the oxide semiconductor film 120b respectively.

[0326] like Figure 2B As shown, the oxide semiconductor film 108 is located opposite the conductive film 104 used as the first gate electrode and the oxide semiconductor film 120b used as the second gate electrode, sandwiched between the two films used as gate electrodes. The length of the channel in the length direction and the length in the width direction of the oxide semiconductor film 120b used as the second gate electrode are both greater than the length of the channel in the length direction and the length in the width direction of the oxide semiconductor film 108. The oxide semiconductor film 120b covers the entire oxide semiconductor film 108 through the insulating films 114 and 116. Furthermore, since the oxide semiconductor film 120b used as the second gate electrode and the conductive film 104 used as the first gate electrode are connected in the openings 152b and 152c formed in the insulating films 106 and 107 and the insulating films 114 and 116, the side of the oxide semiconductor film 108 in the width direction of the channel is opposite to the oxide semiconductor film 120b used as the second gate electrode through the insulating films 114 and 116.

[0327] In other words, in the channel width direction of transistor 150, the conductive film 104 used as the first gate electrode and the oxide semiconductor film 120b used as the second gate electrode are connected in the openings formed in the insulating films 106 and 107 used as the first gate insulating films and the insulating films 114 and 116 used as the second gate insulating films, while the conductive film 104 and the oxide semiconductor film 120b surround the oxide semiconductor film 108 through the insulating films 106 and 107 used as the first gate insulating films and the insulating films 114 and 116 used as the second gate insulating films.

[0328] By employing the above structure, the conductive film 104, which serves as the first gate electrode, and the oxide semiconductor film 120b, which serves as the second gate electrode, are used to surround the oxide semiconductor film 108 included in the transistor 150. The device structure of a transistor, such as transistor 150, in which the electric fields of the first gate electrode and the second gate electrode surround the oxide semiconductor film in which the channel region is formed, can be called a Surrounded channel (S-channel) structure.

[0329] Because transistor 150 has an S-channel structure, the conductive film 104, which serves as the first gate electrode, can be used to effectively apply an electric field to the oxide semiconductor film 108 to induce a channel. This improves the current-driving capability of transistor 150, resulting in a larger on-state current characteristic. Furthermore, the increased on-state current allows for miniaturization of transistor 150. Additionally, the structure of transistor 150 surrounded by the conductive film 104 (serving as the first gate electrode) and the oxide semiconductor film 120b (serving as the second gate electrode) enhances its mechanical strength.

[0330] <1-5-1. The Effects of the S-channel Structure>

[0331] The following explains the effects that can be obtained by using an S-channel structure in transistors including oxide semiconductors (hereinafter, OS-FET) and transistors including low-temperature polysilicon (hereinafter, LTPS-FET).

[0332] <1-5-2. Improvement of Current Driving Capability (Field-Effect Mobility)>

[0333] First, the current density distribution along the thickness direction of the oxide semiconductor film (OS) with the S-channel structure is calculated. Figure 66A The structure used for calculation is shown. Figure 66B The calculated results of the current density distribution are shown.

[0334] like Figure 66A As shown, in the structure used for calculation, the thickness of the oxide semiconductor film (OS) is set to 35 nm, and the gate electrode is located above and below the OS. The length from the lower gate electrode to the OS is set to 250 nm, and the length from the upper gate electrode to the OS is set to 450 nm. The channel length of the OS is set to 10 μm, and the lengths of the source and drain electrodes in contact with the OS are set to 1 μm. InGaZnO is used as the OS. The voltage (Vg) applied to the upper and lower gate electrodes is set to 0.5 V.

[0335] Figure 66B Show Figure 66A The arrows A1-A2 indicate the current density distribution along the thickness direction of the oxide semiconductor film. (See also:) Figure 66B As shown, the current density distribution is approximately uniform along the thickness direction of the oxide semiconductor film. This can be attributed to the fact that the OS-FET is an accumulation-type FET with an intrinsic channel and its active layer is very thin.

[0336] Next, use Figure 67A and Figure 67B This demonstrates the improved field-effect mobility of OS-FET.

[0337] The field-effect mobility of the OS-FET was calculated using a device simulator. Figure 67A The structure used for the calculation is shown. The parameters used for the calculation are as follows: the channel length is set to 6 μm; the channel width is set to 50 μm; InGaZnO is used as the oxide semiconductor for the channel region, and its thickness is set to 35 nm. The thickness of the lower gate insulating film is set to 280 nm, and the thickness of the upper gate insulating film is set to 480 nm. The mobility of InGaZnO is set to 10 cm⁻¹. 2 / Vs.

[0338] The calculation is performed under two conditions. Condition 1 is that the upper gate electrode is not connected to the lower gate electrode, and 0V, 10V, and 10V (V) are applied to the upper gate electrode, the lower gate electrode, and the drain electrode, respectively. d =10V). Sometimes, condition 1 above is referred to as "Bottom Gate Driving".

[0339] As condition 2, the upper gate electrode is connected to the lower gate electrode, and 10V and 10V (V) are applied to the upper gate electrode and the lower gate electrode and drain electrode, respectively. d=10V). Sometimes, condition 2 above is referred to as "Dual Gate Driving".

[0340] Figure 67B The calculated field-effect mobility of the OS-FET under conditions 1 and 2 above is shown. Figure 67B In the diagram, the solid line represents the leakage current (IL). d The dashed line represents the field-effect mobility (μFE).

[0341] like Figure 67B As shown, the field-effect mobility of the structure with the upper gate electrode connected to the lower gate electrode (Dual Gate Driving) is approximately more than twice that of the structure without the upper gate electrode connected to the lower gate electrode (Bottom Gate Driving). On the other hand, the mobility of the structure without the upper gate electrode connected to the lower gate electrode (Bottom Gate Driving) is lower than the mobility of InGaZnO used for the calculation parameters.

[0342] Thus, by employing Dual Gate Driving in OS-FETs, which connects the upper and lower gate electrodes of an oxide semiconductor, the field-effect mobility of the OS-FET can be higher than that achieved with Bottom Gate Driving.

[0343] <1-5-3. Suppression of Inhomogeneous Properties>

[0344] Next, the I-factor caused by the donor density deviation in the channel region is discussed in the analysis of single-gate structure transistors and S-channel structure transistors. d -V g The non-uniformity of characteristics is calculated.

[0345] V is used as a calculation condition. d =10V, OS-FET is used as the computing model.

[0346] Figure 68A and Figure 68B The calculation results are shown. Figure 68A The calculation results for a single-gate structure are shown. Figure 68B The calculation results for the S-channel structure are shown.

[0347] Depend on Figure 68A and Figure 68B It can be seen that by adopting the S-channel structure, the threshold voltage (V) thThe deviation and the negative drift caused by donor density are reduced to about half that of a single-gate structure. Therefore, by employing an S-channel structure and increasing the gate capacitance, the threshold voltage (V) of the transistor is reduced. th The deviation is reduced.

[0348] When the V section of the channel th The negative drift is represented as -ΔV th At that time, the charge Q arising from the donor impurity can be used. D and gate capacitance C OX Calculate -ΔV th Specifically, it can be expressed as -ΔV th =-(Q D / C OX ).

[0349] When using an S-channel structure, the gate capacitance increases. Specifically, the gate capacitance can be expressed as the sum of the gate capacitance of the lower gate insulating film and the gate capacitance of the upper gate insulating film, i.e., C. OX =C OX1 +C OX2 Note that C OX1 C represents the gate capacitance of the upper gate insulating film. OX2 This represents the gate capacitance of the lower gate insulating film. Therefore, due to the increase in gate capacitance, the threshold voltage (V) can be reduced even if there are deviations in the impurity density of the channel. th () deviation.

[0350] Next, the LTPS-FET will be explained. First, the LTPS-FET is manufactured, and the V of the LTPS-FET is... th The deviations were compared. Figure 69A and Figure 69B , Figure 70A and Figure 70B Showing the I of LTPS-FET d -V g Evaluation results for non-uniform characteristics.

[0351] Figure 69A This shows the threshold voltage (V) of a single-gate n-ch FET with a channel length L of 3 μm and a channel width W of 6 μm. th The probability distribution of ). Figure 69B The threshold voltage (V) of an S-channel n-ch FET with a channel length L of 3 μm and a channel width W of 6 μm is shown. th The probability distribution of ). Figure 70A This shows the threshold voltage (V) of a single-gate p-ch FET with a channel length L of 3 μm and a channel width W of 6 μm. thThe probability distribution of ). Figure 70B The threshold voltage (V) of an S-channel p-ch FET with a channel length L of 3 μm and a channel width W of 6 μm is shown. th The probability distribution of ).

[0352] like Figure 69A and Figure 69B , Figure 70A and Figure 70B As shown, by employing an S-channel structure as an LTPS-FET, the threshold voltage (V) of the transistor can be suppressed. th () deviation.

[0353] Next, for I in the subthreshold region of LTPS-FET d -V g Calculations are performed based on non-uniform characteristics.

[0354] I in the subthreshold region d -V g The calculation conditions for the characteristics were set as follows: the channel length of the transistor was set to 6 μm, and the channel width was set to 10 μm. Additionally, the electron mobility and hole mobility of the LTPS die were set to 300 cm⁻¹. 2 / Vs and 30cm 2 / Vs, the thickness of the LTPS is set to 50 nm. Additionally, the electron mobility and hole mobility at the grain boundaries of the LTPS are set to 30 cm⁻¹, respectively. 2 / Vs and 3cm 2 / Vs, the thickness of the LTPS is set to 50 nm, and the grain boundary width of the LTPS is set to 100 nm. Additionally, the doping concentration of the S / D region is set to 5 × 10⁻⁶. 18 cm -3 The doping concentration in the channel region is set to 1×10⁻⁶. 15 cm -3 The dielectric constant of the upper and lower gate insulating films was set to 3.9, and the thickness of the upper and lower gate insulating films was set to 300 nm. Additionally, the work function of the upper and lower gate electrodes was set to 4.1 eV. Furthermore, the voltage applied to the drain electrode (V... d Set to 3V.

[0355] Figure 71A and Figure 71B I is shown in the subthreshold region d -V g Calculation results with non-uniform properties. Figure 71A This is the calculation result for a single-gate structure. Figure 71B This is the calculation result for the S-channel structure. Figure 71A and Figure 71BIn this study, a structure including a LTPS grain boundary in the channel is adopted. As for the location of this grain boundary, nine configurations are assumed within a range from near the source electrode end to near the drain electrode end. Therefore, in Figure 71A and Figure 71B Nine I's are shown in the middle. d -V g characteristic.

[0356] Depend on Figure 71A and Figure 71B It can be seen that by employing an S-channel structure, the threshold voltage (V) can be suppressed. th The negative drift of ) . However, even with the S-channel structure, the property inhomogeneity in the subthreshold region caused by grain boundaries does not change significantly.

[0357] <1-5-4. NBTS durability of S-channel structure>

[0358] Next, the NBTS (Negative Bias Temperature Stress) tolerance of S-channel LTPS-FET and S-channel OS-FET is calculated.

[0359] Figure 72A and Figure 72B The structure used for the calculation is shown. Figure 72A The structure for calculations using LTPS-FET is shown. Figure 72B The structure for calculations using OS-FET is shown.

[0360] exist Figure 72A In this design, the thickness of the Poly-Si is set to 50 nm, the thickness of the bottom gate electrode (located on the lower side of the Poly-Si) is set to 100 nm, and the thickness of the top gate electrode (located on the upper side of the Poly-Si) is set to 100 nm. Additionally, an insulating film with a thickness of 300 nm is included between the bottom gate electrode and the Poly-Si.

[0361] exist Figure 72BIn this design, the thickness of the operating system (OS) is set to 50 nm, the thickness of the bottom gate electrode (Bottom Gate) is set to 100 nm, and the thickness of the top gate electrode (Top Gate) is set to 100 nm. Additionally, an insulating film with a thickness of 300 nm is included between the bottom gate electrode and the OS.

[0362] As a calculation condition, it is assumed that -10V NBTS is applied to the top gate and the bottom gate.

[0363] Figure 73A and Figure 73B The calculated results of the potential distribution in the thickness direction when NBTS is applied are shown. Figure 73A This is the calculation result for LTPS-FET. Figure 73B This is the result of OS-FET calculations.

[0364] Depend on Figure 73A It is known that in an LTPS-FET, the potential between the top gate and the bottom gate changes. That is, an electric field is applied to the Poly-Si, and even when the voltage applied to the top and bottom gates is stopped, the Poly-Si is still subjected to stress caused by the electric field. This can be considered as the generation of minority carriers due to the inversion of the LTPS-FET.

[0365] On the other hand, such as Figure 73B As shown, in an OS-FET, the potential between the top gate and the bottom gate remains unchanged or approximately constant. This can be considered as the top gate and the bottom gate having the same potential, and no electric field is applied to the OS and the insulating film. In other words, by employing an S-channel structure as an OS-FET, the toughness of NBTS can be significantly improved.

[0366] <1-5-5. Channel width in the S-channel structure (length in the W direction)>

[0367] Next, the length of the channel width in the W direction of the S-channel structure will be explained. Here, the manufacturing process... Figures 74A to 74C , Figures 75A to 75CThe transistor shown is subjected to a PBTS (Positive Bias Temperature Stress) test.

[0368] Figure 74A This is a top view of transistor 400. Figure 74B Equivalent to along Figure 74A A cross-sectional view of the dashed-dot line X1-X2. Figure 74C Equivalent to along Figure 74A The cross-sectional view of the dotted line Y1-Y2.

[0369] Figure 75A This is a top view of the transistor 400A. Figure 75B Equivalent to along Figure 75A A cross-sectional view of the dashed-dot line X1-X2. Figure 75C Equivalent to along Figure 75A The cross-sectional view of the dotted line Y1-Y2.

[0370] Transistor 400 and transistor 400A include: a conductive film 404 on a substrate 402; insulating films 406 and 407 on the conductive film 404; an oxide semiconductor film 408 on the insulating film 407; a conductive film 412a electrically connected to the oxide semiconductor film 408; a conductive film 412b electrically connected to the oxide semiconductor film 408; insulating films 414 and 416 on the oxide semiconductor film 408, conductive film 412a, and conductive film 412b; a conductive film 420 on the insulating film 416; and an insulating film 418 on the insulating film 416 and conductive film 420.

[0371] In transistors 400 and 400A, the oxide semiconductor film 408 has a stacked structure of oxide semiconductor film 408a and oxide semiconductor film 408b on oxide semiconductor film 408a. Furthermore, in transistors 400 and 400A, conductive film 404 is used as a first gate electrode, and conductive film 420 is used as a second gate electrode. In transistors 400 and 400A, insulating films 406 and 407 are used as first gate insulating films, and insulating films 414 and 416 are used as second gate insulating films. In transistors 400 and 400A, conductive film 412a is used as a source electrode, and conductive film 412b is used as a drain electrode.

[0372] Notice, Figures 74A to 74C The transistor 400 shown is Figures 75A to 75C The difference between the transistors 400A shown is the length of the conductive film 420 in the channel width W direction. The transistors 400 and 400A have the same structure except for the conductive film 420.

[0373] Specifically, in Figures 74A to 74CIn the transistor 400 shown, the conductive film 420, which serves as the second gate electrode, is shorter than the oxide semiconductor film 408 in the channel width W direction. On the other hand, in Figures 75A to 75C In the transistor 400A shown, the conductive film 420, which serves as the second gate electrode, is longer than the oxide semiconductor film 408 in the channel width W direction. In other words, the transistor 400A has a structure in which the conductive film 420, which serves as the second gate electrode, covers the side of the oxide semiconductor film 408 in the channel width W direction, i.e., an S-channel structure.

[0374] The structures of the conductive film, insulating film, and oxide semiconductor film included in transistors 400 and 400A are as follows.

[0375] As conductive film 404, a tungsten film with a thickness of 200 nm is used; as conductive film 420, an ITSO film with a thickness of 100 nm is used. Conductive films 412a and 412b both employ a stacked structure of a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 200 nm. As oxide semiconductor film 408a, an IGZO film with a thickness of 35 nm (In:Ga:Zn = 3:1:2 [atomic ratio]) is used; as oxide semiconductor film 408b, an IGZO film with a thickness of 15 nm (In:Ga:Zn = 1:3:2 [atomic ratio]) is used. As insulating film 406, a silicon nitride film with a thickness of 400 nm is used; as insulating film 407, a silicon oxynitride film with a thickness of 50 nm is used. As insulating film 414, a silicon oxynitride film with a thickness of 50 nm is used; as insulating film 416, a silicon oxynitride film with a thickness of 400 nm is used. As the insulating film, 418 uses a silicon nitride film with a thickness of 100 nm.

[0376] Figure 76A Showing equivalent to Figures 74A to 74C The I of transistor 400 before and after PBTS test. d -V g characteristic, Figure 76B Showing equivalent to Figures 75A to 75C The I400A transistor before and after PBTS test is shown. d -V g characteristic.

[0377] exist Figure 76A and Figure 76B In the diagram, the first vertical axis represents I. d The second vertical axis represents μFE, and the horizontal axis represents V. g .exist Figure 76A and Figure 76B In the diagram, solid lines represent the results before stress testing, and dashed lines represent the results after stress testing.

[0378] like Figure 76A As shown, in a structure where the conductive film 420, used as the second gate electrode, does not cover the sides of the oxide semiconductor film 408, after PBTS testing, I d -V g Characteristic degradation. On the other hand, such as Figure 76B As shown, in the structure where the conductive film 420, used as the second gate electrode, covers the side of the oxide semiconductor film 408, i.e., the S-channel structure, after PBTS testing, I d -V g The change in characteristics was not observed or I d -V g The characteristics change very little.

[0379] It can be considered Figure 76A and Figure 76B The I shown d -V g The degradation of characteristics occurs due to the formation of parasitic channels in the transistor 400 caused by the n-type transformation of the side ends of the island oxide semiconductor film 408.

[0380] <1-5-6.I d -V g V in the characteristics d Dependency >

[0381] Next, manufacturing is equivalent to Figures 75A to 75C The transistor 400A shown is an S-channel structure transistor, and the transistor without the conductive film 420 used as the second gate electrode included in transistor 400A is a single-gate structure transistor. The I of this transistor... d -V g V in the characteristics d Dependency is evaluated.

[0382] Note that the structures of the insulating film, conductive film, and oxide semiconductor film in the transistor manufactured here are the same as those described in <1-5-5. Length in the direction of the channel width W in the S-channel structure>. In the transistor described above, the channel length L is 2 μm and the channel width W is 50 μm.

[0383] I of the transistors manufactured above d -V g The characteristics are evaluated. In I d -V g In the measurement of characteristics, V is used. d =0.1V and V d Two conditions for =10V.

[0384] Figure 77A and Figure 77B The transistor's I is shownd -V g The measurement results of the characteristics. Figure 77A The measurement results for a single-gate transistor are shown. Figure 77B The measurement results of the S-channel structure transistor are shown.

[0385] like Figure 77A As shown, in a single-gate structure, at different V... d The rise characteristics of the threshold voltage differ under varying voltage conditions. Specifically, in a single-gate structure, the threshold voltage exhibits a negative drift. This is particularly evident when a high drain voltage (V0) is applied. d When the threshold voltage is 10V, the negative drift of the threshold voltage is very obvious.

[0386] The above phenomenon is believed to be caused by the DIBL (Drain-Induced Barrier Lowering) effect. The DIBL effect refers to the phenomenon of the potential barrier between the source and the channel being lowered due to the drain electric field.

[0387] On the other hand, such as Figure 77B As shown, in the S-channel structure, even if V d The rise characteristics of the threshold voltage are roughly the same regardless of the voltage. This is believed to be because the drain electric field is shielded by the gate electrodes above and below it.

[0388] Next, regarding the I of LTPS-FET d -V g V in the characteristics d Dependency was evaluated. As LTPS-FETs, n-ch transistors with L / W = 6 / 50 μm and p-ch transistors with L / W = 6 / 50 μm were fabricated. The aforementioned single-gate structure and S-channel structure were used as the transistor structures.

[0389] Figure 78A and Figure 78B , Figure 79A and Figure 79B Showing the I of LTPS-FET d -V g Characteristic measurement results. Figure 78A This illustrates the I of a single-gate n-ch transistor. d -V g Characteristic measurement results. Figure 78B This illustrates the I of an S-channel n-ch transistor. d -V g Characteristic measurement results. Figure 79A This illustrates the I of a single-gate p-ch transistor. d -V g Characteristic measurement results. Figure 79B This illustrates the I-channel structure of a p-ch transistor. d -V g Characteristic measurement results.

[0390] like Figure 78A and Figure 78B , Figure 79A and Figure 79B As shown, similar to OS-FET, LTPS-FET uses an S-channel structure instead of a single-gate structure, thereby suppressing the influence of V. d The uneven rise characteristics of the threshold voltage occur due to different characteristics. That is, by using an S-channel structure as an LTPS-FET, the DIBL effect can be suppressed.

[0391] like Figure 78A and Figure 78B , Figure 79A and Figure 79B As shown, similar to OS-FET, LTPS-FETs employ an S-channel structure instead of a single-gate structure, resulting in improved field-effect mobility. The field-effect mobility of the S-channel structure LTPS-FET is approximately 1.6 times that of the single-gate structure LTPS-FET.

[0392] <1-5-7.I d -V d Saturation characteristics in the properties>

[0393] Next, the I-channel structure of single-gate transistors and S-channel structure transistors are analyzed. d -V d The saturation characteristic is explained.

[0394] Manufacturing is equivalent to Figures 75A to 75C The transistor 400A shown is an S-channel structure transistor, and the transistor without the conductive film 420 used as the second gate electrode included in transistor 400A is a single-gate structure transistor. The I of this transistor... d -V d The saturation characteristic is evaluated.

[0395] Note that the structures of the insulating film, conductive film, and oxide semiconductor film in the transistor manufactured here are the same as those described in <1-5-5. Length in the direction of the channel width W in the S-channel structure>. In the transistor described above, the channel length L is 3 μm and the channel width W is 50 μm.

[0396] Figure 80A and Figure 80B The I-channel structure of a single-gate transistor and an S-channel structure transistor are shown.d -V d The measurement results of the characteristics. Figure 80A I is shown in the diagram of a single-gate transistor. d -V d The measurement results of the characteristics. Figure 80B The I-channel structure transistor is shown. d -V d The measurement results of the characteristics.

[0397] like Figure 80A and Figure 80B As shown, by adopting the S-channel structure, I d -V d The saturation characteristics of the device are improved. This is believed to be due to the suppression of the aforementioned DIBL effect. In a single-gate OS-FET, due to the DIBL effect, at higher drain voltages, the saturation characteristics of the device are improved. d -V d Leakage current (I) in the saturation region of the characteristic d )Increase.

[0398] For example, the above-mentioned FET in I d -V d When the saturation characteristics are improved, it can be applied to FETs used in driving display devices, including organic EL elements.

[0399] Next, use Figures 81A to 81C , Figures 82A to 82C Explain the I of LTPS-FET d -V d The saturation characteristic of the property.

[0400] Figures 81A to 81C , Figures 82A to 82C Showing the I of LTPS-FET d -V d characteristic. Figure 81A This shows the I of a single-gate transistor with L / W = 6 / 3 μm. d -V d The measurement results of the characteristics. Figure 81B This shows the I of a single-gate transistor with L / W = 10 / 3 μm. d -V d The measurement results of the characteristics. Figure 81C This shows the I of a single-gate transistor with L / W = 50 / 3μm. d -V d The measurement results of the characteristics. Figure 82A This illustrates the I of an S-channel transistor with L / W = 6 / 3 μm. d -V d The measurement results of the characteristics. Figure 82BThis shows the I of an S-channel transistor with L / W = 10 / 3 μm. d -V d The measurement results of the characteristics. Figure 82C This illustrates the I of an S-channel transistor with L / W = 50 / 3μm. d -V d The measurement results of the characteristics.

[0401] like Figures 81A to 81C , Figures 82A to 82C As shown, by employing an S-channel structure as an LTPS-FET, the DIBL effect can be suppressed, while I d -V d The saturation characteristics of the device are improved. However, unlike the OS-FET described above, an increase in leakage voltage (V0) is observed. d The phenomenon that leakage current increases again as the absolute value of the leakage current increases is observed. In particular, this phenomenon of increased leakage current is clearly confirmed in transistors with shorter channel lengths L.

[0402] The above phenomenon can be attributed to the generation of hot carriers (holes) due to the increase in the drain electric field, which causes avalanche breakdown (impact ionization) at the drain end. This can be attributed to the following reason: the band gap of silicon used in LTPS is smaller than that of oxide semiconductor films, so the effect of impact ionization is greater for silicon than for oxide semiconductor films.

[0403] <1-5-8. S value>

[0404] Next, the S-values ​​of single-gate and S-channel transistors are calculated. The "S-value" refers to the gate voltage required to increase the current (subthreshold current) between the source and drain electrodes by an order of magnitude. The smaller the S-value, the greater the slope of the subthreshold current relative to the gate voltage, and the better the switching characteristics.

[0405] Figure 83 The Ig of a single-gate transistor and an S-channel transistor are shown. d -V g The results of the characteristic calculation. In Figure 83 In the diagram, the dashed line represents the Ig of a single-gate transistor. d -V g The calculated characteristics are shown in the solid line, which represents the It of the S-channel transistor. d -V g The results of the characteristic calculation.

[0406] In the calculation of the S value, it is assumed that the OS-FET has an L / W ratio of 2 / 50μm.

[0407] like Figure 83As shown, by adopting an S-channel structure, the S-value decreases. This can be attributed to the following reason: in an S-channel structure, channel controllability is improved due to the upper and lower gate electric fields.

[0408] Table 1 summarizes the effects obtained when using the S-channel structure as both OS-FET and LTPS-FET.

[0409] [Table 1]

[0410]

[0411] Notice: *1) - means "no decision has been made".

[0412] As shown in Table 1, although several effects can be expected with the S-channel structure LTPS-FET, the S-channel structure OS-FET can achieve more effects.

[0413] <1-6. Example 3 of the structure of a semiconductor device>

[0414] Next, use Figures 3A to 3C Explanation and Figures 1A to 1C Examples of different structures of transistor 100 are shown.

[0415] Figure 3A This is a top view of a transistor 160 of a semiconductor device as an embodiment of the present invention. Figure 3B Equivalent to along Figure 3A The cross-sectional view shown is the dotted-dash line X1-X2. Figure 3C Equivalent to along Figure 3A The cross-sectional view of the dotted line Y1-Y2 is shown.

[0416] The transistor 160 differs from the transistor 100 in the structure of the oxide semiconductor film 120a used as the pixel electrode and the structure of the oxide semiconductor film 120b used as the second gate electrode. The other structures of the transistor 160 are the same as those of the transistor 100 and perform the same function. The following describes the structures that differ from those of the transistor 100.

[0417] The oxide semiconductor film 120a included in the transistor 160, which is used as a pixel electrode, has a stacked structure of oxide semiconductor film 120a_1 and oxide semiconductor film 120a_2. The oxide semiconductor film 120b included in the transistor 160, which is used as a second gate electrode, has a stacked structure of oxide semiconductor film 120b_1 and oxide semiconductor film 120b_2.

[0418] When both oxide semiconductor films 120a and 120b have a stacked structure, oxygen can be effectively introduced into the insulating film 116. Alternatively, when both oxide semiconductor films 120a and 120b have a stacked structure, hydrogen contained in the insulating film 118 can be suppressed from entering the insulating film 116.

[0419] The atomic ratio of the metal elements in the sputtering target used to form the oxide semiconductor film 120a_1 and the oxide semiconductor film 120b_1 preferably satisfies In ≤ M. Examples of such atomic ratios for the metal elements in the sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, and In:M:Zn = 1:3:6.

[0420] The atomic ratio of the metal elements in the sputtering target used to form the oxide semiconductor film 120a_2 and the oxide semiconductor film 120b_2 preferably satisfies In≥M. Examples of such atomic ratios for the metal elements in the sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, and In:M:Zn = 4:2:4.1.

[0421] When both oxide semiconductor films 120a and 120b have a two-layer stacked structure, it is preferable that the flow rate of oxygen gas during the formation of the lower oxide semiconductor film is greater than the flow rate of oxygen gas during the formation of the upper oxide semiconductor film. By increasing the flow rate of oxygen gas during the formation of the lower oxide semiconductor film, oxygen can be appropriately added to the insulating film 116. Furthermore, by decreasing the flow rate of oxygen gas during the formation of the upper oxide semiconductor film, the resistance of the oxide semiconductor film can be reduced.

[0422] By employing the above structure as oxide semiconductor film 120a and oxide semiconductor film 120b, a highly reliable semiconductor device can be provided.

[0423] <1-7. Example 4 of the structure of a semiconductor device>

[0424] Next, use Figures 4A to 4C Explanation and Figures 2A to 2C Examples of different structures of transistor 150 are shown.

[0425] Figure 4A This is a top view of a transistor 170 of a semiconductor device as an embodiment of the present invention. Figure 4B Equivalent to along Figure 4A The cross-sectional view shown is the dotted-dash line X1-X2. Figure 4C Equivalent to along Figure 4A The cross-sectional view of the dotted line Y1-Y2 is shown.

[0426] The transistor 170 differs from the transistor 150 in the structure of the oxide semiconductor film 120a used as the pixel electrode and the structure of the oxide semiconductor film 120b used as the second gate electrode. The other structures of the transistor 170 are the same as those of the transistor 150, and they perform the same function. The structures of the oxide semiconductor films 120a and 120b can also be the same as those of the transistor 160 described above.

[0427] <1-8. Example 5 of the structure of a semiconductor device>

[0428] Next, refer to Figures 5A to 5D , Figure 6A and Figure 6B and Figures 7A to 7D illustrate Figures 2A to 2C The modified example of transistor 150 shown Figures 4A to 4C The transistor 170 shown is a modified example.

[0429] Figure 5A and Figure 5B yes Figure 2B and Figure 2C A cross-sectional view of a modified example of transistor 150 shown. Figure 5C and Figure 5D yes Figure 4B and Figure 4C A cross-sectional view of a modified example of transistor 170 shown.

[0430] Figure 5A and Figure 5B The transistor 150A shown has a three-layer structure in addition to the oxide semiconductor film 108, and also has the characteristics of... Figure 2B and Figure 2C The transistor 150 shown has the same structure. Specifically, the oxide semiconductor film 108 of transistor 150A includes oxide semiconductor film 108a, oxide semiconductor film 108b, and oxide semiconductor film 108c.

[0431] Figure 5C and Figure 5D The transistor 170A shown has a three-layer structure in addition to the oxide semiconductor film 108, and also has the characteristics of... Figure 4B and Figure 4C The transistor 170 shown has the same structure. Specifically, the oxide semiconductor film 108 of transistor 170A includes oxide semiconductor film 108a, oxide semiconductor film 108b and oxide semiconductor film 108c.

[0432] Here, refer to Figure 6A and Figure 6BThe band structure of the insulating film in contact with oxide semiconductor films 108a, 108b, and 108c, and the insulating film in contact with oxide semiconductor films 108b and 108c are described.

[0433] Figure 6A An example of a band structure in the thickness direction of a stack is shown, the stack including an insulating film 107, oxide semiconductor films 108a, 108b, 108c and an insulating film 114. Figure 6B An example of a band structure in the thickness direction of a stack is shown, the stack including an insulating film 107, oxide semiconductor films 108b, 108c, and an insulating film 114. For ease of understanding, the energy levels (Ec) at the conduction band bottoms of the insulating films 107, 108b, 108c, and 114 are shown in the band structure.

[0434] exist Figure 6A In the energy band diagram, silicon oxide films are used as insulating films 107 and 114, oxide semiconductor films 108a are formed by using metal oxide targets with an atomic ratio of In:Ga:Zn = 1:1:1.2, oxide semiconductor films 108b and 108c are formed by using metal oxide targets with an atomic ratio of In:Ga:Zn = 4:2:4.1, and oxide semiconductor films 108c are formed by using metal oxide targets with an atomic ratio of In:Ga:Zn = 1:1:1.2.

[0435] exist Figure 6B In the band structure diagram, silicon oxide films are used as insulating films 107 and 114, oxide semiconductor films 108b are formed using metal oxide targets with an atomic ratio of In:Ga:Zn = 4:2:4.1, and oxide semiconductor films 108c are formed using metal oxide targets with an atomic ratio of In:Ga:Zn = 1:1:1.2.

[0436] like Figure 6A and Figure 6B As shown, the energy levels at the bottom of the conduction band change smoothly between oxide semiconductor films 108a and 108b, and between oxide semiconductor films 108b and 108c. It can be said that the energy levels at the bottom of the conduction band change continuously or are continuously coupled. To achieve this band structure, impurities that would cause defect levels such as trap centers or recombination centers are absent at the interfaces between oxide semiconductor films 108a and 108b, or between oxide semiconductor films 108b and 108c.

[0437] In order to form a continuous bond between oxide semiconductor films 108a and 108b and between oxide semiconductor films 108b and 108c, a multi-chamber deposition apparatus (sputtering apparatus) equipped with a lock-in chamber is required to continuously stack the films in a manner that prevents each film from being exposed to the atmosphere.

[0438] By adopting Figure 6A and Figure 6B In the structure shown, the oxide semiconductor film 108b becomes a well, and in the transistor using the above-described stacked structure, the channel region is formed in the oxide semiconductor film 108b.

[0439] By setting oxide semiconductor films 108a and 108c, trap energy levels that could potentially form near the interface between oxide semiconductor film 108b and insulating film (insulating film 107 or insulating film 114) are moved away from oxide semiconductor film 108b.

[0440] Sometimes, the trap level is farther from the vacuum level than the conduction band bottom level (Ec) of the oxide semiconductor film 108b used as the channel region, and electrons tend to accumulate in the trap level. When electrons accumulate in the trap level, they become negative fixed charges, causing the threshold voltage of the transistor to drift in the positive direction. Therefore, it is preferable to use a structure in which the trap level is closer to the vacuum level than the conduction band bottom level (Ec) of the oxide semiconductor film 108b. By using the above structure, electrons are less likely to accumulate in the trap level. As a result, the on-state current of the transistor can be increased, and the field-effect mobility can also be improved.

[0441] Compared to oxide semiconductor film 108b, the conduction band bottom energy levels of oxide semiconductor films 108a and 108c are closer to the vacuum level. Typically, the difference between the conduction band bottom energy level of oxide semiconductor film 108b and that of oxide semiconductor films 108a and 108c is greater than or equal to 0.15 eV or 0.5 eV, and less than or equal to 2 eV or 1 eV. In other words, the difference between the electron affinity of oxide semiconductor films 108a and 108c and that of oxide semiconductor film 108b is greater than or equal to 0.15 eV or 0.5 eV, and less than or equal to 2 eV or 1 eV.

[0442] By employing the above structure, the oxide semiconductor film 108b becomes the main current path. That is, the oxide semiconductor film 108b is used as the channel region, and the oxide semiconductor films 108a and 108c are used as oxide insulating films. Furthermore, since the oxide semiconductor films 108a and 108c include one or more of the metal elements contained in the oxide semiconductor film 108b in which the channel region is formed, interface scattering is less likely to occur at the interface between oxide semiconductor films 108a and 108b, or at the interface between oxide semiconductor films 108b and 108c. Therefore, carrier movement is not hindered at these interfaces, thus improving the field-effect mobility of the transistor.

[0443] Note that, to prevent oxide semiconductor films 108a and 108c from being used as part of the channel region, oxide semiconductor films 108a and 108c are made of materials with sufficiently low conductivity. Therefore, oxide semiconductor films 108a and 108c can be referred to as "oxide insulating films" based on their physical properties and / or functions. Alternatively, oxide semiconductor films 108a and 108c are made of materials whose electron affinity (the difference between the vacuum level and the conduction band bottom level) is lower than that of oxide semiconductor film 108b and whose conduction band bottom level differs from that of oxide semiconductor film 108b (band shift). Furthermore, to suppress the difference between threshold voltages that result from leakage voltage values, oxide semiconductor films 108a and 108c preferably use materials whose conduction band bottom level is closer to the vacuum level than that of oxide semiconductor film 108b. For example, the difference between the conduction band bottom energy level of oxide semiconductor film 108b and the conduction band bottom energy level of oxide semiconductor films 108a and 108c is preferably 0.2 eV or more, and more preferably 0.5 eV or more.

[0444] The oxide semiconductor films 108a and 108c preferably do not have a spinel-type crystalline structure. When the oxide semiconductor films 108a and 108c have a spinel-type crystalline structure, the constituent elements of the conductive films 112a and 112b may sometimes diffuse to the oxide semiconductor film 108b at the interface between the spinel-type crystalline structure and other regions. Note that when the oxide semiconductor films 108a and 108c are CAAC-OS, the performance of blocking constituent elements such as copper in the conductive films 112a and 112b is improved, and therefore this is preferred.

[0445] The thicknesses of the oxide semiconductor films 108a and 108c are greater than or equal to the thickness sufficient to suppress the diffusion of constituent elements of the conductive films 112a and 112b into the oxide semiconductor film 108b, and less than the thickness at which the supply of oxygen from the insulating film 114 to the oxide semiconductor film 108b is suppressed. For example, when the thicknesses of the oxide semiconductor films 108a and 108c are 10 nm or more, the diffusion of constituent elements of the conductive films 112a and 112b into the oxide semiconductor film 108b can be suppressed. Furthermore, when the thicknesses of the oxide semiconductor films 108a and 108c are 100 nm or less, oxygen can be effectively supplied from the insulating film 114 to the oxide semiconductor film 108b.

[0446] In this embodiment, although the oxide semiconductor films 108a and 108c are formed using metal oxide targets with an atomic ratio of In:Ga:Zn of 1:1:1.2, one aspect of the invention is not limited to this. For example, the oxide semiconductor films 108a and 108c can be formed using metal oxide targets with an atomic ratio of In:Ga:Zn of 1:1:1, 1:3:2, 1:3:4, or 1:3:6.

[0447] When oxide semiconductor films 108a and 108c are formed using a metal oxide target with an In:Ga:Zn ratio of 1:1:1 (atomic ratio), the oxide semiconductor films 108a and 108c may have an In:Ga:Zn ratio of 1:β1 (0 < β1 ≤ 2):β2 (0 < β2 ≤ 2). Alternatively, when oxide semiconductor films 108a and 108c are formed using a metal oxide target with an In:Ga:Zn ratio of 1:3:4 (atomic ratio), the oxide semiconductor films 108a and 108c may have an In:Ga:Zn ratio of 1:β3 (1 ≤ β3 ≤ 5):β4 (2 ≤ β4 ≤ 6). In addition, when oxide semiconductor films 108a and 108c are formed using metal oxide targets with an In:Ga:Zn ratio of 1:3:6 [atomic number ratio], oxide semiconductor films 108a and 108c may have an In:Ga:Zn ratio of 1:β5 (1≤β5≤5):β6 (4≤β6≤8).

[0448] Additionally, in the accompanying drawings, the areas of the oxide semiconductor film 108c included in transistor 150 and the oxide semiconductor film 108c included in transistor 150A that are not covered by conductive films 112a and 112b are thin, meaning that a portion of the oxide semiconductor film has a recess. However, one aspect of the invention is not limited to this, and the areas of the oxide semiconductor film not covered by conductive films 112a and 112b may also not have a recess. Figures 7A to 7DAn example of this situation is shown. Figures 7A to 7D This is a cross-sectional view of an example of a semiconductor device. Figure 7A and Figure 7B This diagram shows the structure of the oxide semiconductor film 108c of the transistor 150 when it does not have a recess. Figure 7C and Figure 7D The structure of the oxide semiconductor film 108c of the transistor 150A described above is shown when it does not have a recess.

[0449] The transistors in this embodiment can be freely combined with each other.

[0450] <1-9. Methods for Manufacturing Semiconductor Devices>

[0451] Below, refer to Figures 8A to 8F , Figures 9A to 9F , Figures 10A to 10F and Figures 11A to 11F A method for manufacturing a transistor 100, which is one aspect of the semiconductor device of the present invention, is described.

[0452] Figures 8A to 8F , Figures 9A to 9F , Figures 10A to 10F and Figures 11A to 11F This is a cross-sectional view illustrating the manufacturing method of a semiconductor device. Additionally, Figure 8A , Figure 8C , Figure 8E , Figure 9A , Figure 9C , Figure 9E , Figure 10A , Figure 10C , Figure 10E , Figure 11A , Figure 11C and Figure 11E It is a cross-sectional view along the length of the channel. Figure 8B , Figure 8D , Figure 8F , Figure 9B , Figure 9D , Figure 9F , Figure 10B , Figure 10D , Figure 10F , Figure 11B , Figure 11D and Figure 11F It is a cross-sectional view along the width of the channel.

[0453] First, a conductive film is formed on the substrate 102. This conductive film is then processed through photolithography and etching processes to form a conductive film 104, which serves as the first gate electrode. Next, insulating films 106 and 107 (see reference 104) are formed on the conductive film 104 to serve as the first gate insulating film. Figure 8A and Figure 8B ).

[0454] In this embodiment, a glass substrate is used as substrate 102. A tungsten film with a thickness of 100 nm is formed by sputtering as the conductive film 104, which serves as the first gate electrode. A silicon nitride film with a thickness of 400 nm is formed as the insulating film 106 by PECVD, and a silicon oxynitride film with a thickness of 50 nm is formed as the insulating film 107 by PECVD.

[0455] As the insulating film 106, a stacked structure of silicon nitride films can be adopted. Specifically, as the insulating film 106, a three-layer structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film can be adopted. This three-layer structure can be formed, for example, as shown below.

[0456] For example, a first silicon nitride film can be formed under the following conditions: a thickness of 50 nm, using silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and ammonia at a flow rate of 100 sccm as source gases, supplying the source gases to the reaction chamber of the PECVD apparatus, controlling the pressure in the reaction chamber to 100 Pa, and using a 27.12 MHz high-frequency power supply to provide 2000 W of power.

[0457] The second silicon nitride film can be formed under the following conditions: a thickness of 300 nm, using silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and ammonia at a flow rate of 2000 sccm as source gases, supplying the source gases to the reaction chamber of the PECVD device, controlling the pressure in the reaction chamber to 100 Pa, and using a 27.12 MHz high-frequency power supply to provide 2000 W of power.

[0458] The third silicon nitride film can be formed under the following conditions: a thickness of 50 nm, silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm as the source gas, the source gas is supplied to the reaction chamber of the PECVD device, the pressure in the reaction chamber is controlled at 100 Pa, and 2000 W of power is supplied using a 27.12 MHz high-frequency power supply.

[0459] Alternatively, the substrate temperature during the formation of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be set to 350°C or below.

[0460] By employing a three-layer structure of silicon nitride film as insulating film 106, and for example, using a conductive film containing copper (Cu) as conductive film 104, the following effects can be achieved.

[0461] The first silicon nitride film can suppress the diffusion of copper (Cu) from the conductive film 104. The second silicon nitride film has the function of releasing hydrogen, which can improve the withstand voltage of the insulating film used as the gate insulating film. The third silicon nitride film is a film with low hydrogen release and can suppress the diffusion of hydrogen released from the second silicon nitride film.

[0462] In order to improve the interface characteristics between the insulating film 107 and the oxide semiconductor film 108 (more specifically, oxide semiconductor film 108b) formed subsequently, it is preferable to use an insulating film containing oxygen.

[0463] Next, oxide semiconductor films 108b_0 and 108c_0 are formed on the insulating film 107 (see reference). Figure 8C , Figure 8D , Figure 8E and Figure 8F ).

[0464] Figure 8C and Figure 8D This is a cross-sectional schematic diagram of the deposition apparatus during the formation of an oxide semiconductor film 108b_0 on the insulating film 107. Figure 8C and Figure 8D In the figure, a sputtering apparatus is used as a deposition apparatus, and a target 191 disposed in the sputtering apparatus and a plasma 192 formed below the target 191 are schematically shown.

[0465] First, during the formation of the oxide semiconductor film 108b_0, plasma discharge is performed in an atmosphere containing a first oxygen gas. At this time, oxygen is added to the insulating film 107 on which the oxide semiconductor film 108b_0 is formed. During the formation of the oxide semiconductor film 108b_0, the atmosphere may also contain an inert gas (e.g., helium, argon, xenon, etc.) and the first oxygen gas.

[0466] The first oxygen gas needs to be mixed at least during the formation of the oxide semiconductor film 108b_0. In the overall deposition gas during the formation of the oxide semiconductor film 108b_0, the proportion of the first oxygen gas is greater than 0% and less than 100%, preferably more than 10% and less than 100%, and more preferably more than 30% and less than 100%.

[0467] exist Figure 8C and Figure 8D In the diagram, the oxygen or excess oxygen added to the insulating film 107 is schematically shown by a dashed arrow.

[0468] The substrate temperature for forming the oxide semiconductor film 108b_0 can be the same as or different from the substrate temperature for forming the oxide semiconductor film 108c_0. However, it is preferred to make the substrate temperature for forming the oxide semiconductor film 108b_0 the same as the substrate temperature for forming the oxide semiconductor film 108c_0 to reduce manufacturing costs.

[0469] For example, the substrate temperature for forming the oxide semiconductor film 108 is above room temperature and below 340°C, preferably above room temperature and below 300°C, more preferably above 100°C and below 250°C, and even more preferably above 100°C and below 200°C. By forming the oxide semiconductor film 108 while heating, the crystallinity of the oxide semiconductor film 108 can be improved. On the other hand, when a large glass substrate (e.g., sixth to tenth generation) is used as the substrate 102, the substrate 102 may deform (strain or warp) if the substrate temperature for forming the oxide semiconductor film 108 is above 150°C and below 340°C. Therefore, when using a large glass substrate, by setting the substrate temperature for forming the oxide semiconductor film 108 to above 100°C and below 150°C, deformation of the glass substrate can be suppressed.

[0470] In addition, it is necessary to ensure the high purity of the sputtering gas. For example, the oxygen or argon gas used as the sputtering gas should be a high-purity gas with a dew point of -40°C or below, preferably -80°C or below, more preferably -100°C or below, and even more preferably -120°C or below, so as to prevent moisture and other substances from mixing into the oxide semiconductor film as much as possible.

[0471] Furthermore, when forming oxide semiconductor films by sputtering, it is preferable to use an adsorption-type vacuum pump, such as a cryogenic pump, to perform high-vacuum evacuation (e.g., evacuating to 5 × 10⁻⁶) of the sputtering apparatus chamber. -7 Pa to 1×10 -4 (Approximately Pa) to remove as much water, etc., as impurities to the oxide semiconductor film. Alternatively, a combination of a turbomolecular pump and a cold trap is preferred to prevent backflow of gases, especially gases containing carbon or hydrogen, from the pumping system into the chamber.

[0472] After forming the oxide semiconductor film 108b_0, an oxide semiconductor film 108c_0 is continuously formed on the oxide semiconductor film 108b_0. Note that when forming the oxide semiconductor film 108c_0, plasma discharge can be performed in an atmosphere containing a second oxygen gas.

[0473] The proportion of the first oxygen gas during the formation of the oxide semiconductor film 108b_0 and the proportion of the second oxygen gas during the formation of the oxide semiconductor film 108c_0 can be the same or different. For example, in the total deposition gas during the formation of the oxide semiconductor film 108c_0, the proportion of the second oxygen gas is greater than 0% and less than 100%, preferably more than 10% and less than 100%, and more preferably more than 30% and less than 100%.

[0474] When forming the oxide semiconductor film 108c_0, when using a second oxygen gas and an argon gas, it is preferable to have a higher flow rate of argon gas than the second oxygen gas. By increasing the flow rate of argon gas, a dense oxide semiconductor film 108c_0 can be achieved. Furthermore, to achieve a dense oxide semiconductor film 108c_0, the substrate temperature during formation of the oxide semiconductor film 108c_0 can be increased; typically, it is below 250°C, and preferably above 150°C and below 190°C. With a dense oxide semiconductor film 108c_0, the incorporation of metal elements contained in the conductive films 112a and 112b into the oxide semiconductor film 108b_0 can be suppressed.

[0475] In this embodiment, an oxide semiconductor film 108b_0 is formed by sputtering using an In-Ga-Zn metal oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). Then, in a vacuum, an oxide semiconductor film 108c_0 is continuously formed by sputtering using an In-Ga-Zn metal oxide target (In:Ga:Zn = 1:1:1.2 [atomic ratio]). The substrate temperature for forming the oxide semiconductor film 108b_0 is set to 170°C, and the substrate temperature for forming the oxide semiconductor film 108c_0 is also set to 170°C. As the deposition gases for forming the oxide semiconductor film 108b_0, oxygen gas with a flow rate of 60 sccm and argon gas with a flow rate of 140 sccm are used. As the deposition gases for forming the oxide semiconductor film 108c_0, oxygen gas with a flow rate of 100 sccm and argon gas with a flow rate of 100 sccm are used.

[0476] Next, the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_0 are processed into the desired shape, thereby forming island-shaped oxide semiconductor film 108b and island-shaped oxide semiconductor film 108c (see reference). Figure 9A and Figure 9B ).

[0477] Next, conductive films 112, which will serve as the source and drain electrodes, are formed on the insulating film 107 and the oxide semiconductor film 108 by sputtering (see reference). Figure 9C and Figure 9D ).

[0478] In this embodiment, the conductive film 112 is formed by sputtering an aluminum film with a thickness of 400 nm stacked on a tungsten film with a thickness of 50 nm. Note that in this embodiment, the conductive film 112 adopts a two-layer stacked structure, but the present invention is not limited to this. For example, the conductive film 112 can adopt a three-layer structure in which a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm are stacked sequentially.

[0479] Next, conductive films 112a and 112b, separated from each other, are formed by processing the conductive film 112 into the desired shape (see reference). Figure 9E and Figure 9F ).

[0480] In this embodiment, a dry etching apparatus is used to process the conductive film 112. However, the processing method for the conductive film 112 is not limited to this; for example, a wet etching apparatus can also be used. Compared to a wet etching apparatus, when a dry etching apparatus is used to process the conductive film 112, finer patterns can be formed. On the other hand, compared to a dry etching apparatus, when a wet etching apparatus is used to process the conductive film 112, manufacturing costs can be reduced.

[0481] Furthermore, the surface (back channel side) of the oxide semiconductor film 108 (more specifically, the oxide semiconductor film 108c) can be washed after the conductive films 112a and 112b are formed. Examples of washing methods include washing with a chemical solution such as phosphoric acid. By washing with a chemical solution such as phosphoric acid, impurities (e.g., elements contained in the conductive films 112a and 112b) adhering to the surface of the oxide semiconductor film 108c can be removed. Note that this washing is not always necessary and may be omitted depending on the circumstances.

[0482] In addition, during the formation process of conductive films 112a and 112b and / or the washing process described above, the areas of the oxide semiconductor film 108 not covered by conductive films 112a and 112b may sometimes become thinner.

[0483] Next, insulating films 114 and 116 (see reference) are formed on the oxide semiconductor film 108 and the conductive films 112a and 112b. Figure 10A and Figure 10B ).

[0484] Preferably, after forming the insulating film 114, the insulating film 116 is continuously formed without exposure to the atmosphere. After forming the insulating film 114, the insulating film 116 is continuously formed by adjusting one or more of the source gas flow rate, pressure, high-frequency power, and substrate temperature without exposure to the atmosphere. This reduces the concentration of impurities originating from the atmosphere at the interface between the insulating films 114 and 116, and allows oxygen contained in the insulating films 114 and 116 to move into the oxide semiconductor film 108, thereby reducing the amount of oxygen vacancies in the oxide semiconductor film 108.

[0485] For example, silicon oxynitride film can be formed as insulating film 114 by PECVD. In this case, a silicon-containing deposition gas and an oxidizing gas are preferably used as the source gas. Typical examples of silicon-containing deposition gases are silane, disilane, propane, fluorinated silane, etc. Oxidizing gases include nitrous oxide, nitrogen dioxide, etc. Furthermore, by using PECVD under the following conditions, an insulating film 114 containing nitrogen and with low defect content can be formed: the oxidizing gas flow rate relative to the above-mentioned deposition gas flow rate is greater than 20 times and less than 100 times, preferably more than 40 times and less than 80 times, and the pressure in the processing chamber is less than 100 Pa, preferably less than 50 Pa.

[0486] In this embodiment, as the insulating film 114, a silicon oxynitride film is formed using PECVD under the following conditions: the temperature of the substrate 102 is maintained at 220°C; silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as the source gases; the pressure inside the processing chamber is 20 Pa; and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz and 100 W (power density of 1.6 × 10⁻⁶). -2 W / cm 2 ).

[0487] As the insulating film 116, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the substrate temperature in the processing chamber of the PECVD apparatus, which has been vacuum-evacuated, is maintained at 180°C or higher and 350°C or lower; a source gas is introduced into the processing chamber and the pressure inside the processing chamber is set to 100 Pa or higher and 250 Pa or lower, preferably 100 Pa or higher and 200 Pa or lower; and 0.17 W / cm² is supplied to the electrodes disposed in the processing chamber. 2 Above and 0.5W / cm 2 The preferred value is 0.25 W / cm. 2 Above and 0.35W / cm 2 The following are high-frequency power values.

[0488] In the deposition conditions of the insulating film 116, high-frequency power with the aforementioned power density is supplied to the reaction chamber at the aforementioned pressure. This improves the decomposition efficiency of the source gas in the plasma, increases oxygen free radicals, and promotes the oxidation of the source gas, resulting in an oxygen content in the insulating film 116 exceeding its stoichiometric composition. On the other hand, in the film formed at the substrate temperature within the aforementioned temperature range, since the bonding force between silicon and oxygen is weak, a portion of the oxygen in the film is removed through subsequent heat treatment processes. As a result, an oxide insulating film with an oxygen content exceeding its stoichiometric composition and a portion of the oxygen released through heating can be formed.

[0489] In the process of forming the insulating film 116, the insulating film 114 is used as a protective film for the oxide semiconductor film 108. Therefore, the insulating film 116 can be formed using high-frequency power with high power density while minimizing damage to the oxide semiconductor film 108.

[0490] Furthermore, in the deposition conditions of insulating film 116, by increasing the flow rate of the silicon-containing deposition gas relative to the oxidizing gas, the amount of defects in insulating film 116 can be reduced. Typically, it is possible to form an oxide insulating film with a low amount of defects, wherein the spin density of the signal originating from silicon dangling bonds and appearing at g = 2.001, as measured by ESR, is less than 6 × 10⁻⁶. 17 spins / cm 3 Preferably 3×10 17 spins / cm 3 The following is more preferably 1.5 × 10 17 spins / cm 3 The following results in improved reliability of transistor 100.

[0491] Preferably, the heat treatment (hereinafter referred to as the first heat treatment) is performed after the insulating films 114 and 116 are formed. The first heat treatment can reduce the nitrogen oxides contained in the insulating films 114 and 116. The first heat treatment can also move a portion of the oxygen in the insulating films 114 and 116 into the oxide semiconductor film 108 to reduce the amount of oxygen vacancies in the oxide semiconductor film 108.

[0492] The temperature of the first heat treatment is typically set below 400°C, preferably below 375°C, and more preferably above 150°C and below 350°C. The first heat treatment can be carried out in an atmosphere of nitrogen, oxygen, ultra-dry air (containing less than 20 ppm of water, preferably less than 1 ppm, and more preferably less than 10 ppb of water), or a rare gas (argon, helium, etc.). In this heat treatment, it is preferable that the aforementioned nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc., and the heat treatment can be carried out using an electric furnace, RTA (Rapid Thermal Annealing), or similar equipment.

[0493] Next, a mask is formed on the insulating film 116 using a photolithography process, and an opening 152a is formed in the desired area of ​​the insulating films 114 and 116. The opening 152a is formed in such a way that it reaches the conductive film 112b (see reference). Figure 10C and Figure 10D ).

[0494] Next, an oxide semiconductor film 120 is formed on the insulating film 116 in such a way as to cover the opening 152a (see reference). Figure 10E , Figure 10F , Figure 11A and Figure 11B ).

[0495] Figure 10E and Figure 10F This is a cross-sectional schematic diagram of the deposition apparatus during the formation of an oxide semiconductor film 120 on the insulating film 116. Figure 10E and Figure 10F In the example, a sputtering apparatus is used as a deposition device, and a target 193 disposed in the sputtering apparatus and a plasma 194 formed below the target 193 are schematically shown.

[0496] First, during the formation of the oxide semiconductor film 120, plasma discharge is performed in an atmosphere containing a third oxygen gas. At this time, oxygen is added to the insulating film 116 to which the oxide semiconductor film 120 is formed. The atmosphere during the formation of the oxide semiconductor film 120 may contain an inert gas (e.g., helium, argon, xenon, etc.) in addition to the third oxygen gas. For example, when using argon and the third oxygen gas, it is preferable that the flow rate of the third oxygen gas is greater than that of the argon gas. By increasing the flow rate of the third oxygen gas, oxygen can be effectively added to the insulating film 116. For example, as the formation conditions for the oxide semiconductor film 120, the proportion of the third oxygen gas in the overall deposition gas can be 50% or more and 100% or less, preferably 80% or more and 100% or less.

[0497] exist Figure 10E and Figure 10F In the diagram, the oxygen or excess oxygen added to the insulating film 116 is schematically shown by a dashed arrow.

[0498] For example, the substrate temperature for forming the oxide semiconductor film 120 is above room temperature and below 340°C, preferably above room temperature and below 300°C, more preferably above 100°C and below 250°C, and even more preferably above 100°C and below 200°C. By forming the oxide semiconductor film 120 while heating, the crystallinity of the oxide semiconductor film 120 can be improved. On the other hand, when a large glass substrate (e.g., sixth to tenth generation) is used as the substrate 102, the substrate 102 may deform (strain or warp) if the substrate temperature for forming the oxide semiconductor film 120 is above 150°C and below 340°C. Therefore, when using a large glass substrate, by setting the substrate temperature for forming the oxide semiconductor film 120 to above 100°C and below 150°C, deformation of the glass substrate can be suppressed.

[0499] In this embodiment, an oxide semiconductor film 120 is formed by sputtering using an In-Ga-Zn metal oxide target (In:Ga:Zn = 1:3:6 [atomic ratio]). The substrate temperature for forming the oxide semiconductor film 120 is set to 170°C. An oxygen gas with a flow rate of 100 sccm is used as the deposition gas for forming the oxide semiconductor film 120.

[0500] As the oxide semiconductor film 120, for example, the above-mentioned oxide semiconductor films (e.g., In:Ga:Zn = 1:1:1 [atomic ratio], In:Ga:Zn = 1:3:2 [atomic ratio], In:Ga:Zn = 1:3:4 [atomic ratio], In:Ga:Zn = 1:3:6 [atomic ratio], In:Ga:Zn = 3:1:2 [atomic ratio], In:Ga:Zn = 4:2:3 [atomic ratio], etc.) can be used.

[0501] Next, the oxide semiconductor film 120 is processed into the desired shape, thereby forming island-shaped oxide semiconductor films 120a and 120b (see reference). Figure 11C and Figure 11D ).

[0502] Next, an insulating film 118 is formed on the insulating film 116, the oxide semiconductor film 120a, and the oxide semiconductor film 120b (see reference). Figure 11E and Figure 11F ).

[0503] The insulating film 118 contains one or both of hydrogen and nitrogen. Silicon nitride film is preferably used as the insulating film 118, for example. The insulating film 118 can be formed, for example, by sputtering or PECVD. For example, when forming the insulating film 118 by PECVD, the substrate temperature is kept below 400°C, preferably below 375°C, and more preferably above 180°C and below 350°C. By setting the substrate temperature during the formation of the insulating film 118 to the above range, a dense film can be formed, which is therefore preferred. Furthermore, by setting the substrate temperature during the formation of the insulating film 118 to the above range, oxygen or excess oxygen in the insulating films 114 and 116 can be moved to the oxide semiconductor film 108.

[0504] After the insulating film 118 is formed, a heat treatment equivalent to the first heat treatment described above (hereinafter referred to as the second heat treatment) may be performed. Thus, after oxygen is added to the insulating film 116 when the oxide semiconductor film 120 is formed, a heat treatment is performed at a temperature below 400°C, preferably below 375°C, and more preferably above 180°C and below 350°C. This allows oxygen or excess oxygen in the insulating film 116 to move into the oxide semiconductor film 108 (especially the oxide semiconductor film 108b), thereby filling oxygen vacancies in the oxide semiconductor film 108.

[0505] Here, refer to Figure 12A and Figure 12B The oxygen that moves into the oxide semiconductor film 108 will be explained. Figure 12A and Figure 12B This is a model diagram illustrating oxygen migrating to the oxide semiconductor film 108 due to the substrate temperature during the formation of the insulating film 118 (typically below 375°C) or a second heat treatment after the formation of the insulating film 118 (typically below 375°C). Note that in Figure 12A and Figure 12B In the diagram, the dashed arrows represent oxygen (oxygen radicals, oxygen atoms, or oxygen molecules) that have moved into the oxide semiconductor film 108.

[0506] exist Figure 12A and Figure 12B In the oxide semiconductor film 108 shown, oxygen vacancies are filled by oxygen moving from films (here, insulating films 107 and 114) in contact with the oxide semiconductor film 108. In particular, in a semiconductor device according to one aspect of the invention, when the oxide semiconductor film 108b is formed by sputtering, oxygen is added to the insulating film 107 using an oxygen gas, thus the insulating film 107 contains regions of excess oxygen. Furthermore, when the oxide semiconductor film 120 is formed by sputtering, oxygen is used to add oxygen to the insulating film 116, so the insulating film 116 contains regions of excess oxygen. Thus, oxygen vacancies can be effectively filled in the oxide semiconductor film 108 sandwiched between these insulating films containing regions of excess oxygen.

[0507] Furthermore, an insulating film 106 is disposed below the insulating film 107, and an insulating film 118 is disposed above the insulating films 114 and 116. By using a material with low oxygen permeability, such as silicon nitride, to form the insulating films 106 and 118, the oxygen contained in the insulating films 107, 114, and 116 can be sealed on one side of the oxide semiconductor film 108, so oxygen can be effectively moved to the oxide semiconductor film 108.

[0508] In addition, the insulating film 118 contains one or both of hydrogen and nitrogen. Therefore, when forming the insulating film 118, the oxide semiconductor films 120a and 120b in contact with the insulating film 118 are added with one or both of hydrogen and nitrogen, thereby increasing the carrier density of the oxide semiconductor films 120a and 120b, which can be used as oxide conductive films.

[0509] For example, when forming a silicon nitride film as an insulating film 118 using PECVD, a silicon-containing deposition gas, nitrogen, and ammonia are preferably used as the source gas. By using ammonia in amounts less than nitrogen, active species are generated through ammonia dissociation in the plasma. These active species break the bonds between silicon and hydrogen in the silicon-containing deposition gas and the triple bonds between nitrogen molecules. As a result, silicon-nitrogen bonding is promoted, and a dense silicon nitride film with fewer silicon-hydrogen bonds and fewer defects can be formed. On the other hand, when the amount of ammonia is greater than the amount of nitrogen, the decomposition of the silicon-containing deposition gas and nitrogen does not progress, and silicon-hydrogen bonds remain, resulting in the formation of a silicon nitride film with increased defects and a less dense structure. Therefore, the nitrogen flow rate ratio relative to ammonia in the source gas is set to 5 times or more and 50 times or less, preferably 10 times or more and 50 times or less.

[0510] In this embodiment, as the insulating film 118, a silicon nitride film with a thickness of 50 nm is formed using a PECVD apparatus and silane, nitrogen, and ammonia as source gases. The flow rate of silane is 50 sccm, the flow rate of nitrogen is 5000 sccm, and the flow rate of ammonia is 100 sccm. The pressure of the processing chamber is set to 100 Pa, the substrate temperature is set to 350°C, and a high-frequency power of 1000 W is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power supply. The PECVD apparatus has an electrode area of ​​6000 cm². 2 The parallel plate PECVD device, and the power supplied is converted to power density per unit area as 1.7 × 10⁻⁶. -1 W / cm 2 .

[0511] Note that in this embodiment, a method is shown for increasing the carrier density of oxide semiconductor films 120a and 120b by adding hydrogen or nitrogen from insulating film 118. However, the method for increasing carrier density is not limited to this. For example, the carrier density of oxide semiconductor films 120a and 120b can also be increased by adding impurity elements.

[0512] Typical examples of the aforementioned impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, chlorine, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. When an impurity element is added to an oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film breaks, forming an oxygen vacancy. Alternatively, when an impurity element is added to an oxide semiconductor film, oxygen bonded to a metal element in the oxide semiconductor film bonds to the impurity element, causing the oxygen to detach from the metal element and form an oxygen vacancy. As a result, the carrier density in the oxide semiconductor film increases and the conductivity is improved.

[0513] Through the above steps, it is possible to manufacture Figure 1B and Figure 1C The transistor 100 shown.

[0514] Throughout the manufacturing process of transistor 100, by keeping the substrate temperature below 400°C, preferably below 375°C, and more preferably above 180°C and below 350°C, substrate deformation (strain or warping) can be suppressed even when using a large-area substrate, which is therefore preferred. Typical examples of increasing the substrate temperature in the manufacturing process of transistor 100 include substrate temperatures during the formation of insulating films 106 and 107 (below 400°C, preferably above 250°C and below 350°C), substrate temperatures during the formation of oxide semiconductor film 108 (above room temperature and below 340°C, preferably above 100°C and below 200°C, more preferably above 100°C and below 150°C), substrate temperatures during the formation of insulating films 116 and 118 (below 400°C, preferably below 375°C, more preferably above 180°C and below 350°C), and first or second heat treatments (below 400°C, preferably below 375°C, more preferably above 180°C and below 350°C).

[0515] The structures and methods shown in this embodiment can be implemented by appropriate combination with any structures and methods exemplified in other embodiments.

[0516] Implementation Method 2

[0517] In this embodiment, refer to Figures 17A to 17D , Figures 18A to 18D Figure 19 to Figure 19C , Figure 20A and Figure 20B , Figure 21 , Figure 22 , Figures 23A to 23C , Figures 24A to 24F , Figures 25A to 25G and Figures 26A to 26G The structure of oxide semiconductors is explained.

[0518] <2-1. Structure of Oxide Semiconductors>

[0519] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline Oxide Semiconductor), a-like OS (amorphous like Oxide Semiconductor), and amorphous oxide semiconductors.

[0520] From another perspective, oxide semiconductors are divided into amorphous oxide semiconductors and crystalline oxide semiconductors. Crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS, among others.

[0521] As a definition of amorphous structure, it is generally known that it is in a metastable state and not fixed, and is isotropic without inhomogeneous structure. In other words, the bond angles of amorphous structures are not fixed, and they have short-range order but not long-range order.

[0522] This means that a substantially stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Furthermore, an oxide semiconductor that does not possess isotropy (e.g., has a periodic structure in tiny regions) cannot be called a completely amorphous oxide semiconductor. Note that a-like OS has a periodic structure in tiny regions, but also has voids and an unstable structure. Therefore, a-like OS is physically close to an amorphous oxide semiconductor.

[0523] As an example of the oxide semiconductor film of the present invention, CAAC-OS is particularly preferred among the aforementioned oxide semiconductors. By using CAAC-OS as the oxide semiconductor film, the crystallinity of the oxide semiconductor film can be improved, and the density of impurities, oxygen vacancies, or defect states in the oxide semiconductor film can be reduced.

[0524] <2-2.CAAC-OS>

[0525] First, let's explain CAAC-OS.

[0526] CAAC-OS is one of the oxide semiconductors that contains multiple c-axis oriented crystalline regions (also known as particles).

[0527] In the composite analysis image of the bright-field image and diffraction pattern of CAAC-OS obtained by TEM observation (also known as a high-resolution TEM image), multiple particles were observed. However, in the high-resolution TEM image, no clear boundaries, i.e., grain boundaries, were observed between the particles. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility caused by grain boundaries is not likely to occur.

[0528] The following section describes the CAAC-OS observed using TEM. Figure 17A This shows a high-resolution TEM image of the CAAC-OS cross-section obtained by viewing from a direction approximately parallel to the sample plane. The high-resolution TEM image was obtained using the Spherical Aberration Corrector function. This high-resolution TEM image obtained using the Spherical Aberration Corrector function is specifically referred to as a Cs-corrected high-resolution TEM image. For example, a Cs-corrected high-resolution TEM image can be obtained using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Nippon Electron Ltd.

[0529] Figure 17B Showing will Figure 17A (1) A magnified Cs-corrected high-resolution TEM image of region (1). (By...) Figure 17B It can be confirmed that the metal atoms in the particles are arranged in layers. Each layer of metal atoms has a concave-convex configuration that reflects the surface (also called the forming surface) or the top surface of the CAAC-OS and is arranged in a manner parallel to the forming surface or the top surface of the CAAC-OS.

[0530] like Figure 17B As shown, CAAC-OS has a unique atomic arrangement. Figure 17C It is a diagram that uses auxiliary lines to show the unique atomic arrangement. (From...) Figure 17B and Figure 17C It is known that the size of a single particle is between 1 nm and 3 nm, and the size of the gaps created by the tilt between particles is about 0.8 nm. Therefore, the particles can also be called nanocrystals (nc). In addition, CAAC-OS can be called an oxide semiconductor with CANC (C-Axis Aligned nanocrystals).

[0531] Here, based on Cs-corrected high-resolution TEM images, the configuration of CAAC-OS particles 5100 on substrate 5120 is schematically represented as a structure of stacked bricks or blocks (see reference). Figure 17D ).exist Figure 17CThe portion observed to tilt between particles corresponds to Figure 17D The area shown is 5161.

[0532] Figure 18A This shows a Cs-corrected high-resolution TEM image of the CAAC-OS plane obtained by viewing from a direction approximately perpendicular to the sample surface. Figure 18B , Figure 18C and Figure 18D Show respectively Figure 18A Cs-corrected high-resolution TEM images magnified from regions (1), (2), and (3) in the image. Figure 18B , Figure 18C and Figure 18D It can be seen that the metal atoms in the particles are arranged in triangular, square, or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different particles.

[0533] Next, the analysis of CAAC-OS using an XRD apparatus will be described. For example, when analyzing the structure of CAAC-OS containing InGaZnO4 crystals using the out-of-plane method, such as... Figure 19A As shown, a peak appears around the diffraction angle (2θ) of 31°. Since this peak originates from the (009) plane of the InGaZnO4 crystal, it can be inferred that the crystals in CAAC-OS have a c-axis orientation, and the c-axis is oriented approximately perpendicular to the formation plane or top surface of CAAC-OS.

[0534] Note that when analyzing the structure of CAAC-OS using the out-of-plane method, in addition to the peak near 2θ 31°, a peak sometimes also appears near 2θ 36°. The peak near 2θ 36° indicates that a portion of the CAAC-OS contains crystals without c-axis orientation. Preferably, in the CAAC-OS structure analyzed using the out-of-plane method, a peak appears near 2θ 31° but no peak appears near 2θ 36°.

[0535] On the other hand, in the in-plane method for analyzing the structure of CAAC-OS using X-rays incident on the sample from a direction approximately perpendicular to the c-axis, a peak appears around 2θ = 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. In CAAC-OS, even when 2θ is fixed at around 56° and the sample is rotated about the normal vector of the sample plane (φ-axis) for analysis (φ-scan), the peak is similar to... Figure 19B As shown, no clear peak is observed. In contrast, in single-crystal oxide semiconductors of InGaZnO4, when performing a φ scan with 2θ fixed at around 56°, as shown... Figure 19CAs shown, six peaks originating from the crystal plane equivalent to (110) were observed. Therefore, structural analysis using XRD confirmed that the orientations of the a-axis and b-axis in CAAC-OS are irregular.

[0536] Next, CAAC-OS analysis using electron diffraction will be explained. For example, when an electron beam with a diameter of 300 nm is incident on a CAAC-OS containing InGaZnO4 crystals in a direction parallel to the sample plane, it is possible to obtain... Figure 20A The diffraction pattern shown is also known as a selected area transmission electron diffraction pattern. This diffraction pattern contains spots originating from the (009) plane of InGaZnO4 crystallization. Therefore, electron diffraction also reveals that the particles contained in CAAC-OS have a c-axis orientation, and the c-axis is oriented approximately perpendicular to the formation plane or top surface of CAAC-OS. On the other hand, Figure 20B The diffraction pattern is shown when an electron beam with a diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample plane. Figure 20B A ring-shaped diffraction pattern was observed. Therefore, electron diffraction also indicates that the a-axis and b-axis of the particles contained in CAAC-OS are not oriented. It can be considered that... Figure 20B The first ring in the crystal originates from the (010) and (100) planes of InGaZnO4 crystals. Furthermore, it can be considered that... Figure 20B The second ring in the middle is caused by (110) surface, etc.

[0537] As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors can sometimes decrease due to the introduction of impurities or the formation of defects. It can be said that CAAC-OS is an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

[0538] Furthermore, impurities refer to elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. For example, elements with stronger bonding forces with oxygen than the metal elements constituting the oxide semiconductor (specifically, silicon, etc.) can strip oxygen from the oxide semiconductor, thereby disrupting the atomic arrangement and leading to decreased crystallinity. Additionally, heavy metals such as iron or nickel, argon, carbon dioxide, etc., have large atomic radii (or molecular radii), which can also disrupt the atomic arrangement of oxide semiconductors, resulting in decreased crystallinity.

[0539] When oxide semiconductors contain impurities or defects, their properties can sometimes change due to light or heat. Impurities in oxide semiconductors can sometimes act as carrier traps or carrier sources. In addition, oxygen vacancies in oxide semiconductors can sometimes act as carrier traps or carrier sources by capturing hydrogen.

[0540] CAAC-OS with fewer impurities and oxygen vacancies is an oxide semiconductor with low carrier density (specifically, it can achieve a carrier density of less than 8 × 10⁻⁶). 11 / cm 3 Preferably less than 1×10 11 / cm 3 More preferably less than 1×10 10 / cm 3 And it is 1×10 -9 / cm 3 (Above). Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has low impurity concentration and defect state density. That is, it can be said that CAAC-OS is an oxide semiconductor with stable properties.

[0541] <2-3.nc-OS>

[0542] Next, we will explain nc-OS.

[0543] In high-resolution TEM images of nc-OS, there are regions where crystalline regions are observable and regions where clear crystalline regions are not observed. The crystalline regions in nc-OS are mostly 1 nm or larger than 10 nm and smaller than 3 nm. Note that oxide semiconductors with crystalline regions larger than 10 nm but smaller than 100 nm are sometimes referred to as microcrystalline oxide semiconductors. For example, grain boundaries are sometimes not clearly observable in high-resolution TEM images of nc-OS. Note that the origin of nanocrystals may be the same as that of particles in CAAC-OS. Therefore, the crystalline regions of nc-OS are sometimes referred to as particles below.

[0544] In nc-OS, the atomic arrangement in tiny regions (e.g., regions larger than 1 nm and smaller than 10 nm, particularly regions larger than 1 nm and smaller than 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different particles in nc-OS. Therefore, no orientation is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods. For example, when performing structural analysis of nc-OS using out-of-plane X-rays with a beam diameter larger than the particle size, no peaks representing crystal planes are detected. When electron diffraction is performed on nc-OS using electron beams with a beam diameter larger than the particle size (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when nanobeam electron diffraction is performed on nc-OS using electron beams with a beam diameter close to or smaller than the particle size, spots are observed. Additionally, in the nanobeam electron diffraction pattern of nc-OS, sometimes high-brightness regions resembling circles (rings) are observed. Moreover, in the nanobeam electron diffraction pattern of nc-OS, multiple spots are sometimes observed in the annular region.

[0545] Thus, since there is no regularity in the crystallization orientation between particles (nanocrystals), nc-OS can also be called an oxide semiconductor containing RANC (Random Aligned nanocrystals) or an oxide semiconductor containing NANC (Non-Aligned nanocrystals).

[0546] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore, the defect state density of nc-OS is lower than that of a-like OS or amorphous oxide semiconductors. However, no regularity in crystal orientation is observed between different particles in nc-OS. Therefore, the defect state density of nc-OS is higher than that of CAAC-OS.

[0547] <2-4.a-like OS>

[0548] a-like OS has a structure that falls between nc-OS and amorphous oxide semiconductor.

[0549] Voids are sometimes observed in high-resolution TEM images of a-like OS. Additionally, in high-resolution TEM images, there are areas where crystallization is clearly visible and areas where crystallization is not visible.

[0550] Because a-like OS contains voids, its structure is unstable. To demonstrate that a-like OS has an unstable structure compared to CAAC-OS and nc-OS, the structural changes caused by electron irradiation are shown below.

[0551] As samples for electron irradiation, a-like OS (referred to as sample A), nc-OS (referred to as sample B), and CAAC-OS (referred to as sample C) were prepared. Each sample was an In-Ga-Zn oxide.

[0552] First, high-resolution cross-sectional TEM images of each sample were obtained. The high-resolution cross-sectional TEM images show that each sample has a crystalline structure.

[0553] Note that the determination of which part is considered a crystalline region is as follows. For example, the unit lattice of InGaZnO4 is known to have a structure in which nine layers, comprising three In-O layers and six Ga-Zn-O layers, are stacked in a layered manner along the c-axis. The spacing between these layers that are close to each other is almost equal to the lattice surface spacing (also known as the d-value) of the (009) plane. Its value is determined to be 0.29 nm by crystalline structure analysis. Therefore, the portion with a lattice fringe spacing of 0.28 nm or more and 0.30 nm or less can be considered as an InGaZnO4 crystalline region. Each lattice fringe corresponds to the ab plane of the InGaZnO4 crystal.

[0554] Figure 21 The average size of the crystalline portions (22 to 45 portions) of each sample is shown. Note that the crystalline portion size corresponds to the length of the lattice fringes described above. Figure 21 It can be seen that in a-like OS, the crystal portion gradually increases in size according to the cumulative amount of electron irradiation. Specifically, as... Figure 21 As shown in (1), it can be seen that in the initial observation using TEM, the crystal part with a size of about 1.2 nm (also called the initial crystal nucleus) has a cumulative irradiation dose of 4.2 × 10⁻⁶. 8 e - / nm 2 The growth rate reached approximately 2.6 nm. On the other hand, it was found that the cumulative electron irradiation dose for both nc-OS and CAAC-OS from the start of electron irradiation to the present was 4.2 × 10⁻⁶. 8 e - / nm 2 Within this range, the size of the crystallized portion remained unchanged. Specifically, such as Figure 21 As shown in (2) and (3) in the figure, regardless of the cumulative irradiation of electrons, the average crystal size of nc-OS and CAAC-OS is about 1.4 nm and about 2.1 nm, respectively.

[0555] Thus, electron irradiation can sometimes induce the growth of crystalline regions in a-like OS. On the other hand, it is known that electron irradiation-induced crystalline region growth is almost nonexistent in nc-OS and CAAC-OS. In other words, a-like OS has an unstable structure compared to nc-OS and CAAC-OS.

[0556] Furthermore, because a-like OS contains voids, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is more than 78.6% and less than 92.3% of that of single-crystal oxide semiconductors with the same composition. The densities of nc-OS and CAAC-OS are more than 92.3% and less than 100% of those of single-crystal oxide semiconductors with the same composition. Note that it is difficult to form oxide semiconductors with a density less than 78% of that of single-crystal oxide semiconductors.

[0557] For example, in oxide semiconductors with an atomic ratio of In:Ga:Zn = 1:1:1, the density of a single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm³. 3 Therefore, for example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of a-like OS is 5.0 g / cm³. 3 Above and below 5.9 g / cm 3 Additionally, for example, in oxide semiconductors with an atomic ratio of In:Ga:Zn = 1:1:1, the densities of nc-OS and CAAC-OS are 5.9 g / cm³. 3 Above and less than 6.3 g / cm 3 .

[0558] Note that sometimes identical oxide semiconductors do not exist in a single-crystal structure. In this case, by combining different single-crystal oxide semiconductors in arbitrary proportions, the density of single-crystal oxide semiconductors corresponding to the desired composition can be estimated. The density of single-crystal oxide semiconductors corresponding to the desired composition can be calculated using a weighted average based on the combination proportions of the different single-crystal oxide semiconductors. Note that it is preferable to minimize the number of types of single-crystal oxide semiconductors combined when calculating the density.

[0559] As described above, oxide semiconductors have various structures and properties. Note that oxide semiconductors can be, for example, stacks of two or more of the following: amorphous oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0560] <2-5. Methods for forming CAAC-OS>

[0561] Next, an example of the method for forming CAAC-OS will be explained.

[0562] Figure 22 This is a schematic diagram of the film-forming chamber. CAAC-OS can be formed using sputtering.

[0563] like Figure 22 As shown, the substrate 5220 and the target 5230 are arranged opposite to each other. Plasma 5240 is present between the substrate 5220 and the target 5230. Additionally, a heating mechanism 5260 is provided under the substrate 5220. The target 5230 is attached to a pad (not shown). Multiple magnets are arranged opposite to the target 5230 across the pad. A sputtering method that utilizes the magnetic field of magnets to increase the deposition rate is called magnetron sputtering.

[0564] The distance d between the substrate 5220 and the target 5230 (also called the distance between the target and the substrate (TS distance)) is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. The deposition chamber is almost filled with a deposition gas (e.g., oxygen, argon, or a mixture containing more than 5 vol% oxygen), and the pressure in the deposition chamber is controlled to be 0.01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. Here, by applying a voltage of a certain degree or more to the target 5230, discharge is initiated and plasma 5240 is observed. A high-density plasma region is formed near the target 5230 by the magnetic field. In the high-density plasma region, ions 5201 are generated due to the ionization of the deposition gas. Ions 5201 are, for example, oxygen cations (O). + ) or argon cations (Ar + )wait.

[0565] The target material 5230 has a polycrystalline structure comprising multiple grains, wherein each grain includes a cleaved facet. As an example, Figures 23A to 23C The crystal structure of InMZnO4 (element M is, for example, Al, Ga, Y or Sn) contained in the target material 5230 is shown. Figure 23A This is the crystal structure of InMZnO4 when viewed from a direction parallel to the b-axis. In the InMZnO4 crystal, due to the negative charge of oxygen atoms, a repulsive force is generated between two adjacent M-Zn-O layers. Therefore, the InMZnO4 crystal has a cleavage surface between two adjacent M-Zn-O layers.

[0566] Ions 5201 generated in the high-density plasma region are accelerated by the electric field towards the target 5230 and collide with the target 5230. At this time, particles 5200, which are plate-shaped or granular sputtered particles, are peeled off from the cleaved surface (see reference). Figure 22 Particle 5200 is... Figure 23AThe portion sandwiched between the two cleaved surfaces is shown. Therefore, it can be seen that if only particle 5200 is extracted, its cross-section becomes as follows. Figure 23B As shown, its top surface becomes as Figure 23C As shown. In addition, the structure of particle 5200 can sometimes be distorted by the impact of collisions with ion 5201.

[0567] Particle 5200 is a plate-shaped (granular) sputtered particle with a triangular, such as an equilateral triangle, planar surface. Alternatively, particle 5200 is a plate-shaped (granular) sputtered particle with a hexagonal, such as a regular hexagonal, planar surface. Note that the planar shape of particle 5200 is not limited to triangular or hexagonal. For example, sometimes it is a planar shape combining multiple triangles. For example, sometimes it is also a quadrangle (e.g., rhombus) formed by combining two triangles (e.g., an equilateral triangle).

[0568] The thickness of particle 5200 depends on the type of deposition gas, etc. For example, the thickness of particle 5200 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Additionally, the width of particle 5200 is, for example, 1 nm or more and 100 nm or less, preferably 2 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less. For example, ions 5201 are collided with a target 5230 having an In-M-Zn oxide layer. As a result, particle 5200 having three layers—an M-Zn-O layer, an In-O layer, and an M-Zn-O layer—is peeled off. Furthermore, along with the peeling of particle 5200, particle 5203 is also ejected from the target 5230. Particle 5203 has one or more atoms as aggregates. Therefore, particle 5203 can also be referred to as an atomic particle.

[0569] Particle 5200 sometimes receives an electric charge as it passes through plasma 5240, thus its surface becomes negatively or positively charged. For example, particle 5200 sometimes absorbs O from plasma 5240. 2- It receives a negative charge. As a result, sometimes the oxygen atoms on the surface of particle 5200 are negatively charged. In addition, particle 5200 sometimes grows by bonding with indium, element M, zinc or oxygen in plasma 5240 when passing through plasma 5240.

[0570] Particles 5200 and 5203, after passing through plasma 5240, reach the surface of substrate 5220. In addition, some of the particles 5203, due to their small mass, are sometimes discharged to the outside by means of a vacuum pump or the like.

[0571] Next, refer to Figures 24A to 24F This describes particles 5200 and 5203 deposited on the surface of substrate 5220.

[0572] First, the first particle 5200 is deposited on the substrate 5220. Since the particle 5200 is flat, it is deposited with its plane facing the surface of the substrate 5220. At this time, the charge on the surface of the particle 5200 on the substrate 5220 side is released through the substrate 5220.

[0573] Next, the second particle 5200 reaches the substrate 5220. At this point, because the surfaces of the first and second particles 5200 are charged, they repel each other. As a result, the second particle 5200 avoids deposition on the first particle 5200, and instead deposits on the surface of the substrate 5220 slightly further away from the first particle 5200 with its plane facing the surface of the substrate 5220. By repeating the above deposition process, numerous particles 5200 are deposited on the surface of the substrate 5220, with a thickness equivalent to one layer. Furthermore, regions where no particles 5200 are deposited are created between the particles 5200 (see reference). Figure 24A ).

[0574] Next, particles 5203, which receive energy from the plasma, reach the surface of the substrate 5220. Particles 5203 cannot deposit on active regions such as the surface of particles 5200. Therefore, particles 5203 move to areas where particles 5200 are not deposited and attach to the sides of particles 5200. The bonds of particles 5203 become active through receiving energy from the plasma, thereby chemically bonding with particles 5200 to form a lateral growth portion 5202 (see reference). Figure 24B ).

[0575] Furthermore, the lateral growth portion 5202 grows in the lateral direction, thereby connecting the particles 5200 (see reference). Figure 24C Thus, the lateral growth portion 5202 is formed until it fills the area of ​​the undeposited particles 5200. This mechanism is similar to the deposition mechanism of atomic layer deposition (ALD).

[0576] Even when particles 5200 are deposited in directions opposite to each other, particles 5203 grow laterally to fill the gaps between particles 5200, thus preventing the formation of defined grain boundaries. Furthermore, because particles 5203 are smoothly connected between particles 5200, a crystalline structure different from both single-crystal and polycrystalline structures is formed. In other words, a strained crystalline structure is formed between tiny crystalline regions (particles 5200). Therefore, since the gaps between crystalline regions are strained crystalline regions, it is inappropriate to consider this region as an amorphous structure.

[0577] Next, the new particles 5200 are deposited in a planar-to-surface manner (see reference). Figure 24DAdditionally, particles 5203 are deposited to fill areas where undeposited particles 5200 are not deposited, thus forming lateral growth portions 5202 (see reference). Figure 24E Thus, particle 5203 attaches to the side of particle 5200, and the lateral growth portion 5202 grows in the lateral direction, thereby connecting the particles 5200 in the second layer (see reference). Figure 24F Deposition continues until the m-th layer (where m is an integer greater than or equal to two) is formed, resulting in a thin film structure containing a stack.

[0578] Furthermore, the deposition mechanism of particles 5200 varies depending on factors such as the surface temperature of the substrate 5220. For example, when the surface temperature of the substrate 5220 is high, particles 5200 migrate on the surface of the substrate 5220. As a result, the proportion of particles 5200 directly connected without being sandwiched with particles 5203 increases, resulting in CAAC-OS with higher orientation. The surface temperature of the substrate 5220 during CAAC-OS formation is above room temperature and below 340°C, preferably above room temperature and below 300°C, more preferably above 100°C and below 250°C, and even more preferably above 100°C and below 200°C. Therefore, even when using a large-area substrate of generation 8 or higher as the substrate 5220, warping or other issues caused by CAAC-OS deposition are almost non-existent.

[0579] On the other hand, when the surface temperature of the substrate 5220 is low, the particles 5200 do not easily migrate on the surface of the substrate 5220. As a result, the particles 5200 are stacked, resulting in low-orientation nc-OS, etc. In nc-OS, since the particles 5200 are negatively charged, it is possible for the particles 5200 to be deposited with a certain gap between them. Therefore, although nc-OS has low orientation, it has a denser structure compared to amorphous oxide semiconductors due to its slightly regularity.

[0580] In CAAC-OS, when the gaps between particles are extremely small, a large particle sometimes forms. This large particle contains a single-crystal structure. For example, the particle size, viewed from the top surface, can sometimes be greater than 10 nm and less than 200 nm, greater than 15 nm and less than 100 nm, or greater than 20 nm and less than 50 nm.

[0581] As described in the deposition model above, particles can be considered to be deposited on the surface of the substrate. CAAC-OS can be formed even if the formation surface does not have a crystalline structure. Therefore, the above deposition model, which differs from epitaxial growth, is quite appropriate. Furthermore, using the above deposition model, CAAC-OS and nc-OS can be uniformly deposited on large-area glass substrates, etc. For example, CAAC-OS can be formed even if the substrate surface (formation surface) structure is amorphous (e.g., amorphous silicon oxide).

[0582] Furthermore, it is known that even when the substrate surface (forming surface) is uneven, the particles are arranged along its shape.

[0583] In addition, according to the above deposition model, in order to form highly crystalline CAAC-OS, the following method can be used: first, deposit under high vacuum to increase the mean free path; then, reduce the energy of the plasma to reduce damage near the substrate; and then apply thermal energy to the formation surface to eliminate plasma damage with each deposition.

[0584] Furthermore, the above deposition model is not limited to using targets with a polycrystalline structure of composite oxides such as In-M-Zn oxides containing multiple grains, where any grain contains a cleaved face. For example, it can also be applied to targets containing a mixture of oxides containing indium oxide, element M, and zinc oxide.

[0585] Because the hybrid target material lacks a cleaved surface, atomic particles are stripped from the target during sputtering. During deposition, a strong electric field region with plasma is formed near the target. Consequently, the atomic particles stripped from the target bond and grow laterally due to the strong electric field of the plasma. For example, first, indium atoms, as atomic particles, bond and grow laterally, thereby forming nanocrystals composed of an In-O layer. Then, an M-Zn-O layer is bonded vertically to complement these nanocrystals. Thus, even when using a hybrid target material, it is possible to form particles. Therefore, the above deposition model can be applied even when using a hybrid target material.

[0586] However, in a strong electric field region where no plasma is formed near the target, only atomic particles detached from the target are deposited on the substrate surface. In this case, sometimes the atomic particles grow laterally on the substrate surface. However, the orientation of the atomic particles is inconsistent, resulting in inconsistent crystal orientation of the obtained thin film. That is, it becomes nc-OS, etc.

[0587] <2-6. Lateral Growth>

[0588] The following describes the situation where lateral growth occurs when particle 5203 attaches (also known as bonding or adsorption) to particle 5200.

[0589] Figures 25A to 25E This diagram illustrates the structure of particle 5200 and the location of metal ion attachments. Furthermore, particle 5200 is assumed to be a cluster model of 84 atoms extracted from the InMZnO4 crystal structure while maintaining stoichiometry. Note that the following explanation uses Ga as the atom M. Additionally, Figure 25FThe structure of particle 5200 is shown when viewed from a direction parallel to the c-axis. Figure 25G The structure of particle 5200 is shown when viewed from a direction parallel to the a-axis.

[0590] The attachment sites of metal ions are shown at positions A, B, a, b, and c. Position A is above a lattice site on the top surface of particle 5200, surrounded by one gallium atom and two zinc atoms. Position B is above a lattice site on the top surface of particle 5200, surrounded by two gallium atoms and one zinc atom. Position a is an indium site on the side surface of particle 5200. Position b is an lattice site between the In-O layer and the Ga-Zn-O layer on the side surface of particle 5200. Position c is a gallium site on the side surface of particle 5200.

[0591] Next, the relative energies of metal ions configured at the assumed positions (positions A, B, a, b, and c) were evaluated using first-principles calculations. The calculations employed the VASP (Vienna Ab initio Simulation Package) software for first-principles calculations. Furthermore, the PBE (Perdew-Burke-Ernzerhof) type generalized gradient approximation (GGA) was used as the exchange correlation potential, and the PAW (Projector Augmented Wave) method was used as the ion potential energy. The cutoff energy was set to 400 eV, and the k-point sampling was only the Γ-point. Table 2 shows the relative energies of indium ions configured at positions A, B, a, b, and c. 3 + Gallium ions (Ga) 3+ ) and zinc ions (Zn 2+ The relative energy is the energy of the lowest energy model in the computational model, which is 0 eV.

[0592] [Table 2]

[0593]

[0594] The results above show that any metal ion adheres more easily to the side surface than to the top surface of particle 5200. In particular, at the indium site at position a, not only indium ions but also zinc ions adhere most easily.

[0595] For oxygen ions (O 2- The adhesion of particles 5200 was evaluated. Figures 26A to 26E This is a diagram showing the structure of particle 5200 and the location of oxygen ion attachment. Furthermore, Figure 26FThe structure of particle 5200 is shown when viewed from a direction parallel to the c-axis. Figure 26G The structure of particle 5200 is shown when viewed from a direction parallel to the b-axis.

[0596] The attachment sites of oxygen ions are shown at positions C, D, d, e, and f. At position C, the oxygen ion is bonded to gallium on the top surface of particle 5200. At position D, the oxygen ion is bonded to zinc on the top surface of particle 5200. At position d, the oxygen ion is bonded to indium on the side surface of particle 5200. At position e, the oxygen ion is bonded to gallium on the side surface of particle 5200. At position f, the oxygen ion is bonded to zinc on the side surface of particle 5200.

[0597] Next, the relative energies of oxygen ions at the assumed positions (positions C, D, d, e, and f) are evaluated using first-principles calculations. Table 3 shows the relative energies of oxygen ions (O2) at positions C, D, d, e, and f. 2- The relative energy of the case.

[0598] [Table 3]

[0599]

[0600] The results above show that oxygen ions are more likely to adhere to the side surface compared to the top surface of particle 5200.

[0601] Therefore, it can be concluded that particles 5203 close to particle 5200 preferentially attach to the side of particle 5200. That is, it can be said that the above deposition model of lateral growth of particle 5200 caused by particles 5203 attached to the side of particle 5200 is quite appropriate.

[0602] The structure shown in this embodiment can be implemented by appropriately combining it with any structure shown in other embodiments or other examples.

[0603] Implementation Method 3

[0604] In this embodiment, refer to Figures 27A to 45 A display device having one aspect of the semiconductor device of the present invention will be described. Furthermore, in this embodiment, a structure (liquid crystal display device) with a liquid crystal element as the display element will be specifically described.

[0605] <3-1. Liquid Crystal Display Device>

[0606] Figure 27AThe liquid crystal display device 880 shown includes: a pixel unit 871; a gate driver 874; a source driver 876; m scan lines 877 arranged parallel or substantially parallel to each other and whose potentials are controlled by the gate driver 874; and n signal lines 879 arranged parallel or substantially parallel to each other and whose potentials are controlled by the source driver 876. The pixel unit 871 has a plurality of pixels 870 arranged in a matrix. In addition, there are common lines 875 arranged parallel or substantially parallel to each other along the signal lines 879. In addition, the gate driver 874 and the source driver 876 are sometimes collectively referred to as a driving circuit unit.

[0607] Each scan line 877 is electrically connected to n pixels 870 arranged in any row of a plurality of pixels 870 arranged in m rows and n columns in the pixel section 871. Each signal line 879 is electrically connected to m pixels 870 arranged in any column of a plurality of pixels 870 arranged in m rows and n columns. m and n are both integers greater than or equal to 1. Each common line 875 is electrically connected to m pixels 870 arranged in any row of a plurality of pixels 870 arranged in m rows and n columns.

[0608] Figure 27B It shows what can be used for Figure 27A An example of the circuit structure of pixel 870 of the liquid crystal display device 880 shown.

[0609] Figure 27B The pixel 870 shown has a liquid crystal element 851, a transistor 852 and a capacitor 855.

[0610] The transistor described in the previous embodiment 1 can be used for transistor 852.

[0611] One of the pair of electrodes of the liquid crystal element 851 is connected to the transistor 852, and its potential is appropriately set according to the specifications of the pixel 870. The other of the pair of electrodes of the liquid crystal element 851 is connected to the common line 875 and is applied with the same potential (common potential). The orientation state of the liquid crystal contained in the liquid crystal element 851 is controlled according to the data written to the transistor 852.

[0612] Liquid crystal element 851 is a device that uses the optical modulation effect of liquid crystals to control the transmission or non-transmission of light. The optical modulation effect of liquid crystals is controlled by an electric field (including a transverse electric field, a longitudinal electric field, or a tilting electric field) applied to the liquid crystal. The liquid crystal used in liquid crystal element 851 can be thermotropic liquid crystal, low-molecular-weight liquid crystal, high-molecular-weight liquid crystal, high-molecular-weight dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, homogeneous phase, etc., depending on the conditions.

[0613] Furthermore, when using a lateral electric field, liquid crystals exhibiting a blue phase can be used without an alignment film. The blue phase is a type of liquid crystal phase that appears just before the cholesteric liquid crystal transitions to a homogeneous phase when the temperature is raised. Because the blue phase only appears within a narrow temperature range, a liquid crystal composition containing several wt% or more chiral reagents is used in the liquid crystal layer to broaden the temperature range. Liquid crystal compositions containing both the blue phase liquid crystal and the chiral reagent have a fast response speed and are optically isotropic. Moreover, liquid crystal compositions containing the blue phase liquid crystal do not require alignment processing and have low viewing angle dependence. Additionally, since no alignment film is required, friction processing is unnecessary, thus preventing electrostatic damage caused by friction processing, thereby reducing defects and breakage of the liquid crystal display device during the manufacturing process.

[0614] Furthermore, as a driving method for the liquid crystal display device 880 including the liquid crystal element 851, the following modes can be used: TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, and AFLC (Anti-Ferroelectric Liquid Crystal) mode, etc.

[0615] Alternatively, the LCD display device 880 can also be a normally black LCD display device, such as a transmissive LCD display device using vertical alignment (VA) mode. As for the vertical alignment mode, MVA (Multi-Domain Vertical Alignment), PVA (Patterned Vertical Alignment), and ASV (Advanced Super View) modes can be used.

[0616] <3-2. Liquid Crystal Display Devices Using Lateral Electric Field>

[0617] First, we will explain the transverse electric field modes, typically the FFS mode and the IPS mode.

[0618] exist Figure 27BIn the structure of pixel 870 shown, one of the source and drain electrodes of transistor 852 is electrically connected to signal line 879, and the other of the source and drain electrodes is electrically connected to one of a pair of electrodes of liquid crystal element 851. The gate electrode of transistor 852 is electrically connected to scan line 877. Transistor 852 has the function of controlling the writing of data signals.

[0619] exist Figure 27B In the structure of pixel 870 shown, one of the pairs of electrodes of capacitor 855 is connected to the other of the source and drain electrodes of transistor 852. The other of the pairs of electrodes of capacitor 855 is electrically connected to common line 875. The potential value of common line 875 is appropriately set according to the specifications of pixel 870. Capacitor 855 is used as a storage capacitor to store the data written to it. Note that in the liquid crystal display device 880 driven in FFS mode, one of the pairs of electrodes of capacitor 855 corresponds to part or all of one of the pairs of electrodes of liquid crystal element 851, and the other of the pairs of electrodes of capacitor 855 corresponds to part or all of the other of the pairs of electrodes of liquid crystal element 851.

[0620] <3-3. Example 1 of a substrate structure for a device with a lateral electric field>

[0621] Next, the specific structure of the element substrate included in the liquid crystal display device 880 will be explained. First, Figure 28 The diagram shows a plurality of pixels 870a, 870b and 870c included in a liquid crystal display device 880 driven in FFS mode.

[0622] exist Figure 28 In the figure, the conductive film 813, used as a scan line, extends in a direction substantially orthogonal to the signal line (left-right direction in the figure). The conductive film 821a, used as a signal line, extends in a direction substantially orthogonal to the scan line (up-down direction in the figure). The conductive film 813 used as a scan line is electrically connected to the gate driver 874, while the conductive film 821a used as a signal line is electrically connected to the source driver 876 (see Figure 874). Figure 27A ).

[0623] Transistor 852 is located near the intersection of the scan line and the signal line. Transistor 852 consists of a conductive film 813 serving as the gate electrode and a gate insulating film (in... Figure 28The transistor 852 is composed of an oxide semiconductor film 808 (not shown in the diagram), a channel region formed on a gate insulating film, and conductive films 821a and 821b serving as source and drain electrodes. The conductive film 813 is also used as a scan line, and the region of the conductive film 813 overlapping with the oxide semiconductor film 808 is used as the gate electrode of the transistor 852. The conductive film 821a is used as a signal line, and the conductive film 821a overlapping with the oxide semiconductor film 808 is used as either the source or drain electrode of the transistor 852. Figure 28 In the top view shown, the ends of the scan lines are located outside the ends of the oxide semiconductor film 808. Thus, the scan lines act as a light-shielding film to block light from light sources such as backlights. As a result, the oxide semiconductor film 808 included in the transistor is not illuminated, thereby suppressing variations in the transistor's electrical characteristics.

[0624] The conductive film 821b is electrically connected to the oxide semiconductor film 819a, which serves as a pixel electrode. Additionally, an insulating film (in...) is placed across the oxide semiconductor film 819a. Figure 28 (Not shown in the figure) A common electrode 829 is provided.

[0625] The common electrode 829 includes a striped region extending in a direction intersecting the signal lines. Furthermore, this striped region is connected to a region extending in a direction parallel or substantially parallel to the signal lines. Therefore, in the plurality of pixels included in the liquid crystal display device 880, the potential of the striped region of the common electrode 829 is equal.

[0626] Capacitor 855 is formed in the region where oxide semiconductor film 819a overlaps with common electrode 829. Both oxide semiconductor film 819a and common electrode 829 are transparent. That is, capacitor 855 is transparent.

[0627] Because capacitor 855 is transparent, it can be formed in a relatively large area within pixel 870. This allows for a display device that can increase the amount of charge while simultaneously increasing the aperture ratio (typically to 50% or more, preferably to 60% or more). For example, in high-resolution display devices such as liquid crystal displays, the pixel area is small, and consequently, the capacitor area is also small. Therefore, in high-resolution display devices, the amount of charge stored in the capacitor is small. However, since capacitor 855 shown in this embodiment is transparent, by providing this capacitor within the pixel, a sufficient amount of charge can be obtained in each pixel while simultaneously increasing the aperture ratio. Typically, capacitor 855 can be appropriately applied to high-resolution display devices with pixel densities of 200 ppi or more, 300 ppi or more, or 500 ppi or more.

[0628] Furthermore, in liquid crystal display devices, the larger the capacitance value of the capacitor, the longer the period during which the orientation of the liquid crystal molecules in the liquid crystal element remains fixed under an applied electric field. When displaying static images, since this period can be extended, the number of times image data can be rewritten can be reduced, thereby lowering power consumption. Additionally, by employing the structure shown in this embodiment, the aperture ratio can be increased in high-resolution display devices, thus allowing for efficient utilization of light from light sources such as backlights, thereby reducing the power consumption of the display device.

[0629] then, Figure 29 Show along Figure 28 Cross-sectional views of the dotted-dash lines Q1-R1 and S1-T1. Figure 29 The transistor 852 shown is a channel-etched transistor. Note that the cross-sectional view along the dotted line Q1-R1 is a cross-sectional view of transistor 852 and capacitor 855 along the channel length direction, and the cross-sectional view along the dotted line S1-T1 is a cross-sectional view of transistor 852 along the channel width direction. Additionally, in Figure 28 For clarity, the oxide semiconductor film 819b, which is used as the second gate electrode, is omitted.

[0630] Figure 29 The transistor 852 shown includes: a conductive film 813 on a substrate 811 serving as a first gate electrode; an insulating film 815 formed on the substrate 811 and the conductive film 813 serving as the first gate electrode; an insulating film 817 formed on the insulating film 815; an oxide semiconductor film 808 overlapping the conductive film 813 serving as the gate electrode with the insulating film 815 and the insulating film 817 separated by the insulating film 815 and the insulating film 817; conductive films 821a and 821b serving as source and drain electrodes and in contact with the oxide semiconductor film 808; insulating films 823 and 825 on the oxide semiconductor film 808, the conductive films 821a and 821b serving as source and drain electrodes; an oxide semiconductor film 819b on the insulating film 825 serving as a second gate electrode; and an insulating film 827 on the insulating film 825 and the oxide semiconductor film 819b.

[0631] An oxide semiconductor film 819a is formed on an insulating film 825. The oxide semiconductor film 819a is electrically connected to one of the conductive films 821a and 821b (here, conductive film 821b) used as a source electrode and a drain electrode, through openings formed in the insulating films 823 and 825. An insulating film 827 is formed on the insulating film 825 and the oxide semiconductor film 819a. Furthermore, a common electrode 829 is formed on the insulating film 827.

[0632] In addition, the area where the oxide semiconductor film 819a, the insulating film 827, and the common electrode 829 overlap is used as a capacitor 855.

[0633] Furthermore, the cross-sectional structure of one embodiment of the present invention is not limited thereto. For example, the oxide semiconductor film 819a may have slits. Alternatively, the oxide semiconductor film 819a may be comb-shaped.

[0634] In addition, such as Figure 30 As shown, the common electrode 829 can also be disposed on the insulating film 828 on the insulating film 827. The insulating film 828 is used as a planarization film.

[0635] <3-4. Example 2 of a substrate structure for a device with a lateral electric field>

[0636] then, Figure 31 This is a top view showing the plurality of pixels 870d, 870e, and 870f included in the liquid crystal display device 880. The structure of pixels 870d, 870e, and 870f is similar to... Figure 28 The pixels are different. Figure 31 The liquid crystal display device 880 shown is driven in IPS mode.

[0637] exist Figure 31 In the figure, the conductive film 813, used as a scan line, is provided extending in the left-right direction. The conductive film 821a, used as a signal line, is provided in a V-shape with a portion of it bent, extending in a direction substantially orthogonal to the scan line (vertical direction in the figure). The conductive film 813 used as a scan line is electrically connected to the gate driver 874, while the conductive film 821a used as a signal line is electrically connected to the source driver 876 (see reference). Figure 27A ).

[0638] Transistor 852 is located near the intersection of the scan line and the signal line. Transistor 852 consists of a conductive film 813 serving as the gate electrode and a gate insulating film (in... Figure 31 The transistor 852 is composed of an oxide semiconductor film 808 (not shown in the diagram), a channel region formed on a gate insulating film, and conductive films 821a and 821b serving as source and drain electrodes. The conductive film 813 is also used as a scan line, and the region of the conductive film 813 overlapping with the oxide semiconductor film 808 is used as the gate electrode of the transistor 852. The conductive film 821a is used as a signal line, and the conductive film 821a overlapping with the oxide semiconductor film 808 is used as the source electrode of the transistor 852. Figure 31 In the top view shown, the ends of the scan lines are located outside the ends of the oxide semiconductor film 808. Thus, the scan lines act as a light-shielding film to block light from light sources such as backlights. As a result, the oxide semiconductor film 808 included in the transistor is not illuminated, thereby suppressing variations in the transistor's electrical characteristics.

[0639] The conductive film 821b is electrically connected to the oxide semiconductor film 819a, which serves as a pixel electrode. The oxide semiconductor film 819a is formed in a comb-like shape. Additionally, an insulating film is provided on the oxide semiconductor film 819a. Figure 31 (Not shown in the figure), a common electrode 829 is disposed on the insulating film. In the top view, the common electrode 829 is formed in a comb-like shape to engage with the oxide semiconductor film 819a, so that a portion of the common electrode 829 and the oxide semiconductor film 819a overlap. The common electrode 829 is connected to a region extending in a direction parallel or substantially parallel to the scan line. Therefore, the potential of the common electrode 829 is equal in all pixels included in the liquid crystal display device 880. The oxide semiconductor film 819a and the common electrode 829 have a V-shape that bends along the signal line (conductive film 821a).

[0640] Capacitor 855 is formed in the region where oxide semiconductor film 819a overlaps with common electrode 829. Both oxide semiconductor film 819a and common electrode 829 are transparent. That is, capacitor 855 is transparent.

[0641] then, Figure 32 Show along Figure 31 Cross-sectional views of the dotted-dash lines Q2-R2 and S2-T2. Figure 32 The transistor 852 shown is a channel-etched transistor. Note that the cross-section along the dotted line Q2-R2 is a cross-sectional view of transistor 852 and capacitor 855 along the channel length direction, and the cross-sectional view along the dotted line S2-T2 is a cross-sectional view of transistor 852 along the channel width direction. Additionally, in Figure 31 For clarity, the oxide semiconductor film 819b, which is used as the second gate electrode, is omitted.

[0642] Figure 32 The transistor 852 shown includes: a conductive film 813 on a substrate 811 serving as a gate electrode; an insulating film 815 formed on the substrate 811 and the conductive film 813 serving as a gate electrode; an insulating film 817 formed on the insulating film 815; an oxide semiconductor film 808 overlapping the conductive film 813 serving as a gate electrode with the insulating film 815 and the insulating film 817 separated by the insulating film 815 and the insulating film 817; conductive films 821a and 821b serving as source and drain electrodes and in contact with the oxide semiconductor film 808; insulating films 823 and 825 on the oxide semiconductor film 808, the conductive films 821a and 821b serving as source and drain electrodes; an oxide semiconductor film 819b on the insulating film 825 serving as a second gate electrode; and an insulating film 827 on the insulating film 825 and the oxide semiconductor film 819b.

[0643] An oxide semiconductor film 819a is formed on an insulating film 825. The oxide semiconductor film 819a is electrically connected to one of the conductive films 821a and 821b (here, conductive film 821b) used as a source electrode and a drain electrode, through openings formed in the insulating films 823 and 825. An insulating film 827 is formed on the insulating film 825 and the oxide semiconductor film 819a. Furthermore, a common electrode 829 is formed on the insulating film 827.

[0644] The region where the oxide semiconductor film 819a, the insulating film 827, and the common electrode 829 overlap is used as a capacitor 855.

[0645] exist Figure 31 and Figure 32 In the liquid crystal display device shown, the capacitors included in the pixels have a structure in which the ends and vicinity of the oxide semiconductor film 819a and the ends and vicinity of the common electrode 829 overlap. By adopting this structure, capacitors of an appropriate size, rather than excessively large, can be formed in large liquid crystal display devices.

[0646] In addition, such as Figure 33 As shown, the common electrode 829 can also be disposed on the insulating film 828 on the insulating film 827.

[0647] In addition, such as Figure 34 and Figure 35 As shown, the oxide semiconductor film 819a and the common electrode 829 may not overlap. The positional relationship between the oxide semiconductor film 819a and the common electrode 829 can be appropriately determined based on the size of the capacitor corresponding to the driving method or resolution of the display device. Furthermore, Figure 35 The common electrode 829 included in the display device shown can also be disposed on the insulating film 828, which is used as a planarization film (see reference). Figure 36 ).

[0648] exist Figure 31 and Figure 32 In the liquid crystal display device shown, the width of the region extending in a direction parallel or substantially parallel to the signal line (conductive film 821a) of the oxide semiconductor film 819a is... Figure 32 d1) is less than the width of the region of the common electrode 829 extending in a direction parallel or substantially parallel to the signal line. Figure 32 d2 in the text, but liquid crystal display devices are not limited to this. For example Figure 37 and Figure 38As shown, the width d1 can also be greater than the width d2. Alternatively, the widths d1 and d2 can be equal. Furthermore, in a pixel (e.g., pixel 870d), the widths of multiple regions of the oxide semiconductor film 819a and / or the common electrode 829 extending in a direction parallel or substantially parallel to the signal line can be different.

[0649] like Figure 39 As shown, the insulating film 828 disposed on the insulating film 827 can also be removed such that only the area of ​​the insulating film 828 overlapping with the common electrode 829 remains. In this case, the common electrode 829 can be used as a mask to etch the insulating film 828. Unevennesses of the common electrode 829 on the insulating film 828, which serves as a planarization film, can be suppressed, and the slope of the insulating film 828 from the end of the common electrode 829 to the side of the insulating film 827 is formed to be small. Furthermore, as... Figure 40 As shown, a portion of the area on the surface of the insulating film 828 parallel to the substrate 811 may also be left uncovered by the common electrode 829.

[0650] like Figure 41 and Figure 42 As shown, the common electrode can also be disposed on the same film as the oxide semiconductor film 819a, that is, on the insulating film 825. Figure 41 and Figure 42 The common electrode 819c shown can be formed using the same material as the oxide semiconductor film 819a and by processing the same oxide semiconductor film.

[0651] <3-5. Vertically Oriented Liquid Crystal Display Devices>

[0652] Reference Figure 43 and Figure 44 The structure of a pixel having a liquid crystal element that operates in vertical alignment (VA) mode is explained. Figure 43 This is a top view of the pixels in a liquid crystal display device. Figure 44 It includes along Figure 43 A side view of the cross-section along the cutting line A1-B1. Additionally, Figure 45 It is the equivalent circuit diagram of the pixels in a liquid crystal display device.

[0653] VA type refers to a method of aligning liquid crystal molecules in a liquid crystal display panel. In a VA type liquid crystal display device, the liquid crystal molecules are oriented in a direction perpendicular to the panel surface when no voltage is applied.

[0654] Specifically, pixels are divided into several regions (sub-pixels) so that molecules are directed in different directions. This is called multi-domain sizing or multi-domain design. The following description illustrates a liquid crystal display device that incorporates multi-domain design.

[0655] Figure 43 Z1 is a top view of the substrate 600 on which the pixel electrode 624 is formed. Z3 is a top view of the substrate 601 on which the common electrode 640 is formed. Z2 is a top view of the substrate 600 on which the pixel electrode 624 is formed and the substrate 601 on which the common electrode 640 is formed, in a state where they overlap.

[0656] A transistor 628, a pixel electrode 624, and a capacitor 630 connected thereto are formed on a substrate 600. The drain electrode 618 of the transistor 628 is electrically connected to the pixel electrode 624 through an opening 633 formed in insulating films 623 and 625. An insulating film 627 is disposed on the pixel electrode 624.

[0657] The transistor 628 can be the same transistor described in Embodiment 1 above.

[0658] The capacitor 630 includes wiring 613, insulating film 623, insulating film 625, and pixel electrode 624 on capacitor wiring 604, which serves as the first capacitor wiring. Capacitor wiring 604 can be formed simultaneously using the same material as the gate wiring 615 of transistor 628. Furthermore, wiring 613, drain electrode 618, and wiring 616 can be formed simultaneously using the same material.

[0659] As the pixel electrode 624, a thin-film oxide semiconductor film with low resistance as described in Embodiment 1 can be used.

[0660] The pixel electrode 624 has a slit 646. The slit 646 is provided to control the orientation of the liquid crystal.

[0661] Transistor 629, pixel electrode 626 connected to transistor 629, and capacitor 631 can be formed in the same manner as transistor 628, pixel electrode 624, and capacitor 630. Transistors 628 and 629 are both connected to wiring 616. Wiring 616 serves as a source electrode in transistors 628 and 629. In the liquid crystal display panel shown in this embodiment, pixels are composed of pixel electrodes 624 and 626. Pixel electrodes 624 and 626 are sub-pixels.

[0662] A coloring film 636 and a common electrode 640 are formed on a substrate 601, and a structure 644 is formed on the common electrode 640. The common electrode 640 has a slit 647. An alignment film 648 is formed on a pixel electrode 624. Furthermore, an alignment film 645 is also formed on the common electrode 640 and the structure 644. A liquid crystal layer 650 is formed between the substrate 600 and the substrate 601.

[0663] The slit 647 and structure 644 formed in the common electrode 640 have the function of controlling the orientation of the liquid crystal.

[0664] When a voltage is applied to the pixel electrode 624 on which the slit 646 is formed, an electric field strain (tilted electric field) is generated near the slit 646. By configuring the slit 646 in an interlocking manner with the structure 644 and the slit 647 on the substrate 601 side, a tilted electric field is effectively generated to control the orientation of the liquid crystal, thereby making the orientation direction of the liquid crystal different according to each position. That is, the viewing angle of the liquid crystal display panel is expanded by performing multi-domain configuration. Alternatively, one of the structure 644 and the slit 647 can be provided on the substrate 601 side.

[0665] Figure 44 This diagram shows substrates 600 and 601 overlapping and incorporating liquid crystal. Pixel electrode 624, liquid crystal layer 650, and common electrode 640 overlap to form a liquid crystal element.

[0666] Figure 45 The equivalent circuit of the pixel structure described above is shown. Transistors 628 and 629 are both connected to gate wiring 602 and wiring 616. In this case, by making the potentials of capacitor wiring 604 and capacitor wiring 605 different, the operation of liquid crystal element 651 and liquid crystal element 652 can be made different. That is, by controlling the potentials of capacitor wiring 604 and capacitor wiring 605 respectively, the orientation of the liquid crystal can be precisely controlled to expand the viewing angle.

[0667] Note that this embodiment can be appropriately combined with any other embodiment shown in this specification.

[0668] Implementation Method 4

[0669] In this embodiment, using Figure 46A and Figure 46B and Figure 47A and Figure 47B This description includes a display device comprising a semiconductor device according to one aspect of the present invention. In this embodiment, the structure of the display element having an electroluminescent (EL) element as the display device will be specifically described.

[0670] <4-1. Display Device>

[0671] Figure 46A The display device shown includes: a region having pixels with display elements (hereinafter referred to as pixel section 502); a circuit section (hereinafter referred to as driving circuit section 504) disposed outside the pixel section 502 and having circuitry for driving the pixels; a circuitry having the function of a protection element (hereinafter referred to as protection circuitry 506); and a terminal section 507. Alternatively, the protection circuitry 506 may not be provided.

[0672] Part or all of the drive circuit section 504 is preferably formed on the same substrate as the pixel section 502, thereby reducing the number of components or terminals. When part or all of the drive circuit section 504 is not formed on the same substrate as the pixel section 502, part or all of the drive circuit section 504 can be mounted by COG or TAB (Tape Automated Bonding).

[0673] The pixel unit 502 includes circuitry (hereinafter referred to as pixel circuitry 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driving circuit unit 504 includes driving circuitry such as circuitry that supplies signals (scan signals) for selecting pixels (hereinafter referred to as gate driver 504a) and circuitry that supplies signals (data signals) for driving the display elements in the pixels (hereinafter referred to as source driver 504b).

[0674] The gate driver 504a includes a shift register, etc. The gate driver 504a receives signals for driving the shift register via terminal 507 and outputs signals. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has the function of controlling the potential of the wiring (hereinafter referred to as scan lines GL_1 to GL_X) to which scan signals are supplied. Alternatively, multiple gate drivers 504a can be provided, and each of the multiple gate drivers 504a can individually control scan lines GL_1 to GL_X. Alternatively, the gate driver 504a has the function of supplying an initialization signal. However, it is not limited to this; the gate driver 504a can also supply other signals. For example, such as... Figure 46A As shown, the gate driver 504a is electrically connected to the wiring (hereinafter also referred to as ANODE_1 to ANODE_X) that controls the potential of the light-emitting element.

[0675] The source driver 504b includes a shift register, etc. The source driver 504b receives signals for driving the shift register and signals from which data signals (image signals) are derived via terminal section 507. The source driver 504b has the function of generating data signals to be written to the pixel circuit 501 based on the image signals. Furthermore, the source driver 504b has the function of controlling the output of the data signals in response to pulse signals generated by inputs such as start pulse signals and clock signals. Additionally, the source driver 504b has the function of controlling the potential of the wiring to which the supplied data signals are located (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b may supply an initialization signal. However, it is not limited to this; the source driver 504b may supply other signals.

[0676] The source driver 504b can be configured using, for example, multiple analog switches. By sequentially turning on multiple analog switches, the source driver 504b can output a signal obtained by time-dividing an image signal as a data signal. Alternatively, the source driver 504b can also be configured using a shift register or the like.

[0677] Pulse signals and data signals are input to each of the plurality of pixel circuits 501 via one of the plurality of scan lines GL supplied with scan signals and one of the plurality of data lines DL supplied with data signals, respectively. Furthermore, gate driver 504a controls the writing and holding of data signals in each of the plurality of pixel circuits 501. For example, a pulse signal is input from gate driver 504a to the pixel circuit 501 in the m-th row and n-th column via scan line GL_m (m is a natural number less than or equal to X), and a data signal is input from source driver 504b to the pixel circuit 501 in the m-th row and n-th column via data line DL_n (n is a natural number less than or equal to Y) according to the potential of scan line GL_m.

[0678] Figure 46A The protection circuit 506 shown is connected, for example, to the scan line GL between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to the data line DL between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 may be connected to the wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 may be connected to the wiring between the source driver 504b and the terminal portion 507. Furthermore, the terminal portion 507 refers to the portion provided with terminals for inputting power, control signals, and image signals to the display device from external circuitry.

[0679] The protection circuit 506 is a circuit that electrically connects the wiring to other wiring when a potential outside a certain range is supplied to the wiring connected to it.

[0680] like Figure 46AAs shown, by providing a protection circuit 506 to the pixel section 502 and the driving circuit section 504, the display device's tolerance to overcurrent caused by ESD (Electro Static Discharge) and the like can be improved. However, the structure of the protection circuit 506 is not limited to this. For example, a structure in which the gate driver 504a is connected to the protection circuit 506 or a structure in which the source driver 504b is connected to the protection circuit 506 may also be used. Alternatively, a structure in which the terminal section 507 is connected to the protection circuit 506 may also be used.

[0681] In addition, although Figure 46A The diagram shows an example of a drive circuit section 504 formed by a gate driver 504a and a source driver 504b, but the structure is not limited to this. For example, only the gate driver 504a may be formed and a substrate with a separately prepared source drive circuit (e.g., a drive circuit substrate formed of a single-crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

[0682] <4-2. Example of a pixel circuit structure>

[0683] in addition, Figure 46A The multiple pixel circuits 501 shown can, for example, employ... Figure 46B The structure shown.

[0684] Figure 46B The pixel circuit 501 shown includes transistor 552, transistor 554, capacitor 562, and light-emitting element 572. Any of the transistors shown in the previous embodiments can be used for one or both of transistors 552 and 554.

[0685] One of the source and drain electrodes of transistor 552 is electrically connected to a wiring (hereinafter referred to as data line DL_n) on which a data signal is supplied. Furthermore, the gate electrode of transistor 552 is electrically connected to a wiring (hereinafter referred to as scan line GL_m) on which a gate signal is supplied.

[0686] Transistor 552 has the function of controlling the writing of data signals by being turned on or off.

[0687] One electrode of the pair of electrodes of capacitor 562 is electrically connected to the other of the source and drain electrodes of transistor 552. Additionally, the other electrode of the pair of electrodes of capacitor 562 is electrically connected to the second gate electrode (also called the back gate) of transistor 554. Capacitor 562 functions as a storage capacitor to store the data that has been written to it.

[0688] One of the source and drain electrodes of transistor 554 is electrically connected to the anode line (ANODE_m).

[0689] One of the anode and cathode of the light-emitting element 572 is electrically connected to the other of the source and drain electrodes of the transistor 554, and the other of the anode and cathode of the light-emitting element 572 is electrically connected to the cathode wire. In addition, one of the anode and cathode of the light-emitting element 572 is electrically connected to the other of a pair of electrodes of the capacitor 562.

[0690] As the light-emitting element 572, an organic EL element can be used, for example. Note that the light-emitting element 572 is not limited to this, and an inorganic EL element using inorganic materials can also be used.

[0691] Including Figure 46B In the display device shown by pixel circuit 501, through Figure 46A The gate driver 504a shown sequentially selects the pixel circuits 501 of each row, thereby turning on the transistor 552 to write data signals.

[0692] When transistor 552 is turned off, the pixel circuit 501, on which data is being written, remains in a held state. Furthermore, the amount of current flowing between the source and drain electrodes of transistor 554 is controlled according to the potential of the data signal being written. The light-emitting element 572 emits light with a brightness corresponding to the amount of current flowing. By performing the above steps line by line, an image can be displayed.

[0693] Furthermore, although this embodiment shows a structure including a light-emitting element 572 as an example of a display element of a display device, the present invention is not limited to this, and the display device may also include a variety of elements.

[0694] The aforementioned display devices include, for example, at least one of the following: liquid crystal elements, LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron emitters, electronic ink, electrophoretic elements, grating light valves (GLV), plasma display panels (PDP), display elements using micro-electromechanical systems (MEMS), digital micromirror devices (DMD), digital micro-shutters (DMS), MIRASOL (a trademark registered in Japan), IMOD (interferometric modulation) elements, MEMS shutter display elements, MEMS display elements using optical interference, electrowetting elements, piezoelectric ceramic displays, and display elements using carbon nanotubes. In addition, they may include display media whose contrast, brightness, reflectivity, transmittance, etc., change due to electrical or magnetic effects. Examples of display devices using electron emitters include field emission displays (FED) or surface-conduction electron-emitter displays (SED). Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, intuitive liquid crystal displays, and projected liquid crystal displays). Examples of display devices using electronic ink or electrophoretic elements include electronic paper. Note that when implementing a transflective or reflective liquid crystal display, it is sufficient to make part or all of the pixel electrodes function as reflective electrodes. For example, it is sufficient to make part or all of the pixel electrodes contain aluminum, silver, etc. In this case, storage circuits such as SRAM can also be placed under the reflective electrodes. This further reduces power consumption.

[0695] Furthermore, the display method of the display device can employ progressive scan or interlaced scan, etc. Moreover, the color elements controlled within pixels during color display are not limited to the three colors RGB (R for red, G for green, and B for blue). For example, it can be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as with a PenTile arrangement, a color element can be composed of two colors from RGB. Different two colors can be selected depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta can be added to RGB. Additionally, the display area size of each color element's pixel can be different. However, the embodiments of the disclosed invention are not limited to color display devices, but can also be applied to black-and-white display devices.

[0696] In addition, white light (W) can be emitted from a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) in a display device. Furthermore, a color layer (also called a filter) can be provided in the display device. As a color layer, red (R), green (G), blue (B), yellow (Y), etc., can be appropriately combined, for example. By using a color layer, color reproduction can be further improved compared to not using a color layer. At this time, it is also possible to directly use the white light from the area excluding the color layer for display by setting up areas including and excluding the color layer. By partially setting up areas excluding the color layer, when displaying bright images, the brightness reduction caused by the color layer can sometimes be reduced, resulting in a power consumption reduction of about 20% to 30%. However, when using self-emissive elements such as organic or inorganic EL elements for full-color display, R, G, B, Y, and W can be emitted from elements having each luminous color. By using self-emissive elements, power consumption can sometimes be further reduced compared to using a color layer.

[0697] <4-3. Examples of pixel structure in display devices>

[0698] Here, refer to Figure 47A and Figure 47B For those with Figure 46B An example of a display device with pixel circuitry is illustrated below. Figure 47A This is a top view of the pixel section of the display device. Figure 47B It is along Figure 47A The cross-sectional view of the dashed line X1-X2. Note that in... Figure 47A In the top view shown, for the sake of simplicity, some of the constituent elements have been omitted.

[0699] Figure 47A and Figure 47BThe display device shown includes: a conductive film 704 on a substrate 702 serving as a first gate electrode; insulating films 706 and 707 on the conductive film 704; an oxide semiconductor film 708 on the insulating film 707; conductive films 712a and 712b on the insulating film 707 and the oxide semiconductor film 708 serving as source and drain electrodes, respectively; a conductive film 712c on the insulating film 707; insulating films 714 and 716 covering the oxide semiconductor film 708, conductive films 712a, 712b, and 712c; and a conductive film 716 on the insulating film 716. The oxide semiconductor film 720 used as a second gate electrode; the insulating film 716 and the insulating film 718 on the oxide semiconductor film 720; the insulating film 722 on the insulating film 718 used as a planarization insulating film; the conductive films 724a and 724b on the insulating film 722 used as pixel electrodes; the structure 726 having the function of suppressing the electrical connection between the conductive films 724a and 724b; the EL layer 728 on the conductive films 724a and 724b and the structure 726; and the conductive film 730 on the EL layer 728.

[0700] The conductive film 712c is electrically connected to the conductive film 704 through openings 752c provided in the insulating films 706 and 707. Furthermore, the oxide semiconductor film 720, which serves as the second gate electrode, is electrically connected to the conductive film 712b through openings 752a formed in the insulating films 714 and 716. Additionally, the conductive film 724a is electrically connected to the conductive film 712b through openings 752b formed in the insulating films 714, 716, 718, and 722.

[0701] Furthermore, the light-emitting element 572 is composed of the conductive film 724a used as the pixel electrode, the EL layer 728, and the conductive film 730. The EL layer 728 can be formed by any of the following methods: sputtering, evaporation (including vacuum evaporation), printing (e.g., letterpress printing, gravure printing, photogravure printing, offset printing, and screen printing), inkjet printing, and coating.

[0702] like Figure 46B , Figure 47A and Figure 47B As shown, a pixel in a display device comprises two transistors and one capacitor, which can reduce the number of wires. For example, as Figure 46B and Figure 47A As shown, a pixel can have three wirings: a gate line, a data line, and an anode line. This structure increases the aperture ratio of the pixels in the display device. Furthermore, by reducing the number of wirings, short circuits between adjacent wirings are less likely to occur. Therefore, a display device with high yield can be provided.

[0703] The structure shown in this embodiment can be implemented by appropriately combining it with the structure shown in any other embodiment.

[0704] Implementation Method 5

[0705] In this embodiment, refer to Figure 48A and Figure 48B , Figure 49A and Figure 49B , Figure 50 , Figure 51A and Figure 51B , Figure 52A and Figure 52B and Figure 53 The description includes a display device with a semiconductor device according to one aspect of the present invention, and an electronic device with an input device mounted on the display device.

[0706] <5-1. Touch Panel>

[0707] Note that in this embodiment, a touch panel 2000 including a display device and an input device will be described as an example of an electronic device. Additionally, an example using a touch sensor as an input device will be described.

[0708] Figure 48A and Figure 48B This is a perspective view of the Touch Panel 2000. Figure 48A and Figure 48B For clarity, only the typical components of the touch panel 2000 are shown.

[0709] Touch panel 2000 includes display device 2501 and touch sensor 2595 (see reference). Figure 48B Furthermore, the touch panel 2000 includes substrates 2510, 2570, and 2590. Additionally, substrates 2510, 2570, and 2590 are all flexible. Note that any one or all of substrates 2510, 2570, and 2590 may not be flexible.

[0710] The display device 2501 includes a plurality of pixels on a substrate 2510 and a plurality of wirings 2511 capable of supplying signals to the pixels. The plurality of wirings 2511 are guided on the outer periphery of the substrate 2510, a portion of which forms a terminal 2519. The terminal 2519 is electrically connected to an FPC 2509 (1).

[0711] The substrate 2590 includes a touch sensor 2595 and a plurality of wirings 2598 electrically connected to the touch sensor 2595. The plurality of wirings 2598 are guided on the outer periphery of the substrate 2590, a portion of which forms a terminal. This terminal is electrically connected to the FPC 2509(2). Furthermore, for clarity, in Figure 48B The electrodes and wiring of the touch sensor 2595, which are disposed on the back side of the substrate 2590 (the side opposite to the substrate 2510), are shown in solid lines in the middle.

[0712] The 2595 touch sensor can be used with capacitive touch sensors. Examples of capacitive touch sensors include surface-type capacitive touch sensors and projection-type capacitive touch sensors.

[0713] As an example of a projection-type capacitive touch sensor, it is mainly divided into self-capacitance touch sensors and mutual capacitance touch sensors, depending on the driving method. When using a mutual capacitance touch sensor, multiple points can be detected simultaneously, making it the preferred choice.

[0714] Notice, Figure 48B The touch sensor 2595 shown is an example of a projected capacitive touch sensor.

[0715] In addition, the touch sensor 2595 can be used with various sensors that can detect the proximity or contact of objects such as fingers.

[0716] The projection-type capacitive touch sensor 2595 includes electrodes 2591 and 2592. Electrode 2591 is electrically connected to any one of a plurality of wirings 2598, while electrode 2592 is electrically connected to any other one of the plurality of wirings 2598.

[0717] like Figure 48A and Figure 48B As shown, electrode 2592 has a shape in which multiple quadrilaterals arranged in one direction are connected to each other at the corners.

[0718] Electrode 2591 is quadrilateral and is arranged in a direction that intersects the direction in which electrode 2592 extends.

[0719] Wiring 2594 is electrically connected to two electrodes 2591 that sandwich electrode 2592. In this case, the area of ​​the intersection of electrode 2592 and wiring 2594 is preferably as small as possible. This reduces the area of ​​regions without electrodes, thereby reducing transmittance deviation. Consequently, the brightness deviation of light transmitted through touch sensor 2595 can be reduced.

[0720] Note that the shapes of electrodes 2591 and 2592 are not limited to this and can have various shapes. For example, a structure can also be adopted in which multiple electrodes 2591 are arranged with as few gaps as possible between them, and multiple electrodes 2592 are arranged spaced apart by an insulating layer to form areas that do not overlap with the electrodes 2591. In this case, by providing virtual electrodes that are electrically insulated from these electrodes between two adjacent electrodes 2592, the area of ​​regions with different transmittance can be reduced, so this is preferred.

[0721] Note that the materials used for the conductive films such as electrodes 2591, 2592, and wiring 2598, which are the same materials constituting the wiring and electrodes of the touch panel, can be examples of transparent conductive films containing indium oxide, tin oxide, or zinc oxide (e.g., ITO films). Furthermore, low-resistance materials are preferred as materials for constituting the wiring and electrodes of the touch panel. For example, silver, copper, aluminum, carbon nanotubes, graphene, and metal halides (such as silver halides) can be used. Metal nanowires composed of multiple extremely fine (e.g., a few nm in diameter) conductors can also be used. Alternatively, metal meshes that form a mesh of conductors can be used. For example, Ag nanowires, Cu nanowires, Al nanowires, Ag meshes, Cu meshes, and Al meshes can be used. For example, when Ag nanowires are used to constitute the wiring and electrodes of the touch panel, the visible light transmittance can be 89% or higher, and the thin-film resistivity can be 40 Ω / cm. 2 Above and 100Ω / cm 2 Furthermore, examples of materials that can be used for the wiring and electrodes constituting the touch panel include metal nanowires, metal meshes, carbon nanotubes, and graphene, which have high visible light transmittance and can therefore be used for electrodes of display elements (e.g., pixel electrodes or common electrodes).

[0722] <5-2. Display Device>

[0723] Next, refer to Figure 49A and Figure 49B This section describes the detailed contents of display device 2501. Figure 49A and Figure 49B It is along Figure 48B The cross-sectional view shown is cut off by the dotted line X1-X2.

[0724] The display device 2501 includes a plurality of pixels configured in a matrix. Each pixel includes a display element and pixel circuitry for driving the display element.

[0725] [Structure of EL elements used as display elements]

[0726] First, refer to Figure 49A The structure of an EL element used as a display element will be described. Note that the following description shows an example of an EL element that emits white light, but the EL element is not limited to this. For example, EL elements emitting different colors of light can be used such that adjacent pixels emit different colors of light respectively.

[0727] For example, substrates 2510 and 2570 can be suitably used with a water vapor transmission rate of 10. -5 g / (m 2 ·day) or less, preferably 10-6 g / (m 2 A flexible material with a coefficient of thermal expansion of 1 × 10⁻⁶ days or less. Alternatively, materials with approximately the same coefficient of thermal expansion are preferably used for substrates 2510 and 2570. For example, the linear expansion coefficient of the aforementioned materials is preferably 1 × 10⁻⁶. -3 / K or less, preferably 5×10 -5 Below / K, further preferably 1×10 -5 / K or below.

[0728] Note that substrate 2510 is a stacked structure, including an insulating layer 2510a to prevent impurities from diffusing into the EL element, a flexible substrate 2510b, and an adhesive layer 2510c to bond the insulating layer 2510a and the flexible substrate 2510b. Additionally, substrate 2570 is a stacked structure, including an insulating layer 2570a to prevent impurities from diffusing into the EL element, a flexible substrate 2570b, and an adhesive layer 2570c to bond the insulating layer 2570a and the flexible substrate 2570b.

[0729] Adhesive layers 2510c and 2570c may, for example, be made of materials including polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin, polyurethane, epoxy resin or resin having siloxane bonding.

[0730] Furthermore, a sealing layer 2560 is included between substrate 2510 and substrate 2570. The sealing layer 2560 preferably has a refractive index higher than that of air. Furthermore, as... Figure 49A As shown, when light is extracted from one side of the sealing layer 2560, the sealing layer 2560 can also serve as an optical element.

[0731] Additionally, a sealant can be formed on the outer periphery of the sealing layer 2560. Using this sealant, an EL element 2550 can be disposed in the area surrounded by the substrate 2510, substrate 2570, sealing layer 2560, and sealant. Note that an inert gas (such as nitrogen or argon) can be used instead of the sealing layer 2560. Furthermore, a desiccant can be placed within the inert gas to absorb moisture, etc. Additionally, epoxy resin or glass powder is preferably used as the sealant, for example. Furthermore, a material that does not allow moisture or oxygen to permeate is preferably used as the material for the sealant.

[0732] in addition, Figure 49A The display device 2501 shown includes a pixel 2505. Furthermore, the pixel 2505 includes a light-emitting module 2580, an EL element 2550, and a transistor 2502t that can supply power to the EL element 2550. Note that the transistor 2502t is used as part of the pixel circuitry.

[0733] Furthermore, the light-emitting module 2580 includes an EL element 2550 and a coloring layer 2567. Additionally, the EL element 2550 includes a lower electrode, an upper electrode, and an EL layer between the lower and upper electrodes.

[0734] In addition, when the sealing layer 2560 is disposed on the light extraction side, the sealing layer 2560 contacts the EL element 2550 and the coloring layer 2567.

[0735] The coloring layer 2567 is located at the position overlapping with the EL element 2550. Therefore, a portion of the light emitted by the EL element 2550 passes through the coloring layer 2567 and... Figure 49A The light is emitted to the outside of the light-emitting module 2580 in the direction indicated by the arrow.

[0736] Furthermore, in the display device 2501, a light-shielding layer 2568 is provided on the light extraction side. The light-shielding layer 2568 is provided in a manner that surrounds the color layer 2567.

[0737] The color layer 2567 can be configured to allow light in a specific wavelength range to pass through. For example, it can be a color filter that allows light in the red wavelength range to pass through, a color filter that allows light in the green wavelength range to pass through, a color filter that allows light in the blue wavelength range to pass through, and a color filter that allows light in the yellow wavelength range to pass through. Each color filter can be formed using various materials by printing, inkjet printing, etching using photolithography, etc.

[0738] Furthermore, an insulating layer 2521 is provided in the display device 2501. The insulating layer 2521 covers transistors 2502t and the like. In addition, the insulating layer 2521 has the function of flattening the unevenness caused by pixel circuitry. Furthermore, the insulating layer 2521 can suppress impurity diffusion. Therefore, the reliability reduction of transistors 2502t and the like due to impurity diffusion can be suppressed.

[0739] Furthermore, an EL element 2550 is formed above the insulating layer 2521. Additionally, a partition wall 2528 is provided such that it overlaps with the end of the lower electrode included in the EL element 2550. Furthermore, spacers controlling the distance between the substrate 2510 and the substrate 2570 can be formed on the partition wall 2528.

[0740] Additionally, the scan line driving circuit 2504 includes a transistor 2503t and a capacitor 2503c. Note that the driving circuit and the pixel circuit can be formed on the same substrate in the same process.

[0741] Additionally, a signal supply wiring 2511 is provided on the substrate 2510. Furthermore, a terminal 2519 is provided on the wiring 2511. The FPC 2509 (1) is electrically connected to the terminal 2519. Furthermore, the FPC 2509 (1) has the function of supplying video signals, clock signals, start signals, reset signals, etc. Additionally, a printed circuit board (PWB) can be mounted on the FPC 2509 (1).

[0742] Note that any of the transistors shown in the preceding embodiments can be applied as transistor 2502t and / or transistor 2503t. The transistor used in this embodiment comprises a highly purified oxide semiconductor film with high crystallinity. This transistor can reduce the current in the off-state (off-state current). Therefore, the hold time of electrical signals such as image signals can be extended, and the write interval can also be extended in the on-state. Therefore, the refresh frequency can be reduced, thereby suppressing power consumption. Furthermore, details of the refresh operation will be explained later.

[0743] Furthermore, the transistors used in this embodiment exhibit high field-effect mobility, enabling high-speed driving. For example, by using such high-speed driving transistors in the display device 2501, the switching transistors for the pixel circuit and the driving transistors for the driving circuit can be formed on the same substrate. That is, since a separate semiconductor device formed from silicon wafers or the like is not required for the driving circuit, the number of components in the semiconductor device can be reduced. Additionally, by using high-speed driving transistors also in the pixel circuit, high-quality images can be provided.

[0744] [Structure of a liquid crystal element used as a display element]

[0745] Next, refer to Figure 49B The structure of a liquid crystal element used as a display element will be described. Note that in the following description, a reflective liquid crystal display device that displays by reflecting external light will be described; however, the present invention is not limited to this. For example, a transmissive liquid crystal display device or a semi-transmissive liquid crystal display device may also be constructed by providing a light source (backlight, sidelight, etc.).

[0746] Figure 49B The display device 2501 shown has, except as follows, the same as Figure 49A The display device 2501 shown has the same structure.

[0747] Figure 49B The pixel 2505 of the display device 2501 shown includes a liquid crystal element 2551 and a transistor 2502t capable of supplying power to the liquid crystal element 2551.

[0748] Furthermore, the liquid crystal element 2551 includes a lower electrode (also referred to as a pixel electrode), an upper electrode, and a liquid crystal layer 2529 between the lower electrode and the upper electrode. The orientation state of the liquid crystal layer 2529 in the liquid crystal element 2551 can be changed by applying a voltage between the lower electrode and the upper electrode. In addition, spacers 2530a and 2530b are provided in the liquid crystal layer 2529. Furthermore, although in Figure 49B Although not shown in the figure, an alignment film can be provided on the side of the upper and lower electrodes that is in contact with the liquid crystal layer 2529.

[0749] As the liquid crystal layer 2529, thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals can be used. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, and isotropic phases, depending on the conditions. Furthermore, in the case of a lateral electric field type liquid crystal display device, a blue-phase liquid crystal that does not require an alignment film can also be used. When using a blue-phase liquid crystal, an alignment film is not required, thus eliminating the need for rubbing treatment. Therefore, electrostatic damage caused by rubbing treatment can be prevented, thereby reducing defects and damage to the liquid crystal display device during the manufacturing process.

[0750] The spacers 2530a and 2530b can be obtained by selectively etching the insulating film. The spacers 2530a and 2530b are provided to control the distance (cell gap) between the substrate 2510 and the substrate 2570. Note that the dimensions of the spacers 2530a and 2530b can be different, and the spacers 2530a and 2530b are preferably columnar or spherical. Furthermore, in... Figure 49B Although the structure in the illustration shows spacers 2530a and 2530b disposed on one side of substrate 2570, it is not limited to this and can be disposed on one side of substrate 2510.

[0751] Furthermore, the upper electrode of the liquid crystal element 2551 is disposed on one side of the substrate 2570. An insulating layer 2531 is also disposed between the upper electrode and the coloring layer 2567 and the light-shielding layer 2568. The insulating layer 2531 functions to flatten the unevenness caused by the coloring layer 2567 and the light-shielding layer 2568. An organic resin film can be used, for example, as the insulating layer 2531. Additionally, the lower electrode of the liquid crystal element 2551 functions as a reflective electrode. Figure 49B The display device 2501 shown is a reflective liquid crystal display device, in which external light is reflected from the lower electrode and the light passes through the color layer 2567 to achieve display. Note that in the case of a transmissive liquid crystal display device, a transparent electrode is provided as the lower electrode.

[0752] in addition, Figure 49BThe display device 2501 shown includes an insulating layer 2522. The insulating layer 2522 covers transistors 2502t, etc. Note that the insulating layer 2522 has the function of flattening the unevenness caused by the pixel circuit and forming unevenness on the lower electrode of the liquid crystal element. Therefore, unevenness can be formed on the surface of the lower electrode. Thus, when external light is incident on the lower electrode, the light can be diffusely reflected on the surface of the lower electrode, thereby improving visibility. Note that in the case of a transmissive liquid crystal display device, the above-mentioned unevenness may not be provided.

[0753] <5-3. Touch Sensor>

[0754] Next, refer to Figure 50 This section provides detailed information about the touch sensor 2595. Figure 50 It is along Figure 48B The cross-sectional view shown is cut off by the dotted line X3-X4.

[0755] The touch sensor 2595 includes: electrodes 2591 and 2592 arranged in an interleaved shape on a substrate 2590; an insulating layer 2593 covering the electrodes 2591 and 2592; and wiring 2594 that electrically connects adjacent electrodes 2591.

[0756] Electrodes 2591 and 2592 are formed using a transparent conductive material. Transparent conductive materials can include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and gallium-added zinc oxide. Alternatively, a graphene-containing film can be used. A graphene-containing film can be formed, for example, by reducing a film containing graphene oxide. Examples of reduction methods include heating.

[0757] For example, a transparent conductive material is formed on a substrate 2590 by sputtering, and then unwanted parts are removed by various patterning techniques such as photolithography, thereby forming electrodes 2591 and 2592.

[0758] In addition, as materials used for the insulating layer 2593, in addition to resins such as acrylic resin, epoxy resin, and resins with siloxane bonds, inorganic insulating materials such as silicon oxide, silicon oxynitride, and aluminum oxide can also be used.

[0759] Furthermore, the opening reaching electrode 2591 is provided in insulating layer 2593, and wiring 2594 is electrically connected to adjacent electrode 2591. Since a light-transmitting conductive material can increase the aperture ratio of the touch panel, it can be used for wiring 2594. In addition, since a material with higher conductivity than electrode 2591 and electrode 2592 can reduce resistance, it can also be used for wiring 2594.

[0760] An electrode 2592 extends in one direction, and multiple electrodes 2592 are arranged in a stripe pattern. In addition, wiring 2594 intersects with the electrode 2592.

[0761] An adjacent electrode 2591 is provided sandwiched between an electrode 2592. In addition, wiring 2594 electrically connects the adjacent electrode 2591.

[0762] In addition, the multiple electrodes 2591 do not necessarily need to be arranged in a direction orthogonal to one electrode 2592, but can also be arranged to form an angle greater than 0° and less than 90° by intersecting one electrode 2592.

[0763] Furthermore, a wiring 2598 is electrically connected to electrode 2591 or electrode 2592. Additionally, a portion of wiring 2598 is used as a terminal. Wiring 2598 can be made of metallic materials such as aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molybdenum, iron, cobalt, copper, or palladium, or alloys containing any of the aforementioned metallic materials.

[0764] Alternatively, the touch sensor 2595 can be protected by providing an insulating layer that covers the insulating layer 2593 and the wiring 2594.

[0765] In addition, the connection layer 2599 is electrically connected to the wiring 2598 and the FPC 2509 (2).

[0766] As the connecting layer 2599, anisotropic conductive film (ACF) or anisotropic conductive paste (ACP) can be used.

[0767] <5-4. Touch Panel>

[0768] Next, refer to Figure 51A This section provides detailed information about the Touch Panel 2000. Figure 51A It is along Figure 48A The cross-sectional view shown is cut off by the dotted line X5-X6.

[0769] exist Figure 51A In the touch panel 2000 shown, Figure 48A The described display device 2501 and Figure 50 The touch sensor 2595 described is attached together.

[0770] in addition, Figure 51A The touch panel 2000 shown, in addition to Figure 49A In addition to the structure described, it also includes an adhesive layer 2597 and an anti-reflective layer 2569.

[0771] The adhesive layer 2597 is provided in contact with the wiring 2594. Note that the adhesive layer 2597 adheres the substrate 2590 to the substrate 2570 such that the touch sensor 2595 overlaps the display device 2501. Furthermore, the adhesive layer 2597 preferably has light transmittance. Additionally, as the adhesive layer 2597, a thermosetting resin or a UV-curable resin can be used. For example, acrylic resins, urethane resins, epoxy resins, or silicone resins can be used.

[0772] An anti-reflective layer 2569 is disposed at a position overlapping the pixel. For example, a circular polarizer can be used as the anti-reflective layer 2569.

[0773] Next, refer to Figure 51B to and Figure 51A The different structures of the touch panels shown are explained.

[0774] Figure 51B This is a cross-sectional view of the touch panel 2001. Figure 51B The touch panel 2001 shown is Figure 51A The difference between the touch panel 2000 shown is the position of the touch sensor 2595 relative to the display device 2501. The different structures will be described in detail below, while the description of the touch panel 2000 will be used for parts that can use the same structure.

[0775] The color layer 2567 is located below the EL element 2550. Furthermore, Figure 51B The EL element 2550 shown emits light onto the side where the transistor 2502t is located. Consequently, a portion of the light emitted by the EL element 2550 passes through the coloring layer 2567 and... Figure 51B The arrow in the image indicates that the light is emitted to the outside of the light-emitting module 2580.

[0776] In addition, a touch sensor 2595 is disposed on one side of the substrate 2510 of the display device 2501.

[0777] The adhesive layer 2597 is located between the substrate 2510 and the substrate 2590, and attaches the display device 2501 and the touch sensor 2595 together.

[0778] like Figure 51A and Figure 51B As shown, light can be emitted from the light-emitting element by passing through one or both of the substrates 2510 and 2570.

[0779] <5-5. Touch Panel Driving Method>

[0780] Next, refer to Figure 52A and Figure 52B An example of a driving method for a touch panel is provided.

[0781] Figure 52A This is a block diagram illustrating the structure of a mutual capacitance touch sensor. Figure 52A The diagram shows a pulse voltage output circuit 2601 and a current detection circuit 2602. Additionally, in... Figure 52A In the diagram, six wirings (X1 to X6) represent the electrode 2621 to which a pulse voltage is applied, and six wirings (Y1 to Y6) represent the electrode 2622 to which a change in current is detected. Furthermore, Figure 52A The capacitor 2603 is shown as formed by overlapping electrodes 2621 and 2622. Note that the functions of electrodes 2621 and 2622 can be interchanged.

[0782] The pulse voltage output circuit 2601 is used to sequentially apply pulse voltages to the wiring from X1 to X6. By applying pulse voltages to the wiring from X1 to X6, an electric field is generated between electrodes 2621 and 2622 of capacitor 2603. By shielding or otherwise blocking the electric field generated between the electrodes, the mutual capacitance of capacitor 2603 changes. By utilizing this change, the proximity or contact of the detected object can be detected.

[0783] The current detection circuit 2602 is used to detect changes in the current flowing through the wiring from Y1 to Y6 caused by changes in the mutual capacitance of capacitor 2603. In the wiring from Y1 to Y6, if no object is approaching or making contact, the detected current value remains unchanged. However, if the mutual capacitance decreases due to the approach or contact of an object, a decrease in the current value is detected. Furthermore, the current value can be detected using an integrating circuit or similar means.

[0784] then, Figure 52B Show Figure 52A The diagram shows the timing of the input / output waveforms in a mutual capacitance touch sensor. Figure 52B In this process, the detection of objects in each row and column is performed during a frame. Additionally, in... Figure 52B The diagram shows two periods: when no object was detected (not touched) and when an object was detected (touched). Furthermore, regarding the wiring from Y1 to Y6, the waveforms of the voltage values ​​corresponding to the detected current values ​​are shown.

[0785] Pulse voltages are applied sequentially to wirings X1 to X6, and the waveforms of wirings Y1 to Y6 change according to these pulse voltages. When no object is near or in contact with the detector, the waveforms of Y1 to Y6 change according to the voltage changes of wirings X1 to X6. On the other hand, when an object is near or in contact with the detector, the current value decreases, and therefore the waveform of the voltage value also changes.

[0786] Thus, by detecting changes in mutual capacitance, the proximity or contact of the object being detected can be determined.

[0787] <5-6. Sensor Circuit>

[0788] In addition, as a touch sensor, although Figure 52A The diagram shows a passive touch sensor with only a capacitor 2603 at the intersection of the wiring, but an active touch sensor including a transistor and a capacitor can also be used. Figure 53 This illustrates an example of the sensor circuitry included in an active touch sensor.

[0789] Figure 53 The sensor circuit shown includes capacitor 2603, transistor 2611, transistor 2612 and transistor 2613.

[0790] A signal G2 is applied to the gate of transistor 2613. A voltage VRES is applied to one of the source and drain of transistor 2613, and the other of the source and drain of transistor 2613 is electrically connected to one electrode of capacitor 2603 and the gate of transistor 2611. One of the source and drain of transistor 2611 is electrically connected to one of the source and drain of transistor 2612, and a voltage VSS is applied to the other of the source and drain of transistor 2611. A signal G1 is applied to the gate of transistor 2612, and the other of the source and drain of transistor 2612 is electrically connected to wiring ML. A voltage VSS is applied to the other electrode of capacitor 2603.

[0791] Next, for Figure 53 The operation of the sensor circuit shown will be explained. First, by applying a potential as signal G2 to turn on transistor 2613, a potential corresponding to voltage VRES is applied to node n, which is connected to the gate of transistor 2611. Next, by applying a potential as signal G2 to turn off transistor 2613, the potential of node n is maintained.

[0792] Then, as the detected object, such as a finger, approaches or touches it, the mutual capacitance of capacitor 2603 changes, and the potential of node n changes from VRES accordingly.

[0793] During readout, a potential is applied as signal G1 to turn on transistor 2612. The current flowing through transistor 2611, i.e., the current flowing through wiring ML, varies according to the potential of node n. By detecting this current, the proximity or contact of the object being detected can be determined.

[0794] Any of the transistors shown in the preceding embodiments can be used as transistors 2611, 2612, and 2613. In particular, by using any of the transistors shown in the preceding embodiments as transistor 2613, the potential of node n can be maintained for a long period of time, thereby reducing the frequency of resupplying VRES to node n (refresh operation).

[0795] The structure shown in this embodiment can be implemented by appropriately combining it with the structure shown in any other embodiment.

[0796] Implementation Method 6

[0797] In this embodiment, refer to Figure 54A and Figure 54B , Figure 55A and Figure 55B , Figures 56A to 56E and Figures 57A to 57E A display device including a semiconductor device according to one aspect of the present invention and a driving method for the display device will be described.

[0798] The display device of one embodiment of the present invention may also include an information processing unit, a computing unit, a storage unit, a display unit, and an input unit, etc.

[0799] In one aspect of the present invention, when a display device continuously displays the same image (static image), power consumption can be reduced by decreasing the number of times signals are written to the same image (also called "refreshing"). Note that the frequency of refreshing is also called the refresh rate (also called the scan frequency or vertical synchronization frequency). The following describes a display device that reduces eye fatigue by reducing the refresh rate.

[0800] Eye fatigue is broadly categorized into two types: nerve fatigue and muscle fatigue. Nerve fatigue is caused by prolonged, continuous viewing of the luminous or flickering images on a display device. This is because the brightness stimulates the retina, optic nerve, and brain, leading to fatigue. Muscle fatigue is caused by overuse of the ciliary muscle, which is used to adjust focus.

[0801] Figure 54A This is a schematic diagram illustrating the display of an existing display device. For example... Figure 54A As shown, in existing display devices, the image is rewritten 60 times per second. Prolonged continuous viewing of such images could likely strain the user's retina, optic nerve, and brain, causing eye fatigue.

[0802] In one aspect of the display device of the present invention, an oxide semiconductor transistor, such as a CAAC-OS transistor, is applied to the pixel portion of the display device. The off-state current of this transistor is extremely small. Therefore, the brightness of the display device can be maintained even when the refresh rate of the display device is reduced.

[0803] In other words, such as Figure 54B As shown, the image can be rewritten, for example, every 5 seconds. This allows the same image to be displayed for as long as possible, reducing the flicker perceived by the user. This, in turn, reduces stimulation to the user's retina, optic nerve, and brain, thus alleviating nerve fatigue.

[0804] In addition, such as Figure 55A As shown, when a pixel is large (e.g., at a resolution below 150 ppi), the text displayed on the screen becomes blurry. When viewing blurry text on a screen for extended periods, the ciliary muscles constantly move to adjust the focus, which can strain the eyes.

[0805] On the contrary, such as Figure 55B As shown, in a display device according to one aspect of the present invention, because the size of a single pixel is small, a high-definition image can be displayed, thus enabling the display of detailed and smooth images. Consequently, the ciliary muscle's focus adjustment of the text becomes easier, reducing user muscle fatigue. By setting the resolution of the display device to 150 ppi or more, preferably 200 ppi or more, and more preferably 300 ppi or more, user muscle fatigue can be effectively reduced.

[0806] Note that methods for quantitatively measuring eye fatigue are under discussion. For example, critical flicker (fusion) frequency (CFF) is known as an indicator of nerve fatigue. Focusing time and near distance are known indicators of muscle fatigue.

[0807] In addition, known methods for evaluating eye fatigue include brain wave measurement, thermography, blink counting, tear volume measurement, pupillary contraction response speed measurement, and questionnaires used to investigate subjective symptoms.

[0808] For example, by employing the various methods described above, a driving method for a display device according to one aspect of the present invention can be evaluated.

[0809] <6. Driving methods for display devices>

[0810] Here, refer to Figures 56A to 56E A driving method for a display device according to one aspect of the present invention will be described.

[0811] [Example of image information display]

[0812] Below is an example of moving and displaying an image containing two different image data.

[0813] Figure 56A An example is shown where a window 451 is displayed on the display unit 450, and a first image 452a is displayed within the window 451.

[0814] At this point, it is preferable to display at the first refresh rate. The first refresh rate can be set to 1.16 × 10⁻⁶. -5 Hz (refreshed approximately once a day) or higher but less than 1Hz, or 2.78×10 -4 Hz (refreshed approximately every hour) or higher and below 0.5Hz, or 1.67×10 -2 Hz (refreshed approximately once per hour) or higher and below 0.1Hz.

[0815] In this way, by setting the first refresh rate to a very small value, the frequency of screen rewriting is reduced, thereby achieving a virtually flicker-free display and more effectively reducing eye strain for users.

[0816] Window 451 can be displayed, for example, by executing image display application soft...

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: Forming a first oxide semiconductor film; A gate insulating film is formed on the first oxide semiconductor film; and A gate electrode is formed on and in contact with the gate insulating film. in, The gate electrode includes a second oxide semiconductor film. In the steps of forming the first oxide semiconductor film and the second oxide semiconductor film, an oxygen gas mixed with an inert gas is introduced into the deposition chamber. In the step of forming the second oxide semiconductor film, the proportion of oxygen gas in the total deposition gas is more than 50% and less than 100%. After the step of forming the second oxide semiconductor film, a heat treatment is performed, and The proportion of oxygen gas in the step of forming the first oxide semiconductor film is lower than the proportion of oxygen gas in the step of forming the second oxide semiconductor film.

2. A method for manufacturing a semiconductor device, comprising the following steps: Forming a first oxide semiconductor film; A gate insulating film is formed on the first oxide semiconductor film; and A gate electrode is formed on and in contact with the gate insulating film. in, The gate electrode includes a second oxide semiconductor film. In the steps of forming the first oxide semiconductor film and the second oxide semiconductor film, an oxygen gas mixed with an inert gas is introduced into the deposition chamber. In the step of forming the second oxide semiconductor film, the proportion of oxygen gas in the total deposition gas is more than 50% and less than 100%. After the step of forming the second oxide semiconductor film, a first heat treatment is performed. The first heat treatment is performed at a temperature above 150°C and below 350°C, and The proportion of oxygen gas in the step of forming the first oxide semiconductor film is lower than the proportion of oxygen gas in the step of forming the second oxide semiconductor film.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, in, The first oxide semiconductor film comprises In, Ga, and Zn, and The second oxide semiconductor film contains In, Ga and Zn.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, in, A channel region is formed in the first oxide semiconductor film.

5. The method for manufacturing a semiconductor device according to claim 1 or 2, further comprising the following steps: An insulating film is formed on the gate electrode.

6. The method for manufacturing a semiconductor device according to claim 5, in, The insulating film contains at least one of hydrogen and nitrogen.

Images