Driver circuit, related integrated circuit, electronic converter and method

Abstract

The present disclosure relates to a driver circuit, a related integrated circuit, an electronic converter, and a method. The driver circuit includes a comparator that generates a first control signal indicative of when a resonant current changes sign. A first ramp generator circuit outputs a first ramp signal, and a comparison circuit determines whether the first ramp signal has reached a reference threshold. The driver circuit drives a half-bridge via a drive signal during successive first and second switching half-cycles, and each switching half-cycle ends when the comparison circuit indicates that the first ramp signal has reached the reference threshold. A control circuit generates control signals indicative of a first interval and a second interval in each of the first and second switching half-cycles. A correction circuit modifies the first ramp signal to have a first gradient value during the first interval and a second gradient value during the second interval. Alternatively, the correction circuit modifies the reference threshold by adding a second ramp signal to an initial threshold.

Description

Technical Field

[0001] Embodiments of the present specification relate to a control device for a switched resonant converter. Background Art

[0002] Resonant converters are a widespread type of switched converter, characterized by the presence of a resonant circuit that plays an active role in determining the input-output power flow. Considering the most common implementations, in these converters, a full bridge (or half bridge) powered by a DC voltage and composed of four (or two) power switches (usually power field-effect transistors FETs, such as metal-oxide-semiconductor field-effect transistors MOSFETs) generates a voltage square wave that is applied to the resonant circuit, the frequency of which is tuned to a frequency close to the fundamental frequency of the above-mentioned square wave. Thus, due to its selective characteristics, the resonant circuit mainly responds to the fundamental wave component while ignoring the higher harmonics of the square wave.

[0003] As a result, the circulating power can be modulated by changing the frequency of the square wave while keeping the duty cycle constant at 50%. Additionally, depending on the resonant circuit configuration, the current and / or voltage associated with the power flow has a sinusoidal or piecewise-sinusoidal shape.

[0004] These voltages are rectified and filtered in order to provide DC power to the load. In offline applications, in order to comply with safety regulations, the rectification and filtering system powering the load is usually coupled to the resonant circuit through a transformer that provides the isolation between the source and the load required by the above-mentioned regulations. As with all isolated network converters, in this case, it is also necessary to distinguish between the primary side connected to the input source (related to the primary winding of the transformer) and the secondary side powering the load through the rectification and filtering system (related to the (multiple) secondary windings of the transformer).

[0005] Currently, among many types of resonant converters, the so-called LLC resonant converter is widely used, especially in its half-bridge version. The name LLC comes from the use of two inductors (L) and a capacitor (C) in the resonant circuit.

[0006] Figure 1 An example of an LLC resonant converter 20 is shown. Generally, the electronic converter 20 includes:

[0007] - a positive input terminal 200a and a negative input terminal 200b for receiving a DC input voltage Vin; and

[0008] - a positive output terminal 202a and a negative output terminal 202b for providing a regulated (DC) output voltage Vout or output current Iout.

[0009] For example, the input voltage Vin can be provided by a DC voltage generator 10 such as a battery. However, the input voltage Vin can also be obtained from an AC voltage, for example, by means of a rectifier circuit (such as a bridge rectifier) and an optional filter circuit (such as a capacitor). Conversely, the regulated output voltage Vout or the output current Iout can be used to power a load 30.

[0010] In the example considered, the electronic converter 20 includes a half-bridge that includes two electronic switches SW1 and SW2 (for example, directly) connected in series between the input terminals 200a and 200b, such as FETs, such as n-channel FETs, for example NMOS, where the negative input terminal 200b generally represents a first ground GND1. For example, in the example considered, the drain terminal of transistor SW1 is directly connected to terminal 200a, the source terminal of transistor SW1 is directly connected to the drain terminal of transistor SW2, and the source terminal of transistor SW2 is directly connected to terminal 200b.

[0011] Thus, the half-bridge SW1, SW2 is powered via the input voltage Vin, and the intermediate node between the electronic switches SW1 and SW2 (for example, the drain terminal of transistor SW1) represents the switching node HB.

[0012] In the example considered, the control terminals of the electronic switches SW1 and SW2 (for example, the gate terminals of the corresponding FETs) are driven via a driver circuit 210 that is configured to generate corresponding drive signals HSGD and LSGD for the electronic switches SW1 and SW2.

[0013] Typically, the driver circuit 210 is configured to generate the drive signals HSGD and LSGD to repeat the following four phases for each switching cycle:

[0014] - During a first time interval, the first electronic switch SW1 is closed and the second electronic switch SW2 is opened, thereby connecting the switching node HB to the positive input node 200a, i.e., the input voltage Vin;

[0015] - During a second time interval, the first and second electronic switches SW1 / SW2 are opened;

[0016] - During a third time interval, the first electronic switch SW1 is opened and the second electronic switch SW2 is closed, thereby connecting the switching node HB to the negative input node 200a, such as ground GND1; and

[0017] - During a fourth time interval, the first and second electronic switches SW1 / SW2 are opened.

[0018] In the example considered, the switching node HB between the electronic switches SW1 and SW2 is connected to a (resonant) circuit block.

[0019] Specifically, in the example considered, the circuit includes a transformer T, which includes a primary winding T1 and a center-tapped secondary winding, and the center-tapped secondary winding includes a first secondary winding T2a and a second secondary winding T2b connected in series.

[0020] In the example considered, the primary winding T1 of the transformer T (e.g., directly) is connected between the switching node HB and the negative terminal 200b in series with the capacitor Cr and the first inductor Ls. In addition, the second inductor Lp is connected in parallel with the primary winding T1 (e.g., directly). Thus, in the example considered, the capacitor Cr, the first inductor Ls, and the second inductor Lp are connected in series (thus resulting in the name LLC converter), and the inductor Lp is connected in parallel to the primary winding T1. For example, in Figure 1 it, the first terminal of the capacitor Cr (e.g., directly) is connected to the switching node HB, the second terminal of the capacitor Cr is connected to the first terminal of the primary winding T1 via the inductor Ls (e.g., directly), and the second terminal of the primary winding T1 (e.g., directly) is connected to the terminal 200b.

[0021] In any case, in an actual transformer T, the two windings T1 and T2 are not perfectly coupled, and the transformer T also includes leakage inductance and magnetizing inductance. Basically, this leakage inductance can be modeled by an inductor connected in series with the primary winding T1. In contrast, the magnetizing inductance of the transformer T (for modeling the magnetic flux) can be modeled using an inductor connected in parallel with the primary winding T1. Thus, the inductor Ls can be included in the leakage inductance of the transformer T, can be implemented by an inductor connected in series with the primary winding T1, or can be generated by both the leakage inductance of the transformer T and such an inductor. Similarly, the inductor Lp can be included in the magnetizing inductance of the transformer T, can be implemented by an inductor connected in parallel with the primary winding T1, or can be generated by both the magnetizing inductance of the transformer T and such an inductor.

[0022] As previously mentioned, in Figure 1A center-tap arrangement is used on the secondary side, i.e., the secondary winding includes a first terminal, a second terminal, and a center-tap terminal. Specifically, in the example considered, the center-tap terminal is (e.g., directly) connected to one of the output terminals 202a / 202b, and the first and second terminals of the secondary winding T2 are (e.g., directly) connected to the other output terminal 202a / 202b via respective diodes Da and Db. For example, in the example considered, the center-tap terminal is (e.g., directly) connected to the output terminal 202b, and the first and second terminals of the secondary winding T2 are (e.g., directly) connected to the anodes of the respective diodes Da and Db, and the cathodes of the diodes Da and Db are (e.g., directly) connected to the terminal 202a. Thus, due to the rectifying function of the diodes Da and Db, the terminal 202a corresponds to the positive output terminal and the terminal 202b corresponds to the negative output terminal, which typically corresponds to the second ground GND2. However, by reversing the orientation of the diodes Da and Db, the terminal 202b will correspond to the positive output terminal.

[0023] Generally, other rectifiers (instead of the diodes Da and Db) can also be used between the secondary winding T2 and the output terminals 202a and 202b. For example, the first and second terminals of the secondary winding T2 (and thus may not include the center-tap terminal) can be connected to the output terminals 202a and 202b via a bridge rectifier.

[0024] Generally, the electronic converter 20 can also include an output filter connected between the rectifier and the output terminals 202a and 202b. For example, in Figure 1 a capacitor Cout is (e.g., directly) connected between the output terminals 202a and 202b.

[0025] Compared with traditional switching converters (non-resonant converters, usually pulse-width modulation PWM controlled), resonant converters have obvious advantages, such as waveforms without steep edges, low switching losses of power switches due to their "soft" switching, high conversion efficiency (usually up to >95%), the ability to operate at high frequencies, low EMI (electromagnetic interference) generation, and / or high power density (i.e., enabling a conversion system capable of handling a considerable power level to be built in a relatively small space).

[0026] Thus, in the example considered, the electronic converter provides a voltage Vout and a current Iout via the output terminals 202a and 202b. Generally, a closed loop (usually implemented by a negative feedback control system) will thus keep the output voltage Vout or the output current Iout of the converter constant when the operating conditions change (e.g., changes in the input voltage Vin and / or the output load 30).

[0027] For example, Figure 2Shows an example of a control circuit for a general half - bridge resonant converter 20.

[0028] As previously described, the half - bridge resonant converter 20 includes a half - bridge that includes two electronic switches connected in series between the input terminals 200a and 200b of the electronic converter 20. In addition, the converter 20 includes a circuit 204 that includes a resonant tank (e.g., capacitor Cr, inductors Ls and Lp, and transformer T), a rectifier circuit (e.g., diodes Da and Db), and an optional filter circuit (e.g., capacitor Cout). Specifically, the circuit 204 is connected on one side to the switch node HB (between the electronic switches SW1 and SW2) and the negative input terminal 200b (or alternatively the positive input terminal 200a) to receive a signal that is substantially a square wave, and on the other side to the output terminals 202a and 202b to provide an output voltage Vout or an output current Iout.

[0029] To implement closed - loop control, the converter 20 includes a sensor 212 configured to monitor the output voltage Vout (for a voltage source) or the output current Iout (for a current source). For example, in Figure 2 , the converter 20 is configured to provide a stable voltage. Thus, the sensor 212 can be a voltage sensor configured to monitor the output voltage Vout. For example, in Figure 2 a voltage divider including two resistors R1 and R2 connected between the terminals 202a and 202b is used, so that the voltage sensor provides a measurement signal proportional to the output voltage Vout.

[0030] The measurement signal (indicating the current Iout or the voltage Vout) provided by the sensor 212 is provided to an error amplifier configured to generate an error signal Er. For example, the error amplifier can compare the measurement signal with a reference signal (such as a reference voltage Vref) and generate an error signal Er indicating the difference between the measurement signal and the reference voltage Vref.

[0031] In the example considered, then, the error signal Er is provided to the driver circuit 210 in order to modify the given control quantity x, where the energy transferred during each switching period depends substantially on the control quantity x. Typically, the error signal Er can be provided directly to the driver circuit 210 or, for example, indirectly via an optocoupler 218 (which is typically used in the case of isolating an electronic converter) to the driver circuit 210. Additionally, the error signal Er provided to the driver circuit 210 or a signal indicative of the error signal Er (e.g., proportional to the error signal Er) (e.g., in the case where an optocoupler 218 is also used) can be any suitable control signal, such as a voltage Vc or a current Ic. Without loss of generality, it will be assumed hereinafter that the quantity x is modified in accordance with the control current Ic. Additionally, although the current Ic is mainly indicated as representing the output voltage Vout of the converter, the current Ic can also represent the output current Iout.

[0032] Typically, the error amplifier is implemented using an operational amplifier 214 which receives at its input a measurement signal (e.g., at the inverting / negative input) and a reference signal (e.g., at the non-inverting / positive input). Additionally, the operational amplifier 214 is associated with a feedback network 216 connected between the output of the operational amplifier and one of the input terminals (typically the inverting input terminal). For example, the feedback network 216 can include components for implementing the error amplifier as a regulator having proportional (P) components (e.g., via resistors) and / or integral (I) components (e.g., via capacitors). Thus, typically, the feedback network 216 implements the filter of the error amplifier. For example, such a filter 216 may be useful in order to select the appropriate frequency response of the error amplifier, e.g., in order to ensure:

[0033] - a stable control loop (i.e., when the operating conditions of the converter are perturbed, once the transients caused by the perturbation subside, the output parameters Vout / Iout tend to return to a constant steady state;

[0034] - good regulation (i.e., the new constant to which the output parameters Vout / Iout recover after a perturbation is very close to the constant before the perturbation); and

[0035] - good dynamic performance (i.e., during the transient period after a perturbation occurs, the output parameters Vout / Iout do not deviate excessively from the desired value and the transient itself is short).

[0036] The above control objectives can be expressed in terms of some characteristic quantities of the transfer function of the control loop, such as bandwidth, phase margin, dc gain. For example, in a DC-DC converter, these objectives can be achieved by modifying the feedback network 216 in order to:

[0037] - modify the frequency response of the error amplifier,

[0038] - Modify its gain, and

[0039] - Conveniently place the poles and zeros of its transfer function (frequency compensation).

[0040] As previously mentioned, this is typically achieved by using a passive feedback network 216 including one or more resistors and / or one or more capacitors of appropriate values.

[0041] However, in order to determine the frequency compensation required to obtain the desired characteristics of the transfer function of the control loop, it is desirable to know both the modulator gain (i.e., the gain of the system that converts the control current Ic into the control quantity x) and the frequency response of the converter itself to changes in the control quantity x.

[0042] The inventors have observed that the modulator gain generally does not depend on the switching frequency (at least within the relevant frequency range) and is fixed inside the driver circuit 210. In addition, although DC-DC converters are strongly nonlinear systems (due to the switching action), under appropriate approximations and certain assumptions, their frequency response can be described and represented by a transfer function characterized by gain, zeros, and poles. This transfer function essentially depends on the topology of the converter (i.e., the mutual configuration of the elements that handle power), depends on its operating mode (i.e., whether there is a continuous current loop in the magnetic component during the switching cycle (continuous current mode CCM) or not (discontinuous current mode DCM)), and depends on the control quantity x controlled by the control loop.

[0043] For example, in a resonant converter, the control quantity x used to control the converter is typically directly the switching frequency of the square wave applied to the resonant circuit (direct frequency control DFC).

[0044] However, the inventors have observed that this simple control method suffers from dynamic characteristics characterized by a large variation in DC gain and the number of poles varying between one and three and having a very movable position depending on the operating point. In addition, the energy transfer depends to a large extent on the input voltage Vin (e.g., resulting in poor audio sensitivity), so the control loop must significantly change the operating frequency to compensate for the above changes, which are difficult to avoid in converters operating from the power line (due to the variation of the rectified mains voltage, the input voltage Vin may vary), which implies a need for a high open-loop gain in the relevant frequency range.

[0045] All these characteristics make it practically impossible to obtain optimized dynamic performance under all operating conditions and require a considerable trade-off between stability, dynamic performance, and input ripple rejection.

[0046] The inventors have observed that possible remedies for these drawbacks include using a driver circuit 210 that includes a control module 220 implementing a control technique known as "time-shift control" (TSC). The literature teaches that the dynamics of a TSC-controlled converter are those of a low-Q second-order system, i.e., it is characterized by a pair of real poles that are completely separated from each other (by at least a factor of 5). In practice, this means that excellent dynamic performance can be achieved with little trade-off with other constraints and a greatly reduced design effort.

[0047] For example, U.S. Patent No. 8,773,872 B2 discloses two TSC implementations.

[0048] In the first implementation (as shown in Figure 4 US 8,773,872 B2), TSC is implemented as follows:

[0049] 1. When the voltage applied to the resonant tank and the current flowing through the resonant tank have the same sign, during a time interval of a switching period, the capacitor is alternately charged and discharged with a constant current between two voltage levels.

[0050] 2. When the signs of the tank voltage and current are opposite, during a time interval of a switching period, the capacitor voltage is kept constant.

[0051] 3. When the capacitor voltage reaches any of the above voltage levels, the half-bridge is toggled and the charging / discharging phase of the capacitor is reversed.

[0052] In the second implementation (as shown in Figure 6 or Figure 9 US 8,773,872 B2), TSC is implemented as follows:

[0053] 1. When the voltage applied to the resonant tank and the current flowing through the resonant tank have the same sign, during a time interval of a switching half-period, the capacitor is charged with a constant current until a voltage level is reached.

[0054] 2. When the signs of the tank voltage and current are opposite, during a time interval of a switching half-period, the capacitor voltage is kept constant.

[0055] 3. When the capacitor voltage reaches the above voltage level, the half-bridge is toggled and the capacitor is reset (usually to zero).

[0056] In both of these implementations, the constant current used to charge the capacitor (and also discharge the capacitor in the first implementation) is proportional to the control current Ic. Additionally, in both of these implementations, the control module 220 also monitors the current Is flowing into the resonant tank from the half-bridge SW1 / SW2. For example, as previously described, the resonant tank can be connected between the switch node HB and the negative terminal 200b (or alternatively the positive terminal 200a). In this case, the current sensor 222 can be connected in series with the resonant tank. For example, the current sensor 222 can be a shunt resistor (e.g., connected between the resonant tank and the terminal 200b, e.g., between the primary winding T1 of the transformer T and the terminal 200b), which provides a voltage Vs indicative of the current flowing through the resonant tank (e.g., proportional to this current). Specifically, US 8,773,872 B2 uses a zero-current comparator in order to detect the sign of the current Is in the resonant tank. For example, in US 8,773,872 B2, a comparator referred to as zero / ground (reference symbol CO1 in document US 8,773,872 B2) is used, which receives the voltage Vs proportional to the instantaneous tank current.

[0057] The inventors have observed that these implementations tend to make the resonant current Is asymmetric at light (small) loads. Specifically, the inventors have observed that this asymmetry may stem from the input voltage offset of the zero-current comparator and / or perturbations in the signal, resulting in a duty cycle of the square wave at node HB that is different from the ideal 50%. This is due to a cumulative effect: any perturbation or asymmetry at the zero-current moment in one cycle will propagate in subsequent cycles and maintain its positive sign propagation in a kind of "positive feedback loop". If the equivalent gain of this positive loop exceeds 1 (unity), then the loop will become unstable and cause the duty cycle to deviate from the ideal 50%. The worst consequence is uneven secondary current distribution, and for example, uneven thermal rise in the secondary rectifiers (D1 and D2). Another harmful effect is an increase in the output voltage ripple.

[0058] The operating conditions under which this instability occurs depend on the characteristics of the resonant tank, e.g., depend on the values of Cr, Ls, Lp of the LLC converter and the turns ratio of the transformer (in Figure 1is represented as a: 1: 1). For example, the inventors have observed that such instability typically occurs under very light loads (i.e., when the current sensing signal Vs is very small and the offset of the zero-current comparator has a significant effect). However, in such cases, although not understood, due to the small current Is, there are usually no significant practical consequences. On the contrary, in a certain electronic converter, this may occur even under relatively high loads (e.g., half load), and in such cases, unequal thermal stresses may affect the reliability of the system. Also, the increased output voltage ripple may exceed the maximum specified value. SUMMARY OF THE INVENTION

[0059] In view of the foregoing, an object of various embodiments is thus to provide a TSC control device that is insensitive to the input voltage offset of a zero-current comparator and / or to perturbations that tend to change the duty cycle of the generated square wave from 50%. This allows for obtaining a more symmetric slot current and then, for example, a more equal secondary current distribution among rectifier diodes, so that they are subject to the same thermal stress.

[0060] According to one or more embodiments, one or more of the above objects are achieved by a driver circuit for a resonant converter having unique elements specifically set forth in the appended claims. Further, embodiments relate to related integrated circuits, electronic converters, and methods.

[0061] The claims form part of the technical teaching provided in the description herein.

[0062] As previously mentioned, various embodiments of the present disclosure relate to a driver circuit for a resonant converter. For example, such a resonant converter is typically configured to generate an output voltage or output current at two output terminals based on the input voltage applied to a positive input terminal and a negative input terminal. Specifically, in various embodiments, the resonant converter may include at least one half-bridge including a high-side electronic switch and a low-side electronic switch connected in series between the positive input terminal and the negative input terminal, where the intermediate node between the high-side electronic switch and the low-side electronic switch represents the switching node. A resonant tank, a rectifier, and a filter circuit may be connected between the switching node and the two output terminals of the converter. For example, the resonant converter may be an LLC resonant converter as previously described.

[0063] In various embodiments, the driver circuit includes terminals for interacting with an electronic converter. For example, a first terminal and a second terminal may be connected to the control terminals of a high-side electronic switch and a low-side electronic switch, respectively, to drive a half-bridge via respective drive signals. A third terminal may be connected to a current sensor to receive a signal proportional to the resonant current flowing from the switching node to the resonant tank, rectifier, and filter circuits. A fourth terminal may be connected to a feedback circuit to receive a feedback signal determined based on the output voltage or output current.

[0064] In various embodiments, the driver circuit includes an analog zero-current comparator configured to generate a first control signal indicating when the resonant current changes sign based on the signal received at the third terminal.

[0065] In various embodiments, the driver circuit further includes a first ramp generator circuit configured to provide a first ramp signal at an output and a comparator circuit configured to determine whether the first ramp signal reaches at least one reference threshold.

[0066] According to various embodiments of the present disclosure, the driver circuit may periodically drive a high-side electronic switch and a low-side electronic switch via drive signals during successive first and second switching half-cycles, where each of the first and second switching half-cycles ends when the comparator circuit indicates that the first ramp signal has reached a corresponding reference threshold. Specifically, once the first switching half-cycle begins, the driver circuit immediately turns off the low-side electronic switch and, after a delay, turns on the high-side electronic switch, and once the second switching half-cycle begins, the driver circuit immediately turns off the high-side electronic switch and, after a delay, turns on the low-side electronic switch.

[0067] For example, to determine the first and second switching half-cycles, during one of the first and second switching half-cycles, the first ramp generator circuit may be configured to increase the first ramp signal, and the comparator circuit may be configured to determine whether the first ramp signal reaches an upper reference threshold, and during the other of the first and second switching half-cycles, the first ramp generator circuit may be configured to decrease the first ramp signal, and the comparator circuit may be configured to determine whether the first ramp signal reaches a lower reference threshold.

[0068] Alternatively, during each switching half-cycle of the first switching half-cycle and the second switching half-cycle, the first ramp generator circuit may be configured to increase the first ramp signal, and the comparison circuit may be configured to determine whether the first ramp signal reaches an upper reference threshold, wherein when the first ramp signal reaches the upper reference threshold, the first ramp signal is reset. In a complementary manner, during each switching half-cycle of the first switching half-cycle and the second switching half-cycle, the first ramp generator circuit may be configured to decrease the first ramp signal, and the comparison circuit may be configured to determine whether the first ramp signal reaches a lower reference threshold, wherein when the first ramp signal reaches the lower reference threshold, the first ramp signal is reset.

[0069] Specifically, in various embodiments, the driver circuit includes a control circuit and a correction circuit.

[0070] In various embodiments, the control circuit is configured to generate one or more control signals in each of the first switching half-cycle and the second switching half-cycle, the one or more control signals indicating that the first interval starts at the moment when the corresponding half-cycle starts and ends at the moment when the first control signal indicates that the resonant current has changed sign, and the second interval starts from the moment when the first control signal indicates that the resonant current has changed sign and the moment when the comparison circuit indicates that the first ramp signal has reached the corresponding reference threshold.

[0071] In various embodiments, the correction circuit is configured to modify the first ramp signal provided at the input of the comparison circuit, such that the first ramp signal has a first gradient value during the first interval and a second gradient value during the second interval, the first gradient value being a non-zero value, and the absolute value of the second gradient value being greater than the absolute value of the first gradient value.

[0072] For example, in various embodiments, the first ramp generator circuit includes an integrator circuit configured to generate the first ramp signal by integrating a first signal. In this case, the correction circuit may modify the first ramp signal by adding a second signal to the first signal at the input of the analog integrator circuit. For example, for this purpose, the integrator circuit may include an integration capacitor, the driver circuit may include a first current generator configured to generate the first signal, and the correction circuit may include a second current generator configured to generate the second signal.

[0073] For example, in various embodiments, the first signal may be set to zero during a first interval and to a non-zero value during a second interval, and the second signal may be set to a constant non-zero value during the first and second intervals. Alternatively, the first signal may be set to a non-zero value during the first and second intervals, and the second signal may be set to zero during the first interval and to a constant non-zero value during the second interval. Alternatively, the first signal may be set to zero during the first interval and to a non-zero value during the second interval, and the second signal may be set to a constant non-zero value during the first interval and to zero during the second interval.

[0074] In contrast, in a digital implementation, the first ramp generator circuit may include a digital counter configured to generate a first ramp signal by incrementing a count value by a given step size. In this case, the correction circuit may be configured to modify the first ramp signal by setting the step size to a first step size value during the first interval and to a second step size value during the second interval. Alternatively, the correction circuit may set the clock signal of the digital counter to a first clock signal during the first interval and to a second clock signal during the second interval.

[0075] Instead of modifying the input of the first ramp generator, the correction circuit may also modify the output of the first ramp generator. For example, when the first ramp generator circuit includes an integrator circuit configured to generate a first ramp signal by integrating a first signal, the correction circuit may modify the first ramp signal by adding a second ramp signal to the first ramp signal at the output of the analog integrator circuit. For example, in various embodiments, the first signal is set to zero during the first interval and to a non-zero value during the second interval, and the second ramp signal corresponds to a linear ramp signal during the first and second intervals. Alternatively, the first signal is set to a non-zero value during the first and second intervals, and the second ramp signal corresponds to zero during the first interval and to a linear ramp signal during the second interval.

[0076] Instead of modifying the first ramp signal, the correction circuit may modify one or more reference thresholds of the comparison circuit by adding a second ramp signal to a corresponding initial threshold. For example, in various embodiments, the first ramp generator circuit may again include an integrator circuit configured to generate a first ramp signal by integrating a first signal. In this case, the first signal may be set to zero during the first interval and to a non-zero value during the second interval, and the second ramp signal may correspond to a linear ramp signal during the first and second intervals. Alternatively, the first signal may be set to a non-zero value during the first and second intervals, and the second ramp signal may correspond to zero during the first interval and to a linear ramp signal during the second interval.

[0077] In various embodiments, to adjust the output voltage or output current, at least one reference threshold of the second gradient value or the reference threshold may be determined according to the feedback signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] The features and advantages of the present disclosure will become apparent from the following detailed description of actual embodiments of the present disclosure shown by way of non-limiting examples in the drawings, in which:

[0079] Figure 1 A circuit schematic diagram of an LLC resonant converter according to the known art is shown;

[0080] Figure 2 A block diagram of a resonant converter with TSC regulation of the output voltage according to the known art is shown;

[0081] Figure 3 A first embodiment of a control device for a resonant converter using an enhanced TSC method is shown;

[0082] Figure 4 Shows Figure 3 A first embodiment of the control device of

[0083] Figure 5 Shows Figure 3 A second embodiment of the control device of

[0084] Figure 6 Shows Figure 4 A timing diagram of the voltage involved in the device of

[0085] Figure 7 Shows Figure 5 A timing diagram of the voltage involved in the device of

[0086] Figure 8 Shows Figure 4 An embodiment of the control device of

[0087] Figure 9 Shows Figure 5 An embodiment of the control device of

[0088] Figure 10 A second embodiment of a control device for a resonant converter using an enhanced TSC method is shown;

[0089] Figure 11 A third embodiment of a control device for a resonant converter using an enhanced TSC method is shown;

[0090] Figure 12 And Figure 13 Shows Figure 10Digital implementation of the control device;

[0091] Figure 14 Shows an example of the generation of a current control signal proportional to the input voltage of the converter;

[0092] Figure 15 Shows a fourth embodiment of a control device for a resonant converter using an enhanced TSC method;

[0093] Figure 16 Shows Figure 15 A timing diagram of the voltages involved in the device;

[0094] Figure 17 Shows a fifth embodiment of a control device for a resonant converter using an enhanced TSC method;

[0095] Figure 18 Shows Figure 17 A timing diagram of the voltages involved in the device;

[0096] Figure 19 Shows a sixth embodiment of a control device for a resonant converter using an enhanced TSC method;

[0097] Figure 20 Shows Figure 19 A timing diagram of the voltages involved in the device;

[0098] Figure 21 Shows another embodiment of the control device, which is Figure 8 A modification of the control device shown;

[0099] Figure 22 Shows another embodiment of the control device, which is Figure 9 A modification of the control device shown;

[0100] Figure 23 Shows the generation of a reference voltage that can be utilized by the Figure 21 Shown control device;

[0101] Figure 24 Shows the generation of a reference voltage that can be utilized by the Figure 22 Shown control device; and

[0102] Figure 25 Shows Figure 23 And Figure 24 A timing diagram of the voltages involved in the voltage generator circuit shown. Detailed Description

[0103] In the following description, various specific details are set forth in order to provide a thorough understanding of the embodiments. The embodiments may be provided without one or more of the specific details or in other ways, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments are not obscured.

[0104] References to "an embodiment" or "one embodiment" in the context of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear in various aspects of this specification do not necessarily refer to the same embodiment. Moreover, in one or more embodiments, the particular configurations, structures, or characteristics may be combined in any suitable manner.

[0105] The references used herein are provided for convenience only and thus do not delimit the scope of protection or the scope of the embodiments.

[0106] In the following description Figures 3 to 20 of Figures 1 to 2 the components, elements, or assemblies described have been represented by the same reference numerals as previously used in these figures. The descriptions of these elements have been made and will not be repeated hereinafter so as not to burden this detailed description.

[0107] Figure 3 A schematic circuit diagram of a control device 210a for a resonant converter according to a first embodiment of the present disclosure is shown.

[0108] For example, such a control device 210a can be used to control the operation of an (LLC) electronic converter as shown in Figure 1 and Figure 2 and the corresponding description applies generally.

[0109] Thus, also in the embodiments considered, the driver circuit 210a receives a feedback signal determined according to the output voltage Vout or the output current Iout, such as the current Ic. For example, in various embodiments, the control signal Ic is determined via a negative feedback control loop of the output voltage (see the description in Figure 2 ). For example, when the driver circuit 210a is implemented in an integrated circuit, the driver circuit 210a can receive the feedback signal Ic via a pin of the integrated circuit.

[0110] Specifically, in the embodiments considered, the control current Ic is connected to an optional input stage 2100 that essentially implements a power amplifier.

[0111] For example, as shown in Figure 8As shown, the input stage can be implemented using operational amplifier OA1 and bipolar transistor Q1 (such as an npn bipolar transistor). Specifically, in the embodiment under consideration, the control current Ic is connected to the first input terminal (e.g., the inverting terminal) of operational amplifier OA1, where operational amplifier OA1 receives the reference voltage Vref at the second input terminal (e.g., the non-inverting terminal) of operational amplifier OA1. The output of operational amplifier OA1 is connected to the base terminal of bipolar transistor Q1, and the emitter terminal of bipolar transistor Q1 is connected to the first input terminal (e.g., the inverting terminal) of operational amplifier OA1. Thus, the output of the input stage 2100 (e.g., the collector terminal of bipolar transistor Q1) provides the current Ic.

[0112] In Figure 3 the embodiment shown, the driver circuit includes:

[0113] - an integrating circuit 2300 configured to generate an integration signal INT proportional to the integral of the feedback signal Ic over a given time period; and

[0114] - a control circuit 2106 configured to control the operation of the integrating circuit 2300 via one or more control signals CTR1 based on the measurement signal Vs (proportional to the resonant current Is) and the integration signal INT.

[0115] In addition, the control circuit 2106 is configured to generate drive signals HSGD and LSGD for the high-side switch SW1 and the low-side switch SW2, respectively, based on the measurement signal Vs and the integration signal INT.

[0116] For example, in Figure 3 it, the integrating circuit 2300 includes an analog integrator that includes a capacitor C T and a current generator 2302 configured to supply a current I1 to the capacitor C T where the current I1 is proportional to the feedback signal Ic. In various embodiments, with respect to the integrated circuit including the driver circuit 210a, the capacitor C T can be external. Thus, the node N1 can be connected to a pin of such an integrated circuit. Thus, in the embodiment under consideration, the integration signal INT corresponds to the voltage V T at the capacitor C CT .

[0117] Figure 4Shows a first embodiment of the analog integration circuit 2300. Specifically, in the considered embodiment, the driver circuit 210a includes a charging circuit / current generator 2102 that supplies a current k·Ic to node N1 and a discharging circuit / current generator 2104 that supplies a current -k·Ic to node N1, where the charging circuit 2102 can be disabled / enabled according to the control signal S1, and where the discharging circuit 2104 can be disabled / enabled according to the control signal S2. In the considered embodiment, node N1 is connected to the first terminal of the capacitor C T and the second terminal of the capacitor C T is connected to ground, e.g., GND1.

[0118] Thus, in the considered embodiment, the charging circuit 2102 and the discharging circuit 2104 substantially implement a current generator 2302 that is configured to supply a current I1 to the capacitor C via node N1 T and the current I1 can be set to:

[0119] - current k·Ic (signal S1 enables the charging circuit and signal S2 disables the discharging circuit)

[0120] - current -k·Ic (signal S1 disables the charging circuit and signal S2 enables the discharging circuit); or

[0121] - zero (signals S1 and S2 disable both the charging circuit 2102 and the discharging circuit 2104).

[0122] Therefore, as Figure 6 shown, essentially, Figure 4 the embodiment shown allows the capacitor C to be charged and discharged during a given half-cycle TA and TB of each switching period Ts, thereby generating a voltage V with a triangular waveform T . CT

[0123] In the considered embodiment, the control circuit 2106 is thus configured to generate the control signals S1 and S2 and the drive signals LSGD and HSGD according to the voltage V T at the capacitor C (node N1) and the measurement signal Vs. CT

[0124] Specifically, in various embodiments, the driver circuit 210a is configured to generate the drive signals HSGD and LSGD to repeat the following four phases for each switching period:

[0125] - During a first time interval Δt1, close the first electronic switch SW1 and open the second electronic switch SW2, thereby connecting the switching node HB to the positive input node 200a, i.e., the input voltage Vin;

[0126] - During a second time interval Δt2, both the first electronic switch and the second electronic switch SW1 / SW2 are opened;

[0127] - During a third time interval Δt3, the first electronic switch SW1 is opened and the second electronic switch SW2 is closed, thereby connecting the switch node HB to the negative input node 200a, e.g., to ground GND1; and

[0128] - During a fourth time interval Δt4, both the first electronic switch and the second electronic switch SW1 / SW2 are opened.

[0129] Thus, in the considered embodiment, the half - period TA corresponds to the second time interval Δt2 and the third time interval Δt3 (TA = Δt2 + Δt3), and the half - period TB corresponds to the fourth time interval Δt4 and the first time interval Δt1 (TB = Δt4 + Δt1).

[0130] Specifically, in various embodiments, the time intervals Δt2 and Δt4 have a constant duration Td. Thus, the driver circuit 210a must determine the durations of the time intervals Δt1 and Δt3. For example, in various embodiments, the control circuit 2106 is configured to determine the moments at which the intervals TA and TB should end, i.e., the moments at which the intervals Δt3 and Δt1 should end.

[0131] For example, in Figure 4 the illustrated embodiment, the control circuit 2106 can be configured to perform the following steps during the time interval TA:

[0132] - Once the interval TA starts, wait for the signal Vs to indicate that the resonant current becomes zero / negative (during this interval, the current generators 2102 and 2104 are disabled);

[0133] - At the moment when the signal Vs indicates that the resonant current becomes negative, enable the current generator 2102 (via the signal S1), thereby charging the capacitor C with the current k·Ic T and

[0134] - Once the integration signal (the voltage V T at the capacitor C CT ) reaches the upper threshold Vp, disable the current generator 2102 (via the signal S1) and end the interval TA, thereby ending the interval Δt3 and starting the interval TB.

[0135] Conversely, the control circuit 2106 can be configured to perform the following steps during the time interval TB:

[0136] - Once the interval TB starts, wait for the signal Vs to indicate that the resonant current becomes zero / positive (during this interval, the current generators 2102 and 2104 are disabled);

[0137] - At the moment when the signal Vs indicates that the resonant current becomes positive, enable the current generator 2104 (via the signal S2), so as to discharge the capacitor C with the current -k·Ic, and T - Once the integration signal (the voltage V at the capacitor C

[0138] ) reaches the lower threshold Vv, disable the current generator 2104 (via the signal S2) and end the interval TB, thereby ending the interval Δt1 and starting the interval TA. T - At the voltage V CT ) reaches the lower threshold Vv, disable the current generator 2104 (via the signal S2) and end the interval TB, thereby ending the interval Δt1 and starting the interval TA.

[0139] In parallel, the control circuit 2106 can:

[0140] - Once the interval TA starts, set the signal LSGD to high after the period Td, thereby closing the low - voltage side switch SW2, and at the end of the interval TA, simultaneously set the signal LSGD to low, thereby disconnecting the low - voltage side switch SW2,

[0141] - Once the interval TB starts, set the signal HSGD to high after the period Td, thereby closing the high - voltage side switch SW1, and at the end of the interval TB, simultaneously set the signal HSGD to low, thereby disconnecting the high - voltage side switch SW1.

[0142] Generally, during the intervals TA and TB, the functions of the current generators 2102 and 2014 can also be reversed, that is, during the interval TB, the current generator 2102 can be enabled and the voltage V at the capacitor C T can be compared with the upper threshold Vp, while during the interval TA, the current generator 2104 can be enabled and the voltage V at the capacitor C CT can be compared with the lower threshold Vv. T - At the voltage V CT is compared with the lower threshold Vv.

[0143] Figure 5 Shows a second embodiment of the analog integration circuit 2300. Specifically, in the considered embodiment, the driver circuit includes a charging circuit / current generator 2102 that provides the current k·Ic to the capacitor C T and a reset circuit 2118, where the charging circuit 2102 can be disabled / enabled according to the control signal S1, and the reset circuit 2118 is configured to reset the charge at the capacitor C T according to the control signal S5.

[0144] Therefore, asFigure 7 As shown, in essence, Figure 5 the illustrated embodiment allows the capacitor C to be reset during each half - cycle TA and TB T and charge the capacitor C T to generate a voltage V with a saw - tooth waveform CT .

[0145] In the considered embodiment, the control circuit 2106 is thus configured to generate the control signals S1 and S5 and the drive signals LSGD and HSGD based on the voltage V T (at node N1) and the measurement signal Vs. CT Specifically, also in this embodiment, the driver circuit 210a can generate the drive signals HSGD and LSGD to repeat the following four phases for each switching cycle:

[0146] - During a first time interval Δt1, close the first electronic switch SW1 and open the second electronic switch SW2, thereby connecting the switching node HB to the positive input node 200a, i.e., the input voltage Vin;

[0147] - During a second time interval Δt2, open both the first electronic switch and the second electronic switch SW1 / SW2;

[0148] - During a third time interval Δt3, open the first electronic switch SW1 and close the second electronic switch SW2, thereby connecting the switching node HB to the negative input node 200a, e.g., ground GND1; and

[0149] - During a fourth time interval Δt4, open both the first electronic switch and the second electronic switch SW1 / SW2.

[0150] - During a fourth time interval Δt4, open both the first electronic switch and the second electronic switch SW1 / SW2.

[0151] Thus, also in this case, the half - cycle TA corresponds to the second time interval Δt2 and the third time interval Δt3 (TA = Δt2 + Δt3), and the half - cycle TB corresponds to the fourth time interval Δt4 and the first time interval Δt1 (TB = Δt4 + Δt1). Specifically, in various embodiments, the time intervals Δt2 and Δt4 can again have a constant duration Td.

[0152] Therefore, the driver circuit 210a must determine the durations of the time intervals Δt1 and Δt3. Specifically, in various embodiments, the control circuit 2106 is configured to determine the moments when the intervals TA and TB should end, i.e., the moments when the intervals Δt3 and Δt1 should end.

[0153] For example, in Figure 5In the illustrated embodiment, the control circuit 2106 may be configured to perform the following steps within a time interval TA:

[0154] - once the interval TA starts, wait for the signal Vs to indicate that the resonant current becomes zero / negative (during this interval the current generator 2102 is disabled);

[0155] - At the moment when the signal Vs indicates that the resonant current becomes negative, the current generator 2102 is enabled (via the signal S1), thereby charging the capacitor C with the current k·Ic. T Charging, and

[0156] - Once the integrated signal (capacitor C T The voltage V CT ) reaches the upper threshold Vp, the current generator 2102 is disabled (via signal S1), the integration signal is reset via the reset circuit 2118 (via signal S5) and the interval TA ends, thereby ending the interval Δt3 and starting the interval TB.

[0157] Instead, the control circuit 2106 may be configured to perform the following steps within the time interval TB:

[0158] - once the interval TB starts, wait for the signal Vs to indicate that the resonant current becomes zero / positive (during this interval the current generator 2102 is disabled);

[0159] - At the moment when the signal Vs indicates that the resonant current becomes positive, the current generator 2102 is enabled (via the signal S1), thereby charging the capacitor C with the current k·Ic. T Charging, and

[0160] - Once the integrated signal (capacitor C T The voltage V CT ) reaches the upper threshold Vp, the current generator 2102 is disabled (via signal S1), the integrated signal is reset by the reset circuit 2118 (via signal S5) and the interval TB ends, thereby ending the interval Δt1 and starting the interval TA.

[0161] In parallel, control circuit 2106 may again:

[0162] - once the interval TA starts, the signal LSGD is set to a high level after the period Td, thereby closing the low-side switch SW2, and at the end of the interval TA, the signal LSGD is simultaneously set to a low level, thereby opening the low-side switch SW2,

[0163] - Once the interval TB starts, the signal HSGD is set high after the period Td, thereby closing the high-side switch SW1, and at the end of the interval TB, the signal HSGD is set low simultaneously, thereby opening the high-side switch SW1.

[0164] Thus, what the embodiments have in common is that the driver circuit 210a includes a current generator that provides a current proportional to the current Ic. Specifically, during each half-cycle of the half-cycles TA or TB, the control circuit 2106 is configured to:

[0165] - Once the corresponding half-cycle starts, wait for the signal Vs to indicate that the resonant current changes sign, i.e., becomes positive or negative;

[0166] - At the moment when the signal Vs indicates that the resonant current has changed sign, enable the current generator 2102, thereby applying a current proportional to the current Ic to the capacitor C T and,

[0167] - Once the integration signal INT (the voltage V T at the capacitor C CT ) reaches a given threshold Vp / Vv, disable the current generator and end the corresponding half-cycle, thereby starting the next half-cycle (TB or TA).

[0168] As Figure 3 shown, in various embodiments, the integration circuit 2300 includes a second current generator 2306. Specifically, this current generator 2306 provides a second current I2 to the capacitor C T

[0169] Specifically, in various embodiments, this current generator 2306 is always enabled, so that

[0170] - During the time period between the moment when the corresponding half-cycle TA / TB starts and the moment when the signal Vs indicates that the resonant current has changed sign, the capacitor C T receives a constant current I2 = Io from the current generator 2306 (where I1 = 0 because the current generator 2302 is disabled); and

[0171] - During the time period between the moment when the signal Vs indicates that the resonant current has changed sign and the moment when the corresponding half-cycle TA / TB ends, the capacitor C T receives a constant current I2 = Io from the current generator 2306 and a current I1 proportional to the current Ic from the current generator 2302.

[0172] Generally, especially when using alternative charging and discharging (see Figure 4 ​In the embodiment), the current I2 has the same sign as the current I1. Thus, as Figure 3 shown, the current generator 2306 can receive the control signal CTR2 to switch the sign of the current I2.

[0173] For example, this is also shown in Figure 4 wherein the current generator 2306 is implemented by a current generator 2114 that provides a current Io and a current generator 2116 that provides a current -Io, and one of the current generators 2114 or 2116 is enabled according to the signal S4. In contrast, in Figure 5 the embodiment shown, the current generator 2306 can be implemented only by the current generator 2114 that provides the current Io.

[0174] For example, Figure 8 shows Figure 4 an embodiment of the driver circuit 210a shown.

[0175] In Figure 8 the embodiment shown, the current Ic (e.g., at the output Q1 of the input stage OA1) is supplied to the input of a first current mirror (Q2, Q3, Q4). For example, in this embodiment, the current mirror is implemented using bipolar transistors (such as pnp bipolar transistors). Thus, in the considered embodiment, the current Ic flows through the input Q2 of the current mirror (implemented, for example, using a first pnp bipolar transistor) and is mirrored to the first output Q3 of the current mirror (implemented, for example, using a second pnp bipolar transistor) and the second output Q4 of the current mirror (implemented, for example, using a second pnp bipolar transistor). Thus, the output Q3 of the current mirror (Q2 - Q3) provides a first current proportional to the current Ic, and the output Q4 of the current mirror (Q2 - Q4) provides a second current proportional to the current Ic.

[0176] Then, this first current provided by the output Q3 of the current mirror (Q2 - Q3) is applied to the input Q5 of a second current mirror (Q5, Q6) (implemented, for example, using bipolar transistors such as npn bipolar transistors). Thus, the output Q3 of the current mirror (Q5 - Q6) provides a current proportional to the first current, which in turn is proportional to the current Ic.

[0177] In the considered embodiment, the output Q4 of the first current mirror (Q2 - Q4) and the output Q6 of the second current mirror (Q5 - Q6) are both connected to the node N1. Specifically, in various embodiments, by determining the size of the current mirror in a suitable manner, the output Q4 of the first current mirror (Q2 - Q4) supplies a current k·Ic to the node N1 and the output Q6 of the second current mirror (Q5 - Q6) supplies a current -k·Ic to the node N1.

[0178] In the embodiment under consideration, the circuit further includes sub - circuits for selectively disabling the current flow from the output Q4 of the first current mirror (Q2 - Q4) and from the output Q6 of the second current mirror (Q5 - Q6) to node N1, respectively.

[0179] For example, in the embodiment under consideration, to selectively disable the current flow from the output Q4 of the first current mirror (Q2 - Q4) to node N1, the first sub - circuit includes:

[0180] - Diode D1, connected between the output Q4 of the first current mirror and node N1;

[0181] - Electronic switch Q8, such as a bipolar transistor, for example an npn bipolar transistor, connected between the output Q4 of the first current mirror and ground, where the electronic switch Q8 is driven according to a binary control signal S1.

[0182] Thus, when the electronic switch Q8 is closed, the current provided by the output Q4 of the first current mirror (Q2 - Q4) flows to ground, and the diode D1 blocks the current flow from node N1.

[0183] Conversely, in the embodiment under consideration, to selectively disable the current flow from the output Q6 of the second current mirror (Q5 - Q6) to node N1, the second sub - circuit includes:

[0184] - Electronic switch Q7, such as a bipolar transistor, for example an npn bipolar transistor, configured to disable the second current mirror (Q5 - Q6), where the electronic switch Q8 is driven according to a binary control signal S2.

[0185] Thus, in the embodiment under consideration, the current mirror Q2 - Q4 and the first sub - circuit D1, Q8 implement a charging circuit 2102 that provides a current k·Ic, where the charging circuit 2102 can be disabled / enabled according to the control signal S1, and the current mirror Q2 - Q3, the current mirror Q5 - Q6 and the second sub - circuit (Q7) implement a discharging circuit 2104 that provides a current - k·Ic, where the discharging circuit 2104 can be disabled / enabled according to the control signal S2.

[0186] As previously described, in the embodiment under consideration, the control circuit 2106 is configured to generate the control signals S1 and S2 ( T (at node N1) voltage V CT and the measurement signal Vs to generate control signals S1 and S2 ( Figure 4 ) or control signals S1 and S5.

[0187] For example, in various embodiments, a signal Vs proportional to the resonant current is provided to a comparator 2108, and the comparator 2108 thus generates a binary control signal S3 indicating whether the signal Vs (resonant current) is positive or negative. For example, in Figure 4 the illustrated embodiment, the circuit 2108 is implemented using a comparator CO1 that receives the voltage Vs at its positive input terminal, has its negative input terminal connected to ground, such as GND1, and the output of the comparator CO1 provides the signal S3. Thus, in the considered embodiment, when the signal Vs (resonant current) is positive, the signal S3 is high.

[0188] In addition, in the considered embodiment, the control circuit 2106 includes a circuit 2110 that is configured to set the binary control signal S4 to a first logic level (e.g., set to low) when the voltage V CT is less than a lower threshold Vv, and to set the binary control signal S4 to a second logic level (e.g., set to high) when the voltage V CT is greater than an upper threshold Vp. Thus, the circuit 2110 substantially implements a comparator with hysteresis that has a corresponding lower threshold Vv and upper threshold Vp.

[0189] For example, in various embodiments, the circuit 2106 includes:

[0190] - A first comparator CO3 that receives the voltage V CT at its negative input terminal and receives the voltage Vv at its positive input terminal;

[0191] - A second comparator CO2 that receives the voltage V CT at its positive input terminal and receives the voltage Vp at its negative input terminal; and

[0192] - A set-reset flip-flop FF1 that receives the signal at the output of the comparator CO3 at its set input terminal and receives the signal at the output of the comparator CO2 at its reset input terminal, where the output (Q) of the flip-flop FF1 provides the signal S4.

[0193] In various embodiments, the signals S3 and S4 are elaborated by a circuit 2112 to generate the signals S1 and S2, as well as drive signals HSGD and LSGD for the switches SW1 and SW2.

[0194] Specifically, in the considered embodiment, when the signal S3 indicates that the resonant current is negative and the signal S4 indicates that the voltage V CT is less than the upper threshold Vp, the charging circuit 2102 is enabled. Conversely, in the considered embodiment, when the signal S3 indicates that the resonant current Is is positive and the signal S4 indicates that the voltage V CTWhen greater than the lower threshold Vv, the discharge circuit 2104 is enabled.

[0195] In the embodiment under consideration, the signal S4 is also fed to the monostable device MF1. Specifically, after a delay Td with respect to each rising or falling edge of the signal S4, the output of the monostable device MF1 is set high. The output of the monostable device MF1 and the signal S4 are fed to a logic gate AND1 (such as an AND gate) to generate the signal LSGD. In addition, the output of the monostable device MF1 and the inverted version of the signal S4 (e.g., at the inverted output of the flip-flop FF1) are fed to a logic gate AND2 (such as an AND gate) to generate the signal HSGD. Thus, in essence, the monostable device MF1 and the logic gates AND1 and AND2 implement a circuit configured to perform the following operations:

[0196] - After a delay Td with respect to the rising edge in the signal S4, set the signal LSGD high (thereby closing the low-side electronic switch SW2);

[0197] - When the signal S4 goes low (substantially simultaneous with the falling edge of the signal S4), set the signal LSGD low (thereby opening the low-side electronic switch SW2);

[0198] - After a delay Td with respect to the falling edge in the signal S4, set the signal HSGD high (thereby closing the high-side electronic switch SW1); and

[0199] - When the signal S4 goes high (substantially simultaneous with the rising edge of the signal S4), set the signal HDGD low (thereby opening the high-side electronic switch SW1).

[0200] Generally, the monostable device MF1 can also be implemented with other delay circuits such as a delay line.

[0201] Thus, also as Figure 6 shown, when the signal HSDG is set high (the high-side electronic switch SW1 is closed) and the resonant current is positive, the control circuit 2106 enables the discharge circuit 2104. Once the voltage V CT reaches the lower threshold Vv, the signal S4 is set high, whereby the control circuit 2106 sets the signal HSDG low. After a (dead) time Td, the control circuit 2106 then sets the signal LSDG high (the low-side electronic switch SW2 is closed). Once the resonant current becomes negative, the control circuit 2106 enables the charging circuit 2102. Once the voltage V CTWhen the upper threshold Vp is reached, the signal S4 is set to a low level, so that the control circuit 2106 sets the signal LSDG to a low level. After a (dead) time Td, the control circuit 2106 then sets the signal HSDG to a high level. Once the resonant current becomes positive, the control circuit 2106 enables the discharge circuit 2102 again.

[0202] Specifically, in the embodiment considered, the control circuit 2106 is configured to CT The time interval Δt1 ends when the lower threshold Vv is reached. Specifically, in the embodiment considered, the control circuit 2106 simultaneously deactivates the discharge circuit 2104 and activates the charging circuit 2102 once the resonant current becomes positive. Similarly, the control circuit 2106 is configured to activate the charging circuit 2102 at the voltage V CT The time interval Δt3 ends when the upper threshold Vp is reached. Specifically, in the embodiment considered, the control circuit 2106 simultaneously deactivates the charging circuit 2102, and once the resonant current becomes negative, the control circuit 2106 activates the discharging circuit 2102. Therefore, although the time Td (voltage e V CT The time between the moment when the upper threshold / reset of signal LSGD is reached and the moment when signal HSGD is set) is fixed, but the voltage e V CT The time Tz between the moment when the upper threshold Vp is reached and the moment when the discharge circuit is activated (because the resonant current becomes positive) is variable.

[0203] In the embodiment considered, the current generator 2114 is implemented using:

[0204] - a bias circuit, such as a resistor or a current generator, generating a current Io; and

[0205] - a current mirror, for example implemented using a bipolar transistor such as a pnp bipolar transistor, wherein the input Q9 of the current mirror receives the current Io provided by the bias circuit and the output Q11 of the current mirror is connected to the node N2, which in turn is connected to the capacitor C T .

[0206] In the embodiment considered, the current generator 2116 is implemented using:

[0207] - a second output Q10 of the current mirror Q9-Q11; and

[0208] - a second current mirror, for example implemented with bipolar transistors such as npn bipolar transistors, wherein the input Q12 of the current mirror receives the current provided by the output Q10 of the first current mirror and the output Q13 of the second current mirror is connected to the node N2.

[0209] Specifically, the second current mirror Q12-Q13 can be selectively enabled via an electronic switch Q14, which is driven via a signal S4 (such as a bipolar transistor). Additionally, the output Q11 of the current mirror Q9-Q11 always provides a current Io. Thus, in order to provide a current Io or -Io, the size of the current mirror Q12-Q13 can be determined (e.g., via a mirror factor of 2) to provide a current of -2Io to node N2.

[0210] Thus, in the embodiment under consideration, if the signal S2 at the output of CO1 is initially high, the output of the NAND gate NAND1 that receives the inverted output of the comparator CO1 and the output Q of the flip-flop FF1 at the input is thus high. The transistor Q8 connected between the transistor Q4 and the ground GND (corresponding to, for example, GND1) is turned on and conducts the current flowing through the bipolar transistor Q4 to the ground. Since the output Q of FF1 is high, the transistor Q14 is turned on, causing the mirror Q12-Q13 to be turned off and Q11 to conduct the current Io to the timing capacitor C T . In this way, C T is charged only by the current Io, and a rising voltage ramp with a slope of Io / C T will be observed.

[0211] After a certain period of time, the resonant current becomes negative and the signal Vs also becomes negative: the output of the comparator CO1 (signal S3) will become low, both inputs of the NAND gate NAND1 will be high, and thus, its output (signal S1) will become low. The transistor Q8 is turned off and the current mirrored from the transistor Q4 is conducted to the capacitor C T through the diode D1. On the other hand, since the output Q of the flip-flop FF1 is low, the output of the NAND gate NAND2 that receives the signal Q and the output of the comparator CO1 are high, causing the transistor Q7 connected between the common base terminal of the transistors Q5 and Q6 and the ground GND to be turned on and the mirror Q5-Q6 to be turned off. The current kIc from the transistor Q4 will be added to Io and charge the capacitor C T , and thus a rising voltage ramp with a slope of (kIc + Io) / C T will be observed on it. A ramp with such a slope starts from the moment when the current of the resonant circuit is negative (and that is, its sign is the same as the sign of the voltage applied to the resonant circuit itself, which is negative when the transistor SW2 of the half-bridge is turned on).

[0212] Once the voltage on the capacitor C T reaches the reference voltage Vp, it is configured to connect the voltage V T at the end of the capacitor C CTComparator CO2, which compares with the reference voltage Vp, resets SR flip-flop FF1 whose output Q becomes zero. This causes the half-bridge to be switched: the output LSGD immediately becomes zero, and after a delay Td generated by MF1 and gate AND2 together, the output HSGD of gate AND2 becomes high, and transistor SW1 of the half-bridge conducts. The output of gate NAND1 is forced to be high, and transistor Q8 conducts; the current flowing through transistor Q4 is sent to ground GND. The reverse-biased diode D1 isolates capacitor C T , thus preventing it from discharging through transistor Q8. At the same time, since the output Q of FF1 is low, transistor Q14 is cut off, enabling mirror Q12 - Q13 to conduct and Q13 to absorb current 2Io; since Q11 still delivers current Io, timing capacitor C T is charged by a net current equal to Io, and a falling voltage ramp with a slope of -Io / C T will be observed.

[0213] So far, mirrors Q5 - Q6 are cut off. However, at the input of gate NAND2, signal Q is now high, so the output of the gate depends on the state of comparator CO1. Due to the conduction period of transistor SW2 of the half-bridge, when the half-bridge is switched, the current is negative, so the output of comparator CO1 remains low, the output of gate NAND2 is high, transistor Q7 conducts and mirrors Q5 - Q6 are cut off. However, due to the switching, the voltage applied to the resonant circuit is now positive, so after a short time, the current and voltage Vs of the resonant circuit will also become positive. The output of CO1 becomes high, the output of NAND2 with both inputs high becomes low, and mirrors Q5 - Q6 conduct, taking out a current equal to Ic from capacitor C T . A falling voltage ramp with a slope of –(kIc + Io) / C T will be observed. A ramp with such a slope starts to be generated from the moment when the current of the resonant circuit is positive and its sign is the same as the sign of the voltage applied to the resonant circuit itself (which is positive when MOSFET SW1 of the half-bridge conducts).

[0214] Discharging continues until voltage V CT reaches value Vv, at which time comparator CO3 sets SR flip-flop FF1 high again, making its output Q high, and still cutting off mirrors Q5 - Q6 and Q12 - Q13, stopping the discharge of capacitor C T . The output of gate NAND1 remains high because the current of the resonant circuit is still positive and the output of comparator CO1 is high, transistor Q8 conducts and diode D1 is reverse-biased. Therefore, the current charging C T is only Io.

[0215] However, due to the switching, the voltage applied to the resonant circuit is now negative, and thus, after a short time, the current and voltage Vs of the resonant circuit will also become negative. The output of the comparator CO1 goes low, and thus the output of the NAND1 also goes low, the transistor Q8 is turned off, and the current flowing through the transistor Q4 charges the capacitor C again, etc. T Charging, etc.

[0216] Thus, basically, Figure 4 and Figure 8 the control circuit 210a shown is configured to:

[0217] - When the tank voltage and current have opposite signs (S3 is high and S4 is high, or S3 is low and S4 is low), during the time interval of the switching period Ts, charge and discharge the capacitor C alternately with a first, non-zero, constant current Io T alternately,

[0218] - When the voltage applied to the resonant tank is equal to the sign of the current flowing through the resonant tank (S3 is high and S4 is low, or S3 is low and S4 is high), during the time interval of the switching period Ts, charge and discharge the capacitor C alternately with a second constant current kIc + Io T alternately, where the second constant current includes the current Ic representing the feedback loop (which controls the output voltage or output current of the converter) and is greater than the first non-zero constant current Io, and

[0219] - When the capacitor voltage V CT contacts the lower threshold Vv or the upper threshold Vp, repeatedly half-bridge and reverse the charge / discharge phase of the capacitor C T of.

[0220] The equation describing the charge of the capacitor C during the half-switching period starting from t = 0 and ending at t = Ts / 2 (the switching period is Ts) can be as follows. Ideally, this half-switching period should correspond to the durations of the half-periods TA and TB, and where the tank current changes sign at t = Tz, where the valley voltage of the waveform on the capacitor C T is represented by Vv (e.g., equal to 1 V) and the peak voltage of the waveform on the capacitor C T is represented by Vp (e.g., equal to 4 V): T is represented by Vp (e.g., equal to 4 V):

[0221]

[0222] Note that the commanded time shift T SH is equal to Ts / 2 - Tz, and this equation can be rewritten as:

[0223]

[0224] By solving this equation to obtain T SH , a control law that links the commanded time shift to the control current Ic can be found:

[0225]

[0226] Figure 9 shows a circuit schematic of a control device consistent with the Figure 5 illustrated embodiment.

[0227] The control current Ic (which is modulated by a negative feedback control loop of the output voltage or current) is again provided to an optional input stage that includes an operational amplifier OA1 and a transistor Q1 (see also the corresponding description in Figure 8 ). Thus, the output of the operational amplifier OA1 controls the bipolar transistor Q1, allowing the current Ic to again be passed to the current mirror Q2-Q4, which is implemented, for example, by bipolar transistors, such as pnp bipolar transistors connected to the supply voltage Vdd. Thus, when enabled, the output Q4 of the current mirror again provides a current kIc to node N1, which is also connected to capacitor C T .

[0228] Figure 9 An alternative sub-circuit for enabling the output Q4 of the current mirror Q2-Q4 is also shown, which can also be used in place of diode D1 and electronic switch Q8.

[0229] Specifically, in the considered embodiment, the current mirror Q2-Q4 can be selectively disabled via an electronic switch Q8a (e.g., a pnp bipolar transistor). In the considered embodiment, in order to correctly drive the control terminal (e.g., the base terminal of the corresponding transistor) of the electronic switch Q8a, the sub-circuit can also include a pull-up resistor R1, and an electronic switch Q8a connected (optionally via another resistor R2) between the control terminal of the electronic switch Q8a and ground (e.g., GND1). Thus, in the considered embodiment, the signal S1 can be applied to the control terminal of the electronic switch Q8b.

[0230] Thus, in the considered embodiment, the current mirror Q2-Q4 and the sub-circuit including components Q8a, R1, R2, and Q8b implement Figure 5 a current generator 2102 that provides a current kIC, which can be selectively enabled / disabled according to a control signal S1.

[0231] In the considered embodiment, the current generator 2114 is implemented via the following (similar to Figure 8The illustrated embodiment):

[0232] - A bias circuit configured to generate a current Io, such as resistor R3; and

[0233] - A current mirror Q9-Q11 that receives the current Io at the input Q9 and provides the current Io at the output Q11 to a node N2, which is again connected to the capacitor C T .

[0234] Thus, in the considered embodiment, when the current mirror Q2-Q4 is enabled, i.e., when the bipolar transistor Q8a between the collector and emitter terminals coupled between the power supply voltage Vdd and the base terminals of the transistors Q2 and Q4 is cut off, the mirror Q2-Q4 provides the current kIc to the node N1 / capacitor C T to charge it. When the bipolar transistor Q8b is cut off, the bipolar transistor Q8a is cut off (and the mirrors Q2, Q4 are conducting); when the bipolar transistor Q8b driven by the XOR gate XOR1 is conducting, the bipolar transistor Q8a is conducting (and the mirrors Q2, Q4 are cut off). The capacitor C T is also charged by the current Io delivered by the current source composed of Q9, Q11, and R3 (assuming Vdd >> Vbe, defining the value of Io as Io ≈ Vdd / R3). In various embodiments, the generator is always on.

[0235] In accordance with Figure 5 the description of, in the considered embodiment, the driver circuit 210a further includes a reset circuit 2118. Specifically, in the considered embodiment, the reset circuit 2118 is implemented using an electronic switch Q6, such as an npn bipolar transistor Q6, which is configured to short-circuit the capacitor C, for example, by grounding the node N1 according to the control signal S5 T .

[0236] Thus, in the considered embodiment, the control circuit 2106 must generate various control signals. Generally, in accordance with Figure 8 the description of, the comparator CO1 is used to generate the control signal S3 according to the measurement signal Vs.

[0237] In addition, during each half-cycle TA / TB, the driver circuit 210a is configured to:[[]]

[0238] a) When the signal Vs indicates that the resonant current has changed sign, enable the current generator 2102, i.e., enable the output Q4 of the current mirror Q2-Q4;

[0239] b) Determine when the voltage V CT reaches the threshold Vp; and

[0240] c) When the voltage VCT When the threshold Vp is reached, capacitor C is reset T and a new half - cycle begins.

[0241] To this end, the circuit again includes a comparator CO2 configured to determine when the voltage V CT reaches / exceeds the threshold Vp. Then, the output of the comparator can be provided to an optional trigger generator circuit, e.g., in the form of a monostable circuit MF2, which is configured to generate a control signal S5 for resetting capacitor C at the end of half - cycles TA and TB T of the capacitor C.

[0242] In the embodiment under consideration, the output of comparator CO2 is also provided to a flip - flop FF1, which changes its output level in response to each rising edge of the signal at the output of the comparator. For example, in various embodiments, a J - K flip - flop is used, which receives the signal at the output of comparator CO2 as a clock signal. Generally, such a J - K flip - flop can be associated with a circuit providing corresponding values so as to perform a toggle / inversion of the output level, e.g., by applying a "1" to the J terminal of J - K flip - flop FF1 and a "1" to the K terminal of J - K flip - flop FF1. Thus, the output of flip - flop FF1 can again be used as control signal S4.

[0243] In the embodiment under consideration, then a logic gate XOR1 such as an XOR gate can be used to generate signal S1 from signals S3 and S4, since current kIc should be enabled when signal S3 is high and signal S4 is low or signal S3 is low and signal S4 is high. In fact, in Figure 5 and Figure 9 the embodiment shown, driver circuit 210a is configured to:

[0244] - when the slot voltage and current have opposite signs (S3 is high and S4 is high, or S3 is low and S4 is low), charge capacitor C with a first non - zero constant current Io during the time interval Tz of the switching half - cycles TA, TB T of the capacitor C,

[0245] - when the signs of the voltage applied to the resonant slot and the current flowing through the resonant slot are equal (S3 is high and S4 is low, or S3 is low and S4 is high), charge capacitor C with a second constant current kIc + Io during the time interval of the switching half - cycles (TA, TB), where the second (constant) current includes the current Ic representing the feedback loop (which controls the output voltage or output current of the converter) and is greater than the first non - zero constant current Io, and T of the capacitor C, and

[0246] - When the capacitor voltage C T reaches the threshold voltage Vp, the half - bridge is repeated and the capacitor C is reset T .

[0247] In the embodiment under consideration, for example, by using a monostable circuit MF1 and two logic gates AND1 and AND2, as Figure 8 shown, signals LSGD and HSGD are generated according to signal S4 (and its inverted version).

[0248] Specifically, in the embodiment under consideration, the voltage V T across the capacitor C CT is initially zero. The initialization circuit 2117 sets the inputs J and K of the flip - flop FF1 to, for example, "0" and "1" respectively, such that its output Q (signal S4) is low (and thus its non - Q is high), and then sets J = K = "1". Thus, from now on, the flip - flop FF1 will act as a Toggle at each positive edge applied to its asynchronous input / clock input from the comparator CO2, which is adapted to compare the voltage V T across the capacitor C CT with the reference voltage Vp. Since signal S4 is asserted low, after a delay Td performed by the monostable device MF1 and the gate AND1 together, the output LSGD becomes high and the low - side transistor of the half - bridge conducts. Signal Vs is initially positive, such that the output of the comparator CO1 (signal S3) is first high, and the output (signal S1) of the "exclusive - or" port XOR1 receiving signals S3 and S4 is thus high. The bipolar transistor Q8b conducts and thus the bipolar transistor Q8a also conducts, so the mirror Q2 - Q4 is cut off, and the capacitor C T is charged only by the current Io, and a ramp with a slope of Io / C T will be observed.

[0249] When signal Vs becomes negative due to the natural evolution of the slot current, signal S3 becomes low, both inputs of the gate XOR1 will be low, and thus its output (signal S1) will become low. Transistor Q8b cuts off, transistor Q8a thus cuts off, and the mirror Q2 - Q4 conducts, such that the current kIc flowing through transistor Q4 charges the capacitor C T and a rising voltage ramp with a slope of (kIc + Io) / C T is observed on it. Such a higher - slope ramp starts to be generated from the moment when the current of the resonant circuit becomes negative (i.e., its sign is the same as the sign of the voltage applied to the resonant circuit itself, which is negative when the low - side transistor of the half - bridge is conducting).

[0250] Once the capacitor CT voltage V across CT reaches the reference voltage Vp, the output of the comparator CO2 goes high, thereby inverting the state of the output of the flip-flop FF1, and the output Q (signal S4) of the flip-flop FF1 goes high (and not-Q goes low). This causes the half-bridge to be switched: the output LSGD immediately goes to zero, and after a delay Td generated by the monostable device MF1 and the gate AND2 together, the output HSGD goes high, and the high-side transistor SW1 of the half-bridge conducts.

[0251] At the same time, the high output of the comparator CO2 triggers the monostable device MF2, which releases a short pulse that temporarily conducts the bipolar transistor Q6, thereby discharging the capacitor C T rapidly. The duration of the pulse output by MF2 and thus the conduction time of Q6 should be sufficient to discharge C T completely, such that the voltage V CT is essentially reset to zero.

[0252] The signal Vs remains negative, so the output of the comparator CO1 (signal S3) is low, and since signal S4 is high, the output of the XOR1 gate (signal S1) is forced high, and thus transistors Q8b and Q8a conduct, thereby turning off the current mirror Q2 - Q4. Again, the capacitor C T is charged only by the current Io, and a ramp with a slope of Io / C T is observed as long as the voltage Vs remains negative.

[0253] However, due to the switching, the voltage applied to the resonant circuit is now positive, so after a short time, the current in the resonant circuit will also become positive, and thus the voltage Vs will also be positive. The output of the comparator CO1 (signal S3) goes high, the output of the XOR1 gate (signal S1) with both inputs high (signals S3 and S4) goes low, transistors Q8b and Q8a turn off, and the current mirror Q2 - Q4 turns on to charge the capacitor C T with its current kIc. An increasing voltage ramp with a slope of (kIc + Io) / C T will be observed thereon. Such a ramp starts from the moment when the current in the resonant circuit is positive and i.e., its sign is the same as the sign of the voltage applied to the resonant circuit itself (which is positive when the high-side transistor of the half-bridge conducts).

[0254] Charging continues until across the capacitor C TThe voltage reaches the value Vp again, and the output of CO2 goes high, thus inverting the state of the output of FF1, and its output Q (signal S4) becomes zero. This causes the half-bridge to be switched: the output HSGD immediately goes to zero, and after a delay Td generated by MF1 and AND1 together, the output LSGD goes high, and the low-side transistor of the half-bridge conducts.

[0255] At the same time, the high output of CO2 triggers the monostable device MF2, which releases a short pulse that temporarily conducts the bipolar transistor Q6, thereby discharging the capacitor C T rapidly. The duration of the pulse output by MF2 and then the conduction time of Q6 should again be sufficient to discharge C T completely, such that the voltage V CT is essentially reset to zero, and a new cycle with the same phase as above begins.

[0256] Also in this case, the feedback current Ic controls the time distance between the zero-crossing of the current of the resonant circuit and the subsequent switching of the half-bridge. The equations describing the operation of the circuit and the resulting control law can be found in (1), (2), and (3), where Vv = 0.

[0257] The inventors have observed that the embodiments disclosed herein allow for the implementation of the driver circuit 210a, which is less likely to change the duty cycle of the generated square wave from 50%, and thus can mitigate the problems of asymmetry in the resonant current and non-uniform distribution of the secondary current.

[0258] For example, referring to Figure 9 the embodiment shown, and assuming that the zero-current comparator CO1 has a positive offset, such as 5 mV, then as long as the voltage Vs is less than 5 mV, the slot current is identified as negative, and is positive only when Vs is greater than 5 mV. Thus, in the positive half-cycle TB (i.e., when the high-side switch SW1 of the half-bridge is closed), when the slot current has become greater than zero, the positive zero-crossing of the slot current is detected, and subsequently in the negative half-cycle TA (i.e., when the low-side switch SW2 of the half-bridge is closed), when the slot current is still greater than zero, the negative zero-crossing of the slot current is detected. As a result, with a fixed commanded time shift T SH , the duration of the positive half-cycle TB will be longer than that of the negative half-cycle TA.

[0259] In the absence of the above compensation technique, such as Io = 0, the commanded time shift T SH is exactly the same in the two half-cycles, so any mismatch ΔTz in the detection of the zero-crossing moment will be converted into the same mismatch in the durations of the two half-cycles.

[0260] Using the proposed method, solely through the proposed compensation technique, the value of the ramp at the end of the slow charging phase will be higher in the positive half-cycle TB (which has a longer duration) than in the negative half-cycle TA (which is shorter). Thus, in the positive half-cycle TB, it will take less time for the ramp to reach the reference level Vp, while it will take longer in the negative half-cycle TA. The mismatch ΔT of the commanded time shift in the two half-cycles SH will have a sign opposite to that of ΔTz and thus tends to compensate for ΔTz.

[0261] Generally speaking, other perturbations that cause a change ΔTz in the moment Tz at which the zero-crossing of the Vs signal is detected can also be partially compensated for by the change ΔT SH which will reduce the change in the duration of the resulting half-cycle. SH It is worth noting that in the considered embodiment, the constant current source Io is always active along each switching half-cycle (TA or TB).

[0262] As an alternative option, this current source may be active only during the first interval Tz of each half-cycle TA / TB (i.e., for 0 ≤ t ≤ Tz), and thus, the slope of the ramp in each switching half-cycle will be ±kIc / C

[0263] for Tz < t ≤ Ts / 2 (instead of ±(kIc + Io) / C T ). T

[0264] As another alternative option, the constant current source Io may be active only during the time interval Tz < t ≤ Ts / 2, while the current ±kIc is always active within each switching half-cycle, and thus for 0 ≤ t ≤ Tz, the slope of the ramp will be ±kIc / C T and for the remainder of the switching half-cycle, it will again be ±(kIc + Io) / C T .

[0265] In fact, the inventors have observed that any current generator (or combination of current generators) configured to generate a smaller slope in the time interval 0 ≤ t ≤ Tz and a larger slope in the time interval Tz < t ≤ Ts / 2 can be used.

[0266] In the embodiments considered so far, the amplitude of the ramp is constant, and the feedback current Ic modulates the slope of the ramp in the time interval Tz < t ≤ Ts / 2 and optionally also in the time interval 0 ≤ t ≤ Tz, thereby modulating the commanded T SH ​. Typically, by keeping the slope of the ramp constant (smaller slope in the time interval 0 ≤ t ≤ Tz and larger slope in the time interval Tz < t ≤ Ts / 2) and modulating / changing the amplitude of the ramp according to the current Ic, a similar modulation of the time T SH can be achieved. This modulation can involve any one (or both) of two voltage levels Vp or Vv.

[0267] For example, Figure 10 shows an embodiment consistent with the arrangement shown in Figure 8 where the feedback current Ic only modulates the voltage level Vp.

[0268] In this case, the input Q2 of the current mirror Q2-Q3 / Q2-Q4 is connected to a biasing circuit, such as a resistor R1, which is configured to generate a (constant) reference current Iref. Thus, when enabled, the output Q4 supplies a current k·Iref to node N1, and the output Q6 of the current mirror Q5-Q6 supplies a current -k·Iref to node N1.

[0269] As previously mentioned, different from the previous embodiments where Vp is fixed internally and the control current Ic determines the slope of the ramp V CT , in this case, the control current Ic (which can again be received from an external pin) is used to modulate the reference voltage Vp. For example, in the considered embodiment, the terminal receiving the current Ic (e.g., directly) is connected to the first terminal of a resistor R3, and the second terminal of the resistor R3 (e.g., directly) is connected to the supply voltage Vdd. Thus, the voltage at the first terminal of the resistor R3 can be used as the reference voltage Vp, where Vp = Vdd - R3·Ic.

[0270] The inventors have observed that this operation is still consistent with the required operation of the loop: in the embodiments where Ic controls the slope of the ramp V CT , a larger Ic results in faster charging and thus a shorter T SH ; vice versa, a smaller Ic results in slower charging and thus a longer T SH . Similarly, in this embodiment, a larger Ic results in a smaller Vp and thus a shorter T SH ; a smaller Ic results in a larger Vp and thus a longer T SH .

[0271] The remaining blocks / circuits and the operation of this circuit are the same as those of the circuit shown in Figure 8 , and thus will not be elaborated further.

[0272] Therefore, the commanded time shift T SHThe control law linked to the control voltage Vp (which is a function of the control current Ic) is as follows:

[0273]

[0274] Thus, in the embodiment considered, the driver circuit 210a is configured to:

[0275] - When the slot voltage and current have opposite signs, in a time interval of the switching period, charge and discharge the capacitor C alternately with a first non-zero constant current Io T alternately,

[0276] - When the voltage applied to the resonant slot and the current flowing through the resonant slot have the same sign, in a time interval of the switching period, charge and discharge the capacitor C alternately with a second constant current greater than the first non-zero constant current T alternately; and

[0277] - When the capacitor voltage reaches a lower threshold or an upper threshold, repeatedly half-bridge and reverse the charge / discharge phase of the capacitor C T wherein the (at least) upper threshold is determined according to the feedback control signal Ic.

[0278] Generally, although in the above embodiment, fixed currents Io and optional Iref have been used, one or more of these currents can also be made adjustable, for example, by providing terminals of the driver circuit 210a to be connected to corresponding external biasing circuits (such as an external resistor R2 or resistor R1).

[0279] Conversely, Figure 14 An embodiment is shown in which the current can be set via a voltage signal. For example, in the embodiment considered, the voltage signal is provided via a resistive voltage divider that includes two resistors R5 and R6 connected between a voltage such as the input voltage Vin and ground (e.g., GND1). For example, this has the advantage that the voltage signal is determined according to (proportional to) the input voltage Vin. For example, this provides a feedforward control to allow reducing the change in the control signal Ic required to keep the output voltage (or current) stable when the input voltage Vin changes, thereby further improving the transient response to input voltage changes and the suppression of input voltage ripple.

[0280] In the embodiment under consideration, a voltage signal (e.g., at resistor R6) is connected to the first (e.g., non-inverting) input of operational amplifier OA2, and the output of operational amplifier OA2 is connected to a variable current generator Q20 (e.g., implemented using an (e.g., npn) bipolar transistor). The output of current generator Q20 is connected to ground via resistor R7, thereby generating a voltage at the resistor proportional to the current provided by current generator Q20. By connecting the voltage to the second (e.g., inverting) input terminal of operational amplifier OA2, operational amplifier OA2 will substantially change the output signal, thereby changing the current provided by current source Q20 in order to impose the voltage signal on the first input terminal of resistor R7.

[0281] In the embodiment under consideration, a current mirror Q21 - Q22 (e.g., which can be implemented using an (e.g., pnp) bipolar transistor) can be used to provide a current proportional to the voltage signal.

[0282] In Figure 9 the embodiment of, similar modifications to those discussed with respect to Figure 10 can also be performed. Specifically, in this case, a current generator 2102 that can be selectively enabled according to signal S1 provides a current k·Iref, and current generator 2114 always provides a current Io.

[0283] For example, in Figure 11 an embodiment is shown in which both current generators 2102 and 2114 are implemented using the same current generator, which includes:

[0284] - A first biasing circuit, such as a first resistor R1,

[0285] - An electronic switch Q8 configured to selectively enable the first biasing circuit according to a control signal S1, and

[0286] - A second biasing circuit, such as a second resistor R2, configured to provide a current Io,

[0287] - A current mirror Q2 - Q4, where the input Q2 of the current mirror is connected to the first biasing circuit and the second biasing circuit.

[0288] Specifically, in the embodiment under consideration, capacitor C T is charged by the current delivered by the output Q4 of current mirror Q2 - Q4. In the embodiment under consideration (when using resistors as biasing circuits), the value of this current is differently defined depending on the state of electronic switch Q8 / signal S1: Assuming Vdd >> Vbe, when electronic switch Q8 is off, output Q4 provides a current Io l≈Vdd / R2, and when the electronic switch Q8 is turned on, the output Q4 provides a current Io2≈Vdd / (R1 / / R2) (parallel connection of resistors R1 and R2), where Io2 > Io1.

[0289] Specifically, considering the logic level of the signal S1, the electronic switch Q8 is driven by the inverted / inverting signal S1, i.e., when the signal S1 is at a high level (i.e., when the tank current and the applied voltage have opposite signs), the electronic switch Q8 is turned off, and when the signal S1 is at a low level (i.e., when the tank current and the applied voltage have the same sign), the electronic switch Q8 is turned on.

[0290] In the considered embodiment, this current generator is always on, but can be optionally turned off during the discharge / reset of C T to reduce the total consumption. This also applies to the embodiments described with respect to Figure 5 and Figure 9 described embodiments.

[0291] In addition, in accordance with the description of Figure 10 a resistor R3 connected to the supply voltage can be used to generate a reference voltage Vp according to the current Ic.

[0292] The remaining blocks / circuits and the operation of this circuit are the same as those of the circuit shown in Figure 9 and will not be described in detail herein.

[0293] Therefore, in the considered embodiment, the voltage V T across the capacitor C CT is initially zero. The initialization circuit 2117 sets the inputs J and K of the flip-flop FF1 to "0" and "1" respectively, such that its output Q (signal S4) is at a low level, and then the circuit 2117 sets J = K = "1". Therefore, from now on, the flip-flop FF1 will act as a Toggle at each positive edge applied to its asynchronous / clock input from the comparator CO2, which is adapted to compare the voltage V T across the capacitor C CTIt is compared with a reference voltage Vp determined according to a control current Ic. Since Q (signal S4) is asserted low, after a delay Td performed by a monostable device MF1 having at its input the output Q (signal S4) of a flip-flop FF1 and a gate AND1, the output LSGD becomes high and the low-side transistor SW2 of the half-bridge conducts. The signal Vs is initially positive, such that the output of the comparator CO1 is first high. The output (signal S1) of an "exclusive OR" port XOR1 receiving at its input the output of the comparator CO1 and the output Q (signal S4) of the flip-flop FF1 (currently low) is thus high. Accordingly, the bipolar transistor Q8 is cut off, and the current generator Q2-Q4 charges the capacitor C T with a current Io1, and a ramp with a slope of Io1 / C T will be observed.

[0294] When the signal Vs becomes negative due to the natural development of the tank current, the output (signal S3) of the comparator CO1 will become low, both inputs of the gate XOR1 will be low, and thus its output (signal S1) will become low. Accordingly, the transistor Q8 conducts, and the current generator Q2-Q4 charges the capacitor C T with a current Io2, where typically Io2 = k·Io1, and a rising voltage ramp with a slope of Io2 / C T will be observed thereon. Such a (k times) higher slope ramp is generated starting from the moment when the current of the resonant circuit becomes negative (i.e., its sign is the same as the sign of the voltage applied to the resonant circuit itself, which is negative when the low-side transistor of the half-bridge conducts).

[0295] Once the voltage V T across the capacitor C CT reaches the reference voltage Vp, the output of the comparator CO2 becomes high, thereby inverting the state of the output (signal S4) of the flip-flop FF1, and the output Q (signal S4) of this flip-flop becomes 1. This causes the half-bridge to be switched: the output LSGD immediately becomes zero, and after a delay Td generated by the monostable device MF1 and a gate AND2 together, the output HSGD becomes high and the high-side transistor of the half-bridge conducts.

[0296] At the same time, the high output of CO2 triggers the monostable device MF2, which releases a short pulse that temporarily conducts the bipolar transistor Q6, thereby discharging the capacitor C T rapidly. The duration of the pulse output by MF2 and then the conduction time of Q6 should be sufficient to fully discharge C T such that the voltage V CT is essentially reset to zero.

[0297] The signal Vs remains negative, so the output of comparator CO1 is low, and since Q (signal S4) is high, the output of gate XOR1 (signal S1) is forced high, and thus transistor Q8 is cut off. Similarly, capacitor C T is charged by the current Io1 delivered by current generators Q2 - Q4, and a ramp with a slope of Io1 / C T is observed as long as voltage Vs remains negative.

[0298] However, due to the switching, the voltage applied to the resonant circuit is now positive, so after a short time, the current in the resonant circuit will also become positive, and thus voltage Vs will also be positive. The output of comparator CO1 (signal S3) becomes high, the output of gate XOR1 (signal S1) with both inputs high becomes low, transistor Q8 conducts, and current generators Q2 - Q4 charge capacitor C T with their current Io2. An upward voltage ramp with a slope of Io2 / C T (k times greater than Io1 / C T ) will be observed on it. Such a ramp starts from the moment when the current in the resonant circuit is positive and that is, its sign is the same as the sign of the voltage applied to the resonant circuit itself (which is positive when the high - side transistor SW1 of the half - bridge conducts).

[0299] This faster charging continues until the voltage across capacitor C T reaches the value Vp again, and the output of CO2 becomes high, thus inverting the state of the output of FF1, whose output Q (signal S4) becomes zero. This causes the half - bridge to be switched: the output HSGD immediately becomes zero, and after a delay Td generated by MF1 and gate AND1 together, the output LSGD becomes high, and the low - side transistor SW2 of the half - bridge conducts.

[0300] At the same time, the high output of CO2 triggers monostable device MF2, which releases a short pulse that temporarily conducts bipolar transistor Q6, thus discharging capacitor C T rapidly. The duration of the pulse output by MF2 and then the conduction time of Q6 should be sufficient to fully discharge C T so that voltage V CT is basically reset to zero, and a new cycle of the same phase as described above starts.

[0301] Following the same method used to derive (1), (2), (3), and (4), the equations describing the operation of the circuit and the resulting control law can be found, where Vv = 0. The result is:

[0302]

[0303] Thus, in the embodiments considered, the driver circuit 210a is configured to perform the following steps during each half-cycle (TA or TB):

[0304] - When the slot voltage and current have opposite signs (i.e., before the comparator CO1 signals that the resonant current has changed sign), during a first time interval Tz of the switching half-cycle (TA or TB), charge the capacitor C with a first non-zero constant current T charging,

[0305] - When the voltage applied to the resonant slot and the current flowing through the resonant slot have equal signs (i.e., after the comparator CO1 signals that the resonant current has changed sign), during a second time interval of the switching half-cycle, charge the capacitor C with a second constant current greater than the first non-zero constant current T charging up to an upper reference voltage Vp, which is a function of the feedback signal Ic, where the feedback signal Ic represents a feedback loop that controls the output voltage or output current of the converter, and

[0306] - When the capacitor voltage V CT reaches the upper reference voltage, repeatedly half-bridge and reset the capacitor C T (and end the corresponding half-cycle TA or TB).

[0307] Thus, in the embodiments discussed so far, during each half-cycle TA and TB, the integrating circuit 2300 is configured to:

[0308] - During a first interval (Tz) between the moment when a corresponding interval (TA or TB) starts and the moment when the comparator CO1 signals via the signal S3 that the resonant current has changed sign / reached zero (i.e., the voltage and resonant current at the resonant slot have opposite signs), generate an integration signal INT by integrating a signal having a given first (and preferably constant) amplitude (e.g., V CT ); and

[0309] - During a second interval between the moment when the comparator CO1 signals via the signal S3 that the resonant current has changed sign / reached zero and the moment when the comparator CO2 signals that the integration signal has reached a given threshold (i.e., the voltage and resonant current at the resonant slot have the same sign), generate an integration signal INT by integrating a signal having a given second amplitude (e.g., V CT ), where the second amplitude is generally greater than the first amplitude.

[0310] Specifically, in relation to Figures 3 to 9In the discussed embodiment, the driver circuit 210a is configured to determine a second amplitude during a second time interval (and optionally also determine a first amplitude during a first time interval) based on the feedback control signal Ic, while the threshold Vp remains constant. In contrast, in Figure 10 and Figure 11 the illustrated embodiment, the driver circuit 210a is configured to determine the threshold Vp (and / or Vv) based on the feedback control signal Ic, while the first and second amplitudes remain constant during the first and second time intervals.

[0311] Generally, although current signals (Ic, Iref, and Io) have been processed so far, these signals can also be replaced with voltage signals. Additionally, instead of performing analog processing, at least a portion of the operations can also be implemented digitally, for example, by appropriate programming of a digital microprocessor.

[0312] For example, Figure 12 shows a possible implementation in which Figure 10 the part of the block is implemented digitally.

[0313] Specifically, in the considered embodiment, the driver circuit 210a includes an analog-to-digital converter (ADC) 2400 for determining a digital signal indicative of the feedback signal Ic. For example, in the considered embodiment, the feedback current Ic is connected to a first terminal of a resistor R3, and a second terminal of the resistor is connected to the supply voltage Vdd. Thus, the ADC 2400 can convert the voltage at the first terminal of the resistor R3. Generally, the circuit (R3) for Ic-to-Vp conversion, and / or the ADC 2400 can be inside or outside the integrated circuit of the driver circuit 210a.

[0314] Thus, in the considered embodiment, the digital sample obtained by the ADC 2400 corresponds to (or can generally be used to determine) a digital version Vp* of the upper threshold Vp.

[0315] In the considered embodiment, the binary word Vp* is applied to one input of a (digital) multiplexer MUX2. On another input, the (digital) multiplexer MUX2 receives a binary word Vv* indicative of the lower threshold Vv. The digital signal selected by the multiplexer MUX2 is applied to the inverting input of a digital comparator CO2. The digital comparator CO2 also receives the output of an up-down N-bit counter 2406 at its non-inverting input.

[0316] In the embodiment under consideration, the counter direction of counter 2406 and the selection performed by multiplexer MUX2 are determined according to the signal provided by comparator CO2 and are inverted at the start of each switch half-cycle (TA or TB): when the output of comparator CO2 is low, counter 2406 counts up, and MUX2 provides Vp* to the inverting input of CO2; when the output of comparator CO2 is high, counter 2406 counts down, and MUX2 passes Vv* to the inverting input of CO2.

[0317] For example, in Figure 12 the embodiment shown, the output of comparator CO2 can again be fed to a J-K flip-flop with an associated initialization circuit 2117, which thus provides a signal S4 indicating whether the half-cycle is the interval TA (low-side switch closed) or TB (high-side switch closed).

[0318] Conversely, Figure 13 it is shown that in a digital implementation, flip-flop FF1 is not strictly necessary (and can be omitted) because when immediately switching the threshold at multiplexer MUX2, the signal at the output of comparator CO2 directly corresponds to signal S4. However, in this case, a circuit 2408 configured to select the initial configuration for counter 2406 and multiplexer MUX2 is preferably used.

[0319] In the embodiment under consideration, digital counter 2406 is thus configured (in each half-cycle TA or TB) to:

[0320] - During a first interval (Tz) between the moment at the start of the corresponding interval (TA or TB) and the moment when comparator CO1 signals via signal S3 that the resonant current has changed sign / reached zero (i.e., the voltage and the resonant current at the resonant tank have opposite signs), generate an integration signal INT by integrating (i.e., increasing or decreasing) the count value in a first step size STEP1; and

[0321] - During a second interval between the moment when comparator CO1 signals via signal S3 that the resonant current has changed sign / reached zero and the moment when comparator CO2 signals that the integration signal has reached a given threshold, generate an integration signal INT by integrating (i.e., increasing or decreasing) the count value in a second step size STEP2, where the second step size is greater than the first step size.

[0322] For example, in Figure 12 it, multiplexer MUX3 is used to provide step size STEP1 or STEP2 to counter 2406 according to signal S3 (e.g., again at the output of XOR gate XOR1 receiving signals S3 and S4).

[0323] Conversely, asFigure 13 As shown, the step size can also remain constant, but the counter clock signal changes, i.e.:

[0324] - During a first interval (Tz) between the moment when a corresponding interval (TA or TB) starts and the moment when the comparator CO1 signals via signal S3 that the resonant current has changed sign / reached zero (i.e., the voltage and the resonant current at the resonant tank have opposite signs), an integration signal INT is generated by integrating (i.e., increasing or decreasing) the count value with a constant step size in response to a first clock signal CLK1; and

[0325] - During a second interval between the moment when the comparator CO1 signals via signal S3 that the resonant current has changed sign / reached zero and the moment when the comparator CO2 signals that the integration signal has reached a given threshold, an integration signal INT is generated by integrating (i.e., increasing or decreasing) the count value with a constant step size in response to a second clock signal CLK2, where the second clock signal CLK2 is faster than the first clock signal CLK1.

[0326] For example, in the considered embodiment, the clock signal for the counter 2406 is selected from among the clock signals CLK1 and CLK2 via a multiplexer MUX3, which is driven via a logic (e.g., XOR gate) XOR1 that receives signals S3 and S4 at the input. For example, the clock signal CLK1 can be derived from the clock signal CLK2 by means of a frequency divider. In the considered embodiment, the signal S3 is determined again via an analog comparator CO1 as in the previous embodiment.

[0327] Generally, the block MF1 and the gates AND1 and AND2 can also be implemented via corresponding digital processing in order to set:

[0328] - In response to the rising edge of the signal S4, the signal LSGD is set to low level and the signal HSGD is set to high level immediately after a delay Td; and

[0329] - In response to the falling edge of the signal S4, the signal HSGD is set to low level and the signal LSGD is set to high level immediately after a delay Td.

[0330] Thus, in Figure 12 and Figure 13In the illustrated embodiment, for example, due to the initialization circuit 2117 or 2408, the counter 2406 is initially set to zero, the counting direction is upward, and the multiplexer MUX2 provides the value Vp*. Consistent with this, the output of the comparator CO2 is low, causing the drive signal HSGD to be asserted low, and after a delay Td (e.g., via a monostable device MF1 having the output Q of the flip-flop FF1 at the input and the gate AND1 together), the output LSGD goes high and the low-side transistor SW2 of the half-bridge conducts.

[0331] Assume that the signal Vs is initially positive, so the output of the comparator CO1 (signal S3) is initially high, and thus the output of the port XOR1 (signal S1) is high. Therefore, the multiplexer MUX3 selects the smaller step size STEP1 ( Figure 12 ) or the slower clock signal CLK1 ( Figure 13 ), and the counter 2406 starts counting. When the signal Vs becomes negative due to the natural development of the slot current, the output of the comparator CO1 (signal S3) will become low, both inputs of the gate XOR1 will be low, and thus its output (signal S1) will become low. Therefore, the multiplexer MUX3 selects the larger step size STEP2 ( Figure 12 ) or the faster clock signal CLK2 ( Figure 13 ), and the counter continues to count.

[0332] Therefore, in both cases, the effective increase rate / gradient of the signal INT at the output of the counter 2406 (with respect to a given reference period, e.g., 1 s) starts to increase from the moment when the current of the resonant circuit becomes negative (i.e., its sign is the same as the sign of the voltage applied to the resonant circuit itself, which is negative when the low-side transistor of the half-bridge conducts).

[0333] Once the signal INT at the output of the counter 2406 reaches the reference digital word Vp*, the output of the digital comparator CO2 becomes high, thereby setting the signal S4 high. This causes the half-bridge to be switched: the output LSGD immediately goes to zero, and after a delay Td (e.g., generated by the monostable device MF1 and the gate AND2 together), the output HSGD goes high and the high-side transistor SW1 of the half-bridge conducts.

[0334] At the same time, since the signal S4 is high, the counter 2406 reverses its direction from upward to downward, and the multiplexer MUX2 outputs Vv*, which confirms that the output of CO2 remains high. For the reasons described above, the flip-flop FF1 can be omitted.

[0335] The signal Vs remains negative, so the output of comparator CO1 (signal S3) is at a low level. And since signal S4 is at a high level, the output of gate XOR1 (signal S1) is forced to a high level. Therefore, multiplexer MUX3 selects the smaller step size STEP1 ( Figure 12 ) or the slower clock signal CLK1 ( Figure 13 ), and counter 2406 starts counting down. When signal Vs becomes positive due to the natural development of the tank current, the output of comparator CO1 (signal S3) will become high level, both inputs of gate XOR1 will be at high level, and thus its output (signal S1) will become low level. Therefore, multiplexer MUX3 selects the larger step size STEP2 ( Figure 12 ) or the faster clock signal CLK2 ( Figure 13 ), and the counter continues to count.

[0336] Therefore, in both cases, the effective increase rate / gradient of the signal INT at the output of counter 2406 (with respect to a given reference period, e.g., 1 s) starts to increase from the moment when the current of the resonant circuit becomes positive (i.e., its sign is the same as the sign of the voltage applied to the resonant circuit itself, which is positive when the low-side transistor of the half-bridge is conducting).

[0337] Once the signal INT at the output of counter 2406 reaches the reference digital word Vv*, the output of digital comparator CO2 becomes low level, thus setting signal S4 to low level. This causes the half-bridge to be switched: output HSGD immediately becomes low level, and after a delay Td (e.g., generated by MF1 and gate AND1 together), output LSGD becomes high level, and the low-side transistor SW2 of the half-bridge conducts.

[0338] At the same time, since the output of digital comparator CO2 is at a low level, the counter reverses its direction from down to up, and multiplexer MUX2 selects the value Vp*, which confirms that the output of CO2 remains low level, and starts a new cycle with the same phase as described previously.

[0339] Therefore, also in the digital implementation, during each half-cycle TA and TB, the integrating circuit 2300 is configured to:

[0340] - During a first interval (Tz) between the moment when a corresponding interval (TA or TB) starts and the moment when comparator CO1 signals via signal S3 that the resonant current has changed sign / reached zero (i.e., the voltage and the resonant current at the resonant tank have opposite signs), generate an integrating signal INT with a first (non-zero) rising rate / gradient (e.g., V CT ); and

[0341] - During a second interval between the moment when comparator CO1 signals that the resonant current has changed sign / reached zero via signal S3 and the moment when comparator CO2 signals that the integral signal has reached a given threshold, an integral signal INT (e.g., V CT ) is generated with a second rate of rise / gradient, where the second rate of rise / gradient is greater than the first rate of rise / gradient.

[0342] Also in this case, the second rate of rise / gradient of at least one of the half - periods TA and TB or alternatively the threshold values (Vp and Vv, or only Vp) can be determined based on the feedback control signal Ic.

[0343] Typically, the frequency of clock signals CLK1 and / or CLK2, or the step sizes STEP1 and / or STEP2 can be settable.

[0344] Thus, in essence, the integral signal INT results from a combination of:

[0345] - A first linear part / ramp signal generated by the integration of a constant signal (e.g., Io) during a complete half - period TA or TB, and

[0346] - A second (usually linear) part / ramp generated by the integration of a second signal (e.g., Iref or kIC) only within the second time interval.

[0347] Thus, the signal INT can be considered as a superposition of two ramps, one ramp starting at the beginning of each half - period and the other ramp starting at the moment when the zero - current comparator detects a sign change in the resonant current. In the embodiments considered so far, this ramp superposition is mainly achieved by summing (or generally modifying) the signals at the input of an (analog or digital) integrator. However, typically, instead of adding the signal Io to the input of the integration circuit, the corresponding first linear part / ramp signal can also be added directly to the output of the integration circuit.

[0348] For example, this is schematically shown in Figure 15 which is essentially based on the embodiment of Figure 9 .

[0349] Specifically, the following modifications have been introduced with respect to Figure 9 :

[0350] - The current generator 2114 (implemented, for example, using components R3, Q9, and Q11) has been removed;

[0351] - A ramp generator 2122 has been added, where the ramp generator 2122 essentially provides a voltage signal Vx corresponding to the integration of a constant value (which corresponds to, for example, the aforementioned current Io); and

[0352] -(Voltage) adder 2120 has been added, where adder 2120 receives the integration signal INT / voltage V at the input CT and voltage signal Vx, and provides signal INT' at the output, which is provided to the input of comparator CO2.

[0353] Normally, the ramp generator 2122 should be reset at the end or start of each half-cycle TA / TB. Therefore, the ramp generator 2122 can be reset together with capacitor C, for example, via the reset circuit 2118 (e.g., via the monostable device MF2). Conversely, in the considered embodiment, capacitor C T is reset via signal S1 (in this range, the capacitor should not be charged during the initial part Tz of half-cycles TA and TB), while the ramp generator 2122 is reset individually at the end or start of each half-cycle TA / TB, for example, by using the monostable device MF2 again or by using the signal at the output of the monostable device MF1. T For example,

[0354] For example, Figure 16 shows exemplary waveforms for the voltage V T at capacitor C, CT voltage Vx, and the combined integration signal INT.

[0355] Normally, similar modifications can also be performed in other embodiments.

[0356] Therefore, generally, the driver circuit 210a includes terminals (e.g., pins of the corresponding integrated circuit) configured to be connected to the following:

[0357] - Control (e.g., gate) terminals of the high-side electronic switch SW1 and the low-side electronic switch SW2 connected in series between the positive terminal 200a and the negative terminal 200b, where the intermediate node between the two electronic switches SW1 and SW2 represents the switching node HB;

[0358] - Current sensor 222 capable of monitoring the resonant current Is flowing from the switching node HB to the resonant tank; and

[0359] - Feedback circuit 212 - 218 providing a feedback signal Ic determined according to the output voltage Vout or current Iout.

[0360] Specifically, the driver circuit 210a includes an (analog or digital) integration circuit 2300, an (analog) comparator 2108 / CO1, and a comparison circuit 2110 including at least one (analog or digital) comparator CO2 / CO3.

[0361] Specifically, in various embodiments, comparator 2108 / CO1 is configured to generate a signal S3 that indicates when the resonant current changes sign based on the signal Vs provided by current sensor 222. Integrator circuit 2300 receives a first signal at its input and provides an integrated signal INT at its output. A comparison circuit is configured to determine whether the integrated signal INT reaches at least one reference threshold Vp / Vv.

[0362] Specifically, during each half-cycle TA / TB of each switching period Ts, driver circuit 210a is configured to:

[0363] - Set the first signal to zero during a first time interval (Tz) between the moment when a respective half-cycle (TA or TB) starts and the moment when comparator CO1 signals via signal S3 that the resonant current has changed sign (i.e., when the voltage and the resonant current at the resonant tank have opposite signs); and

[0364] - Determine the first signal (kIc or -kIc) based on a second signal (Ic or Iref) during a second interval between the moment when comparator CO1 signals via signal S3 that the resonant current has changed sign / reached zero and the moment when the comparison circuit signals that the integrated signal INT has reached at least one reference threshold Vp / Vv.

[0365] In various embodiments, the second signal (Ic) is determined based on the feedback signal Ic or alternatively at least one reference threshold Vp / Vv is determined.

[0366] Specifically, in the embodiments considered so far, driver circuit 210a is configured to modify the integrated signal INT provided to comparison circuit 2110 by:

[0367] - Adding a constant offset (e.g., based on Io or -Io of the half-cycle) to the input of integrator circuit 2300; or

[0368] - Adding a linear ramp signal (Vx) to the integrated signal INT at the output of integrator circuit 2300 / input of comparison circuit 2110.

[0369] Specifically, when the first signal at the input of integrator circuit 2300 is positive, a positive ramp signal must be added to the threshold signal Vp, and when the first signal at the input of integrator circuit 2300 is negative, a negative ramp signal must be added to the threshold signal Vp.

[0370] However, the inventors have found that adding a linear ramp signal (Vx) to the integral signal INT at the first input of a comparator (e.g., CO2) is equivalent to subtracting the same ramp signal (Vx) from the upper threshold Vp at the second input of the comparator (or adding its negative version). Specifically, when the threshold signal corresponds to the upper threshold Vp, a negative ramp signal must be added to the threshold signal Vp, and when the threshold signal corresponds to the lower threshold Vv, a positive ramp signal must be added to the threshold signal Vv.

[0371] For example, this is schematically shown in Figure 17 where the adder 2120 has been removed and a (adder or subtractor) circuit 2124 has been added, which is configured to generate a modified threshold signal Vp' at the input of the comparator CO2 by adding a negative ramp signal to the threshold signal Vp or subtracting a positive ramp signal from the threshold signal Vp.

[0372] For example, Figure 18 shows exemplary waveforms for the voltage V T across the capacitor C CT , the voltage Vp, and the modified threshold signal Vp'.

[0373] Conversely, Figure 19 shows an embodiment consistent with the Figure 8 arrangement shown.

[0374] Also in this case, the additional current generators 2114 / 2116 have been removed. In addition, a ramp generator 2122 and a subtractor circuit 2124 have been added.

[0375] Thus, in the considered embodiment, the lower threshold signal Vv provided to the comparison circuits (CO2, CO3) corresponds to the ramp signal Vx, and the upper threshold signal Vp' provided to the comparison circuits (CO2, CO3) corresponds to the upper threshold Vp minus the ramp signal Vx.

[0376] For example, Figure 20 shows exemplary waveforms for the voltage V T across the capacitor C CT , the voltage Vp, and the modified threshold signal Vp'.

[0377] Thus, in the considered embodiment, the driver circuit 210a may include a correction circuit (e.g., block 2306; 2114; 2114 and 2116; Mux3, 2122), which is configured to:

[0378] - Modify the (first) ramp signal INT provided at the input of the comparison circuit 2110 (by modifying the input signal of the ramp generator / integrator circuit, or adding a ramp signal to the signal at the output of the ramp generator / integrator circuit), such that the ramp signal INT has a first gradient value (e.g., Io or kIc) during an interval Tz, and then has a second gradient value (e.g., kIc + Io or Io + kIref) during the remainder of the corresponding half - period, where the first gradient value is a non - zero value and the absolute value of the second gradient value is greater than the absolute value of the first gradient value (preferably, the first gradient value and the second gradient value have the same sign), or

[0379] - Modify one or more of the reference thresholds (Vp / Vv) of the comparison circuit (2110) by adding a (second) ramp signal (e.g., Vx) to the corresponding initial threshold.

[0380] For example, to implement the first option, the driver circuit 210a can be configured to modify the (first) ramp signal INT by:

[0381] - Setting the input signal of the integration circuit 2300 to a first value (e.g., Io, kIref, or kIc) during a first interval (Tz), and

[0382] - Setting the input signal of the integration circuit 2300 to a second value (e.g., kIref + Io, kIc + Io, or kIref or kIc (if these values are greater than the first value)) during a second interval (Tz).

[0383] For example, any of the following solutions can be used for this purpose:

[0384] - The first signal can be set to zero during the first interval (Tz) and to a non - zero value (kIc; kIref) during the second interval, and the second signal can be set to a constant non - zero value (Io) during the first interval (Tz) and the second interval; or

[0385] - The first signal can be set to a constant non - zero value (kIc; kIref) during the first interval (Tz) and the second interval, and the second signal can be set to zero during the first interval (Tz) and to a constant non - zero value (Io) during the second interval; or

[0386] - The first signal can be set to zero during the first interval (Tz) and to a non - zero value (kIc; kIref) during the second interval, and the second signal can be set to a constant non - zero value (Io) during the first interval (Tz) and to zero during the second interval.

[0387] Alternatively, the input signal of the integrating circuit 2300 can be set to zero during a first interval (Tz) and to a non-zero value (e.g., kIc; kIref) during a second interval. In this case, the (first) ramp signal INT can be modified by adding a second ramp signal (Vx) to the ramp signal INT, where the ramp signal corresponds to a linear ramp signal during the first interval (Tz) and the second interval. In a complementary manner, the input signal of the integrating circuit 2300 can be set to a constant non-zero value (kIc; kIref) during the first interval (Tz) and the second interval, and the ramp signal (Vx) can correspond to zero during the first interval (Tz) and to a linear ramp signal during the second interval.

[0388] Conversely, to implement the second option, the input signal of the integrating circuit 2300 can be set to zero during a first interval (Tz) and to a non-zero value (kIc; kIref) during a second interval. In this case, the second ramp signal added to the threshold (Vx) can correspond to a linear ramp signal during the first interval (Tz) and the second interval. In a complementary manner, the input signal of the integrating circuit 2300 can be set to a non-zero value (kIc; kIref) during the first interval (Tz) and the second interval, and the second ramp signal (Vx) can correspond to zero during the first interval (Tz) and to a linear ramp signal during the second interval.

[0389] In general, although the above-described embodiments are equivalent from a functional point of view, a particular embodiment can be more or less complex and / or suitable for analog or digital implementation. For example, the embodiment shown in the figure provides a solution with very low complexity.

[0390] Moreover, various known integrated control circuits for implementing time-shift control (without the above modifications) are already available. Therefore, the embodiments disclosed herein can also be used to modify such integrated circuits or to add the above modifications externally to the driver circuit. For example, in the driver circuit 210 using an external capacitor C T an additional current generator 2114 and optionally 2116 can be added to the electronic converter (thus implementing option a) without having to modify the integrated circuit of the driver circuit 210. Similarly, in the driver circuit 210 where the thresholds Vp and / or Vv can be set externally, these signals can be modified externally to implement option c).

[0391] A series of simulations have been performed on an exemplary converter to compare the secondary current mismatch caused by the input offset of the zero-current comparator using the prior art TSC method and the novel TSC method. In addition, the small-signal response of the converter has been examined to evaluate the impact of the novel method on its dynamic characteristics.

[0392] The example converter is an LLC resonant converter operating from a 400 Vdc bus ( Figure 1 Vin in) and rated for 12 V / 20 A output, characterized by the following key parameters: a = 16, Cr = 39 nF, Ls = 105 μH, Lp = 560 μH. The controller device from Figure 9 has been used. Tests have been done at 10% load, where the peak amplitude of the Vs signal is about 0.26 V. The input offset of the zero-current comparator CO1 has been swept from 0 to 5 mV in 1 mV steps (corresponding to about 2% of the peak amplitude of Vs). The tests show that with the proposed modified TSC method, the mismatch is reduced on average by a factor of 2.

[0393] Repeating the test at half the signal amplitude of Vs, the benefits of the proposed modified TSC method are even more evident. For example, at a 5 mV offset, without performing the proposed compensation, the mismatch of the secondary current exceeds 91% (which means that the output current is almost entirely carried by one rectifier), while with the proposed modified TSC method, the mismatch is reduced by 38.4%, so the factor is 2.4.

[0394] Regarding the dynamic characteristics of the converter, the traditional and the proposed modified TSC are actually equivalent.

[0395] The following reference Figures 21 to 25 provides other embodiments of the present disclosure for enhanced time-shift control (ETSC) applicable to resonant converters. Embodiments that have been disclosed and their operation have been described in detail hereinbefore, and at least some aspects of the embodiments previously described herein will be referred to hereinafter. Figures 1 to 20

[0396] Regarding Figures 1 to 20 at least four different basic ETSC implementations are described. They are based on generating a dual-slope ramp voltage across capacitor C T Figure 6 For example, as shown and described regarding Figure 7 in some embodiments, a dual-slope ramp appears when the capacitor is charged and discharged between two voltage reference levels, such that the waveform is somewhat symmetric. In other embodiments, for example, as Figure 7 shown, the dual-slope ramp only charges the capacitor, while the discharge is instantaneous in an ideal case, thus generating a kind of sawtooth wave. As previously mentioned, in some embodiments, the control loop acts on the charge and discharge currents, and in other embodiments, the control loop acts on one of the reference voltages.

[0397] In the embodiments to be described hereinafter with reference to Figures 21 to 25 the control loop acts on the charge and discharge currents.

[0398] In the embodiments described with reference to Figures 21 to 25 as long as the current in the resonant tank and the applied voltage have opposite signs, the double-slope ramp has a first lower slope in the initial part of each switch half-cycle. While in the remaining part of the switch half-cycle where the current and voltage have the same sign, it has a second steeper slope.

[0399] The first lower slope is associated with a fixed current Io that charges the capacitor throughout the switch half-cycle, while the second steeper slope is associated with the superposition of this fixed current and a second current k*Ic, where k is a constant and Ic is the control current of the control loop that regulates the output voltage (or current) of the converter. For example, this has been described previously herein with respect to Figure 6 and Figure 7 is described.

[0400] Generally, in any implementation or embodiment of the ETSC, the second slope will always be greater than the first slope. This is helpful for the basic objective of the ETSC, that is, it reduces the sensitivity of the input voltage offset of the comparator that senses the sign of the resonant current to the duty cycle of the generated square wave. This offset can cause the duty cycle to deviate from the ideal target of 50%, and in some cases, the sensitivity of the traditional TSC method has become a problem.

[0401] Regarding Figures 21 to 25 The additional embodiments described are based on swapping the currents that act along the switch half-cycle. More specifically, the first lower slope will be determined by the current k*Ic representing the feedback loop, which charges the capacitor throughout the switch half-cycle; the second steeper slope will be determined by the superposition of k*Ic and the fixed current Io.

[0402] Those skilled in the art can easily understand modifying the circuits in Figure 8 and 9 to swap the currents, but Figure 21 and 22 The circuits shown respectively illustrate these embodiments in which the circuits in Figure 8 and 9 are modified to swap the currents. More specifically, Figure 21 The circuit shown is the same as the circuit in Figure 8 with modifications that facilitate the swapping of the charging / discharging currents of capacitor C T . Similarly, Figure 22 The circuit shown is the same as the circuit in Figure 9 with modifications that facilitate the swapping of the charging / discharging currents of capacitor C T .

[0403] Since Figure 8 and 9 In addition, they are respectively the same asFigure 21 and 22 are substantially the same, and thus Figure 21 and 22 the operation of the circuit can be described exactly as previously described herein with respect to the corresponding circuit ( Figure 8 and 9 ), considering only the current exchange, and will not be repeated here.

[0404] Referring to the waveforms shown in Figure 6 , which are related to the circuit shown in Figure 20 , where Vv (e.g., equal to 1V) represents the lower threshold or valley voltage of the waveform on capacitor C T , and Vp (e.g., equal to 4V) represents the upper threshold or peak voltage of the waveform, the equation for the charge of capacitor C T during the switching half - period starting from t = 0 and ending at t = Ts / 2 (where Ts is the switching period and where the slot current changes sign at t = Tz) can be written as:

[0405]

[0406] Note that the commanded time shift T SH is equal to Ts / 2 - Tz, and this equation can be rewritten as:

[0407]

[0408] By solving this equation for T SH , the control law that relates the commanded time shift to the control current Ic can be written as:

[0409]

[0410] Note that the commanded time shift T SH is a linear function of the control current Ic, which is different from the previously described embodiment where the relationship between T SH and I C is hyperbolic.

[0411] Referring to the waveforms shown in Figure 21 related to the circuit shown in Figure 7 , the equations that describe the operation of the associated circuit and the resulting control law can be found from equations (6), (7), and (8), where Vv = 0.

[0412] Ic can be expressed as a function of Tz. Solving equation (6) gives Ic:

[0413]

[0414] Note that the term Tz / Ts is proportional to the current-voltage phase shift Φ:

[0415]

[0416] In the spirit of the first harmonic approximation (FHA) modeling of the resonant converter, it corresponds to the parameter of the input admittance of the resonant tank.

[0417] Making Vp - Vv proportional to Ts will result in direct control of the current-voltage phase shift by Ic. In fact, if λTs is used to replace Vp - Vv in equation (9), the following relationship can be obtained:

[0418]

[0419] This is Figure 23 and 24 the purpose of the circuits shown, where the output of each circuit is a comparator (e.g., Figure 21 and 22 the comparators CO2 or CO3 of the circuits shown) that resets the SR latch or SR flip-flop FF1 and uses the voltage Vp as a reference. In particular, Figure 23 shows the voltage generator circuit 2210 that generates the reference voltage Vp, which can be utilized in the circuit shown in Figure 21 to achieve direct control of the current-voltage phase shift. Figure 24 shows the voltage generator circuit 2310 that generates the reference voltage Vp, which can be utilized in the circuit shown in Figure 22 to achieve direct control of the current-voltage phase shift.

[0420] The key waveforms of the voltage generator circuits 2210 and 2310 are equal to each other and are shown in Figure 25 . Figure 21 and 22 The key waveforms of the resulting embodiments shown are respectively the same as those shown in Figure 6 and 7 .

[0421] Referring to Figures 23 to 25 , the timing capacitor C x is charged with a constant current I x to generate a voltage ramp V Cx . A pulse delivered via the monostable device MF3 (e.g., a pulse delivered at the Q output of the monostable device MF3) samples the peak value V Cx of the voltage ramp V x = I x Ts / C xSampling and holding are performed (e.g., by a sample-and-hold circuit S / H). After a short delay (e.g., a delay longer than the duration of the pulse delivered by MF3), the ramp is reset to zero. The ramp can be reset, for example, by closing switch SW1 (which can be a transistor or any suitable switch in some embodiments). Switch SW1 can be controlled by the output of a delay circuit (Delay), e.g., selectively closed or opened, which can operate based on the pulse transmitted at the Q output of the monostable device MF3. The difference between the voltage generator circuits 2210 and 2310 is that, Figure 23 the voltage generator circuit 2210 of Figure 23 includes an adder that adds a voltage Vv (e.g., equal to 1V) to the voltage signal V x . Thus, in Figure 23 the voltage generator circuit 2210 of Figure 23 (as opposed to Figure 24 the voltage generator circuit 2310 of Figure 24 ), V x is offset by Vv and then output as Vp; thus:

[0422]

[0423] According to one or more embodiments of the present disclosure, controlling the current-voltage phase shift brings many benefits to the controlled system.

[0424] First, assuming that the slot current lags behind the applied square-wave voltage, the converter controlled in this way is absolutely stable regardless of its operating conditions. This constraint is not a practical limitation because soft-switching operation of the switches of the half-bridge (which is an important design goal of resonant converters) is the same necessary condition.

[0425] Second, the control quantity (e.g., Ic in some embodiments) hardly depends on the parameters of the resonant slot and is very insensitive to its tolerance. This robustness is easily understood if it is considered that in a resonant converter designed to operate with soft-switching, when scanning the entire input voltage and load range, the slot current lags behind the applied voltage by an angle between 0° and 90°, regardless of the design and operating frequency range of the resonant slot.

[0426] Finally, directly controlling the phase shift enables the control circuit to cover the entire operating range of the converter with a fixed Ic range. Referring to Equation (11), this implies that limiting the range of Ic to the minimum positive value will limit the minimum phase shift, which will ensure that the necessary conditions for the converter to operate with soft switching are not violated. On the other hand, considering light load operation, since the tank current tends to lag the applied voltage by 90°, regardless of the design of the resonant tank and the input voltage, the value of Ic is more dependent on the load compared to other aspects, so that it can be effectively used as a load monitor. This enables the simple implementation of functions such as burst mode, etc., which are designed to improve the efficiency of the converter at light loads, and are characterized by good repeatability of the starting threshold in mass production.

[0427] Of course, without prejudice to the principles of the present disclosure, the details of the construction and embodiments can vary widely relative to what is described and shown herein by way of example only, without departing from the scope of the present disclosure.

[0428] For example, while mainly referring to LLC resonant converters, the present solution is also applicable to other resonant converters, such as LCC, LLCC, etc. resonant converters.

[0429] Similarly, while mainly referring to a half-bridge configuration, there is no impediment to applying the solution to the problem of converters using a full-bridge configuration, where the resonant tank is connected to the intermediate node between two half-bridges, and the high-side switch of the first half-bridge is switched together with the low-side switch of the second half-bridge, and the low-side switch of the first half-bridge is switched together with the high-side switch of the second half-bridge.

[0430] Moreover, while mainly referring to bipolar transistors, field effect transistors (FETs) can also be used, for example, in order to implement various current generators, current mirrors or electronic switches.

[0431] The various embodiments described above can be combined to provide other embodiments. These and other changes can be made to the embodiments in accordance with the above detailed description. Generally, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Thus, the claims are not limited by the present disclosure.

Claims

1. A driver circuit for a resonant converter configured to generate an output voltage or an output current at two output terminals based on an input voltage applied to a positive input terminal and a negative input terminal, the resonant converter comprising: At least one half-bridge including a high-side electronic switch and a low-side electronic switch connected in series between the positive input terminal and the negative input terminal, wherein an intermediate node between the high-side electronic switch and the low-side electronic switch represents a switching node; And A resonant tank, a rectifier, and a filter circuit connected between the switching node and the two output terminals; Wherein the driver circuit includes: A first terminal and a second terminal configured to be connected to a control terminal of the high-side electronic switch and a control terminal of the low-side electronic switch to drive the half-bridge via respective drive signals; A third terminal configured to be connected to a current sensor to receive a signal proportional to a resonant current flowing from the switching node to the resonant tank, rectifier, and filter circuit; A fourth terminal configured to be connected to a feedback circuit to receive a feedback signal determined based on the output voltage or the output current; A comparator configured to generate a first control signal indicating when the resonant current changes sign based on the signal received at the third terminal; A first ramp generator circuit configured to output a first ramp signal; and A comparison circuit configured to determine whether the first ramp signal reaches at least one reference threshold; Wherein the driver circuit is configured to: During successive first and second switching half-cycles, drive the high-side electronic switch and the low-side electronic switch via the drive signals, wherein each of the first and second switching half-cycles ends when the comparison circuit indicates that the first ramp signal has reached a corresponding reference threshold; Once the first switching half-cycle starts, disconnect the low-side electronic switch and close the high-side electronic switch after a delay; and Once the second switching half-cycle starts, disconnect the high-side electronic switch and close the low-side electronic switch after the delay; Wherein the driver circuit further includes: A control circuit configured to generate one or more control signals in each of the first and second switching half-cycles, the one or more control signals indicating: A first interval starting at the moment when the respective half-cycle starts and ending at the moment when the first control signal indicates that the resonant current has changed sign; and A second interval starting at the moment when the first control signal indicates that the resonant current has changed sign and the moment when the comparison circuit indicates that the first ramp signal has reached a corresponding reference threshold; and A correction circuit configured to: Modify the first ramp signal provided at the input of the comparison circuit such that the first ramp signal has a first gradient value during the first interval and a second gradient value during the second interval, the first gradient value being non-zero and the absolute value of the second gradient value being greater than the absolute value of the first gradient value; or Modify one or more of the reference thresholds of the comparison circuit by adding a second ramp signal to the respective initial threshold.

2. The driver circuit according to claim 1, wherein the driver circuit is configured to: Determine at least one of the first gradient value or the second gradient value according to the feedback signal.

3. The driver circuit according to claim 1, wherein the driver circuit is configured to: Determine at least one of the reference thresholds according to the feedback signal.

4. The driver circuit according to claim 1, wherein the first ramp generator circuit includes an integrator circuit configured to generate the first ramp signal by integrating a first signal, and wherein the correction circuit is configured to modify the first ramp signal by adding a second signal to the first signal at the input of the analog integrator circuit.

5. The driver circuit according to claim 4, wherein the first signal is set to zero during the first interval and to a non-zero value during the second interval, and the second signal is set to a constant non-zero value during the first and second intervals.

6. The driver circuit according to claim 4, wherein the first signal is set to a non-zero value during the first and second intervals, and the second signal is set to zero during the first interval and to a constant non-zero value during the second interval.

7. The driver circuit according to claim 4, wherein the first signal is set to zero during the first interval and to a non-zero value during the second interval, and the second signal is set to a constant non-zero value during the first interval and to zero during the second interval.

8. The driver circuit according to claim 4, wherein the integrator circuit includes an integrating capacitor and the driver circuit includes a first current generator configured to generate the first signal, and the correction circuit includes a second current generator configured to generate the second signal.

9. The driver circuit according to claim 1, wherein the first ramp generator circuit includes a digital counter configured to generate the first ramp signal by incrementing a count value by a step size, and wherein the correction circuit is configured to modify the first ramp signal by: Setting the step size to a first step size value during the first interval and to a second step size value during the second interval; or Setting the clock signal of the digital counter to a first clock signal during the first interval and to a second clock signal during the second interval.

10. The driver circuit according to claim 1, wherein the first ramp generator circuit includes an integrator circuit configured to generate the first ramp signal by integrating a first signal, and wherein the correction circuit is configured to modify the first ramp signal by adding a second ramp signal to the first ramp signal at the output of the analog integrator circuit, and wherein: the first signal is set to zero during the first interval and set to a non-zero value during the second interval, and the second ramp signal corresponds to a linear ramp signal during the first interval and the second interval; or the first signal is set to a non-zero value during the first interval and the second interval, and the second ramp signal corresponds to zero during the first interval and corresponds to a linear ramp signal during the second interval.

11. The driver circuit according to claim 1, wherein the first ramp generator circuit includes an integrator circuit configured to generate the first ramp signal by integrating a first signal, and wherein the correction circuit is configured to modify one or more of the reference thresholds of the comparison circuit by adding a second ramp signal to a corresponding initial threshold.

12. The driver circuit according to claim 11, wherein the first signal is set to zero during the first interval and set to a non-zero value during the second interval, and the second ramp signal corresponds to a linear ramp signal during the first interval and the second interval.

13. The driver circuit according to claim 11, wherein the first signal is set to a non-zero value during the first interval and the second interval, and the second ramp signal corresponds to zero during the first interval and corresponds to a linear ramp signal during the second interval.

14. The driver circuit according to claim 1, wherein: during one switching half-cycle of the first switching half-cycle and the second switching half-cycle, the first ramp generator circuit is configured to increase the first ramp signal, and the comparison circuit is configured to determine whether the first ramp signal reaches an upper reference threshold; and during the other switching half-cycle of the first switching half-cycle and the second switching half-cycle, the first ramp generator circuit is configured to decrease the first ramp signal, and the comparison circuit is configured to determine whether the first ramp signal reaches a lower reference threshold.

15. The driver circuit according to claim 1, wherein during each of the first switching half-cycle and the second switching half-cycle, the first ramp generator circuit is configured to increase the first ramp signal, and the comparison circuit is configured to determine whether the first ramp signal reaches an upper reference threshold, wherein when the first ramp signal reaches the upper reference threshold, the first ramp signal is reset.

16. The driver circuit according to claim 1, wherein during each of the first switching half - period and the second switching half - period, the first ramp generator circuit is configured to decrease the first ramp signal, and the comparison circuit is configured to determine whether the first ramp signal reaches a lower reference threshold, wherein when the first ramp signal reaches the lower reference threshold, the first ramp signal is reset.

17. An integrated circuit comprising the driver circuit according to claim 1, wherein the first terminal, the second terminal, the third terminal, and the fourth terminal of the driver circuit are connected to respective pins of the integrated circuit.

18. An electronic converter comprising: a positive input terminal and a negative input terminal; two output terminals for providing an output voltage or an output current; at least one half - bridge including a high - side electronic switch and a low - side electronic switch connected in series between the positive input terminal and the negative input terminal, wherein an intermediate node between the high - side electronic switch and the low - side electronic switch represents a switching node; a resonant tank, a rectifier, and a filter circuit connected between the switching node and the two output terminals; a current sensor configured to generate a signal proportional to a resonant current flowing from the switching node to the resonant tank, rectifier, and filter circuit; a feedback circuit configured to generate a feedback signal determined according to the output voltage or the output current; and a driver circuit, the driver circuit comprising: a first terminal and a second terminal configured to be connected to a control terminal of the high - side electronic switch and a control terminal of the low - side electronic switch to drive the half - bridge via respective drive signals; a third terminal configured to be connected to the current sensor to receive a signal proportional to the resonant current flowing from the switching node to the resonant tank, rectifier, and filter circuit; a fourth terminal configured to be connected to the feedback circuit to receive a feedback signal determined according to the output voltage or the output current; a comparator configured to generate a first control signal indicating when the resonant current changes sign according to the signal received at the third terminal; a first ramp generator circuit configured to output a first ramp signal; and a comparison circuit configured to determine whether the first ramp signal reaches at least one reference threshold; wherein the driver circuit is configured to: during consecutive first and second switching half - periods, drive the high - side electronic switch and the low - side electronic switch via the drive signals, wherein each of the first and second switching half - periods ends when the comparison circuit indicates that the first ramp signal has reached a corresponding reference threshold; once the first switching half - period starts, disconnect the low - side electronic switch and close the high - side electronic switch after a delay; and Once the second switching half - cycle begins, the high - side electronic switch is turned off after the delay and the low - side electronic switch is turned on; wherein the driver circuit further comprises: a control circuit configured to generate one or more control signals in each of the first switching half - cycle and the second switching half - cycle, the one or more control signals indicating: a first interval that begins at the moment when the respective half - cycle begins and ends at the moment when the first control signal indicates that the resonant current has changed sign; and a second interval that begins at the moment when the first control signal indicates that the resonant current has changed sign and at the moment when the comparison circuit indicates that the first ramp signal has reached a respective reference threshold; and a correction circuit configured to: modify the first ramp signal provided at the input of the comparison circuit such that the first ramp signal has a first gradient value during the first interval and a second gradient value during the second interval, the first gradient value being non - zero and the absolute value of the second gradient value being greater than the absolute value of the first gradient value; or modify one or more of the reference thresholds of the comparison circuit by adding a second ramp signal to a respective initial threshold.

19. The electronic converter according to claim 18, wherein the resonant tank, rectifier, and filter circuit comprises: a transformer including a primary winding and a secondary winding; a capacitor and a first inductor connected in series with the primary winding between the switching node and the positive input terminal or the negative input terminal; a second inductor connected in parallel with the primary winding; and a rectifier circuit connected between the secondary winding and the two output terminals.

20. A method of operating an electronic converter according to claim 18, comprising: during successive first and second switching half - cycles, driving the high - side electronic switch and the low - side electronic switch by: once the first switching half - cycle begins, turning off the low - side electronic switch and turning on the high - side electronic switch after the delay; once the second switching half - cycle begins, turning off the high - side electronic switch and turning on the low - side electronic switch after the delay; and in each of the first and second switching half - cycles: determining when the resonant current changes sign; generating a first ramp signal and determining when the first ramp signal reaches at least one reference threshold; determining a first interval that begins at the moment when the respective half - cycle begins and ends at the moment when the resonant current changes sign; determining a second interval that begins at the moment when the resonant current changes sign and at the moment when the first ramp signal reaches a respective reference threshold; and Modify the first ramp signal provided at the input of the comparison circuit such that the first ramp signal has a first gradient value during the first interval and a second gradient value during the second interval, the first gradient value being a non-zero value and the absolute value of the second gradient value being greater than the absolute value of the first gradient value; or Modify one or more of the reference thresholds by adding a second ramp signal to the respective initial threshold.

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