A gate driving circuit

Abstract

The present invention discloses a gate driving circuit, which includes a left circuit and a driving circuit. The left circuit includes a high-voltage power supply VCC, a Q1 triode, a Q2 triode, a d1 diode, a dz1 Zener diode, a dz2 Zener diode, a dz3 Zener diode, a C1 capacitor, an I1 bias current source, an I2 bias current source, an N1 MOS transistor, an N2 MOS transistor, an N3 MOS transistor, and an N4 MOS transistor. The driving circuit includes an INV1 driver, the INV1 driver is connected to an INV2 driver, the INV2 driver is connected to an HN1 driving transistor, the drain of the HN1 driving transistor is connected to the source of an HP3 driving transistor, the drain of the HP3 driving transistor is connected to the source of an HP1 driving transistor and the gate of an HP2 driving transistor, the source of the HP2 driving transistor is connected to the drain of an HP4 driving transistor, the source of the HP4 driving transistor is connected to the drain of an HN2 driving transistor, the drain of the HP4 driving transistor is connected to the gate of the HP1 driving transistor. The HN1 driving transistor, the HN2 driving transistor, the HP1 driving transistor, the HP2 driving transistor, the HP3 driving transistor, and the HP4 driving transistor form a level shift circuit. This driving circuit can ensure safe operation even in a thin gate oxide process.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supply circuits, and particularly to a gate drive circuit. Background Art

[0002] In a switching power supply topology, there is always a power switching transistor, so it is called a switching power supply. However, this power switching transistor requires a drive circuit to control its switching. Usually, the drive circuit is integrated in a control IC. When designing the IC, the operating voltage of its power supply pin is usually between 10V and 30V. A higher power supply voltage can, on the one hand, ensure that the driving ability of the IC is strong enough, and on the other hand, a wider operating voltage range can ensure that the IC can better adapt to various working environments and has strong adaptability. However, in IC design, a low-voltage internal power supply (such as 5V) is usually designed. By adopting a low-power supply design, a large number of low-voltage transistors can be used inside the IC, so the integration degree of the IC can be greatly improved. This is also the development trend of IC design. The typical driving circuit structure inside the IC is as Figure 1 shown. P1 / N1 are low-voltage transistors, HN1~HN6, HP1~HP6 are high-voltage transistors, the DRV signal is a low-voltage driving signal processed by logic inside the IC, the Gate signal is the driving output signal of the IC, VDD is the low-voltage power supply inside the IC, VCC is the high-voltage power supply of the IC pin, and N1 / P1 / HN1 / HN2 / HP1 / HP2 form a level shift circuit, which can convert the low-level DRV signal into a high-level signal. After passing through the driving circuit with 4 groups of driver structures behind, the driving ability is enhanced step by step, and finally an output signal Gate with strong driving ability is obtained. Of course, some structures will make some improvements, and a dead time is designed for the last-stage driving transistors HP6 / HN6 to prevent HP6 and HN6 from conducting simultaneously and being damaged. However, the core idea is within this structural framework. The application premise of this driving structure is that not only the drain-source terminal (Vds) of the high-voltage transistor can withstand high voltage, but also the gate oxide (Vgs) can withstand high voltage without being damaged. In a large number of process technologies, usually, by adding a photolithography mask, thick gate oxide and thin gate oxide can be realized simultaneously. The thick gate oxide has higher breakdown voltage. By adopting the thick gate oxide design in high-voltage transistors, the gate oxide can be well protected from being broken down. Therefore, this driving structure can be widely adopted. However, in some smaller-size process technologies, such as the 0.18um process, many Fabs do not provide the option of thick gate oxide and thin gate oxide, but only provide thin gate oxide. If this driving circuit continues to be used, it is bound to cause damage to the high-voltage transistor due to insufficient breakdown voltage of the gate oxide. Summary of the Invention

[0003] To solve the above problems, the present invention provides a gate driving circuit that can ensure safe operation even in a thin gate oxide process. The circuit includes a left circuit and a driving circuit. The left circuit generates a low-voltage power supply VDDL and a high-voltage signal VDDH. The right part is the driving circuit. VCC is the high-voltage power supply that powers both the left and right circuits. The left circuit includes a high-voltage power supply VCC, a Q1 transistor, a Q2 transistor, a d1 diode, a dz1 Zener diode, a dz2 Zener diode, a dz3 Zener diode, a C1 capacitor, an I1 bias current source, an I2 bias current source, an N1 MOS transistor, an N2 MOS transistor, an N3 MOS transistor, and an N4 MOS transistor. The I1 bias current source is connected to the drain of the N1 MOS transistor and provides a bias current for the N1 MOS transistor. The I2 bias current source is connected to the base of the Q1 transistor. The gate of the N1 MOS transistor is connected to the gate of the N2 MOS transistor. The drain and gate of the N1 MOS transistor are connected to the gate of the N2 MOS transistor. The d1 diode and the dz1 Zener diode are connected to the base of the Q1 transistor. The emitter of the Q1 transistor is connected to the base of the Q2 transistor and the drain of the N2 MOS transistor. The emitter of the Q2 transistor is connected to the drain of the N3 MOS transistor to output VDDL. There is a dz2 Zener diode between VDDL and the ground, which usually does not break down and serves a protective function. The drain of the N4 MOS transistor is connected to the high-voltage power supply VCC through the dz3 Zener diode and the C1 capacitor. The driving circuit includes an INV1 driver, which is connected to an INV2 driver. The INV2 driver is connected to an HN1 driving transistor. The drain of the HN1 driving transistor is connected to the source of an HP3 driving transistor. The drain of the HP3 driving transistor is connected to the source of an HP1 driving transistor and the gate of an HP2 driving transistor. The source of the HP2 driving transistor is connected to the drain of an HP4 driving transistor. The source of the HP4 driving transistor is connected to the drain of an HN2 driving transistor. The drain of the HP4 driving transistor is connected to the gate of the HP1 driving transistor. The HN1 driving transistor, the HN2 driving transistor, the HP1 driving transistor, the HP2 driving transistor, the HP3 driving transistor, and the HP4 driving transistor form a level shift circuit, and the output is connected to the gate of an HP5 driving transistor. The source of the HP5 driving transistor is connected to the drain of an HP6 driving transistor. The source of the HP6 driving transistor is connected to the drain of an HN3 driving transistor. The HN3 driving transistor, the HP6 driving transistor, and the HP5 driving transistor form a driver, and the output voltage is connected to the gate of an HP7 driving transistor. The HN4 driving transistor is driven by the INV4 to INV7 drivers in a step-by-step amplification manner. The source of the HP7 driving transistor is connected to the drain of the HN4 driving transistor. The INV1 driver is connected to an INV3 driver, and the INV3 driver is connected to the gate of the HN3 driving transistor. DRV is a low-voltage driving signal, and Gate is the driving output signal.

[0004] As an improvement of the present invention, the N1MOS tube, N2MOS tube, N3MOS tube and N4MOS tube form a current mirror, and the Q1 transistor and the Q2 transistor form a power supply structure with a relatively strong current capability.

[0005] As an improvement of the present invention, the gate electrodes of the HP3 driving tube, the HP4 driving tube and the HP6 driving tube are connected to the VDDH high voltage signal.

[0006] As an improvement of the present invention, the drain electrodes of the HP1 driving tube, the HP2 driving tube, the HP5 driving tube and the HP7 driving tube are connected, and the source electrodes of the HN1 driving tube, the HN2 driving tube and the HN3 driving tube are connected.

[0007] As an improvement of the present invention, the circuit also includes an INV4 driver, an INV5 driver, an INV6 driver and an INV7 driver, the INV1 driver is connected to the INV4 driver, INV5 driver, INV6 driver and INV7 driver in sequence, the INV7 driver is connected to the gate of the HN4 driver tube, and the INV4~INV7 drivers have a step-by-step driving enhancement effect.

[0008] As an improvement of the present invention, the INV1 to INV7 drivers are low-voltage drivers, and their power supply is VDDL.

[0009] The beneficial effects of the present invention are as follows: the gate-source voltage of the MOS device in the gate drive circuit provided by the present invention will not exceed 4.8V, and the voltage resistance requirement for the gate oxide is not high, which can ensure that it can work safely even in a thin gate oxide process. It is very suitable for some processes that do not provide gate oxide thickness selection, and as the lithography size continues to shrink, the application prospects of the drive circuit structure of the present invention continue to improve. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a structural diagram of the existing driving circuit described in the background technology.

[0011] Figure 2 This is a structural diagram of the gate drive circuit described in the present invention.

[0012] Figure 3 This is the left circuit structure diagram described in the present invention.

[0013] Figure 4 This is a structural diagram of the driving circuit described in the present invention. DETAILED DESCRIPTION

[0014] The following is combined with Figures 2 to 4 The present invention will be further illustrated with the following specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0015] Embodiment: The circuit includes a left circuit and a driving circuit. The left circuit generates a low-voltage power supply VDDL and a high-voltage signal VDDH. The right part is the driving circuit. VCC is the high-voltage power supply that supplies power to the circuits on both the left and right sides. The left circuit includes the high-voltage power supply VCC, transistor Q1, transistor Q2, diode d1, Zener diode dz1, Zener diode dz2, Zener diode dz3, capacitor C1, bias current source I1, bias current source I2, MOS transistor N1, MOS transistor N2, MOS transistor N3, and MOS transistor N4. The bias current source I1 is connected to the drain of the MOS transistor N1, and the bias current source I1 provides a bias current for the MOS transistor N1. The bias current source I2 is connected to the base of the transistor Q1. The gate of the MOS transistor N1 is connected to the gate of the MOS transistor N2, and the drain and gate of the MOS transistor N1 are connected to the gate of the MOS transistor N2. The diode d1 and the Zener diode dz1 are connected to the base of the transistor Q1. The emitter of the transistor Q1 is connected to the base of the transistor Q2 and the drain of the MOS transistor N2. The emitter of the transistor Q2 is connected to the drain of the MOS transistor N3 to output VDDL. There is a Zener diode dz2 between VDDL and the ground, which usually does not break down and plays a protective role. The drain of the MOS transistor N4 is connected to the high-voltage power supply VCC through the Zener diode dz3 and the capacitor C1. The driving circuit includes an INV1 driver, the INV1 driver is connected to an INV2 driver, the INV2 driver is connected to an HN1 driving transistor. The drain of the HN1 driving transistor is connected to the source of an HP3 driving transistor. The drain of the HP3 driving transistor is connected to the source of an HP1 driving transistor and the gate of an HP2 driving transistor. The source of the HP2 driving transistor is connected to the drain of an HP4 driving transistor. The source of the HP4 driving transistor is connected to the drain of an HN2 driving transistor. The drain of the HP4 driving transistor is connected to the gate of the HP1 driving transistor. The HN1 driving transistor, HN2 driving transistor, HP1 driving transistor, HP2 driving transistor, HP3 driving transistor, and HP4 driving transistor form a level shift circuit, and the output is connected to the gate of an HP5 driving transistor. The source of the HP5 driving transistor is connected to the drain of an HP6 driving transistor. The source of the HP6 driving transistor is connected to the drain of an HN3 driving transistor. The HN3 driving transistor, HP6 driving transistor, and HP5 driving transistor form a driver, and the output voltage is connected to the gate of an HP7 driving transistor. The HN4 driving transistor is driven by several levels of drivers in a step-by-step amplification manner. The source of the HP7 driving transistor is connected to the drain of the HN4 driving transistor. The INV1 driver is connected to an INV3 driver, and the INV3 driver is connected to the gate of the HN3 driving transistor. DRV is a low-voltage driving signal, and Gate is a driving output signal.

[0016] The N1MOS tube, N2MOS tube, N3MOS tube and N4MOS tube form a current mirror, the Q1 transistor and the Q2 transistor form a power supply mechanism with strong current capacity, the gates of the HP3 driving tube, HP4 driving tube and HP6 driving tube are connected to the VDDH high-voltage signal, the drains of the HP1 driving tube, HP2 driving tube, HP5 driving tube and HP7 driving tube are connected, the sources of the HN1 driving tube, HN2 driving tube and HN3 driving tube are connected, the circuit also includes an INV4 driver, an INV5 driver, an INV6 driver and an INV7 driver, the INV1 driver is connected to the INV4 driver, INV5 driver, INV6 driver and INV7 driver in sequence, the INV7 driver is connected to the gate of the HN4 driving tube, the INV1 to INV7 drivers are low-voltage drivers, and their power supply is VDDL.

[0017] Working principle: Circuit on the left: The base voltage of Q1 transistor is clamped at Vdz+Vd1, about 6.2V, so the low-voltage power supply VDDL generated is Vdz+Vd1-2Vbe, about 4.8V; and the high-voltage signal VDDH generated is VCC-Vdz, that is, VDDH always remains 5.5V lower than VCC.

[0018] Circuit on the right: When DRV is high, the gate voltage of the HN1 driver is VDDL (4.8V), the gate voltage of the HN2 driver is 0V, and the source voltage of the HP3 driver is pulled down to VDDH+VSG_HP3. Here, VSG_HP3 is the threshold voltage of the HP3 driver, which is about 0.7V. For the HP2 driver, its gate-source voltage is VCC- VDDH-VSG_HP3, which is about 4.8V. Similarly, when DRV is low, the gate voltage of the HN1 driver is 0V, the gate voltage of the HN2 driver is VDDL (4.8V), and the gate-source voltage of the HP1 driver is also 4.8V. When DRV is high, the gate voltage of the HN3 driver is 4.8V, the gate voltage of the HP5 driver is VCC, and the source voltage of the HP6 driver is VDDH+VSG_HP6, which means that the HP7 driver The gate-source voltage of the driving tube is also 4.8V, and the HP7 driving tube is turned on; the gate voltage of the HN4 driving tube is 0V, and the output Gate of the driving circuit is a high level VCC. Similarly, when DRV is a low level, the gate-source voltage of the HP7 driving tube is 0V, the gate voltage of the HN4 driving tube is VDDL (4.8V), and the output Gate of the driving circuit is 0V. In this circuit structure, the gate-source voltage of all MOS devices will not exceed 4.8V, and the voltage resistance requirement for the gate oxide is not high.

[0019] In the description of the present invention, it should be noted that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, unless otherwise clearly specified and defined, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium. It can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0020] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or equivalently replace some or all of the technical features, and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate driving circuit, characterized in that, The circuit includes a left circuit and a drive circuit. The left circuit includes a high-voltage power supply VCC, a Q1 transistor, a Q2 transistor, a d1 diode, a dz1 Zener diode, a dz2 Zener diode, a dz3 Zener diode, a C1 capacitor, an I1 bias current source, an I2 bias current source, an N1 MOS transistor, an N2 MOS transistor, an N3 MOS transistor, and an N4 MOS transistor. The I1 bias current source is connected to the drain of the N1 MOS transistor. The I2 bias current source is connected to the base of the Q1 transistor. The gate of the N1 MOS transistor is connected to the gate of the N2 MOS transistor. The drain and gate of the N1 MOS transistor are connected to the gate of the N2 MOS transistor. The d1 diode and the dz1 Zener diode are connected to the base of the Q1 transistor. The emitter of the Q1 transistor is connected to the base of the Q2 transistor and the drain of the N2 MOS transistor. The emitter of the Q2 transistor is connected to the drain of the N3 MOS transistor and outputs VDDL. There is a dz2 Zener diode between VDDL and the ground. The N4 MOS transistor is connected to the high-voltage power supply VCC through the dz3 Zener diode and the C1 capacitor. The drive circuit includes an INV1 driver. The INV1 driver is connected to an INV2 driver. The INV2 driver is connected to an HN1 drive transistor. The drain of the HN1 drive transistor is connected to the source of an HP3 drive transistor. The drain of the HP3 drive transistor is connected to the source of an HP1 drive transistor and the gate of an HP2 drive transistor. The source of the HP2 drive transistor is connected to the drain of an HP4 drive transistor. The source of the HP4 drive transistor is connected to the drain of an HN2 drive transistor. The drain of the HP4 drive transistor is connected to the gate of the HP1 drive transistor. The HN1 drive transistor, the HN2 drive transistor, the HP1 drive transistor, the HP2 drive transistor, the HP3 drive transistor, and the HP4 drive transistor form a level-shifting circuit, and the output is connected to the gate of an HP5 drive transistor. The source of the HP5 drive transistor is connected to the drain of an HP6 drive transistor. The source of the HP6 drive transistor is connected to the drain of an HN3 drive transistor. The HN3 drive transistor, the HP6 drive transistor, and the HP5 drive transistor form a driver, and the output voltage is connected to the gate of an HP7 drive transistor. The source of the HP7 drive transistor is connected to the drain of an HN4 drive transistor. The INV1 driver is connected to an INV3 driver, and the INV3 driver is connected to the gate of the HN3 drive transistor.

2. The gate driving circuit according to claim 1, wherein The gates of the HP3 drive transistor, the HP4 drive transistor, and the HP6 drive transistor are connected to the VDDH high-voltage signal.

3. The gate driving circuit according to claim 2, wherein The drains of the HP1 drive transistor, the HP2 drive transistor, the HP5 drive transistor, and the HP7 drive transistor are connected together. The sources of the HN1 drive transistor, the HN2 drive transistor, and the HN3 drive transistor are connected together.

4. The gate driving circuit according to claim 3, wherein The circuit further includes an INV4 driver, an INV5 driver, an INV6 driver, and an INV7 driver. The INV1 driver is sequentially connected to the INV4 driver, the INV5 driver, the INV6 driver, and the INV7 driver. The INV7 driver is connected to the gate of the HN4 drive transistor.

5. The gate driving circuit according to claim 4, wherein The INV1 to INV7 drivers are low-voltage drivers, and their power supply is VDDL.

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