Semiconductor device

Abstract

Embodiments of the present disclosure relate to a semiconductor device. The semiconductor device has a split-gate type MONOS structure using a FinFET, and includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel formation layer formed under a control gate and formed of a semiconductor layer doped with a p-type impurity, and a second channel formation layer formed under a memory gate and formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer formed under the second channel formation layer and having a higher impurity concentration than an impurity concentration of a semiconductor substrate.

Description

[0001] Cross Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2019-205649 filed on November 13, 2019, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to semiconductor devices, and particularly to a technology suitable for semiconductor devices including a transistor having a fin structure (FinFET: Fin Field Effect Transistor). BACKGROUND

[0004] Flash memories have been widely used as electrically writable and erasable nonvolatile memories. These storage devices have a charge-trapping insulating film under a gate electrode of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), and are configured to use a charge accumulation state in the charge-trapping insulating film as storage information, and read it out as a threshold value of the transistor. The charge-trapping insulating film mentioned here is an insulating film capable of accumulating electric charges, and examples thereof include a silicon nitride film. By shifting the threshold value of the MISFET by injecting electric charges into such a charge accumulation film and emitting electric charges from the charge accumulation film, the MISFET can be used as a nonvolatile memory. This flash memory is also called a MONOS (Metal Oxide Nitride Oxide Semiconductor) transistor.

[0005] In addition, a split-gate type memory cell has been widely used, which uses a MONOS transistor as a memory transistor, and further adds a control transistor. Additionally, a FinFET has been recognized as a field effect transistor capable of achieving an improvement in operation speed, a reduction in leakage current and power consumption, and a miniaturization of semiconductor elements. The FinFET is, for example, a semiconductor element configured to have a semiconductor layer protruding on a semiconductor substrate as a channel region, and a gate electrode formed so as to straddle the protruding semiconductor layer. Japanese Unexamined Patent Application Publication No. 2017-45860 (Patent Literature 1) discloses an example of a FinFET. SUMMARY

[0006] First, features in the operation of the FinFET will be described. The FinFET is characterized by having a dual-gate structure in which a gate is arranged on both sides of a fin serving as a channel. Therefore, the FinFET has a flat potential distribution in the channel. Figure 1A The potential distribution of the FinFET in the channel depth direction is shown, and Figure 1BThe potential distribution in the channel depth direction of a conventional planar MOSFET is shown. Note that Figure 1A and Figure 1B The potential distribution in the case where both FETs are N-type MOSFETs is shown schematically.

[0007] The potential distribution is formed by the bias applied between the substrate and the gate. The potential distribution depends on the impurity concentration doped into the channel. In order to suppress characteristic degradation due to short channel effects, it is necessary to increase the impurity concentration of the channel, and thus as Figure 1B shown, the potential distribution becomes steep in a conventional planar MOSFET. That is, the difference between the gate potential Vg and the substrate potential Vsub is large.

[0008] On the other hand, as Figure 1A shown, a gate electrode having the same potential is arranged on both sides of the fin in a FinFET, and the surfaces on both sides of the channel have the same potential. Thus, the difference between the gate potential Vg and the substrate potential Vsub is small. In a FinFET, short channel effects can be suppressed by this dual-gate structure, and thus the impurity concentration can be kept low. Thus, the potential distribution in the channel is almost flat as Figure 1A schematically shown in the middle, that is, the vertical electric field can become extremely small.

[0009] When the operation of a transistor is considered, many advantages such as high inversion layer mobility and noise reduction can be obtained by a weak vertical electric field, and this is considered to be the reason why a FinFET is used as a standard device structure. Note that in Figure 1A and Figure 1B , the reference numerals φC, φV, and EF indicate the conduction band, the valence band, and the Fermi level in the energy band.

[0010] On the other hand, in a split-gate type memory having a charge-trapping insulating film, at the time of writing and erasing, charge injection to the charge retention portion and charge extraction from the charge retention portion can be performed by using a vertical electric field. Thus, if the vertical electric field is low, there is a problem that writing efficiency and erasing efficiency deteriorate.

[0011] The structure of a memory cell MC of a MONOS transistor will be described below with reference to Figure 2 . The memory cell MC includes a control gate CG serving as a word line WL, a memory gate MG serving as a writing and erasing electrode, a drain DR arranged on the side of the control gate CG and formed of an n + -type diffusion layer, and a source SR arranged on the side of the memory gate MG and formed of an n +A control gate CG controls a channel formation layer CGC under the control gate CG via a gate insulating film GI by a field effect, the control gate CG is formed in a surface of a p-type substrate PSUB, and a memory gate MG controls a channel MGC under the memory gate MG via a charge trapping film CTF.

[0012] In addition, a predetermined potential is supplied to each of the drain DR, the source SR, the p-type substrate PSUB, and the memory gate MG via the bit line BL, the source line SL, the substrate potential line VSUB, and the sub word line SWL. Generally, the names of the source and the drain are used depending on the flow direction of the channel carriers, but since the split gate type MONOS has an asymmetric structure, for convenience, the names of the source and the drain are used as the electrode names of the specific diffusion layer. Thus, depending on the operation mode, the carriers can flow from the drain electrode to the source electrode.

[0013] In the split gate type MONOS, by using SSI (source side injection) in writing, electrons are injected into the charge trapping film by a vertical electric field. In erasing, holes are injected into the charge trapping film by being accelerated by a horizontal electric field of the MG channel, the holes being generated by band to band tunneling at the end of the diffusion layer (source). Thus, a low vertical electric field in the channel has a poor effect on the writing characteristics.

[0014] As described above, an important problem when formed by the split gate type MONOS using the FinFET is to improve the writing characteristics.

[0015] Other problems and novel features will become apparent from the description and drawings.

[0016] A semiconductor device according to one embodiment has a split gate type MONOS structure using a FinFET, and includes a source and a drain each formed by an n-type impurity diffusion layer; a first channel formation layer formed under a control gate and formed by a semiconductor layer doped with a p-type impurity; and a second channel formation layer formed under a memory gate and formed by a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer formed under the second channel formation layer and having a higher impurity concentration than that of a semiconductor substrate.

[0017] By the semiconductor device according to the embodiment, the writing characteristics of the split gate type MONOS using the FinFET can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1A is a potential distribution diagram of the FinFET structure researched by the inventor;

[0019] Figure 1B is a potential distribution diagram in a planar MOSFET structure researched by the inventors;

[0020] Figure 2 is a cross-sectional view showing a main part of a split-gate type MONOS memory cell researched by the inventors;

[0021] Figure 3 is a circuit diagram showing a memory module configuration according to an embodiment;

[0022] Figure 4 is a planar layout diagram showing a split-gate type MONOS using a FinFET according to an embodiment;

[0023] Figure 5A is a cross-sectional view showing a main part of a unit cell UC corresponding to a line A-A in Figure 4

[0024] Figure 5B is a cross-sectional view showing a main part of a unit cell UC corresponding to a line B-B in Figure 4

[0025] Figure 6 is a band diagram showing a potential distribution of a channel formation layer in a write operation of a split-gate type MONOS using a FinFET according to an embodiment;

[0026] Figure 7A is a cross-sectional view showing a main part in a manufacturing process of a split-gate type MONOS using a FinFET according to an embodiment;

[0027] Figure 7B is a cross-sectional view showing a main part in a manufacturing process of a split-gate type MONOS using a FinFET according to an embodiment;

[0028] Figure 8A is a cross-sectional view showing a main part in a manufacturing process of a split-gate type MONOS using a FinFET after Figure 7A

[0029] is a cross-sectional view showing a main part in a manufacturing process of a split-gate type MONOS using a FinFET after Figure 8B Figure 7B is a cross-sectional view showing a main part in a manufacturing process of a split-gate type MONOS using a FinFET after

[0030] Figure 9A Figure 8A is a cross-sectional view showing a main part in a manufacturing process of a split-gate type MONOS using a FinFET after ​​​​

[0031] Figure 9B is a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET; Figure 8B After that, a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET;

[0032] Figure 10A is a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET; Figure 9A After that, a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET;

[0033] Figure 10B is a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET; Figure 9B After that, a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET;

[0034] Figure 11A is a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET; Figure 10A After that, a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET;

[0035] Figure 11B is a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET; Figure 10B After that, a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET;

[0036] Figure 12A is a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET; Figure 11A After that, a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET;

[0037] Figure 12B is a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET; Figure 11B After that, a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET;

[0038] Figure 13A is a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET; Figure 12A After that, a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET;

[0039] Figure 13B is a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET; Figure 12B After that, a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET;

[0040] Figure 14 is a cross-sectional view showing a main part of a manufacturing process of a split gate type MONOS using a FinFET;

[0041] Figure 15is a cross-sectional view showing a main part of a modification of a manufacturing process of a split-gate type MONOS using a FinFET according to an embodiment;

[0042] Figure 16 is a potential distribution diagram showing a comparison of potential distribution between a cumulative mode and an inversion mode at the same gate bias in a split-gate type MONOS using a FinFET according to an embodiment;

[0043] Figure 17 is a bias condition diagram showing one example of conditions of applied biases during operation of a split-gate type MONOS using a FinFET according to an embodiment; and

[0044] Figure 18 is a bias condition diagram showing another example of conditions of applied biases during operation of a split-gate type MONOS using a FinFET according to an embodiment. DETAILED DESCRIPTION

[0045] A semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings. Note that in the specification and the drawings, the same components or corresponding components are denoted with the same reference numerals, and repeated description thereof will be omitted. Also, the embodiments and each modification can be combined with each other at least in part as needed. Furthermore, in some cases, in order to make the drawings easy to see, a diagonal line indicating that a cross section is not hollow can be omitted in a cross-sectional view. If the cross section is hollow, the fact that the cross section is hollow is obviously described in the specification.

[0046] The symbols "n - " and "p + " indicate the relative concentration of an n-conductivity-type or p-conductivity-type impurity. For example, in the case of an n-type impurity, the impurity concentration becomes higher in the order of "n -- ", "n - ", "n", "n + ", and "n ++ ".

[0047] (First Embodiment)

[0048] A semiconductor device according to a first embodiment will be described with reference to Figure 3 to FIG. 5. First, typical operation in a case where a nonvolatile memory array is configured by using a semiconductor device having a split-gate type MONOS structure will be described. In the split-gate type MONOS structure, a split-gate structure including at least a control gate CG and a memory gate MG is employed.

[0049] Figure 3 A typical array configuration is shown. Figure 3One example of a nonvolatile memory module is shown, and is an equivalent circuit diagram showing the connection relationship of four memory cells MC of a plurality of memory cells MC. Each control gate CG is electrically connected to a word line driver circuit WLD for the control gate CG, each memory gate MG is electrically connected to a memory gate driver circuit MGD for the memory gate MG, the source SR is electrically connected to a source line driver circuit SLD for a source line, and the drain DR is electrically connected to a bit line driver circuit BLD for a bit line. In addition, a predetermined potential is applied to the semiconductor substrate PSUB by a substrate voltage circuit VGEN.

[0050] Figure 4 One example of a planar layout of the memory cell array shown in Figure 3 Figure 4 In Figure 2 , the portion enclosed by the broken line is a unit cell UC, and the cross-sectional structure including the fin FN along the line A-A is shown in

[0051] Figure 17 The operation mode of a typical memory cell MC having a split gate type MONOS structure as shown in Figure 2 is shown. The bias conditions at the terminals in the respective operations are shown by the signs of the ground potential GND and the power supply voltage Vcc in the upper table A such as in Figure 17 , and by the example of a specific voltage (unit: V) in a device assuming 1.5 V such as in the lower table B in Figure 17 . Since the writing uses a source side injection method, and the hot carrier electrons generated in the channel are injected into the charge trapping film, the channel of the memory transistor and the selection transistor enters the on state, and a high memory gate voltage VMG is applied.

[0052] ​On the other hand, since holes are generated by the interband tunnel phenomenon in the electric field between the source line SL and the memory gate MG in erasing, a negative memory gate voltage VMG is applied. The generated holes are accelerated by the electric field to inject them into the charge trapping film, whereby erasing is performed. In the read operation, the transistor is brought into the on state by setting the source line SL to the ground potential, setting the bit line BL to the power supply voltage, and applying the power supply voltage to the control gate CG, and the operation on the nonvolatile memory cell MC is obtained by reading the charge trapping state of the memory gate MG as the amplitude of the current value.

[0053] Next, the structure of a typical memory cell MC according to the first embodiment will be described with reference to Figure 5A and Figure 5B Figure 5A corresponding to the A-A cross section in Figure 4 , and Figure 5B corresponding to the B-B cross section in Figure 4 . In the cell structure shown in Figure 2 , the channel formation layer MGC formed in the fin FN is formed of an n-type impurity doped layer, and a p-type semiconductor layer BP (buried type) formed of a p-type impurity doped layer is provided below the channel formation layer MGC. The impurity concentration of the p-type semiconductor layer BP is set to be higher than the impurity concentration of the semiconductor substrate. Preferably, the impurity concentration of the p-type semiconductor layer BP is set to be higher than the impurity concentration of the channel formation layer CGC.

[0054] Figure 6 The potential distribution of the channel formation layer MGC when the write operation is performed in this channel structure is shown. It can be seen that since the channel formation layer MGC is formed of an n-type semiconductor layer, when the conduction band φC is bent by the field effect to the source potential φS, sufficient carrier accumulation occurs so that the bias applied to the memory gate MG is in turn applied to the gate insulating film, which is the charge trapping film CTF, and a high electric field is generated. At this time, when viewed from the cross-sectional structure including the fin FN, since the source potential φS penetrates into the channel formation layer MGC, a high electric field is generated at the PN junction formed at the boundary between the channel formation layer CGC and the channel formation layer MGC due to the potential difference between the drain DR and the source SR. Thus, electrons can be efficiently injected into the charge trapping film CTF.

[0055] Next, the manufacturing method of the semiconductor device according to the first embodiment will be described with reference to FIGS. 7 to Figure 15 . Here, the manufacturing method will be simply described so as to clarify the basic arrangement relationship of the respective impurity doped layers to be formed in the fin FN and the semiconductor substrate PSUB as important points.

[0056] Figure 7A ​Corresponding to Figure 4 Section AA in the middle, and Figure 7B Corresponding to Figure 4 The BB section in the middle. Therefore, Figure 7A The cross-sectional structure is shown in the following case: Figure 7B In the depth direction of the page, Figure 7B The structure shown is Figure 7B The dotted-dash line shown is CC-cut. (Described later) Figure 8A and Figures 8B to 13A The relationship with Figure 13 and Figure 7A and Figure 7B The relationship is the same.

[0057] First, such as Figure 7A and Figure 7B As shown, by using a conventional ion implantation method, a p-type impurity (e.g., boron) is doped into a silicon-based semiconductor substrate PSUB in the region where the fin is to be formed, thereby forming a p-type semiconductor layer BP, which has, for example, a density of 2 × 10⁻⁶. 18 cm -3 The concentration of impurities.

[0058] Next, as Figure 8A and Figure 8B As shown, fins protruding upwards from the shallow trench isolation unit (STI) are formed. The fins are formed, for example, by selectively etching away the surface of the semiconductor substrate (PSUB) to form fin-shaped silicon layers; depositing an oxide film of approximately 400 nm on the upper surface of the PSUB, including the spaces between the fin-shaped silicon layers; planarizing the oxide film using a CMP (chemical mechanical polishing) method; and then etching back the upper surface of the oxide film. The oxide film formed by the back etching to fill the spaces between the fins serves as the shallow trench isolation unit (STI).

[0059] Next, as Figure 9A and Figure 9B As shown, for example, a gate insulating film GI formed of an oxide film is formed on the exposed surface of the finned FN. A polysilicon film is deposited on the gate insulating film GI, and the polysilicon film is patterned by selective etching, thereby forming the control gate CG. The control gate CG is processed to have... Figure 4 The planar pattern of CG(WL) is shown. Additionally, a so-called high-k film such as HfO can be used as the material for the gate insulating film GI. Furthermore, to achieve resistance reduction, threshold modulation, and work function control, metallic materials such as TaN and Al can be used as materials for controlling the gate CG.

[0060] Next, as Figure 10AAs shown, a photoresist mask PR1 is formed to cover the area that will be the memory gate MG and the source SR. Boron is ion-implanted into the main surface of the semiconductor substrate from the diagonal direction D1 using the control gate CG and the photoresist mask PR1 as a mask, thereby forming an 8×10⁻⁶ area below the control gate CG. 17 cm -3 The impurity concentration of the p-type channel forming layer CGC.

[0061] Next, as Figure 11A As shown, after the photoresist mask PR1 is removed, a photoresist mask PR2 is formed to cover the area that will be the control gate CG and the drain SR. Using the control gate CG and the photoresist mask PR2 as masks, phosphorus is ion-implanted into the main surface of the semiconductor substrate from the vertical direction D2, thereby forming a 1×10⁻⁶ area. 18 cm -3 The impurity concentration of n-type channel MGC.

[0062] Next, after removing the photoresist film PR2, a silicon oxide film, a silicon nitride film, and a silicon oxide film are successively stacked on the upper surface of the semiconductor substrate PSUB, which includes the upper surface of the control gate electrode CG, thereby forming a charge trapping insulating film.

[0063] Next, as Figure 12A and Figure 12B As shown, a polysilicon film is deposited on a charge-trapping insulating film, in which phosphorus is highly doped, and anisotropic etching is performed on the polysilicon film, thereby forming a memory gate MG on the side surface of the control gate CG. Subsequently, the charge-trapping insulating film exposed from the control gate CG and the memory gate MG is selectively removed by etching, thereby forming a charge-trapping film CTF that will remain below the memory gate MG and between the control gate CG and the memory gate MG. The charge-trapping film CTF is formed from: a silicon oxide film with a thickness of approximately 3 nm formed by thermal oxidation, and a silicon nitride film and a silicon oxide film with a thickness of 6 nm formed by a CVD method.

[0064] By anisotropically etching the polysilicon film as described above, the polysilicon film with sidewall shape remains on the side surface of the control gate CG on the opposite side of the memory gate MG, but the remaining polysilicon film is removed by a selective etching process.

[0065] Next, arsenic is ion-implanted into the main surface of the semiconductor substrate using the control gate CG and the memory gate MG as masks, thereby forming an n-type source SR and an n-type drain DR having a higher impurity concentration than that of the channel MGC. The basic structure of the semiconductor device according to the first embodiment is formed by the above manufacturing method. Thereafter, for electrical connection to the drain DR, Figure 4 The bit line contact BLC shown is open. Here, the bit line contact BLC does not appear in the cross section shown in the drawing, and its illustration is omitted.

[0066] Further, after the structure shown in FIG. 13 is completed, a tungsten film is deposited on the entire surface of the semiconductor substrate PSUB, and the tungsten film is planarized by a CMP method. At this time, by planarizing the upper surfaces of the memory gate MG and the control gate CG at the same time, it is possible to prevent the memory array portion from being higher than other peripheral regions and the like. Figure 13A Thereafter, although not shown, an oxide film as an interlayer insulating film is deposited on the entire surface of the semiconductor substrate PSUB to about 200 nm, and a conventional wiring process for forming a wiring is performed, the wiring being formed of a copper film or an aluminum film, thereby forming the wiring of the memory cell array and the peripheral circuit.

[0067] Further, as shown in FIG. 13, a structure in which the upper surface position of the p-type semiconductor layer BP protrudes from the film thickness tCTF of the charge trapping film CTF of the shallow trench isolation portion STI is formed. In this way, a preferable channel controllability can be obtained. For example, when the film thickness of the charge trapping film CTF is 20 nm, the p-type semiconductor layer BP is formed up to a position 20 nm from the lower end of the fin FN (the upper surface of the shallow trench isolation portion STI).

[0068] Figure 13B Additionally, since the memory gate MG that controls the fin FN in the horizontal direction is not disposed in the film thickness region of the charge trapping film CTF, there is a risk of degradation of the controllability of the fin FN, but this risk can be avoided by disposing the p-type semiconductor layer BP.

[0069] As described above, the split-gate type MONOS structure of the semiconductor device according to the first embodiment can be formed. In the above manufacturing process, n-type impurities are doped into the channel formation layer MGC, and a memory cell MC that operates in an accumulation mode can be obtained. Thus, a memory cell MC having excellent write characteristics can be obtained. Further, the p-type semiconductor layer BP is formed below the n-type channel MGC, and a memory operation can be performed without degrading the controllability of the memory gate MG.

[0070] As described above, the split-gate type MONOS structure of the semiconductor device according to the first embodiment can be formed. In the above manufacturing process, n-type impurities are doped into the channel formation layer MGC, and a memory cell MC that operates in an accumulation mode can be obtained. Thus, a memory cell MC having excellent write characteristics can be obtained. Further, the p-type semiconductor layer BP is formed below the n-type channel MGC, and a memory operation can be performed without degrading the controllability of the memory gate MG.

[0071] ​Moreover, in the split-gate type MONOS structure according to the first embodiment, a PN junction is formed at a boundary between the channel formation layer MGC and the channel formation layer CGC. Figure 16 The potential distribution in the charge trapping film CTF (stacked film of oxide film O / nitride film N / oxide film O) near the PN junction is schematically shown. Note that, Figure 16 The solid line in FIG. 19 indicates the accumulation mode, and the broken line indicates the inversion mode. Since the impurity type of the channel changes from p-type to n-type near the PN junction, a potential difference of about 1 V occurs for the same gate voltage. Thus, the gate voltage required to give the same vertical electric field to the channel can be reduced. Additionally, since the difference is concentrated near the PN junction, high hot carrier generation efficiency can be obtained.

[0072] (Modification)

[0073] In the above first embodiment, the process of forming the p-type semiconductor layer BP at the lower portion of the fin FN has been described before the fin FN is formed. Alternatively, the p-type semiconductor layer BP can also be formed at a desired position of the fin FN by performing ion implantation of p-type impurities after the fin FN is formed. By this method, the heat load after ion implantation can be reduced, and thus the p-type semiconductor layer BP is easily formed. For example, as shown in FIG. 20, ion implantation of p-type impurities into the fin FN from the vertical direction D3 is performed in a state where the insulating film IFSTI deposited during the process of processing the fin FN using the hard mask HM and forming the shallow trench isolation portion STI is planarized, thereby forming the p-type semiconductor layer BP. Figure 14

[0074] Additionally, as shown in FIG. 21, ion implantation of p-type impurities into the fin FN from the vertical direction D4 is performed in a state where the fin FN is formed, and then a process of etching back for forming the shallow trench isolation portion STI is completed, thereby forming the p-type semiconductor layer BP. As a preferable example, the fin FN sandwiched between the memory gates MG is formed to have a height of 50 nm to 100 nm. Figure 15

[0075] On the other hand, the fin FN buried in the shallow trench isolation portion STI is formed to have a depth of 200 nm to 300 nm. Thus, even if ion implantation for forming the p-type semiconductor layer BP is performed after the fin FN is formed, the p-type semiconductor layer BP which actually contributes to the write characteristics can also be formed at a desired depth of the lower portion of the fin FN.

[0076] ​​In regions without fins (FN), ion-implanted p-type impurities can be retained in the oxide film of the shallow trench isolation layer (STI), leaving the semiconductor device characteristics virtually unaffected. The average range of ion implantation used to form the aforementioned p-type semiconductor layer (BP) is determined by... Figure 15 The dashed line AD indicates this.

[0077] In the foregoing, the invention made by the inventor has been specifically described based on embodiments. However, the invention is not limited to the above embodiments, and various modifications are possible without departing from its spirit.

[0078] For example, in the first embodiment, a method has been described in which hot carrier injection into the charge trapping membrane is performed via SSI and BTBT (interband tunneling) in a split-gate MONOS structure. Charge injection into the charge trapping membrane can be performed using the same split-gate MONOS structure, but in a different manner.

[0079] For example, electron injection during writing is performed by SSI injection similar to that in the first embodiment, but hole injection into the charge trapping membrane is performed from the memory gate MG by tunneling injection during erasure. Figure 18 An example of the bias setting required in this situation is shown. Figure 18 In Table A above, the bias settings are indicated by symbols such as ground potential GND and supply voltage VCC, and Figure 18 In Table B below, the bias settings are shown as specific voltages (in V) in a device assuming a voltage of 1.5V. As shown in Table B below, in this operating method, hole injection is performed through the potential difference between the gate and source; however, even in this case, operation in accumulation mode can generate a high electric field, thus being effective for improving erase efficiency.

Claims

1. A semiconductor device having a split-gate type MONOS structure, comprising: a semiconductor substrate having a main surface; a fin that is a part of the semiconductor substrate and is formed to selectively protrude from the main surface of the semiconductor substrate; an isolation portion that is formed on the main surface of the semiconductor substrate and is formed to have an upper surface at a position lower than a position of an upper surface of the fin; a control gate that is formed to sandwich the fin via a gate insulating film formed on a surface of the fin; a memory gate that is formed to sandwich the fin via a charge trapping film formed on the surface of the fin and is arranged on a side surface of the control gate; a source that is formed in the fin on one side surface of a split-gate structure configured by the control gate and the memory gate; a drain that is formed in the fin on another side surface of the split-gate structure; a first channel formation layer that is formed in the fin directly below the control gate and is formed of a p-type semiconductor layer; and a second channel formation layer that is formed in the fin below the memory gate and is formed of an n-type semiconductor layer.

2. The semiconductor device according to claim 1, wherein the first channel formation layer and the second channel formation layer form a PN junction at a boundary between the control gate and the memory gate.

3. The semiconductor device according to claim 1, wherein the fin is formed of an n-type semiconductor layer and an impurity concentration of the second channel formation layer is higher than an impurity concentration of the fin.

4. The semiconductor device according to claim 3, wherein the source and the drain are formed of an n-type semiconductor layer and the impurity concentration of the second channel formation layer is lower than impurity concentrations of the source and the drain.

5. The semiconductor device according to claim 1, wherein a transistor configured by the memory gate, the source, the drain, and the charge trapping film operates in an accumulation mode.

6. A semiconductor device having a split-gate type MONOS structure, comprising: a semiconductor substrate having a main surface; a fin that is a part of the semiconductor substrate and is formed of an n-type semiconductor layer formed to selectively protrude from the main surface of the semiconductor substrate; an isolation portion that is formed on the main surface of the semiconductor substrate and is formed to have an upper surface at a position lower than a position of an upper surface of the fin; a control gate that is formed to sandwich the fin via a gate insulating film formed on a surface of the fin; and a memory gate that is formed to sandwich the fin via a charge trapping film formed on the surface of the fin. a memory gate formed to pinch the fin via a charge trapping film formed on the surface of the fin, and arranged on a side surface of the control gate; a source formed in the fin on one side surface of a split gate structure configured by the control gate and the memory gate; a drain formed in the fin on the other side surface of the split gate structure; a first channel formation layer formed in the fin directly below the control gate, and formed of a p-type semiconductor layer; a second channel formation layer formed in the fin below the memory gate, and formed of an n-type semiconductor layer; and a p-type buried semiconductor layer formed on the main surface of the semiconductor substrate, and formed at a lower portion of the fin, wherein the impurity concentration of the buried semiconductor layer is higher than the impurity concentration of the first channel formation layer.

7. The semiconductor device according to claim 6, wherein the upper surface of the buried semiconductor layer is higher than the surface of the isolation portion, and wherein the upper surface of the buried semiconductor layer is higher than the surface of the isolation portion by a film thickness of the charge trapping film in a thickness direction of the semiconductor substrate.

8. The semiconductor device according to claim 6, wherein a transistor configured by the memory gate, the source, the drain, and the charge trapping film operates in an accumulation mode. ​

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