Anti-reverse connection H-bridge driving circuit

Abstract

The application discloses a kind of with anti-reverse H bridge drive circuit, including power supply positive pole VDD and power supply negative pole GND, anti-reverse, control level conversion and dead zone control circuit, transistor NM5 and H bridge drive circuit, power supply positive pole VDD directly to anti-reverse, control level conversion and dead zone control circuit power supply, and it is powered to H bridge drive circuit by the transistor NM5 of anti-reverse effect, can prevent power voltage reverse connection, avoid reverse connection misoperation burn chip, while anti-reverse circuit is realized using N type MOS tube, compared with P type MOS tube realization has smaller on-resistance, also saves chip area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a H-bridge driving circuit with anti-reverse connection. BACKGROUND

[0002] H-bridge circuit structure, named after the shape similar to the letter "H", is often used as a fan, motor output driving circuit. H-bridge circuit includes four transistors and a motor, to make the motor work properly, must make a pair of transistors on the diagonal line, according to the conduction of different diagonal line triode pair, the current flow direction may be from left to right or from right to left, thus determining the direction of the motor. The upper bridge arm of the traditional H-bridge driving circuit is two PMOS tubes, and the lower bridge arm is two NMOS tubes, as shown in Figure 1 Q1 and Q3 are PMOS tubes, and Q2 and Q4 are NMOS tubes. However, there are problems in the traditional structure. Since the hole mobility is lower than the electron mobility, the area of two PMOS tubes Q1 and Q3 is 2-3 times the area of two NMOS tubes Q2 and Q4, which greatly increases the chip area. Especially in high-power driving applications, the area of the chip is mainly determined by the output tube, so in order to reduce the area of the chip, the area of the output tube must be reduced, so that the manufacturing cost of the chip can be lower.

[0003] In addition, during the daily use of the chip, the power supply is often connected in reverse, which may cause the chip to burn out. Especially in the H-bridge driving circuit, when the power supply and ground are connected in reverse, a large current will flow through the output bridge arm, causing the chip to burn out. Therefore, it is very important to design an anti-reverse connection function for the H-bridge driving circuit. SUMMARY

[0004] In view of the deficiencies in the prior art, the purpose of the embodiments of the present application is to provide a H-bridge driving circuit with anti-reverse connection, which can prevent the reverse connection of the power supply voltage and avoid the burning of the chip due to reverse connection misoperation. At the same time, the anti-reverse connection circuit is realized by N-type MOS tube, which has smaller on-resistance than P-type MOS tube, and saves the chip area.

[0005] To achieve the above purpose, the present application provides the following technical scheme:

[0006] A H-bridge driving circuit with anti-reverse connection, comprising a positive power supply VDD and a negative power supply GND, further comprising an anti-reverse, control level conversion and dead zone control circuit, a transistor NM5 and a H-bridge driving circuit, the positive power supply VDD directly supplies power to the anti-reverse, control level conversion and dead zone control circuit, and supplies power to the H-bridge, charge pump circuit and high voltage stabilizing circuit through the transistor NM5 with anti-reverse connection function.

[0007] As a further scheme of the present application, the H-bridge driving circuit comprises a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3 and a fourth NMOS transistor NM4, the drain of the first NMOS transistor NM1 and the drain of the second NMOS transistor NM2 are connected to the drain of a transistor NM5, and the source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are connected to a power supply negative pole GND; the source of the first NMOS transistor NM1 and the drain of the third NMOS transistor NM3 form a first output end DRV1, and the source of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4 form a second output end DRV2, the H-bridge driving circuit composed of the external transistors NM1, NM2, NM3 and NM4 and the transistor NM5 for preventing reverse action.

[0008] In the present application, the H-bridge driving circuit comprises a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3 and a fourth NMOS transistor NM4, the drain of the first NMOS transistor NM1 and the drain of the second NMOS transistor NM2 are connected to the drain of a transistor NM5, and the source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are connected to a power supply negative pole GND; the source of the first NMOS transistor NM1 and the drain of the third NMOS transistor NM3 form a first output end DRV1, and the source of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4 form a second output end DRV2, for single-phase fan, motor and the like.

[0009] As a further scheme of the present application, the H-bridge driving circuit comprises a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3 and a fourth NMOS transistor NM4, the drain of the first NMOS transistor NM1 and the drain of the second NMOS transistor NM2 are connected to the drain of a transistor NM5, and the source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are connected to a power supply negative pole GND; the source of the first NMOS transistor NM1 and the drain of the third NMOS transistor NM3 form a first output end DRV1, and the source of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4 form a second output end DRV2, the H-bridge driving circuit composed of the external transistors NM1, NM2, NM3 and NM4 and the transistor NM5 for preventing reverse action.

[0010] As a further scheme of the present application, the input end of the anti-reverse, control level conversion and dead zone control circuit is connected to the positive pole of the power supply VDD, the high voltage output end CP of the charge pump circuit and the output end of the low voltage control circuit, and the four output ends H1, H2, L1 and L2 are respectively connected to the gate of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3 and the fourth NMOS transistor NM4, specifically, the positive pole of the power supply VDD is respectively connected to the source of the transistor NM5 and the anti-reverse, control level conversion and dead zone control circuit; the output CP of the charge pump circuit is connected to the anti-reverse, control level conversion and dead zone control circuit; the output of the high voltage stabilizing circuit is connected to the low voltage control circuit; the gate VRG of the transistor NM5 is connected to the anti-reverse, control level conversion and dead zone control circuit; and the output H1, H2, L1 and L2 of the anti-reverse, control level conversion and dead zone control circuit are respectively connected to the gate of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3 and the fourth NMOS transistor NM4.

[0011] As a further scheme of the present application, the anti-reverse, control level conversion and dead zone control circuit comprises an input CP, an output VRG, a first resistor R1, a second resistor R2, a PMOS transistor PM1, a first diode D1, a second diode D2 and a third diode D3, the positive pole of the power supply VDD is connected to one end of the first resistor R1 and the second resistor R2, the other end of the first resistor R1 is connected to the positive pole of the third diode D3, the gate of the PMOS transistor PM1 and the negative pole of the second diode D2; the positive pole of the second diode D2 is connected to the negative pole of the power supply GND; the other end of the second resistor R2 is connected to the output VRG and the drain of the PMOS transistor PM1; the input CP is connected to the positive pole of the first diode D1; and the negative pole of the first diode D1 is connected to the negative pole of the third diode D3 and the source of the PMOS transistor PM1.

[0012] As a further scheme of the present application, the third diode D3 is the gate anti-breakdown voltage of the PMOS transistor PM1.

[0013] As a further scheme of the present application, the transistor NM5 is an NMOS transistor for anti-reverse, when the power supply VDD and the ground GND are connected reversely, the transistor NM5 is in normal working mode, but at this time, the gate voltage is low voltage, and the transistor NM5 is turned off.

[0014] As a further scheme of the present application, the input of the charge pump circuit is V1, connected to the drain of transistor NM5, and the output thereof is CP, connected to the anti-reverse, control level conversion and dead zone control circuit for driving the NMOS tube to open.

[0015] As a further scheme of the present application, the power supply positive pole VDD is connected to the source of transistor NM5 and the anti-reverse, control level conversion and dead zone control circuit, respectively, for supplying power to the anti-reverse, control level conversion and dead zone control circuit and the H-bridge circuit.

[0016] The present application is powered by the charge pump circuit, the high-voltage stabilizing circuit, the low-voltage control circuit, the anti-reverse, control level conversion and dead zone control circuit, the H-bridge driving circuit composed of external transistors NM1, NM2, NM3 and NM4, and the transistor NM5 for anti-reverse effect, wherein the anti-reverse circuit is included, the CP end is connected to the gate of NM5 through the control tube PM1, the source voltage of PM1 is higher than the gate voltage when the power supply is normal, PM1 is normally turned on, the voltage of VRG is CP minus the forward conduction voltage of D1 at this time, and MN5 tube is turned on; when the power supply is reversed, the gate and source of PM1 are both high voltage, PM1 is not turned on, the gate end of NM5 is low voltage at this time, and NM5 tube is turned off. The present application can prevent the chip from being burned due to the reverse connection of the power supply ground during use because the power supply ground anti-reverse connection function is adopted. The power supply ground anti-reverse circuit adopted in the present application is realized by N-type tube, which has smaller conduction resistance than P-type tube, and saves the chip area. The power supply ground anti-reverse circuit structure adopted in the present application is simple, and can effectively prevent the anti-reverse connection failure caused by parasitic effects in the layout drawing.

[0017] In order to more clearly illustrate the structural features and effects of the present application, the present application will be described in detail below in combination with the drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a traditional H-bridge driving circuit structure block diagram.

[0019] Figure 2 is a structure block diagram of the present application.

[0020] Figure 3 is the schematic diagram of the reverse connection prevention circuit of the present application. DETAILED DESCRIPTION

[0021] The present application will be further described in conjunction with the drawings and relevant knowledge, and will be clearly and completely described. It is obvious that the described circuit diagram application is only a part of the embodiments of the present application, but not all the embodiments.

[0022] Referring to Figure 2 As shown in the figure, a reverse connection prevention H-bridge driving circuit includes a power supply positive VDD and a power supply negative GND, a charge pump circuit, a high voltage stabilizing circuit, a low voltage control circuit, a reverse prevention, control level conversion and dead zone control circuit, an H-bridge driving circuit composed of external transistors NM1, NM2, NM3 and NM4, a transistor NM5 for reverse prevention, and a power supply for the reverse prevention, control level conversion and dead zone control circuit through the power supply positive, and a power supply for the H-bridge, charge pump circuit and high voltage stabilizing circuit through the transistor NM5 for reverse prevention.

[0023] Among them, the H-bridge driving circuit includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3 and a fourth NMOS transistor NM4 which constitute a bridge arm, the drain of the first NMOS transistor NM1 and the drain of the second NMOS transistor NM2 are connected to the drain of the transistor NM5, and are connected to the input V1 of the charge pump circuit and the input V1 of the high voltage stabilizing circuit, the source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are connected to the power supply negative GND; the source of the first NMOS transistor NM1 and the drain of the third NMOS transistor NM3 form a first output end DRV1, the source of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4 form a second output end DRV2, which is used for single-phase fan, motor, etc.

[0024] Further preferably, the power supply positive pole VDD is connected to the source of the transistor NM5 and the anti-reverse, control level conversion and dead zone control circuit for power supply of the anti-reverse, control level conversion and dead zone control circuit and power supply of the H-bridge circuit. The charge pump circuit, with the input of V1, is connected to the drain of the transistor NM5, and the output of CP is connected to the anti-reverse, control level conversion and dead zone control circuit for driving the NMOS tube to open; the high-voltage stabilizing circuit, with the input voltage of V1, is connected to the drain of the transistor NM5, and the output is connected to the low-voltage control circuit for power supply of other internal circuits of the chip; the low-voltage control circuit, with the input connected to the high-voltage stabilizing circuit, is connected to the output of the anti-reverse, control level conversion and dead zone control circuit, and outputs the control signal after receiving the external control signal and certain control logic operation; the anti-reverse, control level conversion and dead zone control circuit is a circuit with the functions of anti-reverse, control level conversion and dead zone control; the input end is connected to the power supply positive pole VDD, the high-voltage output end CP of the charge pump and the output end of the low-voltage control circuit, and the four output ends H1, H2, L1 and L2 are respectively connected to the gate of the first NMOS tube NM1, the second NMOS tube NM2, the third NMOS tube NM3 and the fourth NMOS tube NM4. The H-bridge driving circuit is realized by N-type tubes.

[0025] Further preferably, the internal anti-reverse circuit includes the input CP, the output VRG, the power supply positive pole VDD, the power supply negative pole GND, the first resistor R1 and the second resistor R2, the PMOS tube PM1, the first diode D1, the second diode D2 and the third diode D3. The power supply positive pole VDD is connected to one end of the first resistor R1 and the second resistor R2, the other end of the first resistor R1 is connected to the anode of the third diode D3, the gate of the PMOS tube PM1 and the cathode of the second diode D2; the anode of the second diode D2 is connected to the power supply negative pole GND; the other end of the second resistor R2 is connected to the output VRG and the drain of the PMOS tube PM1; the input CP is connected to the anode of the first diode D1; the cathode of the first diode D1 is connected to the cathode of the third diode D3 and the source of the PMOS tube PM1, wherein the third diode D3 is the gate anti-breakdown voltage of the PMOS tube PM1.

[0026] The transistor NM5 is an NMOS for anti-reverse. When the power supply VDD and the ground GND are connected reversely, the transistor NM5 is in the normal working mode, but at this time the gate voltage is low, and the transistor NM5 is turned off.

[0027] In the application, when the power supply is normal, the source voltage of PM1 is higher than the gate voltage, PM1 is normally turned on, at this time, the voltage of VRG is CP minus the forward conduction voltage of D1, driving MN5 to be turned on; when the power supply is reversed, the gate and source of PM1 are both high voltage, PM1 is not turned on, at this time, the gate of NM5 is low voltage, NM5 is turned off. The application can prevent the chip from being burned due to the reversed power supply ground during use because the power supply ground anti-reverse function is adopted.

[0028] A specific embodiment of the application is provided below

[0029] Embodiment 1

[0030] Referring to Figures 2-3 The application includes a power supply positive electrode VDD and a power supply negative electrode GND, a charge pump circuit 101, a high-voltage stabilizing circuit 102, a low-voltage control circuit 103, an anti-reverse, control level conversion and dead zone control circuit 104, an H-bridge drive circuit composed of external transistors NM1, NM2, NM3 and NM4, and a transistor NM5 for anti-reverse; wherein the anti-reverse, control level conversion and dead zone control circuit is a circuit with anti-reverse, control level conversion and dead zone control functions; the power supply positive electrode directly supplies power to the anti-reverse, control level conversion and dead zone control circuit, and supplies power to the H-bridge, the charge pump circuit and the high-voltage stabilizing circuit through the transistor NM5 for anti-reverse; the power supply ground anti-reverse circuit adopts N-type tubes, which has smaller conduction resistance than P-type tubes, and saves chip area.

[0031] Referring to Figure 2 The input of the charge pump circuit is V1 from the drain of NM5, and the output is CP. After being boosted by the charge pump, the output is 5V higher than V1, which is used to drive NM5 to be turned on. The output of the charge pump is also connected to the anti-reverse, control level conversion and dead zone control circuit, which is used for control level conversion and dead zone control, and includes an anti-reverse circuit. At the same time, the input of the high-voltage stabilizing circuit also comes from V1, and after being stabilized, the output is output to the low-voltage control circuit to generate low voltage for supplying power to other circuits inside the chip. In addition, the low-voltage control circuit receives external control signals, and after certain control logic operation, outputs control signals to the anti-reverse, control level conversion and dead zone control circuit.

[0032] Referring to Figure 2The H-bridge driving circuit comprises a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3 and a fourth NMOS transistor NM4 which constitute a bridge arm, the drain of the first NMOS transistor NM1 and the drain of the second NMOS transistor NM2 are connected to the drain of a transistor NM5 and are connected to the input V1 of a charge pump circuit and the input V1 of a high-voltage stabilizing circuit, the source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are connected to the negative electrode GND of a power supply; the source of the first NMOS transistor NM1 and the drain of the third NMOS transistor NM3 form a first output end DRV1, the source of the second NMOS transistor NM2 and the drain of the fourth NMOS transistor NM4 form a second output end DRV2, which are used for single-phase fans, motors and the like; the positive electrode VDD of the power supply is connected to the source of the transistor NM5 and an anti-reverse, control level conversion and dead zone control circuit; the four outputs H1, H2, L1 and L2 of the anti-reverse, control level conversion and dead zone control circuit are connected to the gate of the first NMOS transistor NM1, the gate of the second NMOS transistor NM2, the gate of the third NMOS transistor NM3 and the gate of the fourth NMOS transistor NM4 respectively.

[0033] Referring to Figure 3 The internal anti-reverse circuit comprises an input CP, an output VRG, a positive electrode VDD of a power supply, a negative electrode GND of the power supply, a first resistor R1 and a second resistor R2, a PMOS transistor PM1, a first diode D1, a second diode D2 and a third diode D3; the positive electrode VDD of the power supply is connected to one end of the first resistor R1 and one end of the second resistor R2; the other end of the first resistor R1 is connected to the positive electrode of the third diode D3, the gate of the PMOS transistor PM1 and the negative electrode of the second diode D2; the positive electrode of the second diode D2 is connected to the negative electrode GND of the power supply; the other end of the second resistor R2 is connected to the output VRG and the drain of the PMOS transistor PM1; the input CP is connected to the positive electrode of the first diode D1; the negative electrode of the first diode D1 is connected to the negative electrode of the third diode D3 and the source of the PMOS transistor PM1; when the power supply is normal, the voltage of the source of the PM1 is higher than that of the gate, the PM1 is normally turned on, at this time, the voltage of the VRG is the voltage of the CP minus the forward conduction voltage of the first diode D1, and the transistor NM5 is turned on; when the power supply is reversed, the gate and the source of the PM1 are both high voltage, the PM1 is not turned on, at this time, the gate of the NM5 is low voltage, and the transistor NM5 is turned off. The present application adopts the power supply ground anti-reverse function, can prevent the chip from being burned due to the power supply ground reverse connection in the use process, and adopts the power supply ground anti-reverse circuit structure which is simple and can effectively prevent the anti-reverse failure caused by the parasitic effect in the layout drawing.

[0034] In normal working condition, each circuit is normal, the voltage of output CP is 5V higher than VDD after being boosted by charge pump, at this time diode D2 is in reverse bias and not conductive. At the same time, the gate voltage of PM1 is pulled to VDD by R1 resistor. Since the source voltage of PM1 is higher than the gate voltage, PM1 is normally conductive, thus the voltage of VRG is CP minus the forward conduction voltage of D1, driving MN5 to be conductive. D3 is the gate anti-breakdown voltage of PM1.

[0035] When in reverse connection condition, i.e. the power supply VDD and GND are connected reversely, at this time GND is high voltage and VDD is low voltage. Thus the gate voltage of PM1 is VGND minus the forward conduction voltage of D2, and the source is VGND minus the forward conduction voltage of D2 and D3, both are high voltage, so PM1 is not conductive. At this time the voltage of VRG is pulled to VDD voltage by R2 resistor. External NM5 is closed. Further, it can effectively prevent the generation of large current.

[0036] The above describes the technical principles of the present application in combination with specific embodiments, which are only the preferred embodiments of the present application. The protection scope of the present application is not limited to the above-mentioned embodiments only, any technical solution falling within the idea of the present application belongs to the protection scope of the present application. The other specific embodiments of the present application can be conceived by those skilled in the art without creative labor, which will fall within the protection scope of the present application.

Claims

1. A reverse connection prevention H-bridge driving circuit comprising a power supply positive pole VDD and a power supply negative pole GND, characterized in that, It also includes anti-reverse, control level conversion and dead zone control circuit, transistor NM5 and H bridge drive circuit, the positive electrode VDD of power supply directly supplies power to the anti-reverse, control level conversion and dead zone control circuit, and supplies power to the H bridge drive circuit through the transistor NM5 with anti-reverse connection effect; The anti-reverse, control level conversion and dead zone control circuit includes input CP, output VRG, first resistor R1, second resistor R2, PMOS tube PM1, first diode D1, second diode D2 and third diode D3, the positive electrode VDD of power supply is connected to one end of the first resistor R1 and the second resistor R2, the other end of the first resistor R1 is connected to the positive electrode of the third diode D3, the gate of the PMOS tube PM1 and the negative electrode of the second diode D2;The positive electrode of the second diode D2 is connected to the negative electrode GND of power supply;The other end of the second resistor R2 is connected to the output VRG and the drain of the PMOS tube PM1;The input CP is connected to the positive electrode of the first diode D1;The negative electrode of the first diode D1 is connected to the negative electrode of the third diode D3 and the source of the PMOS tube PM1; The third diode D3 is the gate anti-breakdown voltage of the PMOS tube PM1; The transistor NM5 is an NMOS tube with anti-reverse effect, when the power supply VDD and the ground GND are connected reversely, the transistor NM5 is in normal working mode, but at this time the gate voltage is low voltage, and the transistor NM5 is turned off.

2. A reverse connection prevention H-bridge drive circuit as claimed in claim 1, wherein The H bridge drive circuit includes first NMOS tube NM1, second NMOS tube NM2, third NMOS tube NM3 and fourth NMOS tube NM4, the drains of the first NMOS tube NM1 and the second NMOS tube NM2 are connected to the drain of the transistor NM5, the sources of the third NMOS tube NM3 and the fourth NMOS tube NM4 are connected to the negative electrode GND of power supply;The source of the first NMOS tube NM1 and the drain of the third NMOS tube NM3 form a first output end DRV1, and the source of the second NMOS tube NM2 and the drain of the fourth NMOS tube NM4 form a second output end DRV2.

3. A reverse connection prevention H-bridge drive circuit as claimed in claim 1, wherein It also includes charge pump circuit, high voltage stabilizing circuit and low voltage control circuit, the charge pump circuit and the high voltage stabilizing circuit are connected with the positive electrode VDD of power supply through the transistor NM5, one end of the low voltage control circuit is connected with the high voltage stabilizing circuit, and the other end is connected with the anti-reverse, control level conversion and dead zone control circuit.

4. A reverse connection prevention H-bridge drive circuit as claimed in claim 3, wherein the first and second transistors are connected in series between the first and second supply rails. The input end of the anti-reverse, control level conversion and dead zone control circuit is connected to the positive electrode VDD of power supply, the high voltage output end CP of the charge pump circuit and the output end of the low voltage control circuit, and the four output ends H1, H2, L1 and L2 thereof are respectively connected to the gates of the first NMOS tube NM1, the second NMOS tube NM2, the third NMOS tube NM3 and the fourth NMOS tube NM4.

5. A reverse connection proof H-bridge drive circuit as claimed in claim 4, characterized in that The input of the charge pump circuit is V1, connected to the drain of the transistor NM5, and the output thereof is CP, connected to the anti-reverse, control level conversion and dead zone control circuit, used for driving the NMOS tube to open.

6. A reverse connection prevention H-bridge drive circuit as claimed in claim 5, wherein the first and second transistors are connected in series between the first and second supply rails. The power supply positive pole VDD is connected to the source of the transistor NM5 and the anti-reverse, control level conversion and dead zone control circuit, respectively, for supplying power to the anti-reverse, control level conversion and dead zone control circuit and the H-bridge circuit.

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