Non-volatile memory controller with partial logical to physical address translation table

Abstract

Systems, apparatus, and methods for logical-to-physical (L2P) address translation are provided. A method may include receiving a request for a first logical data address (LDA), calculating a first TDU index for a corresponding first translated data unit (TDU). The first TDU may include an L2P entry for the corresponding first LDA. The method may further include searching a cache of lookup directory entries for a recently accessed TDU using the first TDU index, determining a cache miss, generating and storing a pending request for the lookup directory entry for the corresponding first TDU in a miss buffer, obtaining the lookup directory entry for the corresponding first TDU from an in-memory lookup directory, determining that the lookup directory entry for the corresponding first TDU is invalid, reserving TDU space for the corresponding first TDU in memory, and generating a load request for the corresponding first TDU.

Description

Technical Field

[0001] The present application relates to a non-volatile memory system, and more particularly to logical to physical address translation in a non-volatile memory controller. Background Art

[0002] Computer systems have traditionally used a variety of nonvolatile storage devices to maintain and store data and instructions, such as floppy disks, hard disk drives, magnetic tapes, and optical disks. More recently, nonvolatile storage devices have become widely used in memory cards, USB flash drives, and solid-state drives (SSDs). Data is stored in nonvolatile storage devices according to physical data addresses. However, hosts typically access data using logical data addresses, so storage controllers require logical-to-physical translation tables.

[0003] Most storage controllers store a complete logical-to-physical (L2P) address translation table in their memory space for the controller to speed up data access. As the density of non-volatile storage devices increases, this approach will require the controller to have a large memory space, which will increase the cost of non-volatile storage systems (e.g., SSDs). For non-volatile storage systems with smaller sizes (e.g., M.2 format), it also becomes very challenging to place enough memory on the PCB. Therefore, there is a need in the art to minimize the storage space used for logical-to-physical address translation in non-volatile storage controllers. Summary of the Invention

[0004] The subject matter of the present disclosure relates to systems, methods, and apparatus for providing logical-to-physical (L2P) address translation in a storage controller. Techniques described herein for using a partial L2P address translation table in a storage controller can reduce the storage space used for L2P address translation in the storage controller. A subset of entries of a complete L2P address translation table can be loaded into the memory of the storage controller. A lookup directory having a number of entries that matches the number of entries of a translation data unit (TDU) of the complete L2P address translation table can be stored in the memory of the storage controller. The lookup directory can track which TDUs have been loaded into the memory space of the storage controller.

[0005] Whenever a TDU is loaded from a non-volatile storage device into the storage controller's memory or flushed from the storage controller's memory to the non-volatile storage device, the corresponding lookup directory entry can be updated. A TDU can be loaded into any available TDU space in the storage controller's memory, and the lookup directory can track where the TDU is loaded into memory. If the lookup directory entry for the corresponding TDU is invalid, it means that the TDU has not yet been loaded into the storage controller's memory, and a load request for the TDU may be sent to the non-volatile storage device.

[0006] In some embodiments, the most recently accessed lookup directory entries can be kept in a cache, and the cache can be checked first to determine whether the TDU is already in memory. Cache misses can be tracked in a miss buffer (e.g., a miss status holding register (MSHR)). The miss buffer can handle multiple cache misses for requests for lookup directory entries for the same TDU or for lookup directory entries for different TDUs and reduce the TDU load overhead caused by using a partial L2P address table.

[0007] In an exemplary embodiment, a method is provided, which may include: receiving a request for a first logical data address (LDA); calculating a first TDU index for a corresponding first translation data unit (TDU), the first TDU containing a logical-to-physical (L2P) entry for the corresponding first LDA; searching a cache of lookup directory entries for a recently accessed TDU using the first TDU index; determining that the cache does not have a lookup directory entry for the corresponding first TDU; generating and storing a pending request for a lookup directory entry for the corresponding first TDU in a miss buffer; obtaining a lookup directory entry for the corresponding first TDU from an in-memory lookup directory in a memory; determining that the lookup directory entry for the corresponding first TDU is invalid; reserving TDU space for the first TDU in the memory; and generating a load request for the corresponding first TDU.

[0008] In another exemplary embodiment, an apparatus is provided that may include: a processor and a logical-to-physical (L2P) translation engine. The L2P translation engine may include a cache of lookup directory entries for recently accessed translation data units (TDUs) and a miss buffer. Furthermore, the L2P translation engine may be configured to: receive a request for a first logical data address (LDA) from the processor; calculate a first TDU index for a first translation data unit (TDU), the first TDU containing a logical-to-physical (L2P) entry corresponding to the first LDA; search a cache of lookup directory entries for recently accessed TDUs using the first TDU index; determine that the cache does not have a lookup directory entry for the first TDU; generate and store a pending request for the lookup directory entry for the first TDU in the miss buffer; obtain the lookup directory entry for the first TDU from an in-memory lookup directory in a memory coupled to the apparatus; determine that the lookup directory entry for the first TDU is invalid; reserve TDU space for the first TDU in the memory and generate a load request for the first TDU.

[0009] In another exemplary embodiment, the present invention may also include a non-temporary machine-readable medium having executable instructions, which when executed by a storage controller may cause the storage controller to perform the following operations: receive a request for a first logical data address (LDA); calculate a first TDU index for a first translation data unit (TDU), the first TDU containing a logical-to-physical (L2P) entry corresponding to the first LDA; use the first TDU index to search a cache of lookup directory entries for a recently accessed TDU; determine that the cache does not have a lookup directory entry for the corresponding first TDU; generate and store a pending request for a lookup directory entry for the corresponding first TDU in a miss buffer; obtain a lookup directory entry for the corresponding first TDU from an in-memory lookup directory in a memory coupled to the storage controller; determine that the lookup directory entry for the corresponding first TDU is invalid; reserve TDU space for the first TDU in the memory and generate a load request for the first TDU. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The figure schematically shows a non-volatile memory controller according to an embodiment of the present disclosure.

[0011] Figure 2 The diagram schematically illustrates performing L2P translation using a partial logical-to-physical address translation table according to an embodiment of the present disclosure.

[0012] Figure 3A The figure schematically shows multiple entries of a search directory according to an embodiment of the present disclosure.

[0013] Figure 3B The figure schematically shows an entry tag for searching a directory entry according to an embodiment of the present disclosure.

[0014] Figure 4 FIG. 1 schematically illustrates entries of a miss status holding register according to an embodiment of the present disclosure.

[0015] Figure 5 The figure schematically shows an L2P engine according to an embodiment of the present disclosure.

[0016] Figure 6 FIG. 4 is a flowchart of a process of using a partial L2P address translation table according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Now, the specific embodiment according to the present application will be described in detail with reference to the accompanying drawings. For consistency, the same elements in various figures are represented by the same reference numerals.

[0018] The present disclosure provides apparatus, systems, and methods that support various high-speed non-volatile memory (NVM) devices and any combination of various NVM devices. As used herein, a non-volatile memory device can be a computer storage device that can retain stored information after power is off and can retrieve the stored information after power is re-on (turned off and back on). Non-volatile storage devices can include floppy disks, hard disk drives, magnetic tapes, optical disks, NAND flash memory, NOR flash memory, magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase change random access memory (PCRAM), Nano-RAM. In the specification, NAND flash memory can be used as an example of the proposed technology. However, other types of non-volatile storage devices can be used to implement these technologies according to various embodiments disclosed in this specification.

[0019] Figure 1 An exemplary non-volatile storage controller 100 according to one embodiment is schematically shown. The non-volatile storage controller 100 may include a first interface 110, a second interface 112, a third interface 108, a microcontroller unit (MCU) 102, on-chip memory 106, and a logical-to-physical (L2P) engine 104. The first interface 110 may be any existing or yet-to-be-developed interface configured to couple the non-volatile storage controller 100 to a system bus of a host computer system, and to receive data from and send data to the host computer system. In one embodiment, for example, the first interface 110 may be a peripheral component interconnect express (PCIE) interface. The second interface 112 may be any existing or yet-to-be-developed interface configured to couple the storage controller 100 to one or more non-volatile memory (NVM) devices. In one embodiment, the second interface 112 may be a multi-channel interface that may be configured to transmit encoded data (e.g., ECC codewords) on multiple channels in parallel. For example, the second interface 112 may be an Open NAND Flash Interface (ONFI), which may support different protocols (e.g., non-volatile double data rate (NVDDR), NVDDR type 2 (NVDDR2), NVDDR type 3 (NVDDR3)), or may be a Toggle protocol and operate at different transfer speeds. The third interface 108 may be any existing interface or yet-to-be-developed interface (e.g., double data rate (DDR), DDR type 2 (DDR2), or DDR type 3 (DDR3)) configured to couple the storage controller 100 to an off-chip memory (e.g., dynamic random access memory (DRAM)).

[0020] The MCU 102 may be a computer processor configured to execute executable instructions (e.g., software or firmware). In various embodiments, the MCU 102 may be a microprocessor, a microcontroller, a field programmable gate array (FPGA), or an application-specific integrated circuit (ASIC). The non-volatile storage controller 100 may receive commands from the host via the first interface 110, for example, to store data in the non-volatile storage system (e.g., a write command) or to read data stored in the non-volatile storage system (e.g., a read command). Commands from the host may use logical block addresses (LBAs), while non-volatile storage devices may use physical block addresses (PBAs), which need to be converted to physical block addresses (PBAs) at the storage controller 100. This L2P address conversion may be handled using an L2P address translation table, where each entry in the table may be a PBA for storing data. In one embodiment, the non-volatile storage controller 100 may process data in data units (DUs). The LBA for a data unit may be a logical data unit address (LDA), and the PBA for a data unit may be a physical data unit address (PDA).

[0021] The L2P address translation table can be stored in a non-volatile storage device coupled to the second interface 112. When the non-volatile storage system is powered on, a subset of the entries of the L2P address translation table can be loaded into the storage space of the non-volatile storage controller 100 (e.g., on-chip memory 106 or off-chip memory coupled to the controller 100) instead of loading the entire L2P address translation table. The subset of entries of the L2P address translation table can also be referred to as a partial L2P address translation table. In some embodiments, a lookup directory can be used to track which translation data unit (TDU) has been loaded into the storage space of the controller 100. The TDU can be loaded into any available TDU space in the storage space, and the corresponding entry in the lookup directory can contain the storage location of the TDU.

[0022] The L2P engine 104 may be configured to manage portions of the L2P address translation table, for example, maintaining a cache of recently accessed lookup directory entries, generating and managing cache misses, determining whether a TDU may need to be loaded from an L2P address translation table stored in a non-volatile storage device and reserving storage space for the TDU, whether any loaded TDU has been updated, and whether the updated TDU needs to be flushed to the L2P address translation table in the non-volatile storage device.

[0023] Figure 2The schematic diagram shows the use of a partial logical to physical address translation table to perform L2P translation according to an embodiment of the present disclosure. The complete L2P address translation table 204 can be stored in the non-volatile storage device 202 coupled to the non-volatile storage controller 100 (e.g., via the second interface 112). The L2P address translation table 204 can be stored in multiple NVM pages. Each NVM page used to store entries of the L2P table 204 can be referred to as a translation page (TP). Figure 2 As shown, the L2P table 204 may include multiple TPs 206. A data unit (DU) for storing entries of the L2P table may be referred to as a transition DU (TDU). Each TP 206 may include multiple TDUs. Figure 2 A representative TDU 208 is marked in FIG.

[0024] In one embodiment, if the PDA is 4 bytes, a 16-KibiByte (KiB) TP can store 4096 L2P entries. If a 16-KiB TP contains 4 TDUs, each TDU can have 1024 L2P entries. The TP index can be used as an identifier to identify the TP and can be calculated by dividing the LDA by the number of L2P entries in the TP. For example, assuming that in one embodiment, the LDA can be 32 bits, for a 16-KiB TP with 4096 L2P entries, the TP index can be set equal to the most significant 20 bits of the LDA, which can be expressed as LDA[31:12]. Similarly, for a 4-KiB TDU with 1024 L2P entries, the TDU index is used as an identifier to identify the TDU and can be set equal to the most significant 22 bits of the LDA, which can be expressed as LDA[31:10].

[0025] like Figure 2As shown, a lookup directory 212 may be maintained in a dynamic random access memory (DRAM) 210 coupled to the non-volatile storage controller 100. Assuming that the complete L2P table 204 stored in the non-volatile storage device 202 may have a total of N TDUs, the DRAM 210 may need to provide space for M TDUs, where both N and M may be positive integers, and N may be much larger than M (e.g., the M TDUs in the DRAM 210 are a subset of the N TDUs in the L2P table 204). The lookup directory 212 may have N entries (e.g., 216.1 through 216.N), which may match the number of all TDUs in the complete L2P table 204. In one embodiment, the lookup directory 212 may be implemented as a global translation directory (GTD), and each entry of the lookup directory 212 may be referred to as a lookup directory entry or a GTD entry. The lookup directory 212 may track which TDUs have been loaded into the DRAM 210 and the storage location of the loaded TDUs in the DRAM 210. Each time a TDU is loaded from nonvolatile storage device 202 to DRAM 210 or refreshed from DRAM 210 to nonvolatile storage device 202, the corresponding GTD entry may be updated. By using lookup directory 212, a TDU may be loaded into any available TDU space in DRAM 210.

[0026] Figure 3A Schematically illustrates a plurality of entries 302.1 to 302.N of a lookup directory according to an embodiment of the present disclosure. In one embodiment, the lookup directory may be implemented as a global translation directory (GTD). Each of the lookup directory entries 302.1 to 302.N may be identified by a TDU index TDU(i), where "i" is any one of 0 to N-1, and each of the lookup directory entries 302.1 to 302.N may include three fields. The first field may be an entry tag. The second field may be a data tag, which may be a storage address pointing to a DRAM location in DRAM 210 for storing the TDU. The third part may be the PDA of the TDU (e.g., the location where the TDU is stored in the non-volatile storage device 202).

[0027] Figure 3BThe entry tag of a lookup directory entry according to an embodiment of the present disclosure is schematically shown. The entry tag may include multiple bits. The entry tag may include at least a valid bit and a dirty bit. The valid bit may be used to indicate whether the TDU has been loaded into the DRAM. For example, if the TDU has been loaded into the DRAM 210, its corresponding lookup directory entry is valid, and the valid bit may be 1; and if the TDU is not in the DRAM 210, its corresponding lookup directory entry is invalid, and the valid bit may be 0. The dirty bit may be used to indicate whether the TDU in the DRAM 210 is dirty (for example, contains one or more modified L2P entries and is different from the TDU in the non-volatile storage device 202). For example, if the TDU in the DRAM 210 is dirty, it may need to be refreshed to the non-volatile storage device 202 to update the complete L2P address translation table 204. In some embodiments, in addition to the valid bit and the dirty bit, the entry tag may also include one or more other bits.

[0028] Reference again Figure 2 , the L2P engine 104 may include a GTD cache 218 and a miss buffer 220. The GTD cache 218 may be used to store recently accessed GTD entries, and the miss buffer 220 may be used to track cache misses for corresponding GTD entries. In one embodiment, cache misses may be stored as pending requests (e.g., load requests and update requests) for the corresponding GTD entry. When the memory controller 100 receives a command (e.g., read or write) with LDA i from the host and i is a valid number in the LDA (e.g., a 32-bit number for a 32-bit address), a search request for a physical address translation entry for LDA i may be sent from the processor 102 to the L2P engine 104. The TDU index for the LDA i may be calculated (e.g., obtaining LDA i[31:10]). The GTD cache 218 may be checked for the TDU(i). If the GTD entry for the corresponding TDU(i) is found in the GTD cache 218, the data tag in the cached GTD entry can be used to locate the L2P entry for the corresponding LDA i, and the physical address of the corresponding LDA i can be obtained from the L2P entry and the command can be executed accordingly.

[0029] If the GTD entry for the corresponding TDU(i) is not found in the GTD cache, a pending request for the GTD entry for the corresponding TDU(i) may be generated and retained in the miss buffer 220. The pending request for the GTD entry for the corresponding TDU(i) may include LDA(i) (e.g., only the least significant 10 bits, since the TDU index has the most significant 22 bits) and the operation performed for LDA i (e.g., search or update). The L2P engine 104 may then send a GTD entry get request with TDU(i) to the DRAM 210 and get the GTD entry for TDU(i) from the DRAM 210. If the got GTD entry is valid (e.g., the valid bit in the entry tag is 1), the got GTD entry may be inserted into the GTD cache 218, and the pending request in the miss buffer 220 may be serviced and cleared. For valid GTD entries in the GTD 212, the corresponding TDU has been loaded into the DRAM 210. For example, TDUs 214.1, 214.2, 214.3, and 214.4 have been loaded into DRAM 210. If the retrieved GTD entry is invalid (e.g., the valid bit in the entry tag is 0), then TDU(i) is not in DRAM 210. TDU space for TDU(i) may be reserved in DRAM 210, and a load request for the corresponding TDU(i) may be sent to non-volatile memory device 202. To reduce the overhead of loading TDU(i), a pending request for the GTD entry for TDU(i) may be retained in miss buffer 220 while the load request is being serviced.

[0030] In one embodiment, miss buffer 220 may include one or more miss status holding registers (MSHRs). Miss buffer 220 can handle multiple load requests for GTD entries of the same TDU or for GTD entries of different TDUs and reduce TDU load overhead caused by using a partial L2P address translation table. In one embodiment, miss buffer 220 can be used to track all pending requests for GTD entries of multiple TDUs, including pending requests generated to obtain GTD entries from DRAM 210 and any subsequent requests for GTD entries while fetching GTD entries from DRAM 21 or loading TDUs from non-volatile memory device 202 to DRAM 210.

[0031] Figure 4An MSHR 400 according to an embodiment of the present disclosure is schematically illustrated. The exemplary MSHR 400 may include a header 402 and a list portion 404. The header 402 may include a valid bit, a tag for the MSHR (e.g., a TDU index TDU(k) identifying a TDU that has a cache miss), a start pointer pointing to the first entry in the list portion 404, and an end pointer pointing to the last entry in the list portion 404. The valid bit may indicate whether the MSHR is still valid. When the valid bit indicates that the MSHR is valid (e.g., set to 1 when one or more cache misses occur for the corresponding TDU index TDU(k), the list portion 404 may include one or more list entries (e.g., 406.1 through 406.3) in a linked list. An invalid MSHR does not have a list portion 404. Each list entry may include an LDA offset (LDA offset), an operation type (OP TYPE), and a pointer (NEXT POINTER) to the next entry in the linked list. In one embodiment, the LDA offset may be the least significant 10 bits of the LDA (whereas the most significant 22 bits of a 32-bit LDA are used as the TDU index in the header 402). The last entry in the linked list may have a "NULL" pointer for the next entry since there are no entries after the last entry. In one embodiment, the miss buffer 220 may include multiple MSHRs 400. These MSHRs may be initialized by setting the valid bit to invalid, the tag to 0, and the start and end pointers to NULL.

[0032] Typically, there may be one pending request for a GTD entry for a TDU, or there may be multiple pending requests for a GTD entry for the same TDU. For example, LDA m (e.g., where m is a 32-bit address) may have an L2P translation entry in a particular TDU, and thus, a data access command with the address of LDA m may cause a first pending request for the GTD entry of the corresponding TDU to be generated and retained in the miss buffer. A particular TDU may have multiple translation entries (e.g., 1024 entries for 1024 LDAs), and any additional access request for the same L2P entry or another L2P entry in the particular TDU may cause a second or additional pending request for the GTD entry of the corresponding TDU to be generated and stored in a linked list of the GTD entries for the particular TDU. The LDA offset may indicate the LDA that needs to be translated (e.g., among the 1024 entries within the range covered by the TDU), and the operation type may indicate which type of operation (e.g., search or update) is to be performed on the L2P entry.

[0033] Figure 5The L2P engine 500 according to an embodiment of the present disclosure is schematically shown. The L2P engine 500 may be Figure 1 5. The L2P engine 500 may include an L2P request processor 502, a GTD cache control block 504, a GTD cache 506, a miss control block 508, a miss buffer 510, a DRAM control interface 512, and a plurality of queues for communicating with the processor 102. The plurality of queues may include an L2P search request queue 514, an L2P update request queue 516, a TDU load request queue 518, a TDU load completion queue 520, an L2P search result queue 522, an L2P update result queue 524, a TDU flush request queue 526, and a TDU flush completion queue 528. The GTD cache 506 may be Figure 2 In an embodiment of the GTD cache 218, the miss buffer 510 may be Figure 2 An embodiment of the miss buffer 220 in .

[0034] The L2P engine 500 may receive L2P requests from the processor 102. L2P requests may include search requests and update requests. A search request may be a request to search the L2P translation of a corresponding LDA (e.g., LDA m), where m may be a 32-bit address in one embodiment. An update request may be a request to update the L2P translation of a corresponding LDA. The L2P search request queue 514 and the L2P update request queue 516 may be buffers to temporarily store received search requests and update requests before they can be processed by the L2P request processor 102. In one embodiment, upon receiving an L2P request with an LDA (e.g., LDAm), and calculating the TDU index of the corresponding LDA (e.g., the most significant 22 bits of LDA m), the GTD cache 506 may be searched to determine whether the GTD entry identified by the TDU index is already in the GTD cache 506. If there is a hit, the GTD entry is already in the GTD cache, and the data tag of the GTD entry may include the storage location of the TDU. The TDU may include multiple L2P entries (e.g., 1024 entries), including L2P entries of corresponding LDAs. If the L2P request is an L2P search request, the L2P entry may be retrieved from memory and returned to the processor 102. If the L2P request is an L2P update request, the L2P entry in the TDU in DRAM 210 may be updated. In one embodiment, the L2P engine 500 may send the search request result to the L2P search result queue 522 and the update request result to the L2P update result queue 524. The processor 102 may receive the search request result from the L2P search result queue 522 and the update request result from the L2P update result queue 524.

[0035] The L2P engine 500 may send a TDU flush request to the processor 102 and may receive a TDU flush completion notification from the processor 102. For example, if the TDU in the DRAM 210 is dirty (e.g., the dirty bit is set), it may need to be flushed to the non-volatile storage device 202 to update the complete L2P address translation table 204. In one embodiment, the TDU flush request may be generated and pushed into the TDU flush request queue 526. Once the TDU flush is completed, the processor 102 may send a flush completion message to the TDU flush completion queue 528.

[0036] If the search of the GTD cache 506 does not result in a hit, the miss buffer 510 may be searched to determine if there are any pending requests for the GTD entry identified by the corresponding TDU index (e.g., by searching for the TDU index in the header 402 of the MSHR in the miss buffer 510). If there are any pending requests for the GTD entry for the corresponding TDU, then an MSHR with a linked list of GTD entries for the corresponding TDU already exists, and a list entry for the LDA (e.g., a new pending request) may be created and inserted into the already existing MSHR, and an end pointer in the MSHR header may be updated to point to the new pending request. If there are no pending requests for the GTD entry for the corresponding TDU, a GTD entry get request with the TDU index may be sent to the DRAM (e.g., DRAM 210) (e.g., via the DRAM control interface 512), and the MSHR may be assigned to the GTD entry and the TDU index may be inserted into the header of the MSHR. A new pending request for the LDA may be created, and a linked list may be created with the new pending request as the first entry. After the first entry of the linked list can be created, both the start pointer and the end pointer of the MSHR can point to the list entry that was just created.

[0037] It should be noted that when the miss buffer 510 is just initialized, all MSHRs of the miss buffer may have their respective TDU indexes set to 0, but the valid bits of these MSHRs may be set to invalid (e.g., zero) to indicate that the MSHR has no cache misses.

[0038] After sending a GTD get request with a TDU index to DRAM 210, a GTD entry may be received from DRAM 210 (e.g., from GTD 212 in DRAM 210). When the L2P engine 500 receives a GTD entry for the corresponding TDU identified by the TDU index, it may check the valid bit of the GTD entry to determine whether the GTD entry is valid. In one embodiment, after the lookup directory 212 is initialized in DRAM 210, all entries may be invalid (e.g., the valid bit is set to 0), and the GTD entry may become valid only after the corresponding TDU has been loaded from L2P table 204. In the L2P engine 500, if the received GTD entry is invalid, the L2P engine 500 may determine that the TDU has not been loaded from the L2P table 204, and may send a load request for the TDU (e.g., identified by the TDU index) to the NAND interface controller after reserving TDU space for the TDU to be loaded in the memory of the storage controller (e.g., DRAM 210). In some embodiments, the L2P engine may send a TDU load request to the processor 102. In one embodiment, the TDU load request may be pushed into the TDU load request queue 518 and retrieved and processed by the processor 102.

[0039] If the GTD entry received by the L2P engine 500 is valid, the MSHR in the miss buffer 510 corresponding to the GTD entry identified by the TDU index can be processed by traversing all entries in the request linked list of the list portion of this MSHR (e.g., having the TDU index in its header). For example, the data tag in the GTD entry just received is used to obtain the storage location of the TDU, and the operation specified in the operation type field in the linked list entry is performed on each L2P entry corresponding to the LDA offset in the linked list entry (e.g., performing an operation on the L2P entry, such as searching or updating the L2P entry). Once all entries in the linked list have been processed, the linked list can be deleted and the header of the MSHR can be cleaned up. For example, the TDU index can be removed from the header of the MSHR, the valid bit can be set to invalid (e.g., 0), and the start pointer and end pointer can be set to NULL. In addition, the GTD entry can be inserted into the GTD cache 506. In one embodiment, the GTD cache control 504 may be configured to insert a GTD entry into the GTD cache 506 , and the miss control 508 may be configured to process the MSHR in the miss buffer of the corresponding GTD entry.

[0040] When the requested TDU has been successfully loaded into DRAM 210, a TDU load completion message may be sent to the L2P engine 500. In one embodiment, the load completion message may be received in the TDU load completion queue 520. The TDU load completion message may include the TDU index and the storage location of the TDU (e.g., the data tag in the GTD entry). The L2P engine 500 may process the TDU load completion message similarly to processing valid GTD entries retrieved from the lookup directory 212. For example, the MSHR in the miss buffer 510 corresponding to the TDU load completion (e.g., having the TDU index at its header) may be processed by traversing all entries in the request linked list in the list portion of the MSHR. Once all entries in the linked list have been processed, the linked list may be deleted and the header of the MSHR may be cleared. The L2P engine 500 may update the GTD entry corresponding to the TDU in the lookup directory 212 (e.g., via the DRAM control interface 512) and update the GTD cache 506 (e.g., by inserting the GTD entry via the GTD cache control 504).

[0041] Figure 6 6 is a flow chart of a process 600 for using a partial L2P translation table according to an embodiment of the present disclosure. In block 602, a request for a first logical data address (LDA) may be received. For example, the L2P engine 104 may receive a search request or an update request for the LDA. In block 604, a first translation data unit (TDU) index may be calculated for a first TDU. The first TDU may include an L2P entry for the first LDA. In one embodiment, the TDU may include 1024 L2P entries for the first LDA. In block 606, the first TDU index may be used to search a cache for a lookup directory entry. The cache (e.g., the GTD cache 506) may include the storage location of the most recently accessed TDU. For example, the GTD entries in the cache 506 may have the storage location of the TDU in the data tag of each entry.

[0042] In block 608, it may be determined that the cache does not have a lookup directory entry (e.g., a GTD entry) for the corresponding first TDU, and in block 610, a pending request for the lookup directory entry for the corresponding first TDU may be generated and stored in a miss buffer. For example, a search for the TDU index in the cache may not result in a hit. Therefore, a pending request may be generated and stored for a cache miss. In block 612, the lookup directory entry for the corresponding first TDU may be retrieved from an in-memory lookup directory in memory. For example, the lookup directory 212 in DRAM 210 may be an in-memory lookup directory that may contain entries for all TDUs in the L2P translation table, and a first cache miss for the lookup directory entry for the corresponding TDU may result in the lookup directory entry for the TDU being retrieved from DRAM 210. In block 614, it may be determined that the lookup directory entry for the corresponding first TDU is invalid. In block 616, TDU space for the corresponding first TDU may be reserved in memory, and in block 618, a load request for the corresponding first TDU may be generated. For example, after the lookup directory 212 is initialized, all entries may be invalid, and the corresponding TDU may need to be loaded from the L2P table stored in the non-volatile storage device 202. A TDU space may need to be reserved in memory (e.g., DRAM 210) for the TDU to be loaded, and a TDU load request may be pushed into the TDU load request queue 518.

[0043] In various embodiments, process 600 and L2P engine 104 (or L2P engine 500) can be implemented in part or in whole using hardware (e.g., a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)), firmware, a computer processor executing software instructions, or any suitable combination. If L2P engine 104 (or L2P engine 500) is implemented in software, storage elements (e.g., queues, caches, and miss buffers) can be implemented in on-chip memory 106 or in off-chip memory (e.g., DRAM 210). In addition, in at least one embodiment, lookup directory 212 can be stored in on-chip memory 106.

[0044] In some embodiments, high throughput of the non-volatile storage system is not critical, and using part of the L2P translation table in a memory (eg, SRAM or DRAM) can achieve a good balance between cost, area, and throughput of the non-volatile storage system.

[0045] Embodiments of the present disclosure can use a partial logical-to-physical address translation table in a storage controller to reduce the storage space used to store logical-to-physical address translations in the storage controller. A subset of the complete L2P address translation table can be loaded into the memory of the storage controller. A lookup directory having a number of entries that matches the number of TDU entries in the complete L2P address translation table can be retained in the memory of the storage controller. The lookup directory can track which TDUs may have been loaded into the storage space of the storage controller.

[0046] Whenever a TDU is loaded from a non-volatile storage device into the storage controller's memory or flushed from the storage controller's memory to the non-volatile storage device, the corresponding lookup directory entry can be updated. A TDU can be loaded into any available TDU space in the storage controller's memory, and the lookup directory can track where the TDU was loaded into memory. If the lookup directory entry for the corresponding TDU is invalid, it means that the TDU is not in the storage controller's memory, and a load request for the TDU can be sent to the non-volatile storage device.

[0047] In some embodiments, the most recently accessed lookup directory entries can be retained in the cache, and the cache can be checked first to determine whether the lookup directory entry corresponding to the TDU is available in the cache. Cache misses can be tracked in a miss buffer (e.g., a miss status holding register (MSHR)). The miss buffer can handle multiple cache misses for requests for lookup directory entries for the same TDU or for lookup directory entries for different TDUs and reduce the TDU load overhead caused by using a partial L2P address table.

[0048] In an exemplary embodiment, a method is provided, which may include: receiving a request for a first logical data address (LDA); calculating a first TDU index for a corresponding first translation data unit (TDU), the first TDU containing a logical-to-physical (L2P) entry for the corresponding first LDA; searching a cache of lookup directory entries for a recently accessed TDU using the first TDU index; determining that the cache does not have a lookup directory entry for the corresponding first TDU; generating and storing a pending request for a lookup directory entry for the corresponding first TDU in a miss buffer; obtaining a lookup directory entry for the corresponding first TDU from an in-memory lookup directory in a memory; determining that the lookup directory entry for the corresponding first TDU is invalid; reserving TDU space for the first TDU in the memory; and generating a load request for the corresponding first TDU.

[0049] In one embodiment, generating and storing the pending request for the lookup directory entry corresponding to the first TDU in the miss buffer may also include: determining that this is the first cache miss for the lookup directory entry corresponding to the first TDU, adding the first TDU index to a miss status holding register (MSHR), and creating a request link list for the MSHR, wherein the pending request for the lookup directory entry corresponding to the first TDU is the first list entry of the request link list.

[0050] In one embodiment, generating and storing pending requests for the lookup directory entries corresponding to the first TDU in a miss buffer may also include: determining whether a request link list for the lookup directory entries corresponding to the first TDU exists in a miss status holding register (MSHR), inserting the pending requests into the request link list, and updating the end pointer in the MSHR.

[0051] In one embodiment, the first TDU index may be calculated by dividing the first LDA by the total number of L2P entries in the first TDU.

[0052] In one embodiment, the method may further include: obtaining a lookup directory entry corresponding to the second TDU from the in-memory lookup directory; determining that the lookup directory entry of the second TDU is valid; processing all pending requests for the lookup directory entry corresponding to the second TDU in the miss buffer; and updating the cache of lookup directory entries using the lookup directory entry corresponding to the second TDU.

[0053] In one embodiment, processing all pending requests for the lookup directory entries corresponding to the second TDU in the miss buffer may include: processing all pending requests for the lookup directory entries corresponding to the second TDU in a request link list in a miss status holding register (MSHR), releasing the request link list and clearing the MSHR.

[0054] In one embodiment, the method may further include: receiving a TDU load completion message corresponding to the first TDU; processing a pending request for the lookup directory entry corresponding to the first TDU in the miss buffer; updating the lookup directory entry of the first TDU in the in-memory lookup directory using the storage location of the first TDU; and updating the lookup directory entry of the first TDU in the cache of the lookup directory entry using the storage location of the first TDU.

[0055] In another exemplary embodiment, an apparatus is provided that may include: a processor and a logical-to-physical (L2P) translation engine. The L2P translation engine may include a cache of lookup directory entries for recently accessed translation data units (TDUs) and a miss buffer. Furthermore, the L2P translation engine may be configured to: receive a request for a first logical data address (LDA) from the processor; calculate a first TDU index for a first translation data unit (TDU), the first TDU containing a logical-to-physical (L2P) entry corresponding to the first LDA; search a cache of lookup directory entries for recently accessed TDUs using the first TDU index; determine that the cache does not have a lookup directory entry for the first TDU; generate and store a pending request for the lookup directory entry for the first TDU in the miss buffer; obtain the lookup directory entry for the first TDU from an in-memory lookup directory in a memory coupled to the apparatus; determine that the lookup directory entry for the first TDU is invalid; reserve TDU space for the first TDU in the memory and generate a load request for the first TDU.

[0056] In one embodiment, the pending request for the lookup directory entry corresponding to the first TDU is generated and stored in the miss buffer, and the L2P translation engine can also be configured to: determine that this is the first cache miss of the lookup directory entry corresponding to the first TDU, add the first TDU index to a miss status holding register (MSHR), and create a request link list for the MSHR, wherein the pending request for the lookup directory entry corresponding to the first TDU is used as the first list entry of the request link list.

[0057] In one embodiment, pending requests for the lookup directory entries corresponding to the first TDU are generated and stored in a miss buffer, and the L2P conversion engine can also be configured to: have a request link list corresponding to the lookup directory entries of the first TDU in a miss status holding register (MSHR), insert the pending requests into the request link list, and update the end pointer in the MSHR.

[0058] In one embodiment, the first TDU index may be calculated by dividing the first LDA by the total number of L2P entries in the first TDU.

[0059] In one embodiment, the L2P translation engine may be further configured to: obtain a lookup directory entry corresponding to the second TDU from the in-memory lookup directory; determine that the lookup directory entry of the second TDU is valid; process all pending requests for the lookup directory entry corresponding to the second TDU in the miss buffer; and update the cache of lookup directory entries using the lookup directory entry corresponding to the second TDU.

[0060] In one embodiment, all pending requests for the lookup directory entries corresponding to the second TDU are processed in the miss buffer, and the L2P conversion engine can also be configured to: process all pending requests for the lookup directory entries corresponding to the second TDU in the request link list in the miss status holding register (MSHR), release the request link list and clean up the MSHR.

[0061] In one embodiment, the L2P translation engine may be configured to: receive a TDU load completion message corresponding to a first TDU; process a pending request for the lookup directory entry corresponding to the first TDU in a miss buffer; update the lookup directory entry for the first TDU in an in-memory lookup directory using the storage location of the first TDU; and update the lookup directory entry for the first TDU in a cache of lookup directory entries using the storage location of the first TDU.

[0062] In another exemplary embodiment, the present disclosure may also include a non-temporary machine-readable medium having executable instructions that, when executed by a storage controller, may cause the storage controller to perform the following operations: receive a request for a first logical data address (LDA); calculate a first TDU index for a first translation data unit (TDU), the first TDU containing a logical-to-physical (L2P) entry corresponding to the first LDA; use the first TDU index to search a cache of lookup directory entries for a recently accessed TDU; determine that the cache does not have a lookup directory entry for the corresponding first TDU; generate and store a pending request for a lookup directory entry for the corresponding first TDU in a miss buffer; obtain a lookup directory entry for the corresponding first TDU from an in-memory lookup directory in a memory coupled to the storage controller; determine that the lookup directory entry for the corresponding first TDU is invalid; reserve TDU space for the first TDU in the memory and generate a load request for the first TDU.

[0063] In one embodiment, the pending request for the lookup directory entry corresponding to the first TDU is generated and stored in the miss buffer, and the executable instructions, when executed by the storage controller, may cause the storage controller to perform the following operations: determine that this is the first cache miss for the lookup directory entry corresponding to the first TDU, add the first TDU index to a miss status holding register (MSHR), and create a request link list for the MSHR, wherein the pending request for the lookup directory entry corresponding to the first TDU is the first list entry of the request link list.

[0064] In one embodiment, pending requests for the lookup directory entries corresponding to the first TDU are generated and stored in a miss buffer, and when the executable instructions are executed by the storage controller, the storage controller may perform the following operations: a request link list for the lookup directory entries corresponding to the first TDU exists in a miss status holding register (MSHR), the pending requests are inserted into the request link list, and the end pointer in the MSHR is updated.

[0065] In one embodiment, the first TDU index may be calculated by dividing the first LDA by the total number of L2P entries in the first TDU.

[0066] In one embodiment, the executable instructions, when executed by the storage controller, may cause the storage controller to perform the following operations: obtain a lookup directory entry corresponding to the second TDU from the in-memory lookup directory; determine that the lookup directory entry of the second TDU is valid; process all pending requests for the lookup directory entry corresponding to the second TDU in the miss buffer; and update the cache of lookup directory entries using the lookup directory entry corresponding to the second TDU.

[0067] In one embodiment, all pending requests for the lookup directory entries corresponding to the second TDU are processed in the miss buffer, and the executable instructions, when executed by the storage controller, can cause the storage controller to perform the following operations: process all pending requests for the lookup directory entries corresponding to the second TDU in a request link list in a miss status holding register (MSHR), release the request link list and clean up the MSHR.

[0068] In one embodiment, the executable instructions, when executed by a storage controller, cause the storage controller to perform the following operations: receive a TDU load completion message for a first TDU; process pending requests for a lookup directory entry corresponding to the first TDU in a miss buffer; update the lookup directory entry for the first TDU in the in-memory lookup directory using the storage location of the first TDU; and update the lookup directory entry for the first TDU in a cache of lookup directory entries using the storage location of the first TDU.

[0069] Any disclosed methods and operations may be implemented as computer-executable instructions (e.g., software code for the operations described herein) stored on one or more computer-readable storage media (e.g., non-transitory computer-readable media, such as one or more optical disk media, volatile storage components (e.g., DRAM or SRAM), or non-volatile storage components (e.g., SSD hard drives)) and executed on a device controller (e.g., firmware executed by an ASIC). Any computer-executable instructions for implementing the disclosed technology and any data created and used during the implementation of the disclosed embodiments may be stored on one or more computer-readable media (e.g., non-transitory computer-readable media).

[0070] Although various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for illustrative purposes only and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Claims

1. A data access method, characterized in that: include: receiving a request for a first logical data address; calculating a first index corresponding to a first converted data unit, the first converted data unit comprising a logical-to-physical entry corresponding to the first logical data address; searching a cache of lookup directory entries for a most recently accessed translation data unit using said first translation data unit index; determining that the cache does not have a lookup directory entry corresponding to the first translated data unit; generating and storing in a miss buffer a pending request for a lookup directory entry corresponding to the first translation data unit; Obtaining a lookup directory entry corresponding to the first converted data unit from an in-memory lookup directory in the memory; determining that the lookup directory entry corresponding to the first converted data unit is invalid; reserving, in the memory, a conversion data unit space for the first conversion data unit; generating a load request corresponding to the first conversion data unit; receiving a conversion data unit loading completion message corresponding to the first conversion data unit; processing, in the miss buffer, pending requests for the lookup directory entry corresponding to the first translation data unit; Using the storage location of the first converted data unit to update the lookup directory entry of the first converted data unit in the in-memory lookup directory; and A lookup directory entry of the first converted data unit in a cache of lookup directory entries is updated using the storage location of the first converted data unit.

2. The method according to claim 1, characterized in that Generating and storing the pending request for the lookup directory entry corresponding to the first conversion data unit in the miss buffer also includes: determining that this is the first cache miss for the lookup directory entry corresponding to the first conversion data unit, adding the first conversion data unit index to a miss status holding register, and creating a request link list for the miss status holding register, wherein the pending request for the lookup directory entry corresponding to the first conversion data unit is used as the first list entry of the request link list.

3. The method according to claim 1, characterized in that Generating and storing pending requests for the lookup directory entries corresponding to the first conversion data unit in a miss buffer also includes: determining whether a request link list for the lookup directory entries corresponding to the first conversion data unit exists in a miss status holding register, inserting the pending requests into the request link list, and updating the end pointer in the miss status holding register.

4. The method according to claim 1, wherein The first translation data unit index is calculated by dividing the first logical data address by a total number of logical-to-physical entries in the first translation data unit.

5. The method according to claim 1, wherein Also includes: Obtaining a search directory entry corresponding to the second converted data unit from the in-memory search directory; determining that the lookup directory entry of the second converted data unit is valid; processing all pending requests for the lookup directory entry corresponding to the second translation data unit in the miss buffer; and A cache of lookup directory entries is updated using the lookup directory entry corresponding to the second translated data unit.

6. The method according to claim 5, characterized in that Processing all pending requests for the lookup directory entries corresponding to the second conversion data unit in the miss buffer includes: processing all pending requests for the lookup directory entries corresponding to the second conversion data unit in a request link list in a miss status holding register, releasing the request link list and clearing the miss status holding register.

7. A data access device, characterized in that: include: processor, and a logical-to-physical translation engine including a cache of lookup directory entries of recently accessed translation data units and a miss buffer, the logical-to-physical translation engine being configured to; receiving a request for a first logical data address from the processor; calculating a first converted data unit index of a first converted data unit, the first converted data unit comprising a logical-to-physical entry corresponding to the first logical data address; searching a cache of lookup directory entries for a most recently accessed translation data unit using said first translation data unit index; determining that the cache does not have a lookup directory entry corresponding to the first translated data unit; generating and storing in the miss buffer a pending request for a lookup directory entry corresponding to the first translation data unit; obtaining a lookup directory entry corresponding to the first converted data unit from an in-memory lookup directory in a memory coupled to the apparatus; determining that the lookup directory entry corresponding to the first converted data unit is invalid; reserving, in the memory, a conversion data unit space for the first conversion data unit; generating a load request corresponding to the first conversion data unit; receiving a conversion data unit loading completion message corresponding to the first conversion data unit; processing, in the miss buffer, pending requests for the lookup directory entry corresponding to the first translation data unit; Using the storage location of the first converted data unit to update the lookup directory entry of the first converted data unit in the in-memory lookup directory; and A lookup directory entry of the first converted data unit in a cache of lookup directory entries is updated using the storage location of the first converted data unit.

8. The device according to claim 7, characterized in that In order to generate and store the pending request for the lookup directory entry corresponding to the first conversion data unit in the miss buffer, the logical-to-physical conversion engine is further configured to: determine that this is the first cache miss for the lookup directory entry corresponding to the first conversion data unit, add the first conversion data unit index to a miss status holding register, and create a request link list for the miss status holding register, wherein the pending request for the lookup directory entry corresponding to the first conversion data unit is used as the first list entry of the request link list.

9. The device according to claim 7, characterized in that In order to generate and store pending requests for the lookup directory entries corresponding to the first conversion data unit in the miss buffer, the logical-to-physical conversion engine is further configured to: provide a request link list for the lookup directory entries corresponding to the first conversion data unit in the miss status holding register, insert the pending requests into the request link list, and update the end pointer in the miss status holding register.

10. The device according to claim 7, characterized in that The first translation data unit index is calculated by dividing the first logical data address by a total number of logical-to-physical entries in the first translation data unit.

11. The device according to claim 7, characterized in that The logical-to-physical conversion engine is further configured to: obtain a lookup directory entry corresponding to the second conversion data unit from the in-memory lookup directory; determining that the lookup directory entry of the second converted data unit is valid; processing all pending requests for the lookup directory entry corresponding to the second translation data unit in the miss buffer; and A cache of lookup directory entries is updated using the lookup directory entry corresponding to the second translated data unit.

12. The device according to claim 11, characterized in that In order to process all pending requests for the lookup directory entries corresponding to the second conversion data unit in the miss buffer, the logical-to-physical conversion engine is also configured to: process all pending requests for the lookup directory entries corresponding to the second conversion data unit in the request link list in the miss status holding register, release the request link list and clear the miss status holding register.

13. A non-transitory machine-readable medium having executable instructions, characterized in that The executable instructions, when executed by the storage controller, cause the storage controller to perform the following operations: receiving a request for a first logical data address; calculating a first converted data unit index of a first converted data unit, the first converted data unit comprising a logical-to-physical entry corresponding to the first logical data address; searching a cache of lookup directory entries for a most recently accessed translation data unit using said first translation data unit index; determining that the cache does not have a lookup directory entry corresponding to the first translated data unit; generating and storing in a miss buffer a pending request for a lookup directory entry corresponding to the first translation data unit; obtaining a lookup directory entry corresponding to the first converted data unit from an in-memory lookup directory in a memory coupled to the storage controller; determining that the lookup directory entry corresponding to the first converted data unit is invalid; reserving, in the memory, a conversion data unit space for the first conversion data unit; generating a load request for a first conversion data unit; receiving a conversion data unit loading completion message corresponding to the first conversion data unit; processing, in the miss buffer, pending requests for the lookup directory entry corresponding to the first translation data unit; Using the storage location of the first converted data unit to update the lookup directory entry of the first converted data unit in the in-memory lookup directory; and A lookup directory entry of the first converted data unit in a cache of lookup directory entries is updated using the storage location of the first converted data unit.

14. The non-transitory machine-readable medium of claim 13, wherein: In order to generate and store the pending request for the lookup directory entry corresponding to the first conversion data unit in the miss buffer, the executable instructions, when executed by the storage controller, cause the storage controller to perform the following operations: determine that this is the first cache miss for the lookup directory entry corresponding to the first conversion data unit, add the first conversion data unit index to a miss status holding register, and create a request link list for the miss status holding register, wherein the pending request for the lookup directory entry corresponding to the first conversion data unit is the first list entry of the request link list.

15. The non-transitory machine-readable medium of claim 13, wherein: In order to generate and store pending requests for the lookup directory entries corresponding to the first conversion data unit in a miss buffer, the executable instructions, when executed by the storage controller, cause the storage controller to perform the following operations: a request link list for the lookup directory entries corresponding to the first conversion data unit exists in a miss status holding register, the pending requests are inserted into the request link list, and an end pointer in the miss status holding register is updated.

16. The non-transitory machine-readable medium of claim 13, wherein: The first translation data unit index is calculated by dividing the first logical data address by a total number of logical-to-physical entries in the first translation data unit.

17. The non-transitory machine-readable medium of claim 13, wherein: The executable instructions, when executed by the storage controller, further cause the storage controller to perform the following operations: Obtaining a search directory entry corresponding to the second converted data unit from the in-memory search directory; determining that the lookup directory entry of the second converted data unit is valid; processing all pending requests for the lookup directory entry corresponding to the second translation data unit in the miss buffer; and A cache of lookup directory entries is updated using the lookup directory entry corresponding to the second translated data unit.

18. The non-transitory machine-readable medium of claim 17, wherein: In order to process all pending requests for the lookup directory entries corresponding to the second conversion data unit in the miss buffer, the executable instructions, when executed by the storage controller, also cause the storage controller to perform the following operations: process all pending requests for the lookup directory entries corresponding to the second conversion data unit in the request link list in the miss status holding register, release the request link list and clear the miss status holding register.

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