Display panel and manufacturing method thereof, and display device

Abstract

Embodiments of the present disclosure provide a display panel and a preparation method thereof, and a display device, which relate to the field of display technology and are used to improve the problem of uneven brightness of the display panel during the display process. The display panel includes: a base substrate, an active pattern layer and a first conductive layer. Among them, the active pattern layer is arranged on the base substrate, and the active pattern layer includes: at least one first conductive connecting line. The first conductive layer is arranged on a side of the active pattern layer away from the base substrate, and the first conductive layer includes: at least one connecting line extending along a first direction, and a plurality of initialization signal lines arranged along the first direction and extending along a second direction, one end of each initialization signal line is coupled to a connecting line, wherein the first direction intersects with the second direction. A first conductive connecting line is coupled to at least two initialization signal lines, wherein the at least two initialization signal lines are coupled to the same connecting line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Display panels can be divided into multiple types according to different display principles. For example, an organic light-emitting diode (OLED) display panel may include multiple OLED devices containing organic light-emitting materials, wherein the organic light-emitting materials can emit light under the drive of an electrical signal. By adjusting the size of the electrical signal driving each OLED device, the light-emitting brightness of the OLED device can be changed, so that the OLED display panel can display images. Summary of the invention

[0003] In the related art, when the initialization signal line in the display panel transmits the initialization signal to the pixel driving circuit coupled thereto, the transmitted signal gradually attenuates during the transmission process due to the voltage drop on the initialization signal line, resulting in an inaccurate signal finally transmitted to the pixel driving circuit, thereby causing the problem of uneven brightness of the display screen. To solve this problem, the embodiments of the present disclosure adopt the following technical solutions:

[0004] In a first aspect, a display panel is provided, the display panel comprising: a base substrate, an active pattern layer and a first conductive layer. The active pattern layer is arranged on the base substrate, and the active pattern layer comprises: at least one first conductive connection line. The first conductive layer is arranged on a side of the active pattern layer away from the base substrate, and the first conductive layer comprises: at least one connection line extending along a first direction; and a plurality of initialization signal lines arranged along the first direction and extending along a second direction, one end of each initialization signal line is coupled to a connection line, wherein the first direction intersects with the second direction. A first conductive connection line is coupled to at least two initialization signal lines, wherein the at least two initialization signal lines are coupled to the same connection line.

[0005] In some embodiments, the display panel has a through hole. The plurality of initialization signal lines include a plurality of first initialization signal lines, and the other end of each first initialization signal line extends to the through hole. One of the first conductive connection lines is coupled to at least two first initialization signal lines, wherein the at least two first initialization signal lines are coupled to the same connection line.

[0006] In some embodiments, the first conductive layer includes: two connecting lines arranged opposite to each other. The plurality of initialization signal lines also include a plurality of second initialization signal lines arranged along the first direction and extending along the second direction, wherein both ends of each second initialization signal line are coupled to a connecting line respectively. Each first conductive connecting line is also coupled to at least one second initialization signal line.

[0007] In some embodiments, the active pattern layer further includes at least one second conductive connection line, and each second conductive connection line is coupled to at least two second initialization signal lines.

[0008] In some embodiments, the display panel further comprises at least one first connection pattern disposed on a side of the first conductive layer away from the base substrate. One of the first conductive connection lines is coupled to one of the initialization signal lines through one of the first connection patterns.

[0009] In some embodiments, a coupling point where the one first connection pattern is coupled to the one initialization signal line is located at a crossing position of the one first conductive connection line and the one initialization signal line coupled through the first connection pattern.

[0010] In some embodiments, the first conductive connection line extends along the first direction and is in a straight strip shape.

[0011] In some embodiments, the display panel further comprises a second conductive layer, the second conductive layer being disposed between the base substrate and the active pattern layer; the second conductive layer comprising at least one conductive line extending along a third direction. A conductive line is coupled to an initialization signal line through at least two coupling points.

[0012] In some embodiments, the third direction is parallel to the second direction.

[0013] In some embodiments, the display panel further comprises at least one second connection pattern disposed on a side of the first conductive layer away from the base substrate; wherein the one conductive line is coupled to the one initialization signal line through a second connection pattern.

[0014] In some embodiments, a first conductive signal line, an initialization signal line, and a conductive line are coupled through a second connection pattern.

[0015] In some embodiments, the active pattern layer further comprises a plurality of active layers. The second conductive layer further comprises a plurality of light shielding patterns. The orthographic projection of an active layer on the base substrate is located within the orthographic projection of a light shielding pattern on the base substrate.

[0016] In some embodiments, the display panel further includes a power signal line disposed on a side of the first conductive layer away from the base substrate; and the plurality of light shielding patterns are coupled to the power signal line.

[0017] In some embodiments, the display panel further includes: a third connection pattern disposed on a side of the first conductive layer away from the base substrate, the third connection pattern being configured to couple each first initialization signal line.

[0018] At least one first conductive connection line is arranged on the active pattern layer, and one first conductive connection line is coupled to at least two initialization signal lines, so that the at least two initialization signal lines are connected in parallel, and the equivalent resistance of the initialization signal lines after being connected in parallel is smaller than the resistance of each initialization signal line, so that the voltage drop on each initialization signal line can be reduced. When the voltage drop on the initialization signal line is reduced, the attenuation of the initialization signal transmitted through the initialization signal line is also reduced, so that the initialization signal written into each sub-pixel is more accurate, thereby improving the display unevenness problem of the display panel and improving the display quality of the display device.

[0019] In a second aspect, a display device is provided, wherein the display device comprises the display panel described in any one of the above embodiments.

[0020] The beneficial effects that can be achieved by the display device provided by the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display panel described in any of the above embodiments, and will not be elaborated here.

[0021] In a third aspect, a method for preparing a display panel is provided, comprising: forming an active pattern layer on a base substrate, the active pattern layer comprising: at least one first conductorized connecting line; forming a first conductive layer on a side of the active pattern layer away from the base substrate, the first conductive layer comprising: at least one connecting line extending along a first direction, and a plurality of initialization signal lines arranged along the first direction and extending along a second direction, one end of each initialization signal line being coupled to a connecting line; wherein the first direction intersects with the second direction; one of the first conductorized connecting lines is coupled to at least two initialization signal lines, wherein the at least two initialization signal lines are coupled to the same connecting line.

[0022] In some embodiments, forming an active pattern layer on the base substrate includes: forming at least one semiconductor connection line on the base substrate, and conducting the at least one semiconductor connection line to obtain an active pattern layer including at least one first conductorized connection line.

[0023] The beneficial effects that can be achieved by the method for preparing a display panel provided in the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the display panel described in any of the above embodiments, and will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1A A structural diagram of a display panel in the related art;

[0026] Figure 1B is a structural diagram of another display panel in the related art;

[0027] Figure 2A A structural diagram of a display panel provided for some embodiments of the present disclosure;

[0028] Figure 2B for Figure 2A A cross-sectional view of a display panel in FIG.

[0029] Figure 3A A top view of a driving backplane of a display panel provided for some embodiments of the present disclosure;

[0030] Figure 3B A top view of another driving backplane of a display panel provided for some embodiments of the present disclosure;

[0031] Figure 3C For along Figure 3B A cross-sectional view of the drive backplane taken along line A-A';

[0032] Figure 4A is an equivalent circuit diagram of a pixel driving circuit in the related art;

[0033] Figure 4B A top view of a driving backplane of another display panel provided for some embodiments of the present disclosure;

[0034] Figure 5A for Figure 4B A structural diagram of a pattern layer of a driving backplane;

[0035] Figure 5B for Figure 4B The structural diagram of the two pattern layers of the driving backplane;

[0036] Figure 5C for Figure 4BThe structural diagram of the three pattern layers of the driving backplane;

[0037] Figure 5D for Figure 4B The structural diagram of the four pattern layers of the driving backplane;

[0038] Figure 6 A top view of a driving backplane of another display panel provided for some embodiments of the present disclosure;

[0039] Figure 7 A top view of a driving backplane of another display panel provided for some embodiments of the present disclosure;

[0040] Figure 8 For along Figure 7 A cross-sectional view taken along line BB' of the driving backplane shown;

[0041] Fig. 9 A structural diagram of a driving backplane of another display panel provided for some embodiments of the present disclosure;

[0042] Fig.10 A top view of a driving backplane of another display panel provided for some embodiments of the present disclosure;

[0043] Fig.11 A top view of a driving backplane of another display panel provided for some embodiments of the present disclosure;

[0044] Fig.12 A flow chart of a method for preparing a display panel provided for some embodiments of the present disclosure;

[0045] Fig.13 A process flow chart of another method for preparing a display panel provided for some embodiments of the present disclosure;

[0046] Fig.14 A process flow chart of another method for preparing a display panel provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0050] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0051] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0052] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0053] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0057] The "same-layer arrangement" of multiple patterns means that multiple patterns belong to the same pattern layer, that is, multiple patterns are formed by the same composition process, wherein the composition process refers to a process that can simultaneously form multiple patterns on a carrier surface. For example, multiple patterns are organic materials, and the composition process may be evaporation or printing, etc. For another example, multiple patterns are metal materials. In this case, the composition process may include: first forming a thin film by a film forming process, and then patterning the thin film to form a pattern layer containing multiple patterns; wherein the patterning process may include: coating photoresist, exposure, development, etching and other processes. It should be noted that multiple patterns may be at least partially connected or spaced from each other. In addition, multiple patterns may have different thicknesses (it can be said to be heights). For example, the multiple layers shown in the drawings in this embodiment may all be pattern layers, such as an active pattern layer, a first conductive layer, a second conductive layer, and the like.

[0058] Some display panels, such as OLED display panels, include a pixel driving circuit and an initialization signal line, wherein the initialization signal line is configured to transmit an initialization signal to the pixel driving circuit, wherein Figure 1A, the initialization signal line Vint can be led out from the IC and can extend from one side aa of the display panel to the other side bb opposite thereto. In the related art, when the initialization signal line transmits the initialization signal to the pixel driving circuit coupled thereto, due to the voltage drop on the initialization signal line, the transmitted signal gradually attenuates during the transmission process, resulting in an inaccurate signal finally transmitted to the pixel driving circuit, thereby causing the problem of uneven brightness of the display screen.

[0059] In addition, for display devices with camera or sensing functions, it is also necessary to punch holes (i.e., open physical holes) at specific locations on the display panel to ensure that light can pass through the display panel into the camera or sensing device. The physical holes will interrupt some initialization signal lines, and the voltage drop of the interrupted initialization signal lines will be further increased, thereby affecting the normal light emission of the sub-pixels located on both sides of the physical holes, resulting in lateral display unevenness problems in the display panel.

[0060] See also Figure 1B , the edge of the physical hole in the display screen is shown by a circle, and the initialization signal lines a, b, and c are the initialization signal lines that are interrupted in AA as mentioned above; in addition, the display screen also includes several initialization signal lines that are continuous in AA, such as Figure 1B Initialization signal lines d and e in the display. Since the initialization signal lines a, b, and c are disconnected at the location of the physical hole, and the ends of the disconnected initialization signal lines extending to the physical hole cannot be connected to the connection lines CL located on the opposite sides of the display screen, the voltage drop on the interrupted initialization signal lines in AA is larger than the voltage drop on the continuous initialization signal lines in AA. The large voltage drop on the initialization signal line causes the initialization signal transmitted by the initialization signal line to attenuate, and the attenuated initialization signal is written into the corresponding pixel driving circuit, which reduces the charging rate of the pixel driving circuit. For example, from one side of the display screen to the edge of the physical hole, the charging rate of each pixel driving circuit gradually decreases, which will appear as a horizontal bar with a gradually changing brightness on a macro scale, that is, uneven horizontal display.

[0061] In order to solve the above problems, the embodiments of the present disclosure provide a display device. The display device refers to a product with an image display function, and can be, for example, a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a monitor, a navigator, a vehicle, a large-area wall, a home appliance, an information query device (such as business query devices of e-government, banks, hospitals, power departments, etc.), a monitor, etc.

[0062] The display device generally includes a display panel, and illustratively, the display panel may be an OLED (Organic Light Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, a micro LED (including: miniLED or microLED) display panel, etc. In addition, the display device may also include other components, such as a power supply system for supplying power to the display panel, a circuit board connected to the display panel, etc.

[0063] Figure 2A FIG. 1 shows a top view of a display panel provided by some embodiments of the present disclosure. The display panel 10 has a display area AA and a peripheral area SS located at at least one side of the display area AA. Figure 2A , the peripheral area SS is arranged around the display area AA, but is not limited thereto. For example, the peripheral area SS may be arranged only on one side of the display area AA. The display panel 10 further includes a plurality of sub-pixels P arranged in the display area AA. For example, the plurality of sub-pixels P may be arranged as follows: Figure 2A As shown, the sub-pixels P are arranged in an array to form a plurality of sub-pixel rows and a plurality of sub-pixel columns. Of course, the number and arrangement of the sub-pixels P are not limited to those shown in the figure, and can be designed as required.

[0064] Figure 2B The display panel provided by some embodiments of the present disclosure is shown. The display panel 10 may include a driving backplane 100 and a plurality of light-emitting devices 200. For example, the driving backplane 100 includes a substrate 101 and a plurality of pixel driving circuits D disposed on the substrate 101. Each pixel driving circuit D is coupled to a light-emitting device 200 to form a sub-pixel P. The pixel driving circuit D is configured to drive the light-emitting device 200 coupled thereto to emit light. The plurality of pixel driving circuits D may be arranged in order on the substrate 101. For example, the plurality of pixel driving circuits D may be distributed in an array on the substrate 210.

[0065] The light-emitting device 200 is the main structure for the sub-pixel P to realize light emission, and each light-emitting device 200 can be a structure in which multiple layers of thin films are stacked. Exemplarily, the light-emitting device 200 includes a cathode 230 and an anode 210, and a light-emitting functional layer 220 located between the cathode 230 and the anode 210. Among them, the light-emitting functional layer 220 may include, for example, a light-emitting layer 224, a hole transport layer 222 (Hole Transporting Layer) located between the light-emitting layer 224 and the anode 210, and an electron transport layer 226 (Election Transporting Layer) located between the light-emitting layer 224 and the cathode 230. Of course, as needed, in some embodiments, a hole injection layer 221 (Hole Injection Layer) may be provided between the hole transport layer 222 and the anode 210, and an electron injection layer 227 (Election Injection Layer) may be provided between the electron transport layer 226 and the cathode 230. In addition, an electron blocking layer 223 (Electron Blocking Layer) may be provided between the hole transport layer 222 and the light emitting layer 224 , and a hole blocking layer 225 (Hole Blocking Layer) may be provided between the electron transport layer 226 and the light emitting layer 224 .

[0066] Figure 3A A top view of a driving backplane 100 of a display panel provided in some embodiments of the present disclosure. The driving backplane 100 may include a plurality of layers. Figure 3A Shown in different fill patterns.

[0067] Exemplarily, the driving backplane 100 includes an active pattern layer 110 and a first conductive layer 120. The active pattern layer 110 is disposed on the base substrate 101, and the first conductive layer 120 is disposed on a side of the active pattern layer 110 away from the base substrate 120. For example, after the active pattern layer 110 is formed on the base substrate 101, an insulating layer (referred to as a first insulating layer) may be first formed on a side of the active pattern layer 110 away from the base substrate, and then the first conductive layer 120 may be formed on a side of the first insulating layer away from the active pattern layer 110, so that the active pattern layer 110 and the first conductive layer 120 may be separated by the first insulating layer.

[0068] See also Figure 3A, the active pattern layer 110 of the driving backplane 100 includes: at least one first conductorized connecting line 111. Conductivity refers to a process in which an object with originally poor conductivity is subjected to a certain treatment to enhance its conductivity. Among them, poor conductivity is a relative concept. For example, the conductivity of an insulator is poor relative to that of a semiconductor or a conductor, and the conductivity of a semiconductor is poor relative to that of a conductor. Exemplarily, the conductorization can be a doping process. For example, the first conductorized connecting line 111 in the driving backplane 100 can be obtained by doping a semiconductor connecting line, wherein the material forming the semiconductor connecting line can be polysilicon.

[0069] The number of first conductive connecting lines 111 in the active pattern layer 110 can be one or more. Exemplarily, the active pattern layer 110 includes multiple first conductive connecting lines 111, and may also include other conductive patterns or semiconductor patterns, wherein the semiconductor pattern can be used to form the gate of the transistor, and the conductive pattern can be used to form the source or drain of the transistor.

[0070] The embodiment of the present disclosure does not limit the shape of the first conductive connection line 111, and it can be designed as needed. For example, the first conductive connection line 111 can be in a straight bar shape, a wavy shape, or a zigzag shape. When the first conductive connection line 111 is in a wavy shape or a zigzag shape, it can include multiple periodic repeated line segments, and the extension direction of the connection line of each repeated line segment at the same position can be used as the extension direction of the first conductive connection line 111. When there are multiple first conductive connection lines 111, the extension directions of the multiple first conductive connection lines 111 can be roughly parallel, for example, the angle between the extension directions of any two first conductive connection lines 111 does not exceed 5°. The extension directions of these first conductive connection lines 111 can be designed as needed.

[0071] Continue to see Figure 3A The first conductive layer 120 of the driving backplane 100 includes: at least one connecting line 121 extending along the first direction Y, and a plurality of initialization signal lines Vint arranged along the first direction Y and extending along the second direction X, one end of each initialization signal line Vint is coupled to a connecting line 121; wherein the first direction Y intersects the second direction X.

[0072] Exemplarily, the first direction Y is a horizontal direction, and the second direction X is a vertical direction. When the first direction Y intersects the second direction X, the angle between the first direction Y and the second direction X is a right angle. Of course, the embodiments of the present disclosure do not limit the specific directions of the first direction Y and the second direction X. For example, the angle formed by the intersection of the first direction Y and the second direction X may be an acute angle or an obtuse angle.

[0073] The initialization signal line is configured in the display panel to transmit an initialization signal, and the initialization signal may come from the IC of the display device. Exemplarily, each connection line 121 may be located in the peripheral area SS of the display panel 10, and at least one connection line 121 is coupled to a signal providing circuit (e.g., IC) of the display device. When the display device 10 displays a picture, at least one connection line 121 may receive an initialization signal from the IC and transmit the received initialization signal to the sub-pixel P of the display panel 10. Exemplarily, the display panel includes only one connection line, such as Figure 3A 121a or 121b in the display panel receives the initialization signal provided by the IC. For example, the display panel includes two connecting lines 121a and 121b. The connecting line 121a can receive the initialization signal provided by the IC. Of course, only the connecting line 121b can receive the initialization signal provided by the IC, or the connecting lines 121a and 121b can receive the initialization signal from the IC respectively.

[0074] In the case where the first conductive layer 120 includes only one connection line 121, all initialization signal lines Vint in the display panel are coupled to the connection line; in the case where the first conductive layer 120 includes multiple connection lines 121, the initialization signal line Vint can be coupled to at least one connection line 121 among the multiple connection lines 121. Exemplarily, one initialization signal line Vint is coupled to only one connection line 121. For example, the display panel includes two connection lines 121a and 121b, and one initialization signal line Vint can be coupled to only the connection line 121a, or to only the connection line 121b. Then, the display panel can include multiple initialization signal lines coupled only to the connection line 121a and multiple initialization signal lines coupled only to the connection line 121b. Another exemplary embodiment is that one initialization signal line Vint is coupled to two connection lines 121 at the same time. For example, see Figure 3A One end of an initialization signal line Vint is coupled to the connection line 121a, and the other end is coupled to the connection line 121b. For ease of description, hereinafter, an initialization signal line coupled to only one connection line is referred to as a first initialization signal line, and an initialization signal line having both ends coupled to one connection line is referred to as a second initialization signal line.

[0075] A connection line 121 can transmit the initialization signal to the sub-pixels P coupled to the initialization signal lines Vint in the display panel 10 (the sub-pixels P are connected to the initialization signal lines Vint). Figure 2A). Exemplarily, one initialization signal line Vint may be coupled to a plurality of sub-pixels P. For example, the plurality of sub-pixels P coupled to one initialization signal line Vint may be sub-pixels in the same row. Each sub-pixel P is coupled to the initialization signal line Vint through one or more nodes in the pixel driving circuit D to initialize the voltage of the one or more nodes in the pixel driving circuit.

[0076] One first conductive connection line is coupled to at least two initialization signal lines Vint, wherein at least two initialization signal lines Vint are coupled to the same connection line 121 .

[0077] Exemplarily, a first conductive connection line 111 is coupled to two initialization signal lines Vint, for example, Figure 3A The first conductorized connection line 111 is coupled to the initialization signal lines Vint(a) and Vint(b) at the same time. When the initialization signal line Vint(a) and the initialization signal line Vint(a) are coupled together through the first conductorized connection line 111, the initialization signal line Vint(a) and the initialization signal line Vint(b) are connected in parallel, and the equivalent resistance formed after the parallel connection is smaller than the resistance of either the initialization signal line Vint(a) or the initialization signal line Vint(b), so that the voltage drop on each initialization signal line (Vint(a), Vint(b)) is reduced compared to when they are not connected in parallel, so that the signal loss on the first initialization signal line (Vint(a), Vint(b)) can also be reduced.

[0078] When the voltage drop on the initialization signal line decreases, the difference in initialization signals received by each sub-pixel P coupled to the initialization signal line decreases. For example, the initialization signals (initial voltages) received by each pixel driving circuit coupled to the initialization signal line are almost equal. Then, the voltage of the corresponding node in each pixel driving circuit reaches the preset voltage value after initialization, or only has a small deviation from the preset voltage value. In this way, the charging rate of each pixel driving circuit is almost the same, thereby reducing the brightness difference of the light emitted by each sub-pixel.

[0079] In the embodiment of the present disclosure, at least one first conductive connection line 111 is provided on the active pattern layer 110, and one first conductive connection line 111 is coupled to at least two initialization signal lines Vint, so that the at least two initialization signal lines Vint are connected in parallel, and the equivalent resistance of the initialization signal lines Vint after being connected in parallel is smaller than the resistance of each initialization signal line Vint, so that the voltage drop on each initialization signal line Vint can be reduced. When the voltage drop on the initialization signal line Vint is reduced, the attenuation of the initialization signal transmitted through the initialization signal line Vint is also reduced, so that the initialization signal written to each sub-pixel is more accurate, thereby improving the display unevenness problem of the display panel and improving the display quality of the display device.

[0080] Figure 3B A top view of another driving backplane 100 of a display panel provided for some embodiments of the present disclosure. The driving backplane 100 includes a through hole H. The through hole H is a hole that passes through the driving backplane 100 on opposite sides in the thickness direction, and the size and position of the hole can be designed as needed. The number of through holes in the driving backplane 100 can be multiple, and when the driving backplane 100 includes multiple through holes H, the position and arrangement of each through hole can be designed according to actual conditions. The embodiments of the present disclosure are all described by taking the driving backplane including one through hole H as an example.

[0081] Continue to see Figure 3B The first conductive layer 120 of the driving backplane 100 includes: at least one connecting line 121 extending along the first direction Y, and a plurality of first initialization signal lines 122 arranged along the first direction Y and extending along the second direction X, wherein the first initialization signal line 122 is a type of initialization signal line Vint, one end of each first initialization signal line 122 is coupled to a connecting line 121, and the other end extends to the through hole H, wherein the first direction Y intersects the second direction X.

[0082] Exemplarily, the first conductive layer 120 includes a plurality of connection lines 121 extending along the first direction Y, for example, see Figure 3B The first conductive layer 120 includes a connecting line 121a and a connecting line 121b. The connecting lines 121a and 121b can be respectively arranged on opposite sides of the driving backplane 100. For example, the connecting lines 121a and 121b are respectively arranged in the peripheral area SS located on opposite sides of the display panel 10. Figure 3B, the first conductive layer 120 also includes a plurality of first initialization signal lines 122 arranged along the first direction Y and extending along the second direction X. The first initialization signal lines 122 may be broken lines caused by the through hole H, so the number of broken lines depends on the size of the through hole H. Among them, since each row of sub-pixels in the display panel must be connected to the initialization signal lines extending in the X direction, the distance between the initialization signal lines extending in the X direction is roughly the same as the size of a sub-pixel in the Y direction (or the width of a row of sub-pixels extending in the X direction). For example, when the number of sub-pixel rows removed due to the through hole H is multiple (denoted as N, N≥2; for example, N=9, or N=15), the number of first initialization signal lines 122 connected to a connection line 121 is also multiple (denoted as M, M≥2; for example, M=N, or, M=N+1, or M=N-1). Figure 3B 1 and 2 are schematically shown the first initialization signal lines 122a, 122b, 122c and 122d included in the first conductive layer 120. The first initialization signal lines 122a and 122b are connected to the same connection line 121a and are arranged at intervals along the first direction Y. The first initialization signal lines 122c and 122c are connected to the same connection line 121b and are arranged at intervals along the first direction Y. In addition, the distances between two adjacent first initialization signal lines 122 may be equal or unequal.

[0083] One end of each first initialization signal line 122 is coupled to a connection line 121, and the other end extends to the through hole H, for example, see Figure 3B One end of the first initialization signal line 122a (or 122b) may be coupled to a connection line 121a on the left side, and the other end may extend to the through hole H. One end of the first initialization signal line 122c (or 122d) may be coupled to a connection line 121b on the right side, and the other end may extend to the through hole H.

[0084] One first conductive connection line 111 is coupled to at least two first initialization signal lines 122, wherein the at least two first initialization signal lines 122 are coupled to the same connection line 121. The equivalent resistance formed by the two first initialization signal lines 122 coupled by the first conductive connection line 111 is smaller than the resistance of any of the two first initialization signal lines 122, so that the voltage drop on the two first initialization signal lines 122 is reduced, which is conducive to ensuring the accuracy of the signals transmitted by each.

[0085] In the sub-pixels P coupled by a first initialization signal line 122, due to the voltage drop on the first initialization signal line, the pixel driving circuit of the sub-pixel closest to the connection line has the highest charging rate, and the pixel driving circuit of the sub-pixel closest to the through hole H has the lowest charging rate. In the light-emitting stage, the brightness of the sub-pixel closest to the connection line is the brightest, the brightness of the sub-pixel closest to the through hole is the darkest, and the brightness of the middle sub-pixel is between the two. When the voltage drop on the first initialization signal line is reduced, the brightness of each sub-pixel is close to the brightest sub-pixel, so that the brightness difference between the brightest sub-pixel and the darkest sub-pixel is reduced. For the display device, the brightness gradient from one side of the display device to the physical hole will become less obvious.

[0086] In some embodiments, the active pattern layer 110 includes a plurality of first conductive connection lines 111, and each of the first conductive connection lines 111 is coupled to at least two initialization signal lines Vint. The embodiment of the present disclosure does not limit the arrangement of the plurality of first conductive connection lines 111, and can be designed as required, for example, see Figure 3A and Figure 3B , a plurality of first conductive connecting lines 111 may be arranged in parallel.

[0087] For example, see Figure 3B , taking the first initialization signal line as an example, the first initialization signal lines 122a and 122b are coupled through a plurality of first conductive connection lines 111 located between the connection line 121a and the through hole H, wherein the first initialization signal line 122a and the first initialization signal line 122b between each two adjacent first conductive connection lines 111 can be regarded as a parallel relationship, for example, the resistance formed by a portion of the first initialization signal line 122a and a portion of the first initialization signal line 122b in parallel between each two adjacent first conductive connection lines 111 is respectively Figure 3B R1, R2, and R3 are shown in the dotted box. Among them, R1, R2, and R3 are in parallel with each other. In this way, the first initialization signal line 122a and the first initialization signal line 122b between the connection line 121a and the through hole H are connected in parallel for many times, and their equivalent resistance is further reduced compared with only being connected in parallel once, so that the voltage drop on each first initialization signal line 122a and 122b is lower than when coupled through only one first conductive connection line 111, so that the initialization signal written into the pixel driving circuit through the first initialization signal lines 122a and 122b becomes more accurate.

[0088] In some embodiments, see Figure 3B, the first conductive layer 120 includes two connecting lines 121a and 121b arranged opposite to each other; the first conductive layer 120 also includes: a plurality of second initialization signal lines 123 arranged along the first direction Y and extending along the second direction X, wherein the second initialization signal lines 123 are a type of initialization signal lines Vint, and both ends of each second initialization signal line 123 are coupled to a connecting line 121. When both ends of the second initialization signal line 123 are coupled to the connecting line 121, the voltage drop generated on the second initialization signal line 123 is extremely small or almost zero.

[0089] Exemplarily, a plurality of second initialization signal lines 123 may be arranged at certain intervals on both sides of the first initialization signal line 122, for example, Figure 3B The second initialization signal lines 123 are located at the upper and lower sides of the through hole, and each second initialization signal line 123 is arranged at an equal distance. At the same time, the distance between a second initialization signal line 123 and a first initialization signal line 122 is also equal.

[0090] Each first conductive connection line 111 is also coupled to at least one second initialization signal line 123. Exemplarily, each first conductive connection line 111 is coupled to at least two first initialization signal lines 122 and at the same time is coupled to one second initialization signal line 123. Since the voltage drop on the second initialization signal line is extremely small or almost zero, when at least two first initialization signal lines 122 are coupled to one second initialization signal line 123, the at least two first initialization signal lines 122 and one second initialization signal line 123 are connected in parallel, and after the parallel connection, the voltage drop on each first initialization signal line 122 is smaller than the voltage drop on the second initialization signal line 123, so that the voltage drop on the first initialization signal line 122 can be greatly reduced.

[0091] As another example, each first conductive connection line 111 can be coupled to multiple second initialization signal lines 123 while coupling at least two first initialization signal lines 122. The more second initialization signal lines 123 are coupled, the more second initialization signal lines 123 are connected in parallel to each first initialization signal line 122, and the smaller the voltage drop generated on each first initialization signal line 122 after being connected in parallel. For example, each first conductive connection line 111 couples each second initialization signal line 123 in the driving backplane. In this case, the voltage drop on each second initialization signal line 123 can be minimized. For another example, a first conductive connection line 111 only couples a few second initialization signal lines 123 in the driving backplane, that is, the number of second initialization signal lines 123 coupled to the at least one first conductive connection line 111 is less than the total number of second initialization signal lines 123 in the driving backplane.

[0092] In some embodiments, see Figure 3B The active pattern layer 110 further includes: at least one second conductive connection line 112, each second conductive connection line 112 is coupled to at least two second initialization signal lines 123. When at least two second initialization signal lines 123 are coupled through one second conductive connection line 112, the at least two second initialization signal lines 123 can be connected in parallel. When at least two second initialization signal lines 123 are coupled through multiple second conductive connection lines 112, the at least two second initialization signal lines 123 can be connected in parallel for multiple times, thereby further reducing the voltage drop on each second initialization signal line 123. The principle is the same as that when at least two first initialization signal lines 122 are connected in parallel, and will not be repeated.

[0093] Some embodiments of the present disclosure provide a driving backplane 100 , which is provided with a plurality of pixel driving circuits.

[0094] The embodiments of the present disclosure do not limit the specific structure of the pixel driving circuit, and can be designed according to actual conditions. Exemplarily, the pixel driving circuit is composed of electronic devices such as thin film transistors (Thin Film Transistor, referred to as TFT), capacitors (Capacitance, referred to as C). For example, the pixel driving circuit may include two thin film transistors (a switching transistor and a driving transistor) and a capacitor to form a 2T1C structure; of course, the pixel driving circuit may also include more than two thin film transistors (multiple switching transistors and a driving transistor) and at least one capacitor, for example, the pixel driving circuit may include a capacitor and seven transistors to form a 7T1C structure.

[0095] The structure of the pixel driving circuit is described below by taking the pixel driving circuit of 7T1C structure as an example. Figure 4A , which shows an equivalent circuit diagram of a pixel driving circuit of a 7T1C structure. The pixel driving circuit includes: a capacitor Cst, a plurality of switching transistors (T1, T2, T4, T5, T6, T7) and a driving transistor T3. The letters (Vint, Re, G, EM, Vdata, VDD) in the figure represent the signal lines coupled to the corresponding transistors, for example, Vint represents the initialization signal line, Re represents the first reset signal line, Re' represents the second reset signal line, G represents the scanning control signal line, EM represents the light emitting control signal line, Vdata represents the data signal line, and VDD represents the power supply signal line, wherein the signal transmitted by Re' is the same as the signal transmitted by G.

[0096] For example, Figure 4AAs shown, the control electrode (gate) of a part of the switching transistors (for example, T1) is coupled to the reset signal line Re for receiving a first reset signal; the control electrode (gate) of a part of the switching transistors (for example, T7) is coupled to the reset signal line Re' for receiving a second reset signal. The control electrode of another part of the switching transistors (for example, T2, T4) is coupled to the scan control signal line G for receiving a scan control signal. Among them, the second reset signal is the same as the scan control signal. The control electrode of another part of the switching transistors (for example, T5, T6) is coupled to the light-emitting control signal line EM for receiving a light-emitting control signal. For example, transistors T1 and T7 are turned on in response to the reset signal, and the initialization signal (transmitted through the initialization signal line Vint) is transmitted to the control electrode (g) of the driving transistor T3 and the anode of the light-emitting device L through transistors T1 and T7, respectively, so as to achieve the purpose of resetting the anode of the light-emitting device L and the control electrode of the driving transistor T3. Under the control of the scanning control signal (transmitted by the scanning control signal G), transistors T2 and T4 are turned on, the control electrode g of the driving transistor T3 is coupled to the drain electrode (d), and the driving transistor T3 is in a diode-on state.

[0097] (transmitted through the data signal line Vdata) is written to the source (s) of the driving transistor T3 through the transistors T2 and T4, and the threshold voltage of the driving transistor T3 is compensated. Under the control of the light-emitting control signal (transmitted through the light-emitting control signal EM), the transistors T5 and T6 are turned on, and the driving current is transmitted to the light-emitting device L through the above-mentioned current path to drive the light-emitting device L to emit light. Exemplarily, one pole (e.g., an anode) of the light-emitting device L receives the driving current from the pixel circuit, and the other pole (e.g., a cathode) of the light-emitting device L is coupled to a fixed voltage terminal; for example, the fixed voltage terminal is configured to transmit a DC voltage, such as a DC low voltage.

[0098] Figure 4B The structure diagram of the pixel driving circuit of the 7T1C structure on the driving backplane is shown. The driving backplane is formed by stacking multiple pattern layers. Exemplarily, the driving backplane includes a base substrate, and an active pattern layer, a fourth conductive layer, a first conductive layer and a third conductive layer sequentially formed on the base substrate. FIG. 5A to FIG. 5D The specific structure of each pattern layer is shown in sequence.

[0099] in, Figure 5A The specific structure of the active pattern layer in the driving backplane is shown, wherein the active pattern layer includes the active layers T1a to T7a of the switching transistors (T1, T2, T4, T5, T6, T7) and the driving transistor T3, as shown in FIG. Figure 5A As shown in the dotted box in (taking only one pixel driving circuit as an example).

[0100] Figure 5B The specific structure of the fourth conductive layer of the driving backplane is also shown, wherein the fourth conductive layer can form the gates T1g to T7g of the switching transistors (T1, T2, T4, T5, T6, T7) and the driving transistors T3. In addition, the fourth conductive layer can also form the corresponding first reset signal line Re, the second reset signal line Re', the scanning control signal line G, the light emitting control signal line EM and the first plate Cst1 of the capacitor Cst.

[0101] Figure 5C The specific structure of the first conductive layer of the driving backplane is also shown, wherein the first conductive layer can form an initialization signal line Vint, for example, the first conductive layer can form a connection line, a first initialization signal line, etc. described in the embodiment of the present disclosure. In addition, the first conductive layer can also form a second plate Cst2 of the capacitor Cst.

[0102] Figure 5D The specific structure of the third conductive layer of the driving backplane is also shown, wherein the third conductive layer can form the source and drain of the transistor. In addition, the third conductive layer can also form a power signal line VDD and a data signal line Vdata.

[0103] In some embodiments, see Figure 3B The driving backplane 100 further includes at least one first connection pattern 141 disposed on a side of the first conductive layer 120 away from the base substrate 101 . A first conductive connection line 111 is coupled to an initialization signal line Vint through a first connection pattern 141 .

[0104] Exemplarily, one first conductive connection line 111 is coupled to one first initialization signal line 122 via one first connection pattern 141 .

[0105] For example, the first connection pattern 141 may be disposed on the third conductive layer 140, wherein the third conductive layer 140 may be disposed on a side of the first conductive layer 120 away from the base substrate 101. The first conductive layer 120 and the third conductive layer 140 may also be separated by a second insulating layer 104. Figure 3B , Figure 3C and Figure 4BWhen a first conductive connection line 111 is coupled to a first initialization signal line 122 through a first connection pattern 141, a first via hole V1 and a second via hole V2 may be formed after forming the second insulating layer 104, wherein the first via hole V1 penetrates the second insulating layer 104 and the first insulating layer 103 and reaches the first conductive connection line 111, and the second via hole V2 penetrates the second insulating layer 104 and reaches the first initialization signal line 122. Afterwards, when forming the first connection pattern 141, the first connection pattern 141 may cover the first via hole V1 and the second via hole V2 at the same time, so as to couple the first conductive connection line 111 to the first initialization signal line 122.

[0106] Among them, the first connection pattern 141 can be completed through a one-time composition process using a mask plate for making other patterns in the third conductive layer 140. Compared with forming the first insulating layer 103, drilling a hole in the first insulating layer 103 and then forming the first initialization signal line 122 in the first conductive layer 120, so that the first conductor connection line 111 in the active pattern layer 110 is coupled with the first initialization signal line 122 in the first conductive layer 120 through a via located in the first insulating layer 103, a mask plate can be saved, thereby improving the production cost of the driving backplane.

[0107] Similarly, a first conductive connection line 111 and a second initialization signal line 123 may be coupled via a first connection pattern 141 , and the coupling method and beneficial effects thereof are the same as those of the first initialization signal line 122 , and will not be described in detail.

[0108] In some embodiments, a coupling point where a first connection pattern is coupled to an initialization signal line is located at a crossing position of a first conductive connection line coupled through the first connection pattern and the initialization signal line.

[0109] For example, see Figure 4B A coupling point where a first connection pattern 141 is coupled to a first initialization signal line 122 is located at a crossing position of a first conductive connection line 111 and a first initialization signal line 122 coupled through the first connection pattern 141 .

[0110] The coupling point where the first connection pattern 141 is coupled to a first initialization signal line 122 needs to be located on the first initialization signal line 122, so that the second via V2 can be connected to the first initialization signal line 122. For example, the coupling point where the first connection pattern 141 is coupled to a first initialization signal line 122 can be the second via V2. When the coupling point is located at a position other than the intersection of the first initialization signal line 122 and the first conductive connection line 111, the first connection pattern 141 can be made into an "L" shape; when the coupling point is located at the intersection of the first initialization signal line 122 and the first conductive connection line 111, the first connection pattern 141 can be made into a "1" shape. Obviously, when the first connection pattern 141 is made into a "1" shape, the area occupied in the third conductive layer 140 is smaller than that of the "L" shape, which is conducive to the miniaturization design of the sub-pixel.

[0111] Similarly, a coupling point where a first connection pattern 141 is coupled to a second initialization signal line 123 is located at the intersection of a first conductive connection line 111 and a second initialization signal line 123 coupled through the first connection pattern 141, and its beneficial effects are the same as those of the first initialization signal line 122, which will not be repeated.

[0112] In some embodiments, the first conductive connection line 111 is in a straight strip shape and extends along the first direction Y. The straight strip-shaped first conductive connection line 111 is simple in shape and easy to manufacture, which is beneficial to improving the yield rate during the production process of the driving backplane.

[0113] In some embodiments, the driving backplane further comprises a second conductive layer disposed between the base substrate and the active pattern layer. The second conductive layer comprises: at least one conductive line extending along a third direction, and one conductive line is coupled to an initialization signal line through at least two coupling points.

[0114] For example, see Figure 6 The driving backplane 100 further includes a second conductive layer 130, which is disposed between the base substrate 101 and the active pattern layer 110. The second conductive layer 130 includes: at least one conductive line 131 extending along the third direction, and the conductive line 131 is coupled to the first initialization signal line 122 through at least two coupling points. Among the at least two coupling points, at least one coupling point is located on the conductive line 131, and at least one coupling point is located on the first initialization signal line 122.

[0115] Similarly, a conductive line 131 is coupled to a second initialization signal line 123 via at least two coupling points, and the coupling method can refer to the first initialization signal line 122, which will not be described in detail.

[0116] The third direction may cross the first direction Y or the second direction X; the third direction may also be parallel to one of the first direction Y or the second direction X.

[0117] In some embodiments, the third direction is parallel to the second direction X. In this case, the conductive line 131 in the driving backplane 100 may be parallel to the first initialization signal line 122 or the second initialization signal line 123 .

[0118] In some embodiments, the driving backplane further comprises at least one second connection pattern disposed on a side of the first conductive layer away from the base substrate, wherein a conductive line is coupled to an initialization signal line through a second connection pattern. Figure 6 The driving backplane 100 further includes at least one second connection pattern 142 disposed on a side of the first conductive layer 120 away from the base substrate 101 , wherein one conductive line 131 is coupled to one first initialization signal line 122 through one second connection pattern 142 .

[0119] Exemplarily, the second connection patterns 142 may be located at the same layer as the first connection patterns 141 , for example, the second connection patterns 142 are located at the third conductive layer 140 .

[0120] For example, see Figure 7 and Figure 8 After forming the second conductive layer 130, a buffer layer 105 may be formed on the side of the second conductive layer 130 away from the base substrate 101, and then an active pattern layer 110, a first conductive layer 120, etc. may be formed on the side of the buffer layer 105 away from the base substrate 101. After forming the second insulating layer 104, while forming the second via hole V2', a third via hole V3 may also be formed, wherein the third via hole V3 penetrates the second insulating layer 104, the first insulating layer 103 and the buffer layer 105 and reaches the conductive line 131. After that, when forming the third conductive layer 140, a second connection pattern 142 may be formed, wherein the second connection pattern 142 may simultaneously cover the second via hole V2' and the third via hole V3 to couple a conductive line 131 with a first initialization signal line 122. In this case, the coupling point for coupling a conductive line 131 with a first initialization signal line 122 may be, for example, the second via hole V2' and the third via hole V3.

[0121] Similarly, a conductive line 131 is coupled to a second initialization signal line 123 via a second connection pattern 142 , and the coupling method thereof refers to that of the first initialization signal line 122 , which will not be described in detail.

[0122] In some embodiments, the second conductive layer 130 includes a plurality of conductive lines 131 , wherein each first initialization signal line 122 and each second initialization signal line 123 is coupled to one conductive line 131 .

[0123] In some embodiments, a first conductive signal line, an initialization signal line, and a conductive line are coupled via a second connection pattern. Figure 7 , a first conductive signal line 111, a first initialization signal line 122 and a conductive line 131 are coupled via a second connection pattern 142, for example, see Figure 8 , the connection pattern 142 can cover the first through hole V1 , the second through hole V2 , and the third through hole V3 at the same time.

[0124] Similarly, a first conductive signal line 111 , a second initialization signal line 123 and a conductive line 131 are coupled via a second connection pattern 142 , and the coupling method is similar to that of the first initialization signal line 122 , which will not be described in detail.

[0125] In some embodiments, the active pattern layer 110 further includes a plurality of active layers, wherein the plurality of active layers may be a part of the active layers in the active pattern layer 110 , or may be all of the active layers in the active pattern layer 110 .

[0126] For example, see Fig. 9 The active pattern layer 110 includes a plurality of active patterns 112, each of which includes a plurality of active layers. For example, in a 7T1C pixel driving circuit, each active pattern 112 may include 7 active layers, wherein one of the 7 active layers is an active layer DA of a driving transistor. For example, the plurality of active layers in the active pattern layer 110 may include active layers DA of all driving transistors in the active pattern layer 110.

[0127] The second conductive layer 130 further includes: a plurality of light shielding patterns 132 , wherein an orthographic projection of an active layer (eg, each active layer in the plurality of active layers) on the base substrate 101 is located within an orthographic projection of a light shielding pattern 132 on the base substrate.

[0128] Exemplarily, the orthographic projection of the active layer DA of each driving transistor in the active pattern layer 110 on the base substrate 101 is respectively located within the orthographic projection of one light shielding pattern 132 on the base substrate.

[0129] For a display device with an infrared imaging function, the display device generally includes an infrared imaging component, which is generally located on one side of the display panel in the thickness direction of the display device, for example, the infrared imaging component is located on the side of the display panel close to the substrate. When the infrared imaging component is working, the infrared rays emitted by it irradiate the display panel, causing the transistors in the driving backplane of the display panel to produce transistor characteristic deviation, thereby causing the display panel to produce poor bright spots. The shading pattern 132 on the second conductive layer 130 of the driving backplane can block infrared rays, which can prevent infrared rays from continuously irradiating the active layer DA of the driving transistor, and to a certain extent avoid the occurrence of the driving transistor characteristic deviation phenomenon, thereby improving the display quality of the display panel.

[0130] In some embodiments, the driving backplane 100 further includes a power signal line VDD disposed on a side of the first conductive layer 120 away from the base substrate 101 , and the plurality of light shielding patterns 132 are coupled to the power signal line VDD.

[0131] For example, the power signal line VDD may be located in the same layer as the first connection pattern 141, for example, the power signal line VDD is located in the third conductive layer 140. The plurality of light shielding patterns 132 and the power signal line VDD may be coupled by punching holes. Fig.10 , the light shielding patterns 132 in the same row of the driving backplane 100 can be connected first, and the connection line between two adjacent light shielding patterns 132 can be coupled to the power signal line VDD through the fourth via hole V4. The fourth via hole V4 can be formed before forming the third conductive layer 140, and the fourth via hole V4 can penetrate the second insulating layer 104, the first insulating layer 103 and the buffer layer 105 to reach the connection line between two adjacent light shielding patterns 132.

[0132] When the light shielding pattern 132 is connected to a stable signal, for example, the light shielding pattern 132 is connected to a signal provided by the power signal line VDD, the substrate bias effect can be avoided, thereby preventing the substrate bias effect from affecting the corresponding driving transistor and causing display problems.

[0133] In some embodiments, see Fig.11 The driving backplane 100 further includes a third connection pattern 143 disposed on a side of the first conductive layer 120 away from the base substrate 101 , and configured to couple each first initialization signal line 122 .

[0134] Exemplarily, the third connection patterns 143 may be located at the same layer as the first connection patterns 141 . For example, the third connection patterns 143 are located at the third conductive layer 140 .

[0135] For example, the driving backplane 100 includes a plurality of first initialization signal lines 122a-122d, each of which includes a fifth via hole V5, wherein the fifth via hole V5 can be formed before forming the third conductive layer 140, and the fifth via hole V5 penetrates the second insulating layer 104 and reaches the first initialization signal line. The third connection pattern 143 covers the fifth via hole V5 on each first initialization signal line, so that each first initialization signal line is coupled to the third connection pattern 143. When the third connection pattern 143 couples the plurality of first initialization signal lines in the driving backplane 100, the voltage drop on each first initialization signal line can be further reduced.

[0136] The embodiment of the present disclosure also provides a method for preparing a display panel. Fig.12 The preparation method mainly includes step S1 and step S2, wherein:

[0137] Step S1: forming an active pattern layer on a substrate, wherein the active pattern layer comprises: at least one first conductive connection line;

[0138] Step S2: forming a first conductive layer on a side of the active pattern layer away from the base substrate, wherein the first conductive layer comprises: at least one connecting line extending along a first direction, and a plurality of initialization signal lines arranged along the first direction and extending along a second direction, one end of each initialization signal line is coupled to a connecting line, wherein the first direction intersects the second direction. A first conductive connecting line is coupled to at least two initialization signal lines, wherein the at least two initialization signal lines are coupled to the same connecting line.

[0139] In some embodiments, the forming of the active pattern layer on the substrate in step A above includes: forming at least one semiconductor connection line on the substrate, and conducting the at least one semiconductor connection line to obtain an active pattern layer including at least one first conductorized connection line. Exemplarily, step S1 may include: S101 to S103, wherein:

[0140] S101 : forming a plurality of semiconductor patterns 112 s and at least one semiconductor connection line 111 s on a base substrate.

[0141] S102: Covering the active layer in each semiconductor pattern with a photoresist.

[0142] S103 : doping the covered semiconductor pattern and the plurality of semiconductor connection lines 111 s to form an active pattern layer including at least one first conductive signal line 111 .

[0143] For example, see Fig.13A plurality of semiconductor patterns 112s are arranged in an array, each semiconductor pattern 112s is located in a sub-pixel, and semiconductor patterns located in the same column are connected end to end to form a column of semiconductor patterns 112s, and each semiconductor connection line 111s is located between two adjacent columns of semiconductor patterns 112s.

[0144] Fig.13 S102 is the shape after the semiconductor pattern is partially covered by the photoresist PR. After doping the semiconductor pattern 112s and the plurality of semiconductor connection lines 111s covered by the photoresist, an active pattern layer including at least one first conductive connection line 111 can be obtained.

[0145] In addition, after completing steps S101 to S103 to form the active pattern layer, steps S2 and S3 may be continued. Step S2 is to form a first conductive layer, wherein the first conductive layer includes a first initialization signal line 122 and / or a second initialization signal line 123, and step S3 is to form a third conductive layer, wherein the third conductive layer includes a second connection pattern 142. In addition, before forming the first conductive layer, a fourth conductive layer may be formed by step S104.

[0146] After forming the semiconductor pattern layer, the embodiment of the present disclosure uses photoresist to cover the portion corresponding to the transistor channel and to make the uncovered portion conductive, wherein the portion covered by the photoresist forms the active layer of the transistor, and the portion uncovered by the photoresist forms the source-drain metal layer of the transistor. Compared with the related art, in which the active layer of the transistor is first formed on the semiconductor pattern layer, and then the portion of the semiconductor pattern layer where the active layer of the transistor is removed is doped to form the source-drain metal layer of the transistor, the preparation method provided by the embodiment of the present disclosure can avoid lattice damage caused by doping on the active layer of the transistor, because the energy required for doping on the active layer of the transistor is large, and annealing and repair are required after doping, which damages the lattice.

[0147] Fig.14 Another process diagram of a display panel is shown, except that Fig.13 In addition to steps S1 to S3 shown, step S100 is also included, wherein step S100 is to form a second conductive layer on the base substrate, wherein the second conductive layer includes conductive lines 131. In some embodiments, the second conductive layer may further include a light shielding pattern 132.

[0148] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: substrate substrate; An active pattern layer is disposed on the base substrate, and the active pattern layer includes: at least one first conductive connection line; A first conductive layer is arranged on a side of the active pattern layer away from the base substrate, the first conductive layer comprising: two connecting lines extending along a first direction and arranged opposite to each other, and a plurality of initialization signal lines arranged along the first direction and extending along a second direction, one end of each initialization signal line is coupled to a connecting line; wherein the first direction intersects with the second direction; A first conductive connection line is coupled to at least two initialization signal lines, wherein the at least two initialization signal lines are coupled to the same connection line; The display panel has a through hole; The plurality of initialization signal lines include a plurality of first initialization signal lines and a plurality of second initialization signal lines, the other end of each first initialization signal line extends to the through hole, and both ends of each second initialization signal line are respectively coupled to a connection line; One of the first conductive connection lines is coupled to at least two first initialization signal lines, wherein the at least two first initialization signal lines are coupled to the same connection line; Each first conductive connection line is also coupled to at least one second initialization signal line.

2. The display panel according to claim 1, characterized in that: The active pattern layer includes: a plurality of the first conductive connection lines; wherein each of the first conductive connection lines is coupled to at least two initialization signal lines.

3. The display panel according to claim 1, characterized in that: The active pattern layer further includes: at least one second conductive connection line, each of which is coupled to at least two second initialization signal lines.

4. The display panel according to claim 1, characterized in that: Also includes: At least one first connection pattern is arranged on a side of the first conductive layer away from the base substrate; One of the first conductive connection lines is coupled to an initialization signal line through a first connection pattern.

5. The display panel according to claim 4, characterized in that: A coupling point where the one first connection pattern is coupled to the one initialization signal line is located at a crossing position of the one first conductive connection line and the one initialization signal line coupled through the first connection pattern.

6. The display panel according to claim 1, characterized in that: The first conductive connection line extends along the first direction and is in a straight strip shape.

7. The display panel according to any one of claims 1 to 6, characterized in that: Also includes: A second conductive layer is disposed between the base substrate and the active pattern layer; The second conductive layer includes: at least one conductive line extending along a third direction, and one conductive line is coupled to one initialization signal line through at least two coupling points.

8. The display panel according to claim 7, characterized in that: The third direction is parallel to the second direction.

9. The display panel according to claim 7, characterized in that: Also includes: At least one second connection pattern is arranged on a side of the first conductive layer away from the base substrate; The one conductive line is coupled to the one initialization signal line via a second connection pattern.

10. The display panel according to claim 9, characterized in that: A first conductive signal line, an initialization signal line, and a conductive line are coupled through a second connection pattern.

11. The display panel according to claim 7, characterized in that: The active pattern layer further comprises: a plurality of active layers; The second conductive layer further includes: a plurality of light shielding patterns, wherein an orthographic projection of an active layer on the base substrate is located within an orthographic projection of a light shielding pattern on the base substrate.

12. The display panel according to claim 11, characterized in that: Also includes: A power signal line is arranged on a side of the first conductive layer away from the base substrate; The plurality of light shielding patterns are coupled to the power signal line.

13. The display panel according to claim 2, characterized in that: Also includes: A third connection pattern is disposed on a side of the first conductive layer away from the base substrate, and the third connection pattern is configured to couple each first initialization signal line.

14. A display device, characterized in that: A display panel comprising any one of claims 1 to 13.

15. A method for preparing a display panel, characterized in that: include: An active pattern layer is formed on the base substrate, wherein the active pattern layer comprises: at least one first conductive connection line; A first conductive layer is formed on a side of the active pattern layer away from the base substrate, and the first conductive layer includes: at least one connecting line extending along a first direction, and a plurality of initialization signal lines arranged along the first direction and extending along a second direction, one end of each initialization signal line is coupled to a connecting line; wherein the first direction intersects with the second direction; one of the first conductive connecting lines is coupled to at least two initialization signal lines, wherein the at least two initialization signal lines are coupled to the same connecting line; the display panel has a through hole; the plurality of initialization signal lines include a plurality of first initialization signal lines and a plurality of second initialization signal lines, the other end of each first initialization signal line extends to the through hole, and both ends of each second initialization signal line are respectively coupled to a connecting line; one of the first conductive connecting lines is coupled to at least two first initialization signal lines, wherein the at least two first initialization signal lines are coupled to the same connecting line; each first conductive connecting line is also coupled to at least one second initialization signal line.

16. The preparation method according to claim 15, characterized in that: The step of forming an active pattern layer on the substrate comprises: At least one semiconductor connection line is formed on the substrate, and the at least one semiconductor connection line is conductorized to obtain an active pattern layer including at least one first conductorized connection line.

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