Ratio gain error calibration scheme for Delta-Sigma ADCs with programmable gain amplifier input stage

Abstract

This invention discloses an analog-to-digital converter (ADC) including a voltage input terminal, a reference input terminal, a buffer circuit, and control logic. The buffer circuit includes an input terminal, an output terminal, and a variable resistor comprising parallel-connected resistor branches. The control logic is configured, during a calibration phase, to: determine a given gain value for which gain error needs to be calibrated; determine a set of resistor branches in the buffer circuit to be used to achieve the given gain value; sequentially enable different resistor branches of the variable resistor in the set until all resistor branches in the set have been enabled; determine an output code obtained after enabling all resistor branches in the set; and determine the gain error of the given gain value from the output code. The control logic is further configured to take a correction action based on the gain error of the given gain value.

Description

[0001] Related patent applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 852678, filed May 24, 2019, the contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to analog-to-digital converters (ADCs), and more particularly to a ratio gain error calibration scheme for a Delta-Sigma (Δ-∑) ADC having a programmable gain amplifier (PGA) gain input stage. Background Technology

[0004] Analog-to-digital converters (ADCs) are used in electronic devices for consumer and industrial applications. Typically, an ADC includes circuitry for receiving an analog input signal and outputting a digital value proportional to the analog input signal. This digital output value is usually in the form of a parallel word or a serial digital bit string. Many types of ADC schemes exist, such as voltage-to-frequency conversion, charge redistribution, integral modulation, and others. Each of these schemes typically has its advantages and disadvantages. One increasingly common type of ADC is the switched-capacitor delta-to-sigma (Δ-Σ) converter.

[0005] The input stage of an ADC can be implemented using a PGA or switched-capacitor sampling circuit for both the input and reference voltages. The gain of the input stage can then be determined by the ratio between the input sampling capacitor and the reference sampling capacitor, or by the ratio between a pair of capacitors in a fully differential configuration. The gain of the ADC's input stage can be used to more closely match the ADC's input to a range within which the ADC is configured to convert analog signals to digital signals. For example, if the ADC's voltage range is 0 volts to 2 volts, but the expected ADC input is only in the range of 0 volts to 1 volt, a gain of 2 can be applied to the ADC's input to match the possible values ​​of the ADC's input to the ADC's range.

[0006] Using gain in the input stage of an ADC can introduce gain error. Gain error can be tested using a known, accurate reference voltage. However, when an ADC is deployed in various electronic devices, such devices may not have an accurate reference voltage or may not be able to obtain an accurate reference voltage. Therefore, self-testing of such an ADC may be impossible or impractical. Moreover, testing an ADC may require testing every gain arrangement or combination of capacitor gains in the input stage. Therefore, testing such an ADC can be very slow because each gain setting must be tested and its settling time can be long. The inventors of embodiments of this disclosure have discovered systems and methods for testing ADCs that address one or more of these challenges. Summary of the Invention

[0007] Embodiments of this disclosure may include an analog-to-digital converter (ADC). The ADC may include an ADC voltage input terminal, an ADC reference input terminal, a buffer circuit, a multiplexer, and control logic. The buffer circuit may include a buffer voltage input terminal, a buffer voltage output terminal, and a variable resistor comprising resistor branches connected in parallel with each other, wherein each resistor branch is individually selectable. The multiplexer may be connected between the ADC voltage input terminal and the buffer voltage input terminal, and between the ADC reference input terminal and the buffer voltage input terminal. The control logic may be configured, during a calibration phase, to: route the ADC reference input terminal to the buffer voltage input terminal; determine a given gain value for the ADC to be calibrated for gain error; determine a set of resistor branches in the buffer circuit to be used to achieve the given gain value; sequentially enable different resistor branches of the variable resistor in the set until all resistor branches in the set have been enabled; determine an output code obtained after enabling all resistor branches in the set; and determine the gain error of the ADC for the given gain value from the output code. The control logic may also be configured to take a correction action based on the gain error of the ADC for the given gain value.

[0008] Embodiments of this disclosure may include a system. This system may include an ADC reference voltage source connected to any of the embodiments of the ADC described above, as well as to the ADC reference input terminal of any of the embodiments of the ADC described above.

[0009] The embodiments of this disclosure may include methods performed by any of the systems or ADCs described above. Attached Figure Description

[0010] Figure 1 This is a diagram of an example system for ADC gain error calibration based on some implementation methods.

[0011] Figure 2 This is a diagram of an example system for ADC ratio gain error calibration according to an embodiment of this disclosure.

[0012] Figure 3 An example implementation of an analog input multiplexer according to an embodiment of this disclosure is shown.

[0013] Figure 4 This is a diagram illustrating an example implementation of a Δ-Σ modulator circuit according to an embodiment of the present disclosure.

[0014] Figure 5 This is a diagram illustrating an example implementation of a buffer circuit according to an embodiment of this disclosure.

[0015] Figure 6 An example implementation of a variable resistor according to an embodiment of this disclosure is shown.

[0016] Figure 7 An example implementation of a Δ-Σ modulator loop circuit according to an embodiment of the present disclosure is shown.

[0017] Figure 8 An example implementation of a sampling circuit according to an embodiment of this disclosure is shown.

[0018] Figure 9 A timing diagram of commands generated by the control circuit for use by the sampling circuit according to an embodiment of the present disclosure is shown.

[0019] Figure 10 A timing diagram is shown of additional commands generated by the control circuit for use by the sampling circuit according to an embodiment of the present disclosure.

[0020] Figure 11 A timing diagram of commands generated by a control circuit according to an embodiment of the present disclosure is shown, the timing diagram being in conjunction with... Figure 10 When the timing diagrams are combined, they provide an effective gain of 1 for the ADC.

[0021] Figure 12 An example method for determining the ratio gain error of an ADC with a capacitance gain input stage, according to an embodiment of the present disclosure, is shown. Detailed Implementation

[0022] Embodiments of this disclosure include an ADC. The ADC can be implemented within any larger device or can be a standalone device. The ADC may include an ADC voltage input terminal, an ADC reference input terminal, a buffer circuit, a multiplexer, and control logic. The ADC voltage input terminal accepts a voltage signal for which analog-to-digital conversion is performed during normal operation. The ADC reference input terminal accepts a voltage signal that defines the input range of the signal to the ADC voltage input terminal. The buffer circuit can be configured to sample signals routed to it. The buffer circuit may include a buffer voltage input terminal, a buffer voltage output terminal, and a variable resistor. The buffer voltage input terminal can be connected via a multiplexer to either the ADC reference input terminal (during calibration operation) or the ADC voltage input terminal (during normal operation). The variable resistor may include individually selectable resistor branches connected in parallel with each other. A control signal for selecting the resistor branch can be generated by the control logic. Each resistor branch may include two resistors. The value of each of the two resistors may be equal to the value of a feedback resistor in the sampling circuit connected to the variable resistor. The number of enabled resistor branches limits the gain of the ADC. The ADC may include an integrating circuit, such as a Δ-∑ analog loop circuit, to accumulate the values ​​sampled by the buffer circuit and generate an output code. A multiplexer may be connected between the ADC voltage input terminal and the buffer voltage input terminal, and between the ADC reference input terminal and the buffer voltage input terminal; the control logic may be configured to route the ADC voltage input terminal to the buffer voltage input terminal during normal operation. The control logic may be configured to route the ADC reference input terminal to the buffer voltage input terminal during calibration. The control logic may be configured to determine a given gain value for the ADC to be calibrated for gain error during calibration. The control logic may be configured to determine a set of resistor branches in the buffer circuit that will be used to achieve the given gain value during calibration. During calibration, the control logic may be configured to continuously enable different resistor branches of the variable resistors in the set until all resistor branches in the set have been enabled. The control logic may be configured to determine the output code generated after enabling all resistor branches in the set during calibration. The control logic may be configured to determine the gain error of the ADC for the given gain value from the output code during calibration. This control logic unit can be configured to take corrective action based on the gain error of a given gain value of the ADC.

[0023] In conjunction with any of the above embodiments, the control logic unit may be further configured to disable all other resistance branches of the variable resistor while continuously enabling a given different resistance branch of the variable resistor in the set.

[0024] In conjunction with any of the above embodiments, the control logic unit may be further configured to, during the calibration operation phase: determine another gain value for the ADC to be calibrated for gain error; determine another set of resistor branches to be used to achieve the other gain value; sequentially enable a subset of the other set of resistor branches while disabling the remaining resistor branches in the other set of resistor branches until all resistor branches in the other set of resistor branches have been enabled; determine the output code generated after all resistor branches in the other set of resistor branches have been enabled; and determine the gain error of the other gain value of the ADC from the output code. This process may be repeated for any suitable gain value of the ADC.

[0025] In conjunction with any of the above embodiments, the control logic unit can be further configured to enable a given gain value in normal operating mode by enabling the resistor branches of the set.

[0026] In conjunction with any of the above embodiments, the ADC may further include a sampling circuit. This sampling circuit may be configured to sample the output of the buffer circuit, selectively apply gain to the output of the buffer circuit, and provide the sampled output of the buffer circuit with the applied gain to an integrator circuit. The integrator circuit may be configured to add the charge value accumulated by the sampling circuit.

[0027] In combination with any of the above embodiments, the sampled output of the buffer circuit with the applied gain can have an effective gain of 1 relative to the voltage received by the buffer circuit at the ADC reference input terminal.

[0028] In any of the above implementation schemes, the given gain value of the ADC is an integer G, and the size of the set is G-1.

[0029] In combination with any of the above embodiments, each resistor branch in the set can be enabled to sample the same number of samples by the sampling circuit during the transition period. The sampling circuit can be configured to sample the duration of (G-1) transition periods corresponding to the enabling of each resistor branch in the set. The sampling circuit can also be configured to sample additional transition periods corresponding to the disabling of all resistor branches of the variable resistor. The control logic unit can also be configured to determine the gain error based on the average of the samples from each of the (G-1) transition periods and the additional transition periods.

[0030] In combination with any of the above embodiments, each resistor branch can be enabled to sample the same number of samples by the sampling circuit during the conversion period, thereby obtaining the total number of samples. This same number of samples can be equal to the total number of samples divided by the given gain value of the ADC.

[0031] In any of the above implementation schemes, the total number of samples divided by the given gain value of the ADC has no remainder.

[0032] In combination with any of the above implementation schemes, the given gain value can be a multiple of 2, and the ADC can include addition and shifting circuitry to achieve an average charge value, thereby determining the gain error.

[0033] Figure 1 This is a diagram of an example system 100 for ADC gain error calibration according to some implementation. System 100 may include an ADC 102. ADC 102 may be a Δ-∑ADC. System 100 may be configured to determine the gain error in ADC 102.

[0034] The ADC 102 can be configured to convert analog input signals into digital output codes. The analog input signal can be single-ended (not shown; in this case, the received voltage is used as input, and the received voltage is compared with ground voltage) or differential, such as... Figure 1 As shown. The differential analog input can be the voltage difference between the VIN+ and VIN- terminals of ADC 102, thus obtaining the sum VIN (VIN = VIN+ - VIN-). ADC 102 can be configured to receive a reference voltage. The reference voltage can be single-ended (not shown, in which case the received voltage is used as a reference and the received reference voltage is compared with ground) or differential, such as... Figure 1 As shown. The differential analog input can be the voltage difference between the VREF+ and VREF- terminals of the ADC102, thus yielding the total VREF (VREF = VREF+ - VREF-). These differential voltages can be applied to a common-mode voltage, not depicted in the figure. The output code can be a value proportional to VIN / VREF. The ADC code can be given as (ADC code = K * VIN / VREF), where K is a constant.

[0035] ADC 102 may have an analog gain denoted as G. This analog gain G amplifies the input signal VIN internally within ADC 102, such that the voltage converted by ADC 102 is actually G*VIN. In this case, the transfer function of ADC 102 becomes (ADC code = G*K*VIN / VREF).

[0036] VREF defines the range of voltage inputs that can be converted by the ADC 102. For a single-ended converter, the applicable input voltage range for A / D conversion is [0, VREF]. For a fully differential converter, the applicable input voltage range for A / D conversion is [-VREF, +VEF]. When a gain G is applied, the input voltage range of the ADC 102 remains the same, but it is applied as G*VIN, so the input voltage range effectively becomes [0, VREF / G] for the single-ended converter and [-VREF / G, +VREF / G] for the fully differential converter. Outside this range, the A / D conversion may exhibit greater inaccuracies, the output code may be clipped, and the overall linearity of the converter may no longer be guaranteed.

[0037] ADC 102 can be configured to achieve an analog gain G through various methods; however, due to physical implementation limitations (such as mismatch between analog components in ADC 102), the actual transfer function performance of ADC 102 may not be exactly equal to the expected or ideal transfer function performance. Therefore, system 100 allows gain measurement and compensation to be performed within ADC 102 to more closely approximate the desired or ideal transfer function (G*K*VIN / VREF). The error generated in achieving the gain of the transfer function is called the gain error of the ADC. The ADC transfer function can then be equal to G*K'*VIN / VREF, where (K' / K-1) is the gain error of gain G. The inventors of embodiments of this disclosure have discovered that the gain error can vary and depends on the gain G, in addition to parameters such as temperature or supply voltage. The gain error is the error on the slope of the linear transfer function of ADC 102. Other errors may also occur and be characterized, where such errors occur in addition to the gain error. These other errors may include offset error, integral nonlinearity error, and differential nonlinearity error. These other errors are independent of the gain error and can be addressed individually.

[0038] To measure the gain of the ADC 102 (and thus evaluate the gain error), two measurements are performed. The equation of the line at the intersection of these data points can be extracted from these two measurements, and the slope of the line can be determined. If the two points are further apart, the measurement-induced inaccuracies become less significant and, if small, negligible compared to the measured voltage. Typically, these two measurements are performed at 0 voltage input and full-scale voltage range (FS) for a single-ended converter, and at negative full-scale (-FS) and positive full-scale (+FS) for a fully differential converter. The full-scale signal can include the extreme values ​​of the input voltage range. To maximize the accuracy of the gain error measurement, the system is typically measured as follows: for a single-ended converter, VIN is zero (VIN = FS = VREF / G), and for a fully differential converter, VIN = -FS = -VREF / G and VIN = FS = VREF / G. This is in Figure 1 The VIN input of ADC 102 is connected to a voltage source 101 that applies a -FS, 0, or +FS value. Meanwhile, the VREF input of ADC 102 is connected to a voltage source 103, whose value is constant and equal to VREF.

[0039] Zero-value measurement measures the offset of the ADC 102. To measure the offset, a zero-volt voltage is applied to the VIN input of the ADC 102, and the output of the ADC 102 is observed. Zero-value measurement can be achieved by shorting the VIN+ and VIN- inputs together, resulting in VIN = 0 at the VIN input of the ADC 102. This can be performed internally within the ADC 102. However, this may be more difficult to accurately generate the F5 signal, where the entire input range of the ADC 102 is used by voltage inputs. When G = 1, VIN with a VREF voltage can be generated by multiplexing the VREF and VIN inputs with an input switch. However, if G is not equal to 1, the FS signal cannot be easily generated because it is not a simple copy of an existing voltage, such as 0 volts obtained by shorting VIN+ and VIN-, or VREF obtained by connecting to the VREF+ and VREF- terminals. FS = VREF / G input voltage is typically generated by another voltage source or by using a DAC with a reference voltage as a reference element. However, the inventors of this disclosure have discovered that such FS signals can be inaccurate due to the total unadjusted error of the DAC or the inaccuracy of the reference voltage. The inaccuracy of the reference voltage can directly contribute to additional error sources in the gain measurement of the ADC 102, and in some cases, may even become a major source of error in the performance of the ADC 102. Furthermore, adding a DAC or voltage source to generate such a reference voltage can increase the total system cost of the system 100. Additionally, during operation of the system 100, the DAC or voltage source added to generate such a reference voltage may not be effectively applied to the ADC 102 to measure the gain error. Moreover, because a given ADC can include many different gain settings, a different voltage must be generated for each new value of G to be tested. The settling time required to create each such reference voltage can delay the evaluation of the ADC 102.

[0040] Therefore, the inventors of embodiments of this disclosure have found it desirable to have a system for measuring gain error without having to generate an FS signal by dividing a reference voltage by the gain (VREF / G). The inventors of embodiments of this disclosure have found a system that can have significant advantages, such as not requiring the use of an external voltage source or DAC, and having a shorter settling time. Such a system can measure gain error using only a zero-value measurement (VIN = 0) and a VIN = VREF voltage instead of a full-scale (VREF / G) voltage, thereby reducing inaccuracies caused by voltage measurements by using an input voltage across all gains. However, with a standard ADC, a gain greater than 1 cannot allow an input voltage VIN greater than VREF / G (and therefore VIN*G greater than VREF). Embodiments of this disclosure address at least some of these problems and include an ADC that allows an input VIN = VREF for any given gain G while still allowing accurate evaluation of the obtained gain error.

[0041] Figure 2 This is an illustration of an example system 200 for ADC ratio gain error calibration according to an embodiment of this disclosure.

[0042] System 200 may be or include any suitable ADC, such as ADC 203. ADC 203 may be included in a microcontroller, processor, mobile device, computer, smartphone, tablet, power converter, controller, power supply, sensor, vehicle, or any other suitable electronic device. ADC 203 may be a Δ-∑ADC. Furthermore, ADC 203 may include a capacitor gain input stage. System 200 may be configured to determine the gain error in ADC 203. Moreover, system 200 may be configured to calibrate the operation of ADC 203 based on any determined gain error, or to take any other suitable correction action.

[0043] ADC 203 may include ADC voltage input terminals, such as VIN+ and VIN-. ADC 203 may include ADC reference input terminals, such as VREF+ and VREF-.

[0044] The ADC 203 can be configured to convert analog input signals into digital output codes. The analog input signal can be single-ended (not shown; in this case, the received voltage is used as input and compared to ground) or differential, such as... Figure 2As shown. The differential analog input can be the voltage difference between VIN+ and VIN-, thus yielding the sum VIN (VIN = VIN+ - VIN-). ADC 203 can be configured to receive a reference voltage. The reference voltage can be single-ended (not shown, in which case the received voltage is used as a reference and the received reference voltage is compared to ground) or differential, such as... Figure 2 As shown. The differential analog input can be the voltage difference between VREF+ and VREF-, resulting in a sum VREF (VREF = VREF+ - VREF-). These differential voltages can be applied to a common mode, not depicted in the figure. The output code can then be a value proportional to VIN / VREF (ADC code = K * VIN / VREF, where K is a constant).

[0045] ADC 203 can have a variable, selectable gain, denoted as G. This analog gain G amplifies the input signal VIN internally within ADC 203, so that the voltage converted by ADC 102 is actually G*VIN. In this case, the transfer function of ADC 203 becomes: ADC code = G*K*VIN / VREF.

[0046] VREF defines the range of voltage inputs that can be converted by the ADC203. For a single-ended converter, the applicable input voltage range for A / D conversion is [0, VREF]. For a fully differential converter, the applicable input voltage range for A / D conversion is [VREF-, VREF+]. When a gain G is applied, the input voltage range of the ADC203 remains the same, but it is applied as G*VIN, so the input voltage range effectively becomes [0, VREF / G] for the single-ended converter and [VREF- / G, VREF+ / G] for the fully differential converter. Outside this range, A / D conversion may exhibit greater inaccuracies, output codes may be clipped, and the overall linearity of the converter may no longer be guaranteed.

[0047] ADC 203 can be connected to voltage source 201. The voltage of voltage source 201 can be selected between + / -VREF or 0. Voltage source 201 can generate voltages external to system 200 (using an external voltage source or multiplexer) or internally to system 200. These voltages can be applied via analog input multiplexer 204. Analog input multiplexer 204 can be implemented in any suitable manner. Analog input multiplexer 204 can be configured to generate a VOUT signal (VOUT+-VOUT-) such that VOUT = + / -VREF or 0. The VOUT signal can be provided to Δ-Σ modulator circuit 205.

[0048] ADC 203 may be a Δ-Σ ADC, and therefore includes a Δ-Σ modulator circuit 205. The Δ-Σ modulator circuit 205 may be implemented in any suitable manner, such as by digital circuitry, analog circuitry, instructions executed by a processor (not shown), or any suitable combination thereof. The Δ-Σ modulator circuit 205 may include an input buffer stage with an analog gain G to amplify the input received at the VI+ / VI- input terminals. The Δ-Σ modulator circuit 205 can receive a reference voltage signal routed from the VREF+ / - input terminals of ADC 203 without any modification.

[0049] System 100 may include a voltage reference component 202. The voltage reference component 202 may be implemented in any suitable manner. The voltage reference component 202 may generate a reference voltage for system 200. The voltage reference component 202 may be internal to or external to an ADC 203 (not shown) in system 200. Furthermore, the voltage reference component 202 may be external to system 200.

[0050] A Δ-Σ modulator circuit 205 can be configured to generate a bitstream based on its inputs. The voltage inputs of the Δ-Σ modulator circuit 205 (to be amplified according to gain G) can be represented as VI+ and VI-. The Δ-Σ modulator circuit 205 may also include inputs of a reference voltage, represented as VREF+ and VREF-. The bitstream can be sent to a digital filter 206. The digital filter 206 can be implemented by digital circuitry, analog circuitry, instructions executed by a processor (not shown), or any suitable combination thereof. The digital filter 260 can be configured to generate a digital output code at the end of the transition period, with the time increment represented as TCONV. TCONV can be long enough for the Δ-Σ modulator circuit 205 to process its inputs to generate the bitstream.

[0051] In one implementation, system 200 can be configured to evaluate the gain error of ADC 203 for any given gain G (G integer) setting without generating a different reference signal, such as a + / -VREF / G signal. In another implementation, system 200 can be configured to evaluate the gain error of ADC 203 without using analog input multiplexer 204 to switch the existing voltage at the input of Δ-Σ modulator circuit 205 to generate any external voltage reference or DAC.

[0052] ADC 203 may include control logic unit 207. Control logic unit 207 may be implemented by digital circuitry, analog circuitry, instructions executed by a processor, or any suitable combination thereof. Control logic unit 207 may be configured to selectively operate ADC 203 during a calibration phase or a normal phase. During the calibration phase, the inputs to the Δ-Σ modulator circuit 205 may be controlled to operate ADC 203 in a manner that evaluates whether ADC 203 has any gain error, and based on such determination, the operation of ADC 203 is adjusted to account for such gain error. During the normal phase, the inputs to the Δ-Σ modulator circuit 205 may be controlled to operate ADC 203 in a manner that generates a digital code output based on inputs from voltage source 201 and reference unit 202, which reflect the analog signal for which system 200 requests an associated digital value. Control logic unit 207 may be configured to selectively operate one or more of the analog input multiplexer 204, Δ-Σ modulator circuit 205, and digital filter 206.

[0053] Figure 3 An example implementation of an analog input multiplexer 204 according to an embodiment of this disclosure is shown. The analog input multiplexer may include eight switches 301-308. Switch 301 connects VIN+ to VOUT+. Switch 302 connects VIN- to VOUT+. Switch 303 connects VREF+ to VOUT+. Switch 304 connects VREF- to VOUT+. Switch 305 connects VIN+ to VOUT-. Switch 306 connects VIN- to VOUT-. Switch 307 connects VREF+ to VOUT-. Switch 308 connects VREF- to VOUT-. At any given time, only one of switches 301, 302, 303, and 304 can be enabled, and the rest are disabled. Similarly, only one of switches 305, 306, 307, and 308 can be enabled, and the rest are disabled / off. Figure 3Enabling or disabling the switches can be performed in the direction of control logic component 207 (not shown). This implementation allows the generation of the desired + / -VREF or zero differential voltage. For zero-value measurements, switches 301 and 305, or switches 302 and 306, can be enabled. For +VREF measurements, switches 303 and 308 can be enabled. For -VREF measurements, switches 304 and 307 can be enabled. In each of these examples, the remaining switches can be disabled. Although shown as a separate component, analog input multiplexer 104 can be implemented as a specific circuit within ADC 203, outside ADC 203, or within Δ-Σ modulator circuit 205. Analog input multiplexer 204 can also include additional components and can be implemented as part of a larger multiplexer, provided that analog input multiplexer 204 can connect VOUT to + / -VREF or 0 throughout the A / D conversion.

[0054] Figure 4 This is a diagram illustrating an example implementation of the Δ-∑ modulator circuit 205 according to an embodiment of the present disclosure.

[0055] The Δ-Σ modulator circuit 205 may include a buffer circuit 401, a control circuit 402, and a Δ-Σ modulator circuit 403. The buffer circuit 401, the control circuit 402, and the Δ-Σ modulator circuit 403 may be implemented by analog circuits, digital circuits, instructions executed by a processor (not shown), or any suitable combination thereof.

[0056] Buffer circuit 401 may include buffered input voltage terminals VI+ and VI-. Buffer circuit 401 may be configured to sample the input voltages on VI+ and VI-. Furthermore, buffer circuit 401 may be configured to apply a gain G to the input voltage signals and output these signals on buffered output voltage terminals VO+ and VO-. Buffer circuit 401 may be configured to operate based on commands or signals from control circuit 402. Control circuit 402 may also receive commands or signals from control logic unit 207 (not shown). Δ-Σ modulator circuit 403 may be configured to generate an output bitstream that is fed to digital filter 206 in ADC 203. Δ-Σ modulator circuit 403 may be configured to integrate the sampled values ​​output by buffer circuit 401 and received at its input pin VINT+ / -. The reference input signals VREF+ and VREF- (also denoted as VREF+ and VREF-) can be routed to the reference pins of the Δ-Σ analog loop input circuit 403 without modification. The Δ-Σ modulator circuit 403 can be configured to implement a modulator circuit with a fixed gain. Figure 4 For the purpose of this example, the fixed gain can be equal to, for example, 1, because it does not change the gain error measurement.

[0057] Figure 5 This is an illustration of an example embodiment of the buffer circuit 401 according to the present disclosure.

[0058] like Figure 5 The buffer circuit 401 shown may include variable gain implemented via a variable resistor 503 (denoted as RG). The buffer circuit 401 can be implemented as a variable gain precision input buffer using a fully differential amplifier employing two separate operational amplifiers 502A and 502B (denoted as A1 and A2). This implementation can be modified to produce a single-ended version of the depicted input buffer circuit 401.

[0059] The buffer circuit 401 may include input circuits 501A and 501B, which are created by first-order RC filters that can act as anti-aliasing filters or EMI filters. Each input circuit 501 may include an input terminal VI+ / - connected to a resistor (denoted as REMI), which is connected to a capacitor (denoted as CEMI) grounded. REMI may be further connected to the non-inverting terminal of the corresponding operational amplifier 502. Input circuits 501 may be connected on one side to the corresponding VI+ or VI- analog input of the buffer circuit 401 and on the other side to the non-inverting input of the corresponding operational amplifier 502. Operational amplifiers 502 may be matched, and their implementation may be of any suitable type. The inverting input of operational amplifier 502 may be connected to its corresponding output via resistive feedback including corresponding resistors 505A and 505B, the value of which may be denoted as RF. Between the two non-inverting inputs of operational amplifier 502 is a variable resistor 503, the value of which is denoted as RG. The output of each operational amplifier in operational amplifier 502 is connected to another first-order RC filter 504, which acts as an anti-aliasing filter for connection to the input of the Δ-Σ modulator circuit 403 (not shown) at the output terminals VO+ and VO-. The first-order RC filter 504 may include two instances of resistors, denoted as RFLT, connected to the output of the respective operational amplifier 502 and the corresponding output terminal pins VO+ and VO-. The first-order RC filter 504 may also include a capacitor (denoted as CFLT) connected between the output terminal pins VO+ and VO-.

[0060] If the gains of the two operational amplifiers are infinite, then the gain of the transfer function from VI+ / - to VO+ / -- is equal to (G = 1 + 2*RF / RG). The buffer circuit 401 can achieve any gain G, as long as the variable resistor 503 satisfies the equation (RG = 2*RF / (G-1)). Then, according to the definition in this embodiment, G is greater than 1, and G can only be equal to 1 when RG is infinite, which may occur when resistor RG is replaced by an open-circuit circuit (because an open circuit has a first-order approximate infinite resistance). Since the gain is a function of the two resistor values ​​RF and RG, it is susceptible to mismatch between the values ​​of RF and RG. Therefore, the buffer circuit 401 may be prone to gain errors due to resistor mismatch. Embodiments of this disclosure can use a specific implementation of the variable resistor RG to evaluate this gain error without connecting a specific voltage, such as + / -VREF / G, at the input of ADC 203.

[0061] The full-scale value of VREF should not exceed the output range of operational amplifier 502. This is implemented to avoid clipping any voltage in buffer circuit 401 by 2 when a resistor branch is selected in variable resistor 503, as discussed in more detail below. The intermediate voltage (VINT+ / -) may not be clipped to achieve this limitation on VREF.

[0062] Figure 6 An example implementation of a variable resistor 503 according to an embodiment of the present disclosure is shown. In one embodiment, the variable resistor 503 can be implemented by multiple individually selectable resistor branches or paths connected in parallel. Each resistor path between the first terminal 605 and the second terminal 606 of the variable resistor 503 may include two instances of a resistor 602 connected in series with a value RF. Each resistor path can be selectively enabled or disabled using a switch 601. The switch 601 can be controlled by a command SG[1...N]. In a given resistor path, two instances of the switch 601 can be used at either end of the two instances of the series-connected resistor 602. Since all resistors 602 are organized in parallel into groups, each group includes a resistor with a value of 2*RF, the resistance value of the variable resistor 503 is equal to 2RF / N when the switch 601 is closed or enabled (e.g., where the applied command SG[1...N] is logic high). This can be assumed that the on-resistance of a given switch 601 can be ignored. If the switches are matched and their on-resistance is equal to RON, then when all switches are closed or enabled, the resistance of variable resistor 503 is equal to 2(RF+RON) / N. When all switches are open or disabled (where the applied command SG1[...N] is logic low), variable resistor 503 is equivalent to an open circuit with infinite resistance.

[0063] If in such Figure 5 The embodiment of the buffer circuit 401 shown uses, for example Figure 6 In the embodiment of the variable resistor 503 shown, the gain of the buffer circuit 401 can be limited by the command SG[1...N]. If all commands are logic high, the maximum gain will be selected and this gain will be equal to (G = 1 + 2 * RF / RG = N + 1), assuming that the on-resistance of the switch is negligible.

[0064] If the on-resistance is not negligible in the resistor array of variable resistor 503, then the resistance of variable resistor 503 can be given as follows:

[0065] RG = 2(RF + RON) / N

[0066] Where N is the number of activated resistor branches. This is to match the on-resistance present within the variable resistor 503. Figure 5 Resistor 505 can be replaced or superseded by a series circuit comprising a resistor with a value of RF and a closed switch. The resistance of this series circuit will be (RF + RON), and the ratio between the resistances of the resistor elements remains equal to N / 2. Therefore, the effects of a non-ideal switch can be compensated for through matching.

[0067] exist Figure 6 In the variable resistor 503, if only k switches 601 are enabled while the other Nk switches remain disabled, the gain will change to be equal to (G = k + 1). Therefore, the variable resistor 503 can implement an accurate variable gain input buffer that can achieve any value of gain G between 1 and N + 1. The value of gain G can be obtained by enabling any combination of switches 601 via a logic high command of SG[1...N], such that G-1 is enabled and the rest (N-G+1) are disabled. For example, the variable resistor 503 can achieve a gain of 2 by enabling any one of the SG[1...N] commands while disabling all other commands, thus enabling a single resistor branch while disabling all other resistor branches. This is equivalent to enabling only one branch of the resistor between terminals 605 and 606. When all switches 601 are disabled, the variable resistor 503 can achieve a gain of 1. Since resistor 602 is not perfectly matched to resistor 505, the variable resistor 503 is prone to errors due to resistor mismatch. The embodiments of this disclosure can implement specific commands of the switch SG[1...N] such that the gain of the ADC 203 is substantially kept at 1. However, the gain error of the gain G selected for calibration can be evaluated and measured without saturating the ADC 203 and using a simple input selectable between 0 and VREF to obtain the zero measurement and full-scale measurement necessary to calculate the gain error.

[0068] Figure 7 An example implementation of the Δ-∑ modulator loop circuit 403 according to an embodiment of the present disclosure is shown.

[0069] The Δ-Σ modulator loop circuit 403 may include a sampling circuit 701, a control circuit 702, and a Δ-Σ analog loop circuit 703. Circuits 701, 702, and 703 may be implemented by analog circuits, digital circuits, or any suitable combination thereof.

[0070] Sampling circuit 701 may include input voltage terminals VI+ and VI-, and output voltage terminals VO+ and VO-. Sampling circuit 701 may be configured to sample the input at its input voltage terminals, apply a gain to its input voltage, and provide the amplified input voltage to Δ-∑ analog loop circuit 703. Sampling circuit 701 may include a gain. This gain may include a selectable gain, such as a selection between 0.5x and 1x. This gain may be selected by control circuit 702. Control circuit 702 may then be controlled by control logic unit 207. Sampling circuit 701 may be configured to sample the output of buffer circuit 401, selectively apply a gain to the output of buffer circuit 401, and provide the output of buffer circuit 401 with the applied gain to integrator circuit such as Δ-∑ analog loop circuit 703, which is configured to accumulate the charge value from sampling circuit 701. The sampled output of buffer circuit 401 may have an effective gain of 1 relative to the voltage at the ADC reference input terminal received by buffer circuit 401 during the calibration phase.

[0071] The Δ-Σ analog loop circuit 703 may include an input terminal VSD+ / - connected to the output terminal VO+ / - of the sampling circuit 701. The VREF+ / - voltage reference input terminal of the Δ-Σ modulator 403 may be connected to the VREF+ / - input terminal of the Δ-Σ analog loop circuit 703. The bitstream output terminals of circuits 703 and 403 may be connected together and connected to the digital filter 206.

[0072] A gain selection of 0.5x on the sampling circuit 701 can be used such that when one resistor branch of the variable resistor 503 is selected by the control circuit 402, the resulting gain is 1. As shown above, a single resistor branch of the variable resistor 503 can include two resistors 602 with a value of RF. This results in a gain of input buffer 401 that is essentially equal to 2x (if the resistors are matched and the gain of operational amplifier 502 is infinite). Therefore, when the gain of the sampling circuit 701 is set to 0.5x, the total gain of ADC 203 can be equal to 1. A gain of 1 for ADC 203 can also be obtained by selecting a gain of 1x on both the sampling circuit 701 and the input buffer 401 (by switching all SG[1...N] commands low).

[0073] Figure 8 An example implementation of a sampling circuit 701 according to an embodiment of this disclosure is shown. The sampling circuit 701 can be implemented with a selectable gain of 1x or 0.5x. Sampling of the input VI+ / - can be achieved by converting the input voltage into charge via a capacitor 804 with a value of CIN. When double sampling occurs at capacitor 804, the Δ-∑ modulator circuit 403 effectively has a gain of 1x. If simple sampling is performed on capacitor 804, the gain will effectively be 0.5x.

[0074] The sampling function can be performed via switches 801, 802, 803, and 805. Control of switches 801, 802, 803, and 805 is achieved through control circuit 702 and control logic unit 207. Sampling can be performed in two stages. When sampling the input voltage VI+ / - in the first stage, the top plates of capacitor 804 (those closest to VI+ / -) are effectively connected to the low-impedance common-mode voltage source 806 via switch 805. The command S1 controlling switch 805 is logic high, thereby enabling or closing switch 805. In this first stage, switch 801 can connect the bottom plates of capacitor 804 (those closest to VI+ / -) to the input terminal VI+ / -. The command controlling switch 801 is essentially shared with the command controlling switch 805. However, a small non-overlapping delay is applied to the command controlling switch 801. Therefore, the command controlling switch 801 can be represented as S1D. This allows for the transfer of sampled charge without loss. During the second phase, switch 802 or switch 803 is enabled, depending on whether the gain configuration is selected as 1x or 0.5x. During this phase, switch commands S1 and S1D are disabled or logic low. This second phase can be referred to as the transition phase.

[0075] During the transfer phase, if switch 802 is enabled, the signal from VI+ / - can be resampled on capacitor 804. The command signal for switch 802 can be represented as S2G1. In this case, switch 803 can be disabled. The sampling occurring in the first and second phases can be performed with opposite polarities, effectively doubling the transferred charge. For this purpose, the output VO+ / - is connected to the low-impedance input of the integrator circuit during the second (transfer) phase, so that the charge can be effectively transferred for processing by the Δ-∑ modulator circuit 403. The charge difference sampled between the first and second phases on capacitor CIN+804A is given by (Qdiff+ = CIN+ * (VI+ - VI-)). Similarly, the charge difference sampled on the first and second phases on capacitor CIN-804B is given by (Qdiff- = CIN- * (VI- - VI+)). The total charge is given by (Qtot = Qdiff+ - Qdiff-). If both sampling capacitors 804 are matched to the value C, the total charge is given by (Qtot[G=1x]=2*CIN*(VI+-VI-)). The factor of 2 in this formula indicates effective double sampling of the input voltage.

[0076] When switch 802 is disabled and switch 803 is enabled, sampling circuit 701 can perform simple sampling. During the transfer phase, capacitor 804 may not be connected to the input voltage of VI+ / -, but instead shorted together on the VI+ / - baseplate by the operation of switch 803. The command signal of switch 803 can be represented as S2G05. In this case, the charge difference sampled during the transfer phase is equal to zero. Only the charge sampled during the first phase is transferred. Then, the total charge transferred is equal to the charge transferred in the first phase, which is equal to: (Qtot[G=0.5x]=CIN*(VI+-VI-)). Therefore, (Qtot[G=1x]=2*Qtot[G=0.5x]).

[0077] If the given gain value of ADC 203 is an integer G, the size of the set of enabled resistance branches of variable resistor 503 can be G-1. Each resistance branch in this set can be enabled by control logic 207 for sampling the same number of samples by the sampling circuit during a conversion period. Sampling circuit 701 can be configured to sample the output of buffer circuit 401 for a duration of (G-1) conversion periods corresponding to the enabling of each resistance branch in this set. Sampling circuit 701 can be configured to sample additional conversion periods when control logic 207 disables all resistance branches of the variable resistor. Control logic 207 can be configured to determine the gain error based on the average of the samples from each of the (G-1) conversion periods and the additional conversion periods. Each resistance branch in this set for a given gain value can be enabled for the same number of samples sampled by sampling circuit 701 during a conversion period, resulting in a total number of samples. The same number of samples can be equal to the total number of samples divided by the given gain value of ADC 203. The total number of samples divided by the given gain value of the ADC203 may have no remainder. The given gain value can be a multiple of 2, allowing the ADC203 to include adder and shifter circuitry to achieve an average charge.

[0078] During the calibration operation phase, control circuits 702 and 402, along with control logic unit 207, can be configured to issue switching signals to switches 601, 802, 803, and 805. These switching signals are illustrated in more detail in the timing diagram below. Control logic unit 207 can be configured to operate multiplexer 204 to route the reference voltage input (VREF) of ADC 203 to the VI+ / - input of buffer circuit 401 during the calibration operation phase. Control circuits 402 and control logic unit 207 can be configured to determine what gain value to test. The gain value to be tested can be determined on any suitable basis, such as through commands to ADC 203, register values, settings, or any other suitable input. Moreover, possible gain values ​​of ADC 203 can be tested continuously. Based on the gain value to be tested, control circuits 402, 702, and control logic unit 207 can be configured to determine which subsets of the resistive branches of variable resistor 503 are associated with the gain value. Which subsets of the resistance branches of the variable resistor 503 are associated with the gain value can be determined in any suitable manner, such as by referencing user commands, settings, or register values. Based on which subsets of the resistance branches of the variable resistor 503 are associated with the gain value, each subset is sequentially enabled for a determined number of samples, while other subsets and the remainder of capacitor 507 are disabled. This can be performed using control signals sent to switches 601, 802, 803, 804, and 805, as illustrated in more detail below. This process can be repeated for each subset of the resistance branches of the variable resistor 503 associated with the gain value. During the activation of each subset of the resistance branches of the variable resistor 503, the ADC 203 may have an effective gain of 1. Each subset of the resistance branches of the variable resistor 503 can be enabled for the same number of samples. After all subsets of the resistance branches of the variable resistor 503 associated with the gain value have been enabled, the same number of samples can be acquired while all resistance branches of the variable resistor 503 are cut off. The value stored in the sampling circuit can be integrated by the Δ-∑ analog loop circuit 703, which generates an output code in bitstream form. The control logic unit 207 can be configured to take corrective action to correct the gain error based on the gain error determined from the output code. The control logic unit 207 can determine another gain value for the ADC 203 to be calibrated, determine another set of resistance branches of the variable resistor 503 used to achieve that other gain value, successively enable a subset of the set of resistance branches of the variable resistor 503 while disabling the remaining set of resistance branches of the variable resistor 503, determine another output code resulting from enabling all resistance branches of the variable resistor 503 from that other set, and determine another gain error for the other gain value of the ADC 203 from that other output code.Control logic unit 207 can be configured to sample each subset of the set of resistance branches of variable resistor 503 for a subset of the total number of samples. All sampling can be performed across all subsets to obtain a given gain value. The total number of samples taken for a given gain value divided by the given gain value is the number of samples in each subset of the total number of samples. The result of dividing the total number of samples by the gain value may have no remainder. Control logic unit 207 can be configured to enable the selected gain value in normal operating mode by simultaneously enabling the associated resistance branches of variable resistor 503.

[0079] Figure 9 A timing diagram 901 is shown, illustrating commands generated by control circuit 702 for use by sampling circuit 701 according to an embodiment of the present disclosure.

[0080] Timing diagram 901 illustrates commands S1, S2G1, and S2G05 used in sampling circuit 701 to achieve the desired gain of 1x. The time of each sampling period of the Δ-Σ conversion can be represented as TCONV. A conversion involves acquiring a number of OSR samples within the conversion time of TCONV. Each sample is divided into two segments. In the first stage, S1 can be set to logic high and S2G1 can be set to logic low, thus implementing the first sample on capacitor 804. S1D is not specifically shown but can be a copy of S1 with a small, non-overlapping delay, the length of which is negligible relative to the time of one sample. Throughout the conversion, command S2G05 remains logic low, thus disabling switch 803. During the second stage of each sample, S1 is switched to logic low and S2G1 is switched to logic high, causing capacitor 804 to sample the input voltage again with the opposite sign. The stored charge is transferred to the Δ-Σ analog loop circuit 703. Timing diagram 901 depicts the behavior of ADC 203 when the sampling circuit gain is selected as 1x. This can be a typical or preferred case because double sampling is performed in this case. This improves the signal-to-noise ratio of ADC 203. Timing diagram 901 shows all SG[1...G--1] commands used to activate (logic high) switch 601 throughout the conversion time, while all other SG[G...N] commands are disabled. These commands implement the gain G in input buffer circuit 401, and therefore the equivalent ADC gain is effectively G. Timing diagram 901 depicts the standard case of an ADC gain equal to G achieved by a combination of sampling circuit 701 and input buffer 401, which are set to have gains of 1 and G respectively during conversion.

[0081] Figure 10 A timing diagram 1001 is shown, illustrating an embodiment of the present disclosure, in which control circuit 702 will generate additional commands for sampling circuit 701.

[0082] Timing diagram 1001 illustrates commands for an application in which the input sampling circuit 701 is configured to generate a gain of 0.5. In this case, with Figure 9 Compared to the case where the gain is 1, the S1 (and S1D) commands remain unchanged. The S2G1 command remains logic low throughout the entire transition time TCONV of the disabled switch 802. Timing diagram 1001 illustrates the first and second phases. In the first phase, the S1 command is logic high and the S2G05 command is logic low. In the second phase, the S1 command is logic low and the S2G05 command is logic high. Command S2G05 is logic high only during the second (transfer) phase. The combination of different commands enables simple sampling and charge transfer of the analog input voltage on capacitor 804 of sampling circuit 701, thus sampling circuit 701 is configured to produce an analog gain of 0.5 (half the transferred charge compared to an analog gain of 1).

[0083] Figure 11 A timing diagram 1101 showing commands generated by control circuit 702 according to an embodiment of the present disclosure is illustrated, the timing diagram being in conjunction with... Figure 10 The timing diagram 1001 provides an effective gain of 1 for ADC 203 when combined.

[0084] In timing diagram 1101, the SG[1...G-1] commands are successively set to logic high, with only one such command set to logic high at a time. Each command is enabled during the full conversion time TCONV, which includes a number of OSR samples. In timing diagram 1101, a number of G conversions are performed consecutively. In each of the first (G-1) conversions, only one branch of the resistor in variable resistor 503 is selected. If all resistors 602 are matched and have the same value RF, the effective gain achieved by this timing diagram is effectively 2, according to the teachings of this disclosure. If combined with timing diagram 1001, the effective gain of ADC 203 is equal to 1 because the gain of sampling circuit 701 is selected as 0.5. However, if the resistors are mismatched, the gain error of buffer circuit 401 depends on the resistor values, such as (G = 1 + 2RF / RG). The last conversion in timing diagram 1101 shows all SG[1...N] being logic low, causing all switches to be off. According to the teachings of this disclosure, this corresponds to an effective gain of 1 for the buffer circuit 401. In this case, the gain of the sampling circuit 701 is chosen to be equal to 1x, such that the effective gain of the ADC 203 is also equal to 1, thus matching the effective gains of all other conversions. In general, a number of G conversions are performed, where each conversion has an effective gain of 1x for the ADC 203 if all resistors are perfectly matched. However, in practice, each conversion has a different gain. The average of these conversions will produce a representation of the gain error of the ADC 203, which is a known function of the same gain error that the ADC 203 would otherwise experience when a gain of G is used in the input buffer circuit 401.

[0085] If all resistors 602 are mismatched, the equivalent resistor value can be written as ((1 / Req=∑{1 / (2RFk)}) when the SG[1...G-1] switch is enabled (ignoring the on-resistance of the input switch) where k is in the range of 1 to G-1 and 2RFk is the value of the two resistors 602 connected in series, each of which has a nominal resistance value of 2RF. If all resistors are perfectly matched, then 2RFk=2RF. If all resistor branches are matched, then (Req=RG=2RF / (G-1)).

[0086] For the gain G, using timing diagram 901, the circuit gain can be given as (Gmismatch = 1 + 2RF * ∑{1 / (2RFk)}), where k ranges from 1 to G-1. When all resistors 602 are matched to 2RF, the G mismatch is equal to G (and therefore the gain of ADC 203). The gain error is then defined as (Gerr[gain = G] = (Gmismatch - G) / G = (1 + RF * ∑{1 / RFk} - G) / G), where k is in the range of 1 to G-1.

[0087] For the combination of timing diagrams 1001 and 1101, the gain Gk of the k-th conversion in timing diagram 1101 is equal to 1 + 2 * RF / (2RFk) of the buffer circuit 401 and 0.5 of the sampling circuit 701. This combination gives the ADC gain as (Gk = 0.5 * (1 + RF / RFk)). If the value of RFk is equal to RF, then the gain Gk is equal to 1. Furthermore, GG (the gain of the last conversion) is equal to 1 because the selected equivalent resistor is infinite (all switches are on). Then, the average gain used during the G conversions is equal to (Gavg = 0.5 / G * ∑{RF / RFk + G - 1 + 2}), where k is in the range of 1 to G - 1. The gain error in this case is then given by (Gerr = (1 + ∑{RF / RFk} - G) / 2G = Gerr[gain = G] / 2). It can be observed that there is a direct relationship between the average gain error generated by using timing diagram 1101 and the typical case where the gain G is selected on ADC 203.

[0088] The average gain error generated in each conversion in timing diagram 1101 can be determined in digital filter 206. ADC 203 can perform averaging of these conversions using the full-scale range of signal VREF. This is likely possible because the effective gain is 1 in all conversions, allowing the gain error to be fully determined through full-scale measurement. Therefore, ADC 203 can fully evaluate the value of the gain error of ADC 203 for a given choice of gain G, since the average gain error is half the gain error attributable to the gain choice of G. Thus, the average gain error provides a simple and accurate representation of the converter's gain error for any gain G. Furthermore, determining the average gain error while keeping the effective gain 1 eliminates the need to generate a reference voltage such as + / -VREF / G. The input range can be maintained at the full value VREF throughout the measurement, which is beneficial for the extraction of the gain error.

[0089] Timing diagram 1101 can be modified to randomize the order of transitions to any suitable order. This transition order may have no effect on the final average. Timing diagram 1101 can also be modified to add delays between transitions to allow buffer circuit 401 to stabilize in the correct operating state whenever the selection of variable resistor 503 (and therefore its gain) changes. The selected gain can be a multiple of 2, making averaging easier to perform within digital filter 206, which is achieved using summation and shift operations or circuitry instead of full shunt circuitry.

[0090] Figure 12 An example method 1200 for determining the ratio gain error of an ADC with a capacitance gain input stage, according to an embodiment of the present disclosure, is shown. Method 1200 may include a ratio... Figure 12 The steps shown may be more or fewer. Furthermore, the individual steps of method 1200 may be omitted, repeated, executed in parallel, executed in a different order, or executed recursively. Method 1200 may be... Figures 2 to 8 The components used Figures 9 to 11 The timing diagram shown is used to implement this. Specifically, method 1200 can be executed directly or indirectly by control logic unit 207.

[0091] At step 1205, it can be determined whether the ADC is to be operated in the normal phase or the calibration phase. If the ADC is to be operated in the normal phase, method 1200 may proceed to step 1210. Otherwise, method 1200 may proceed to step 1215.

[0092] At step 1210, the gain to be used in the ADC is determined. The gain can be applied to the input voltage to be converted to a digital value. After the gain is applied, the input voltage can be converted within a range defined by the ADC's reference voltage range. The ADC can output a digital code based on the input voltage. Method 1200 can proceed to step 1250.

[0093] At step 1215, different possible gain settings for the ADC can be determined. Additionally, a reference voltage for the ADC can be applied to the ADC voltage input.

[0094] At step 1220, an untested ADC gain setting can be selected for testing. The set of resistor branches in the variable resistor that will be used for the selected ADC gain setting can be determined.

[0095] At step 1225, a subset of the resistance branches, such as a single branch, can be enabled. This branch can be enabled for a sufficient time to capture a large number of samples, defined by the sampling period divided by the gain. When this branch is enabled, other branches can be disabled. At the end of the sampling period, the result can be integrated.

[0096] At step 1230, it can be determined whether there are any additional unsampled resistor branches from the set of resistor branches determined in step 1220. If so, method 1200 can be repeated, for example, at step 1225. Otherwise, method 1200 can proceed to step 1235.

[0097] At step 1235, an additional sample period may be used. The gain error can be determined based on the integration result of the selected gain setting. At step 1240, a gain error correction value for the gain can be set for future operation during the normal phase.

[0098] At step 1245, it can be determined whether there are any untested additional gain settings. If so, method 1200 can be repeated, for example, at step 1220. Otherwise, method 1200 can proceed to step 1250.

[0099] At step 1250, it can be determined whether method 1200 should be repeated. Method 1200 can be repeated based on any suitable criterion, such as whether a larger device or system in which the ADC is implemented has commanded the ADC to continue operation or stop. If method 1200 should be repeated, it can be repeated, for example, at step 1205. Otherwise, method 1200 can proceed to step 1255.

[0100] The embodiments of this disclosure may not require any additional voltage source other than VREF to perform gain error calibration for different gain values. The embodiments of this disclosure may not require precise generation of VREF. VREF is applied to both inputs of the Δ-Σ modulator circuit 403, so the solution for determining the gain error can be considered ratiometric. Furthermore, the embodiments of this disclosure may not require a precision voltage source or device to measure the gain error. The embodiments of this disclosure can utilize any available DC voltage with sufficiently low noise as VREF. It may not be necessary to generate a precise VREF / G value as in other solutions used for testing gain error. Moreover, since VREF is used as the VIN input during calibration, any noise or other non-ideal factors caused by the generation of VREF can be eliminated by ratio measurement. Furthermore, calibration can be performed without waiting for the input to settle between conversions.

[0101] This disclosure has been described according to one or more embodiments, and it should be understood that many equivalents, alternatives, variations, and modifications are possible and within the scope of this disclosure, in addition to those expressly stated. While this disclosure is susceptible to various modifications and alternatives, specific exemplary embodiments thereof have been shown in the accompanying drawings and described in detail herein. However, it should be understood that the description of specific exemplary embodiments herein is not intended to limit this disclosure to the specific forms disclosed herein.

Claims

1. An analog-to-digital converter (ADC) configured to convert an input voltage into an output code, the ADC comprising: ADC voltage input terminal; ADC reference input terminal; A buffer circuit, the buffer circuit comprising: Buffered voltage input terminal; Buffered voltage output terminal; and A variable resistor comprising multiple resistance branches connected in parallel with each other, wherein each resistance branch is individually selectable; A multiplexer connected between the ADC voltage input terminal and the buffer voltage input terminal, and between the ADC reference input terminal and the buffer voltage input terminal; and Control logic unit, the control logic unit being configured to: The multiplexer routes the ADC reference input terminal to the buffer voltage input terminal; Determine the given gain value of the ADC for which the gain error needs to be calibrated; Determine the set of resistor branches in the buffer circuit to be used to achieve the given gain value; Different resistance branches of the variable resistors in the set are enabled sequentially until all resistance branches of the set have been enabled, wherein all other resistance branches of the variable resistor are disabled while a given different resistance branch of the variable resistor in the set is being enabled sequentially; Determine the output code obtained after enabling all resistor branches of the set; and The gain error of the ADC for the given gain value is determined from the output code; The control logic unit is further configured to take a correction action based on the gain error of the given gain value of the ADC.

2. The ADC of claim 1, wherein each resistance branch of the variable resistor comprises a separate resistor pair that is matched to each other and to the feedback resistor of the buffer circuit.

3. The ADC of claim 1, wherein the control logic unit is further configured to enable the given gain value in normal operating mode by enabling the resistor branch of the set.

4. The ADC of claim 1 further includes a sampling circuit, the sampling circuit being configured as follows: The output of the buffer circuit is sampled; The gain is selectively applied to the output of the buffer circuit; as well as The sampled output of the buffer circuit with the applied gain is provided to the integrator circuit.

5. The ADC of claim 4, wherein the sampled output of the buffer circuit having the applied gain has an effective gain of 1 relative to the voltage received by the buffer circuit at the reference input terminal of the ADC.

6. The ADC according to claim 1, wherein: The given gain value of the ADC is an integer G; and The size of the set is G-1.

7. The ADC according to claim 6 further includes a sampling circuit, wherein: Each resistor branch of the set is enabled to be used to sample the same number of samples by the sampling circuit during the switching period; The sampling circuit is configured to sample over a duration of (G-1) switching periods corresponding to the activation of each resistor branch of the set; The sampling circuit is further configured to sample additional transition periods corresponding to the disabling of all the resistance branches of the variable resistor; and The control logic unit is further configured to determine the gain error based on the average value of samples from each of the (G-1) transition periods and the additional transition periods.

8. The ADC according to claim 4, wherein: The given gain value of the ADC is an integer G; Each resistor branch of the set is enabled to obtain the total number of samples by the sampling circuit during the conversion period; and The same number of samples is equal to the total number of samples divided by the given gain value of the ADC.

9. The ADC of claim 8, wherein the result of dividing the total number of samples by the given gain value of the ADC has no remainder.

10. The ADC according to claim 9, wherein: The given gain value is a multiple of 2; and The ADC includes adder and shifter circuits to achieve an average charge value.

11. A system for ADC gain error calibration, comprising: The ADC according to any one of claims 1 to 10; Input voltage, which is connected to the ADC voltage input terminal of the ADC; and A reference voltage source is connected to the reference input terminal of an ADC, the ADC being configured to convert the input voltage within a range defined by the reference voltage source.

12. A method for calibrating ADC gain error, the method comprising operating on the system of claim 11 or the ADC of any one of claims 1 to 10.

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