Error amplifier circuit for a dc-dc converter, dc-dc converter and controller

Abstract

The present disclosure relates to error amplifier circuits for DC-DC converters, DC-DC converters and controllers. An error amplifier circuit for a DC-DC power converter controller for providing an amplified error signal to a switching control circuit is disclosed, the circuit comprising an error amplifier first stage. The first stage comprises: a first input for receiving a voltage proportional to an output voltage of the converter; an output node; a first operational transconductance amplifier in a first path between the input and the output node and having a first input connected to the input, a second input connectable to a reference signal and an output connected to the output node; and a second parallel path comprising a series combination of an amplifier, a second OTA and a capacitor. The second OTA has an output connected to the capacitor, a first input connected to an output of the amplifier and a second input connected to the output. Associated control circuits, controllers and converters are also disclosed.

Description

Technical Field

[0001] This disclosure relates to a DC-DC converter, a controller therefor, and an error amplifier circuit therefor. Background Technology

[0002] DC-DC converters are crucial in a variety of applications, especially in those requiring the supply of power from relatively high voltages, such as mains power or automotive batteries, to low-voltage devices, such as computing and communication equipment, or automotive electronics. Furthermore, DC-DC converters are becoming increasingly important in applications requiring efficient power delivery, even when significant voltage bucking (or bucking) is not necessarily involved.

[0003] Figure 1 The diagram illustrates an example of a typical synchronous DC-DC buck converter. In this example, converter 100 converts an input voltage Vin into an output voltage Vout. The converter includes a pair of switches SH and SL connected in series between the input voltage Vin and ground. A node Vs between the switches SH and SL is alternately switched between the input voltage and ground by means of a control circuit 120 that forms part of a controller 110 and controls the pair of switches, using a defined duty cycle. An inductor L is connected between node Vs and the output Vout. An output capacitor Cout is connected between the output and ground, and in this case, a load shown as a resistive load RL may be connected between the output and ground.

[0004] As will be familiar to those skilled in the art, in this example, under steady-state conditions, the output voltage Vout is typically related to the input voltage based on the "high-low" duty cycle of node Vs.

[0005] Feedback path 105 is typically positioned between the output of the DC-DC converter and the control circuitry 120. The feedback circuitry typically includes an error amplifier circuitry 200, which determines the error between the actual output Vout and the desired or reference output Vref and amplifies the error to provide a signal Vea, which is then provided to the control circuitry 120. However, variations in the load RL can cause disturbances in the output voltage; in some applications, minimizing this disturbance and controlling the stability of the transient response may be important through the design of the error amplifier.

[0006] As will be discussed in more detail below, a delay may exist between the onset of a transient, for example, caused by a load change, and the controller's response to adapt the DC-DC converter to the transient. In recent years, there has been a trend towards increasing the switching frequency of DC-DC converters; this delay can interfere with the feedback response and lead to control instability. Various error amplifier circuits have been developed to provide protection against the effects of this delay and to avoid control instability. Typically, these circuits are described as so-called "Type II compensators" or proportional-integral (PI) circuits and so-called "Type III compensators" or proportional-integral-derivative (PID) circuits. However, such circuits conventionally tend to require passive components, which can be bulky and require dedicated "trimming" (i.e., manual adjustment or value selection depending on the implementation). It is desirable to provide an error amplifier circuit that is easy to implement and requires fewer or even zero trimming components. Summary of the Invention

[0007] According to a first aspect, an error amplifier circuit is provided for a DC-DC power converter controller and configured to provide an amplified error signal to a switching control circuit, the error amplifier circuit including an error amplifier first stage; the error amplifier first stage includes: a first input terminal (V'out) for receiving a voltage proportional to the output voltage of the DC-DC converter; and an output node (V... A The circuit comprises: a first operational transconductance amplifier OTA, the OTA being in a first path between the input terminal and the output node and having a first input connected to the input terminal, a second input connectable to a reference signal, and an output connected to the output node; and a second path, the second path being between the input terminal and the output node and comprising a series combination of the first amplifier, the second OTA, and a first capacitor, wherein the second OTA has an output connected to the first capacitor, a first input connected to the output of the first amplifier, and a second input connected to the output of the second OTA. Thus, a circuit is provided that can be used as a type II compensator or as the first stage of a type III compensator. Operationally, this is equivalent to a proportional-integral (PI) control circuit and can be formed as part of a type III compensator that is operationally equivalent to a proportional-integral-derivative (PID) control circuit.

[0008] Conventional error amplifiers, where the frequency response depends on external or internal passive resistors, typically include numerous trimming components, resistors, and capacitors to adapt the frequency response to a selected switching frequency range and the values ​​of the external inductor L (in voltage-mode control) or the load RL (in current-mode control) and the capacitor Cout (in both cases), allowing the frequency response to be selected for a specific DC-DC converter application (from a certain range). The error amplifier circuit according to this disclosure does not require any external or internal passive resistors; instead, it relies on the OTA. Specifically, the poles and zeros of the error amplifier's transfer function can be defined by the ratio between the OTA transconductance and the compensation capacitor, rather than by defining individual trims for each pole or zero. It is suitable to use a central trimming component to adjust the transconductance or transconductance-to-capacitance ratio for different switching frequencies. Therefore, this error amplifier may require only a single trimming component to fine-tune the frequency response of the error amplifier circuit relative to the values ​​of the external inductor L or the load RL and the capacitor Cout. These potential benefits may be particularly convenient for control circuit designs that require minimal or no customization for different specific applications.

[0009] In one or more embodiments, the first-stage output node is configured to provide an amplified error signal to the switching control circuitry. Such embodiments are effective as type II compensators or PI controllers.

[0010] In one or more other embodiments, the error amplifier circuit further includes a second error amplifier stage having an input node that serves as the output node of the first-stage error amplifier and a second-stage output node, wherein the second-stage output node is configured to provide an amplified error signal to the switching control circuit. Such embodiments are effective as Type III compensators or PID controllers.

[0011] In one or more embodiments, the second-stage error amplifier includes: a first path including a third OTA, wherein the third OTA has an output connected to the output node of the second stage and an input connected to the output node of the first stage; and a second feedback path connected in parallel with the first path and including a series arrangement of a second amplifier, a fourth OTA, and a second capacitor, wherein the fourth OTA has an output connected to a compensation capacitor, a first input connected to the output of the second amplifier, and a second input connected to the output of the fourth OTA. Similarly, by relying on the OTA, trimming resistors can be reduced or eliminated.

[0012] In one or more embodiments, the error amplifier circuit further includes an output capacitor connected between the output node and ground.

[0013] The error amplifier circuit may additionally include a resistor divider comprising two resistors (R1, R2) connected in series and configured to be connected between the output (Vout) of the DC-DC converter and ground, with the node between the two resistors connected to the first input terminal (V'out).

[0014] According to a second aspect of this disclosure, a control circuit is provided for a DC-DC converter, including the aforementioned error amplifier circuit and control logic for controlling a power switch of the DC-DC converter, wherein the power switch is configured to transmit power by means of a switching element. The switching element may be an inductor or one or more capacitors.

[0015] The control circuitry can be integrated as part of an integrated circuit. The first capacitor can be monolithically integrated into the integrated circuit, as can the second capacitor and / or the output capacitor. The integrated circuit can be, or may be included in, the single-chip controller of the DC-DC converter.

[0016] The control circuit may additionally include at least one switch driver configured to drive the DC-DC converter switch via a pulse width modulated (PWM) signal.

[0017] According to a third aspect of this disclosure, a DC-DC converter is provided that includes an error amplifier circuit or integrated circuit and additionally includes at least one switch and a switching inductor element. In other embodiments, the switching element may be one or more capacitors instead of an inductor element.

[0018] These and other aspects of the invention will become apparent from the embodiments described below, and will be explained with reference to the embodiments described below. Attached Figure Description

[0019] The embodiments will be described by way of example only with reference to the accompanying drawings, in which:

[0020] Figure 1 A simplified DC-DC buck converter is shown;

[0021] Figure 2 The gain and phase frequency response of a conventional Type III error amplifier circuit are shown;

[0022] Figure 3 A circuit diagram of a type III error amplifier circuit according to one or more embodiments is shown;

[0023] Figure 4 The gain and phase frequency response of a type III error amplifier circuit according to one or more embodiments are shown;

[0024] Figure 5 The typical frequency response of a PWM control loop (excluding the error amplifier) ​​operating under voltage-mode control is shown.

[0025] Figure 6 It is shown to operate under voltage mode control and has the following characteristics: Figure 2 The loop response of the DC-DC converter in the type III error amplifier circuit shown;

[0026] Figure 7 A circuit diagram of a type II error amplifier circuit according to one or more embodiments is shown;

[0027] Figure 8 The gain and phase frequency response of a type III error amplifier circuit according to one or more embodiments are shown;

[0028] Figure 9 The typical frequency response of a PWM control loop (excluding the error amplifier) ​​operating under current-mode control is shown; and

[0029] Figure 10 It is shown to operate under current-mode control and has the following characteristics: Figure 7 The loop response of the DC-DC converter in the type II error amplifier circuit shown.

[0030] It should be noted that the figures are illustrative and not necessarily drawn to scale. For clarity and convenience in the figures, the relative dimensions and proportions of the parts may be shown by enlarging or reducing them. The same reference numerals are generally used to indicate corresponding or similar features in modified and different embodiments. Detailed Implementation

[0031] Various embodiments are described below that utilize an operational transconductance amplifier as the main component of a novel topology for an error amplifier. The OTA, and specifically its transconductance, replaces the conventionally used passive resistors and is implemented in both Type III and Type II compensated error amplifiers in novel architectures or topologies.

[0032] consider Figure 2 The figure illustrates the gain and phase response of a typical error amplifier providing Type III compensation. It shows various frequencies associated with the poles and zeros of the compensated error amplifier. Those skilled in the art will recognize that the poles correspond to frequencies where the transfer function approaches infinity, and the zeros correspond to frequencies where the transfer function approaches zero.

[0033] The crossover frequency ωc is defined as the frequency at which the open-loop gain of the converter control loop is one (unity). In conventional DC-DC converter designs, the crossover frequency is typically set to about one-tenth to about one-fifth of the switching frequency fsw. Therefore, for an example design with a 1 MHz switching frequency, the crossover frequency would be set to 100 kHz (and for more aggressive designs, this crossover frequency could be as high as 200 kHz). Good stability can then be achieved by appropriately selecting the poles and zeros: typically, the zeros ωz1 and ωz2 are both set close together to compensate for the resonance of the external LC filter (ωLC = (LC)). -0.5 The resonance, under voltage-mode control, can be approximately 5 kHz (or lower for smaller output ripple) to 25 kHz. As shown here, ωc is 100 kHz. The ratio between ωc and ωLC is preferably in the range of about 4 to about 20 (or higher for smaller output ripple). In this example, the first non-dominant pole ωp1 can be arranged at 50% of the switching frequency fsw, or 500 kHz, to ensure sufficient gain margin. Those skilled in the art of feedback control systems will recognize that it is generally necessary to ensure that the gain at 180° phase (referred to as gain margin) does not exceed -6 dB to ensure a stable loop response. If the remaining non-dominant poles are below the switching frequency, these remaining non-dominant poles can be used to compensate for left-half-plane zeros (LHP zeros) caused by the equivalent series resistance (ESR) of the output capacitor, or can be used to set the phase margin in the range of about 50° and about 70°, which is generally considered the optimal choice for transient response. Similarly, those skilled in the art of feedback control systems will recognize that it is generally desirable to ensure that the phase at the crossover frequency is not too close to 0°—too close can lead to instability. Therefore, this figure corresponds on the upper curve 210 to the gain of a conventional Type III compensator trimmed with a passive resistor, and on the lower curve 220 to the frequency response of the phase of the conventional Type III compensator. Those skilled in the art will be familiar with phase increase, which in this example is concentrated at a frequency of 100 kHz in the phase curve 220, and it is expected that the gain curve 210 has a maximum value near the switching frequency, with a specific positive slope below the switching frequency and near the frequency with phase increase.

[0034] Figure 3A circuit diagram of a Type III compensated error amplifier circuit 200, also referred to hereinafter as a "Type III compensator," according to one or more embodiments of the present disclosure is shown. Those skilled in the art will recognize that a Type III compensator is a form of proportional-integral-derivative (PID) amplifier circuit. The error amplifier circuit includes a first input V'out 310, which can be directly connected to the output voltage Vout of a DC-DC converter, or, as shown, can be a scaled version of the output voltage scaled according to voltage dividers R1 and R2 by the coefficient KDIV = R1 / (R1+R2).

[0035] The circuit can be viewed from one angle as having nodes with 320V in between. A The error amplifier has two stages. The first stage is connected to node V at the input. A The first path between them includes a first operational transconductance amplifier (OTA) 230. OTA 230 has a transconductance of Gm1. One input of the OTA is connected to a first input terminal, and the other input is connected to a reference voltage Vref. The first stage of the error amplifier circuit amplifies the error between the voltage at the first input terminal and this reference voltage. The output of the OTA is connected to node V. A .

[0036] In parallel with the OTA is a second path providing feedforward: this path includes an amplifier 240 with gain K1 connected between its first input and the first input of a second operational transconductance amplifier 250 with transconductance Gm2. This OTA 250 is configured as a unity-gain buffer by connecting its output back to its second input at Vb. The feedforward path is accomplished by a DC-blocking feedforward capacitor C1, which can be implemented as (shown at 260) a first compensation capacitor connected between the output of the OTA 250 and node Vb. A Between. The first compensation capacitor C1 typically has a capacitance between approximately a few tenths and several hundred pF. Also, from the perspective of a two-stage error amplifier, the second stage will... A The output node 270 of the error amplifier circuit is connected there. The second stage also includes two parallel paths. Node V A The first path to the output node 270 is provided by a third OTA 295, which is a single-input OTA with a transconductance Gm3. Those skilled in the art will understand that this can be implemented in various ways, such as a common-source MOSFET or a differential input OTA with a voltage-biased positive input. The second path (i.e., the feedback path) includes a second capacitor 265 C2, which can be implemented as connected to node V. AA second compensation capacitor is connected between the output of the other OTA 280 and the OTA 280, which has a transconductance of Gm4. The second compensation capacitor typically has a capacitance between approximately a few tenths and several hundred pF. One input of the OTA 280 is connected to the output node 270 Vea via a second amplifier 290 with a gain K2, and its second input is connected to its output. The second amplifier connects its input to the output node 270 and its output to the OTA 280.

[0037] Capacitor Co 285 is connected between output node 270 Vea and ground. Compared to the first and second capacitors, this capacitor typically has a relatively low capacitance, and can be approximately a few pF. This is provided to limit the high-frequency poles to a frequency typically located at half the switching frequency and to improve the gain margin of the controller's regulation loop. Similarly, this improves the circuit's immunity to any kickback noise from the controller, such as from the comparator in the PWM modulator.

[0038] Analytical methods can be used for analysis. Figure 3 This circuit produces a third-order complex transfer function H(s). Typically, OTA has finite output resistance, which effectively limits the DC gain of the error amplifier and introduces losses into the integrator. However, for the purpose of analyzing the circuit of this disclosure, it can be assumed that these output resistances are infinite, and thus the integrator can be treated as an ideal integrator with infinite DC gain and a first dominant pole at 0 Hz. Then, Figure 2 The transfer function of the circuit shown can be transformed into a factorization form with inverted zeros as follows:

[0039] , of which (1)

[0040] (2)

[0041] The error amplifier is at the first zero point ω Z1 Gain at frequency.

[0042] The first zero point is generated by the finite output impedance of the OTA Gm4, which is configured as a unity-gain buffer and connected in series with the compensation capacitor C2:

[0043] (3).

[0044] The second zero point is generated by the feedforward path through Gm2 250:

[0045] (4)

[0046] The circuit has a dominant pole ωp0 at 0 Hz, and two non-dominant poles ωp1 and ωp2:

[0047] , and (5)

[0048] (6).

[0049] It can be found that the crossover frequency of the control loop of the DC-DC converter, including the error amplifier disclosed in this paper, is:

[0050] , (7)

[0051] When operating in voltage control mode, K PWM It is the gain of the PWM modulator in the converter switching control circuit. (The auxiliary amplifier 200 with gain K2 has the same effect as a capacitor multiplier and is one of the known methods for reducing the size of C2, and can be used to reduce the required layout area).

[0052] It can be seen that, for Figure 2 In the circuit shown, the distance between the first non-dominant pole and the second zero is:

[0053] , (8)

[0054] In some practical designs, its value should preferably be within the range of approximately 20 to approximately 100. (As mentioned above, the resonance of the external LC filter (ωLC = (LC)) -0.5 The ratio of ωc to ωLC can be approximately 5 kHz to 25 kHz, and the ratio between ωc and ωLC is preferably in the range of approximately 4 to approximately 20. ωp1 / ωz2 is approximately 5 times this ratio, i.e., approximately 20 to approximately 100. For any practical design, the ratio between transconductances should not be too high, i.e., Gm2 / Gm1 should not exceed, for example, approximately 10, to avoid layout area and power consumption, as well as reduced accuracy of the Gm2 / Gm1 ratio due to mismatch. An amplifier 240 with gain K1 can be used to avoid the unfeasible high ratio Gm2 / Gm1 between OTA 230 and 250. Without this amplifier, a high ratio between Gm2 and Gm1 would be required to ensure that ωp1 / ωz2 is in the preferred range of approximately 20 to approximately 100. This ensures that the error amplifier design is not too power-intensive, and that the circuit is reproducibly manufactured with sufficient accuracy, taking into account process variations.

[0055] Similarly, the distance or frequency interval between the crossover frequency and the first zero can be seen as:

[0056] , (9)

[0057] Furthermore, in some practical designs, it should preferably be within the range of approximately 4 to approximately 20. For example, for the same practical design, K DIV .K PWM Since the value is approximately 10, the desired ωc / ωz1 in the range of approximately 4 to approximately 20 can be achieved by appropriately selecting the ratio Gm1 / Gm4, and K2≥1, which can be used to reduce the required value of the compensation capacitor C2.

[0058] When a converter is designed to operate at a specific switching frequency, the location of the crossover frequency and non-dominant poles is constrained to be connected to the switching frequency. Conversely, the location of the zeros is typically chosen at the resonant frequency generated by the external inductor L and the output capacitor Cout. To enable the amplifier circuit to be used with a variety of external inductors and / or capacitors, it may be necessary to be able to adjust or trim the location of the zeros without significantly affecting the location of the crossover frequency and non-dominant poles. In equations (8) and (9) above, K DIV and K PWM These can be considered as fixed design parameters; furthermore, Gm1 has a relative effect on ωc / ωz1 and ωp1 / ωz2, and therefore should also be fixed. Thus, at LC resonance ω LC The appropriate design parameters to be adjusted to change the (frequency) positions of the zero points ωz1 and ωz2 are Gm2.K1 and Gm4.K2, either in pairs or individually. Those skilled in the art will understand that these parameters can be changed simultaneously in a single adjustment; that is, by changing the value of Gm2, and / or the value of K1, which is the reciprocal of the change in Gm4 and / or K2.

[0059] We will also learn that Figure 2 The circuit extensively uses transconductance to replace passive resistors, and the crossover frequency, poles and zeros, and transfer function shown in Equations 3 to 7 are proportional to the ratio Gm / C, which can thereby reduce the amount of trimming required. Specifically, it is worth noting that no network of other components (e.g., resistors in a resistor network) needs to be adjusted as is typically required in most prior art error amplifiers. Specifically, while the process and temperature variation effects of integrated capacitors are generally small, the process and temperature variation effects of integrated passive resistors are generally large. Although using a constant Gm bias (accompanied by trimming and zero-point temperature coefficient (ZTC) passive resistors as a central trimming component) will utilize at a specific switching frequency Figure 2 The error amplifier shown stabilizes the resulting loop frequency response of the Gm / C converter and the DC-DC converter. However, in order for the circuit to be reused in other applications at other switching frequencies, the constant Gm bias adjustment should cover the entire permissible range of the switching frequency. Therefore, it is preferable to use a constant Gm / C bias, by means of which the frequency loop response of the DC-DC converter will be relative to the switching frequency. Automatic scaling can allow error amplifiers to be used across a wide range of switching frequencies without requiring special trimming of the central trimming component—that is, without explicit trimming of Gm for all transconductances.

[0060] Incidentally, it should be noted that there are known circuit solutions that may be readily applicable to embodiments of this disclosure for automatically adjusting the switching frequency and maintaining a constant transconductance-to-capacitance ratio, thus omitting the central trimming component.

[0061] Figure 4 As shown at 410 Figure 3 The gain of the error amplifier, including the transconductance amplifier, is shown in the diagram and analyzed above, with the frequency response of the error amplifier's phase displayed at 420°. Intuitively, the shape of the gain is roughly similar to that of a conventional compensator. That is, it has a local maximum at approximately (or in this case, less than) 1 MHz of the normal switching frequency, a positive slope for frequencies below the normal switching frequency and approximately a phase increase center frequency of about 100 kHz, and a negative slope at lower frequencies below 10 kHz in this example (i.e., the gain decreases as the frequency increases).

[0062] Figure 5 Examples of operation under voltage-mode control are shown. Figure 1 The typical frequency response of the PWM control loop (excluding the error amplifier) ​​at 510 and phase at 520 is shown at 120. Note that the LC-order low-pass filter response and LC resonance are affected by the switch S. H and S L load R L The resistance is reduced by the series parasitic resistance through L (not shown), therefore the controller response is not flat within the frequency range of interest. Therefore, when designing the complete loop response of a DC-DC control, the design of the PWM controller and the error amplifier should be considered.

[0063] Figure 6 An example of the loop response is shown, which is the error amplifier response multiplied by the remaining PWM control loop response. Figure 6 The gain was plotted at 610 and the phase response at 620.

[0064] As discussed above, Figure 2 The illustrated error compensation amplifier circuit provides so-called Type III compensation, including two zeros and at least three poles. This form of compensation is particularly suitable for DC-DC converters operating in voltage control mode with input voltage feedforward PWM control, thereby improving K0. PWM Both the stability of the frequency characteristics and the converter's stability are improved. Furthermore, the converter's sensitivity to power supply variations and noise is reduced.

[0065] Those skilled in the art will be familiar with the fact that for current-mode control of a DC-DC converter, Type III compensation may not be necessary, and Type II compensation can be performed adequately. Type II compensation is inherently simpler than Type III compensation; this type of circuit typically has a single zero and two poles.

[0066] Figure 7 A type II compensator or error amplifier circuit 700 according to this disclosure is shown. Those skilled in the art will understand that a type II compensator is generally equivalent to a proportional-integral (PI) circuit. Generally speaking, the circuit is identical to the first amplifier stage of a type III compensator: the circuit is connected to node V at the input. A The first path between them contains a first operational transconductance amplifier (OTA) 230. In this type II compensation case, node V... A OTA 320 is directly connected to the circuit's output Vea. OTA 230 has a transconductance of Gm1. One input of OTA is connected to the first input terminal V'out 310, and the other input is connected to the reference voltage Vref. The error amplifier circuit amplifies the error between the voltage at the first input terminal and this reference voltage. The output of OTA is connected to node V. A .

[0067] In parallel with the OTA is a second path providing feedforward: this path includes an amplifier 240 with gain K1 connected between its first input and the first input of a second operational transconductance amplifier 250 with transconductance Gm2. This OTA 250 is configured as a unity-gain buffer OTA by connecting its output back to its second input at Vb. The feedforward path consists of the output of the OTA 250 connected to node V, as shown at 465. A The capacitor C1 between them is completed.

[0068] It should be noted that, Figure 3 In the Type III compensator circuit, the capacitor corresponding to C1 is the DC blocking feedforward capacitor C1, and the compensation capacitor C2 265 is located in the second stage. However, in Figure 6 In the Type II compensator shown, the first capacitor C1 serves two functions—it functions as both a compensation capacitor Cc and a feedforward capacitor C1.

[0069] The analytical analysis of this circuit is similar to that of the Type III error amplifier: the second-order transfer function H(s) of the ideal integrator with its first dominant pole at 0 Hz can be given by factorization with an inverting zero.

[0070] , of which (10)

[0071] (11)

[0072] This is the gain of the error amplifier at the frequency of the first zero ωz1. The frequencies of the first zero ωz1 and the pole ωp1 are given by the following formula:

[0073] , (12)

[0074] (13)

[0075] Typically, Type II compensation is designed to compensate for poles within ωz1, where the poles are generated by the output impedance of the DC-DC converter under maximum load conditions. The frequency of this pole is defined by the following expression.

[0076] , (14)

[0077] Where Km and Ri depend on the specific DC-DC converter: Km is the gain of the modulator of the current-mode controlled converter, and Ri is the linear gain of the current sensing network. Those skilled in the art will understand that for current-mode control, current can be sensed at one or more locations within the circuit, including input current at switching nodes, output current, etc. The value of Ri will depend on the specific architecture used.

[0078] When ωz1 is exactly at ω RC When the position is such that the crossover frequency of the converter controller transfer function is limited by the following formula:

[0079] (15)

[0080] The gain K of the DC-DC power stage MOD Limited by the following expression:

[0081] (16)

[0082] And K DIV It is the gain of the resistor divider.

[0083] Therefore, the distance between the crossover frequency and the first zero (i.e., the frequency interval) is:

[0084] (17)

[0085] In equation (17) above, Gm1, K DIV and K MODωc should be considered a fixed design parameter that limits its position. Gm2 is also not a suitable parameter because it affects the location of the non-dominant pole ωp1. Therefore, the appropriate design parameter for adjusting the zero-point location with respect to the poles generated by the optional output resistor Rout and output capacitor Cout of the DC-DC converter is K1, and a fixed Gm1 / Gm2 ratio. As in the Type III converter embodiment, separating ωc / ωz1 does not indicate an unrealistically high ratio Gm1 / Gm2.

[0086] Finally, in this circuit, the frequency of ωp1 is typically designed to compensate for the equivalent series resistance (ESR) of the output capacitor when the ESR is below fsw or half of the switching frequency fsw, at which frequency double poles may occur due to the sampling effect of the current control loop.

[0087] Figure 8 As shown at 810 Figure 7 The gain of the error amplifier, including the transconductance amplifier, is shown in the diagram and analyzed above, with the phase response of the error amplifier displayed at 820°. It is readily apparent that the shape of the gain is roughly similar to that of a conventional compensator. That is, the gain stabilizes and the phase increases near the crossover frequency.

[0088] Figure 9 Example of operation under current-mode control is shown at 910. Figure 1 The typical gain of the PWM control loop (excluding the error amplifier) ​​is shown at position 120, and the phase response of the PWM control loop is shown at position 920. It should be noted that the controller response is not flat over the frequency range of interest. Therefore, the PWM controller design and the error amplifier should be considered when designing the complete loop response of the DC-DC control.

[0089] Figure 10 An example of the loop response is shown, which is the error amplifier response multiplied by the remaining PWM control loop response. Figure 10 The gain was plotted at 1010 and the phase response at 1020.

[0090] From the above discussion, it should be understood that, as used herein, the term "amplified error signal" will be broadly interpreted to refer to the modified error signal (i.e., a version of the error signal modified in both amplitude and phase), because both the amplified phase and gain can be frequency-dependent. The term "error amplifier" will be interpreted accordingly.

[0091] By reading this disclosure, those skilled in the art will understand other variations and modifications. Such variations and modifications may involve equivalents and other features known in the field of error amplifier circuits for DC-DC converters and may be used in place of or added to the features described herein.

[0092] Although the appended claims are directed to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or combination of novel features or any generalization of such novel features as expressly or implicitly disclosed herein, regardless of whether such novel feature relates to the same invention as currently claimed in any of the claims and whether such novel feature alleviates any or all of the same technical problems as those alleviated by this invention.

[0093] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, various features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination. The applicant hereby reminds that new claims may be made for such features and / or combinations of such features during the examination of this application or any other application derived therefrom.

[0094] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude multiple, a single processor or other unit can perform the functions of several components described in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

Claims

1. An error amplifier circuit for a DC-DC power converter controller and configured to provide an amplified error signal to a switching control circuit, characterized in that, The error amplifier circuit includes a first stage of the error amplifier; The first stage of the error amplifier includes: A first input terminal (V'out) is used to receive a voltage proportional to the output voltage of the DC-DC power converter. Output node (V) A ); A first operational transconductance amplifier OTA, the first operational transconductance amplifier OTA being in a first path between the first input terminal and the output node and having a first input connected to the first input terminal, a second input connectable to a reference signal, and an output connected to the output node; and The second path is between the first input terminal and the output node and includes a series combination of a first amplifier, a second OTA, and a first capacitor, wherein the second OTA has an output connected to the first capacitor, a first input connected to the output of the first operational transconductance amplifier OTA, and a second input connected to the output of the second OTA; The second stage of the error amplifier has an input node that serves as the output node of the first stage of the error amplifier and a second stage output node, wherein the second stage output node is configured to provide the amplified error signal to the switching control circuit. The second stage of the error amplifier includes: A first path, the first path including a third OTA, wherein the third OTA has an output connected to the second-stage output node and an input connected to the first-stage output node; and The second path, which is in parallel with the first path, includes a series arrangement of a second capacitor, a fourth OTA, and a second amplifier, wherein the fourth OTA has an output connected to the second capacitor, a first input connected to the output of the second amplifier, and a second input connected to the output of the fourth OTA.

2. The error amplifier circuit according to claim 1, characterized in that, Additionally, it includes an output capacitor connected between the output node and ground.

3. The error amplifier circuit according to claim 1, characterized in that, Additionally, a resistor divider is included, comprising two resistors (R1, R2) connected in series and configured to connect between the output (Vout) of the DC-DC power converter and ground, with the node between the two resistors connected to the first input terminal (V'out).

4. A controller (110) for a DC-DC converter and comprising an error amplifier circuit according to any one of the preceding claims and a control circuit for controlling a power switch of the DC-DC converter, characterized in that, The power switch is configured to selectively transmit power through a switching element.

5. An integrated circuit, characterized in that, Includes the controller as described in claim 4.

6. A DC-DC converter, characterized in that, It includes an error amplifier circuit according to any one of claims 1 to 3 or an integrated circuit according to claim 5, and further includes at least one DC-DC converter switch and a switching inductor element.

7. A DC-DC converter, characterized in that, It includes an error amplifier circuit according to any one of claims 1 to 3 or an integrated circuit according to claim 5, and further includes at least one DC-DC converter switch and a switched capacitor element.

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