A low-voltage low-power asynchronous successive approximation analog-to-digital converter device

Abstract

The application discloses a low-voltage and low-power asynchronous successive approximation analog-to-digital converter device, which comprises an asynchronous successive approximation analog-to-digital converter and an output buffer circuit, and the asynchronous successive approximation analog-to-digital converter is connected with the output buffer circuit, characterized in that the asynchronous successive approximation analog-to-digital converter comprises a sample-and-hold circuit, an N-bit capacitor array, an asynchronous dynamic comparator and asynchronous SAR logic; the sample-and-hold circuit is connected with the N-bit capacitor array and connected with the asynchronous dynamic comparator; and the asynchronous dynamic comparator is connected with the asynchronous SAR logic. The application is a kind of analog-to-digital converter with medium-low speed, medium-high precision and low power consumption. The application can be widely applied to the field of digital-analog hybrid integrated circuit design as a kind of low-voltage and low-power asynchronous successive approximation analog-to-digital converter device.

Description

Technical Field

[0001] This invention relates to the field of mixed-signal integrated circuit design, and more particularly to a low-voltage, low-power asynchronous successive approximation analog-to-digital converter device. Background Technology

[0002] In today's information age, various signals exist in our lives in different forms, and signals containing specific data can represent any information in the real physical world, such as audio and images. From a formal perspective, signals can be divided into analog signals and digital signals. In nature, most signals are analog signals, characterized by their amplitude changing continuously over time; while digital signals are discrete. For example, in electronic products, most transmitted and processed signals are binary numbers, i.e., "0" or "1". Therefore, analog and digital signals are not "seamlessly connected." To enable the transfer of analog signals to digital signal processing systems, a medium called an analog-to-digital converter (ADC) was developed. With the rapid advancement of technology and the widespread use of electronic devices, ADCs play a crucial role. Meanwhile, fierce competition among countries in high-tech fields such as biotechnology, medical equipment, and aerospace has gradually increased the performance requirements for ADCs. Currently, ADCs struggle to achieve low power consumption while maintaining high accuracy, presenting a challenge in balancing speed, power consumption, and accuracy. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a low-voltage, low-power asynchronous successive approximation analog-to-digital converter (ADC) device, featuring medium-to-low speed (1k-10MS / s sampling rate), medium-to-high precision (8-12bits resolution), and low power consumption.

[0004] The technical solution adopted in this invention is: a low-voltage, low-power asynchronous successive approximation analog-to-digital converter (ADC) device, comprising an asynchronous successive approximation ADC and an output buffer circuit, wherein the asynchronous successive approximation ADC is connected to the output buffer circuit, characterized in that the asynchronous successive approximation ADC includes a sample-and-hold circuit, an N-bit capacitor array, an asynchronous dynamic comparator, and asynchronous successive approximation (SAR) logic, wherein the sample-and-hold circuit and the N-bit capacitor array are connected and connected to the asynchronous dynamic comparator, and the asynchronous dynamic comparator is connected to the asynchronous SAR logic.

[0005] Preferably, it also includes a signal section, which includes a differential input signal, a sampling clock, an input clock for the parallel-to-serial converter circuit, and three parallel-to-serial converter circuit output signals.

[0006] Preferably, the sample-and-hold circuit adopts a dual-voltage sample-and-hold circuit, and the operation process of the asynchronous successive approximation analog-to-digital converter is as follows:

[0007] The sampling phase begins when the sampling clock is high and follow-up sampling is performed. When the low level is reached, the sample-and-hold circuit switch is turned off, and the sampling phase ends.

[0008] At the start of the conversion phase, the sampled signal is passed to the capacitors of the N-bit capacitor array (CDAC) for storage, the first comparison is performed, and the comparison result is transmitted to the asynchronous SAR logic to execute the binary search algorithm to control the switching of the CDAC and perform the binary search operation.

[0009] The process involves a cyclic sampling phase and a conversion phase to obtain N bits of data.

[0010] Preferably, the asynchronous dynamic comparator includes a comparator of a ring oscillator, a first inverter, a second inverter, an XOR gate, a third inverter, a first capacitor, a fourth inverter, a second capacitor, a fifth inverter, and a first NMOS transistor. The comparator of the ring oscillator is connected to the first inverter, the second inverter, and the fifth inverter respectively. The first inverter and the second inverter are connected to the XOR gate respectively. The XOR gate, the third inverter, and the fourth inverter are connected in sequence. The first capacitor, the third inverter, and the fourth inverter are connected together. The second capacitor is connected to the fourth inverter. The fifth inverter is connected to the comparator of the ring oscillator and the first NMOS transistor respectively. The first NMOS transistor, the XOR gate, and the third inverter are connected together.

[0011] Preferably, the comparator of the ring oscillator consists of two NAND gates and a voltage-controlled delay unit.

[0012] Preferably, the XOR gate includes a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor. The gate of the first PMOS transistor is connected to the drain of the second PMOS transistor, the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor, and the sources of the first PMOS transistor, the second PMOS transistor, the second NMOS transistor, and the second NMOS transistor are connected together.

[0013] Preferably, the N-bit capacitor array is sampled from the top plate of the capacitor array.

[0014] Preferably, the output buffer circuit adopts a parallel-to-serial conversion circuit, and the operation process of the parallel-to-serial conversion circuit is as follows:

[0015] Parallel data is sampled via K-channel D flip-flops, with sampling control performed by the first clock signal;

[0016] After passing through K / 2 2-to-1 MUX, it is controlled by the second clock signal;

[0017] The second clock signal is a frequency divided by two of the first clock signal;

[0018] Then, it passes through a K / 2-channel 2-to-1 MUX and is controlled by a third clock signal;

[0019] The third clock signal is a four-fold division of the first clock signal;

[0020] Finally, the data is output after passing through a three-way MUX.

[0021] The beneficial effects of the method and system of the present invention are as follows: By adding an asynchronous dynamic comparator, the present invention not only maintains the characteristic of adaptive power consumption adjustment, but also improves the conversion rate and sampling rate to a certain extent. In addition, by using a low-voltage XOR gate as a comparator, the comparator can not only operate under low voltage conditions, but also has a simple structure, thereby reducing the overall power consumption. Attached Figure Description

[0022] Figure 1 This is an overall structural diagram of a low-voltage, low-power asynchronous successive approximation analog-to-digital converter device according to the present invention.

[0023] Figure 2 This is a schematic diagram of the structure of an asynchronous successive approximation analog-to-digital converter according to a specific embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the asynchronous dynamic comparator according to a specific embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the comparator structure of a ring oscillator according to a specific embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of the edge propagation in the voltage-controlled delay unit according to a specific embodiment of the present invention;

[0027] Figure 6 This is a timing diagram of the asynchronous dynamic comparator in a specific embodiment of the present invention;

[0028] Figure 7 This is a schematic diagram of the XOR gate in a specific embodiment of the present invention;

[0029] Figure 8 This is a schematic diagram of the structure of an N-bit capacitor array according to a specific embodiment of the present invention;

[0030] Figure 9 This is a schematic diagram of the common-mode level generation circuit according to a specific embodiment of the present invention;

[0031] Figure 10 This is a timing diagram of the parallel-to-serial converter circuit according to a specific embodiment of the present invention;

[0032] Figure 11 This is a schematic diagram illustrating the implementation of the parallel-to-serial circuit DATA serial data output in a specific embodiment of the present invention.

[0033] Figure reference numerals: S / H, Sample and Hold circuit; N-bit DAC, N-bit capacitor array; Comparator, Asynchronous dynamic comparator; SAR logic, Asynchronous SAR logic; Vin_p, Vin_n, Differential input signals; CLKs, Sampling clock; CLKc, Input clock of parallel-to-serial converter; DATA, CLK_out, V_pulse, Output signals of 3-channel parallel-to-serial converter; COMP1, Comparator of ring oscillator; inv1, First inverter; inv2, Second inverter; XOR, Exclusive OR gate; inv3, Third inverter; C1, First capacitor; inv4, Fourth inverter; C2, Second capacitor; inv5, Fifth inverter; M1, First NMOS transistor; NAND, NAND gate; Delay cell, Voltage-controlled delay cell; M2, First PMOS transistor; M3, Second PMOS transistor; M0, Second NMOS transistor; Vcmgenerator, Common-mode level generator; Data register; Shift register. Detailed Implementation

[0034] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

[0035] This invention designs a medium-low speed (1k-10MS / s sampling rate), medium-high precision (8-12bit resolution) and low power consumption ADC, and proposes an asynchronous successive approximation analog-to-digital converter based on a binary weighted capacitor DAC with a 0.5V power supply voltage, Vcm-based capacitor switching and a dynamic comparator with adaptive power consumption adjustment.

[0036] Reference Figure 1 This invention provides a low-voltage, low-power asynchronous successive approximation analog-to-digital converter (SARADC) device, comprising an asynchronous successive approximation SARADC and an output buffer circuit. The asynchronous successive approximation SARADC is connected to the output buffer circuit. The asynchronous successive approximation SARADC includes a sample-and-hold circuit, an N-bit capacitor array, an asynchronous dynamic comparator, and asynchronous SAR logic. The sample-and-hold circuit and the N-bit capacitor array are connected and connected to the asynchronous dynamic comparator, which is connected to the asynchronous SAR logic.

[0037] As a further preferred embodiment of the device, it also includes a signal section, which includes a differential input signal, a sampling clock, an input clock for the parallel-to-serial converter circuit, and three parallel-to-serial converter circuit output signals.

[0038] Specifically, the sampling clock CLKs input is first allocated to two sample-and-hold circuits, converting the continuous-time differential input signal into a discrete-time differential signal. This signal is then passed to a comparator, which compares the sampled input signal with the output voltage generated by the internal CDAC. The other sampling clock CLKs is allocated to the asynchronous SAR logic circuit, controlling its step-by-step conversion for each cycle: triggering the binary search algorithm conversion for each cycle. An N-bit ADC requires N steps to parse the input signal and convert it into N bits of data D. <n:0>Finally, the data is serially output (DATA, CLK_out, and V_pulse) through a parallel-to-serial converter.

[0039] As a further preferred embodiment of this method, the sample-and-hold circuit adopts a dual-voltage sample-and-hold circuit, and the operation process of the asynchronous successive approximation analog-to-digital converter is as follows:

[0040] The sampling phase begins when the sampling clock is high and follow-up sampling is performed. When the low level is reached, the sample-and-hold circuit switch is turned off, and the sampling phase ends.

[0041] At the start of the conversion phase, the sampled signal is passed to the capacitors of the N-bit capacitor array CDAC for storage, the first comparison is performed, and the comparison result is transmitted to the SAR logic circuit to execute the binary search algorithm to control the switching of the CDAC and perform the binary search operation.

[0042] The process involves a cyclic sampling phase and a conversion phase to obtain N bits of data.

[0043] Specifically, the specific structure of the asynchronous successive approximation analog-to-digital converter is described in reference to... Figure 2 Since the power supply voltage is designed to be low, a dual boost sampling and holding circuit is used to enable the sampling MOSFET to conduct better. Its operation includes two stages: sampling stage and conversion stage.

[0044] As a further preferred embodiment of this method, the asynchronous dynamic comparator includes a comparator of a ring oscillator, a first inverter, a second inverter, an XOR gate, a third inverter, a first capacitor, a fourth inverter, a second capacitor, a fifth inverter, and a first NMOS transistor. The comparator of the ring oscillator is connected to the first inverter, the second inverter, and the fifth inverter respectively. The first inverter and the second inverter are connected to the XOR gate respectively. The XOR gate, the third inverter, and the fourth inverter are connected in sequence. The first capacitor, the third inverter, and the fourth inverter are connected together. The second capacitor is connected to the fourth inverter. The fifth inverter is connected to the comparator of the ring oscillator and the first NMOS transistor respectively. The first NMOS transistor, the XOR gate, and the third inverter are connected together.

[0045] Specifically, the structure diagram of the asynchronous dynamic comparator is shown in the reference diagram. Figure 3 .

[0046] As a further preferred embodiment of this device, the comparator of the ring oscillator consists of two NAND gates and a voltage-controlled delay unit.

[0047] Specifically, Figure 4 The structure of comparator COMP1 in a ring oscillator is shown. It consists of two NAND gates and a voltage-controlled delay cell. When the signal CLK_in is low, the comparator is in a static state. When the signal CLK_in changes from low to high, the comparator is triggered to start working, injecting two rising edges into the oscillator. These rising edges move around the ring comparator until one edge surpasses the other, ending the comparison. The differential input signals Vin_p and Vin_n alternately control the current-limiting transistors at the top and bottom of the delay cell, adjusting the propagation delay of the pull-up and pull-down edges. Increasing Vin_p will cause one edge to propagate faster and the other slower (and vice versa for Vin_n). Figure 5 As shown, when one propagating edge surpasses another edge, the comparator output stabilizes at VDD or GND, and the output result depends on the speed of the two edges. Furthermore, when there is a large voltage difference at the differential input of the comparator COMP1 in the ring oscillator, the comparator will not oscillate and will directly output the result, thus saving a significant amount of power. If the differential input voltage difference is small, a ring oscillation will occur, and the number of cycles required for decision-making will automatically increase as the voltage difference decreases. Therefore, this comparator can quickly obtain a comparison result with low power consumption when the voltage difference is large, but the required decision time and power consumption will increase accordingly as the input voltage difference decreases.

[0048] Furthermore, because this comparator cannot determine when the comparison is complete, it is generally only used in synchronous analog-to-digital converters. This design improves upon this characteristic, enabling its use in asynchronous ADCs. This design is implemented by adding a result decision circuit to the comparator's output: an inverter is added to both Voutp and Voutn, and a cascaded XOR gate is used, as shown in the circuit diagram. Figure 3 As shown in the diagram. Once the outputs of Voutp and Voutn stabilize, the XOR gate output changes from 0 to 1. The added first MOSFET M1 is for a reset function; its gate is low during voltage transition and changes to high afterward to reset. When the input voltage difference is small, the outputs of Voutp and Voutn will initially rise and fall simultaneously. Over several cycles, they will gradually diverge. Note that due to the limited precision of the XOR gate, if the voltage difference between inputs a and b is very small, it may prematurely determine that the comparison has ended before the comparator has actually determined the result. However, this time is very small, and the subsequent delay unit cancels out the earlier delay, so this misjudgment will not affect the circuit. The timing diagram is shown in the diagram. Figure 6 As shown.

[0049] As a further preferred embodiment of this device, the XOR gate includes a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor. The gate of the first PMOS transistor is connected to the drain of the second PMOS transistor, the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor, and the source of the first PMOS transistor, the source of the second PMOS transistor, the source of the second NMOS transistor, and the drain of the second NMOS transistor are connected together.

[0050] Specifically, traditional XOR gates struggle to operate properly at low supply voltages, and the large number of stacked transistors results in significant dynamic power consumption. To achieve better power efficiency, this design employs a low-voltage design, such as... Figure 7 As shown, the XOR circuit consists of two PMOS transistors and one NMOS transistor, ultimately connected to two inverters as the output buffer stage. When both inputs a and b are low, the two PMOS transistors M2 and M3 are turned on. Since the drains of the transistors are cross-connected to a and b, a weak low-level signal is transmitted. Because the NMOS transistor M0 is connected in a diode configuration, it acts as a resistor, resulting in a small output voltage close to zero. When one of a and b is high and the other is low, one of the PMOS transistors is turned on, transmitting a high level. Since the PMOS transistor is connected in series with the diode-connected NMOS transistor, a small voltage division occurs, resulting in an output voltage close to a high level. When both a and b are high, M2 and M3 are turned off, but a small leakage current flows through the diode-connected NMOS transistor, resulting in an output voltage close to a low level. Although the output voltage is not full-swing in all cases, the desired effect can still be achieved through waveform restoration via two inverter stages. This XOR structure is not only advantageous for low-voltage designs, but also has a smaller total number of transistors and lower power consumption compared to traditional structures.

[0051] As a further preferred embodiment of this device, the N-bit capacitor array is sampled using the top plate of the capacitor array.

[0052] Specifically, this design proposes a DAC circuit structure, referring to... Figure 8 Sampling is performed using the top plate of the capacitor array. The advantage of top-plate sampling is a smaller capacitor array layout area; a CDAC with N conversions only requires one unit capacitor, whereas bottom-plate sampling would require several unit capacitors. During the sampling phase, since the sampling capacitor arrays for Vinp and Vimn are symmetrical, according to charge conservation, the combined voltage of the bottom plate during sampling is Vdd / 2 (=Vcm). Notably, there is a common-mode level drift in the charge-sharing section. This design uses dynamic diode voltage division to generate the common-mode voltage Vcm, such as... Figure 9 As shown. A dynamic control clock VC is used for control. When sampling and at the end of conversion, VC is set to low level, and the Vcm generation circuit does not work; during ADC conversion, VC is set to high level, generating a voltage of Vdd / 2.

[0053] As a further preferred embodiment of this device, the output buffer circuit adopts a parallel-to-serial conversion circuit, and the operation process of the parallel-to-serial conversion circuit is as follows:

[0054] Parallel data is sampled via K-channel D flip-flops, with sampling control performed by the first clock signal;

[0055] After passing through K / 2 2-to-1 MUX, it is controlled by the second clock signal;

[0056] The second clock signal is a frequency divided by two of the first clock signal;

[0057] Then, it passes through a K / 2-channel 2-to-1 MUX and is controlled by a third clock signal;

[0058] The third clock signal is a four-fold division of the first clock signal;

[0059] Finally, the data is output after passing through a three-way MUX.

[0060] Specifically, the output buffer circuit is a parallel-to-serial converter, and its operating timing is as follows: Figure 10 As shown, the K-bit parallel data output by the ADC is converted into a single-channel serial data DATA. Then, a clock cycle CLK_out is output for each bit. In each cycle T, the first half of the cycle is low, and it transitions from low to high starting at T / 2, remaining high for the second half of the cycle. Simultaneously, to distinguish each sampled data, a pulse V_pulse is added before the DATA output.

[0061] The implementation methods of DATA serial data output, such as Figure 11 As shown, Kbit parallel data D <k-1:0>First, sampling is carried out through K-path D flip-flops, and sampling control is carried out through clock Clk1. Then, control is carried out through K / 2 two-way MUXs, and then control is carried out through K / 2 two-way MUXs, and the control clock is half of clock Clk2 (fourth of clock Clk1) at this time, and finally, data DATA is output through a three-way MUX.

[0062] The beneficial effects of the present application are specifically:

[0063] In the overall architecture of the ADC, in order to reduce the overall power consumption, the overall SAR ADC circuit is designed under the condition of low power supply voltage, and each module adopts low voltage design, such as a double-boost circuit for increasing the sampling tube gate voltage Vg for better conduction of the sampling tube, and a new type of low-voltage structure for the XOR gate, which can better realize the circuit function and meet the requirements of low-voltage environment.

[0064] The power consumption of the dynamic comparator used in the present application is no longer linearly changed, and is adaptively adjusted with the size of the input voltage difference. When the differential input voltage is large, the result is directly output, and the power consumption is low. When the differential input voltage is low, the comparison time is also increased. This structure is generally used in synchronous timing ADC. The present design increases the decision circuit, while retaining adaptive adjustment of power consumption and high precision, and improves the sampling rate, and is suitable for low-speed, high-precision successive approximation analog-digital converters.

[0065] The present application uses a dynamic diode voltage division DAC circuit structure to generate Vcm. In the DAC switching timing sequence, the traditional bottom plate sampling N bit DAC needs 2 N unit capacitors, and if the probability of each digital code is the same, the average power consumption is The present design adopts a capacitor sharing DAC, and N bit only needs 2 N-1 unit capacitors, reducing the layout area by half, and the power consumption is reduced by 87% compared with the traditional bottom plate sampling DAC. In addition, the common mode voltage Vcm is obtained by using the MOS diode connection method, without the need for external solder pads and additional common mode voltage input, which can reduce the chip area. At the same time, the Vcm generating circuit designed is dynamically time-controlled, without static power consumption, which reduces the circuit power consumption to a certain extent.

[0066] This invention uses a circuit to convert parallel data to serial data. Typically, an N-bit ADC generates N bits of data, requiring N pads on the chip. For high-precision chips (12 bits or more), a large number of pads are needed, resulting in a significant increase in chip area. This design uses a parallel-to-serial conversion method, which can convert N bits into three serial data streams, providing greater efficiency for medium-to-high precision ADCs.

[0067] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A low voltage, low power asynchronous successive approximation analog-to-digital converter device comprising an asynchronous successive approximation analog-to-digital converter and an output buffer circuit, the asynchronous successive approximation analog-to-digital converter connected to the output buffer circuit, characterized by, The asynchronous successive approximation analog-digital converter comprises a sample-and-hold circuit, an N-bit capacitor array, an asynchronous dynamic comparator, and asynchronous successive approximation logic, the sample-and-hold circuit and the N-bit capacitor array are connected and connected with the asynchronous dynamic comparator, and the asynchronous dynamic comparator is connected with the asynchronous successive approximation logic. The asynchronous dynamic comparator comprises a ring oscillator comparator, a first inverter, a second inverter, an XOR gate, a third inverter, a first capacitor, a fourth inverter, a second capacitor, a fifth inverter, and a first NMOS transistor, the ring oscillator comparator is connected with the first inverter, the second inverter, and the fifth inverter respectively, the first inverter and the second inverter are connected with the XOR gate respectively, the XOR gate, the third inverter, and the fourth inverter are connected in sequence, the first capacitor, the third inverter, and the fourth inverter are connected, the second capacitor is connected with the fourth inverter, the fifth inverter is connected with the ring oscillator comparator and the first NMOS transistor respectively, and the first NMOS transistor, the XOR gate, and the third inverter are connected. The XOR gate comprises a first PMOS transistor, a second PMOS transistor, and a second NMOS transistor, the gate of the first PMOS transistor is connected with the drain of the second PMOS transistor, the gate of the second PMOS transistor is connected with the drain of the first PMOS transistor, and the source of the first PMOS transistor, the source of the second PMOS transistor, the source of the second NMOS transistor, and the drain of the second NMOS transistor are connected. When the output results of Voutp and Voutn are stable, the output of the XOR gate changes from 0 to 1, and the first NMOS transistor is added to increase a reset function, the gate is low during voltage conversion, and the gate changes from low to high after voltage conversion to reset.

2. The low-voltage low-power asynchronous successive approximation ADC device according to claim 1, wherein, The signal part comprises a differential input signal, a sampling clock, an input clock of a parallel-serial conversion circuit, and a 3-way parallel-serial conversion circuit output signal.

3. The low-voltage low-power asynchronous successive approximation ADC device of claim 2, wherein, The sample-and-hold circuit adopts a double-voltage sample-and-hold circuit, and the working process of the asynchronous successive approximation analog-digital converter is as follows: The sampling stage starts, the sampling clock is high, and sampling is performed, when the low level arrives, the sample-and-hold circuit switch is disconnected, and the sampling stage ends; The conversion stage starts, the sampled signal is transmitted to the capacitor of the N-bit capacitor array for storage, the first comparison is performed, the comparison result is transmitted to the asynchronous successive approximation logic, the binary search algorithm is executed to control the switch of the digital-analog conversion capacitor array, and the binary operation is performed; The sampling stage and the conversion stage are repeated to obtain N-bit data.

4. The low-voltage low-power asynchronous successive approximation ADC device of claim 3, wherein, The ring oscillator comparator is composed of two NAND gates and a voltage-controlled delay unit.

5. The low-voltage low-power asynchronous successive approximation ADC device of claim 4, wherein, The N-bit capacitor array adopts a top plate sampling of a capacitor array.

6. The low-voltage, low-power asynchronous successive approximation ADC device of claim 5, wherein, The output buffer circuit adopts a parallel-serial conversion circuit, and the working process of the parallel-serial conversion circuit is as follows: Parallel data is sampled through K-way D flip-flops, and the sampling is controlled by a first clock signal; The data is controlled by a second clock signal through K / 2 two-way MUXes; The second clock signal is a half frequency of the first clock signal; The data is controlled by a third clock signal through K / 2 two-way MUXes; The third clock signal is a quarter frequency of the first clock signal; Finally, the data is output through a three-select MUX.

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