semiconductor circuits

Abstract

The present invention relates to a semiconductor circuit, comprising a high-voltage integrated circuit and a switching tube; the high-voltage integrated circuit comprises a driving circuit, an undervoltage protection circuit, and a fault logic control circuit; the undervoltage protection circuit comprises multiple voltage comparison circuits and an undervoltage comparator, wherein the output of the undervoltage comparator is connected to the fault logic control circuit; each voltage comparison circuit comprises a pull-down resistor, a reference resistor, and a detection comparator, wherein the first end of the pull-down resistor is connected to a reference power supply, the second end of the pull-down resistor is grounded via the reference resistor, the second end of the pull-down resistor is also connected to the positive input of the detection comparator, the negative input of the detection comparator is used to connect to an external processor of the semiconductor circuit, and the output of the detection comparator is connected to the negative input of the undervoltage comparator. The semiconductor circuit can achieve flexible and adjustable undervoltage thresholds, can adapt to complex undervoltage protection requirements in the semiconductor circuit, and improve the stability and reliability of circuit operation.

Description

Technical Field

[0001] The present invention relates to a semiconductor circuit, belonging to the technical field of semiconductor circuit applications. Background Art

[0002] Semiconductor circuits are power-driven products that combine power electronics and integrated circuit technology. They are also called intelligent power modules (IPMs). IPMs integrate power switching devices with HVICs (High Voltage Integrated Circuits) and have built-in fault detection circuits for overvoltage, overcurrent, and overheating. IPMs receive control signals from the MCU and drive subsequent circuits, while also feeding back system status detection signals to the MCU. Compared to traditional separate layouts, IPMs are gaining a growing market share with their high integration and reliability. They are particularly well-suited for motor drive converters and various inverter power supplies, making them ideal power electronic devices for variable-frequency speed regulation, metallurgical machinery, electric traction, servo drives, and variable-frequency home appliances.

[0003] The undervoltage protection of the intelligent power module refers to the protective action taken on the circuit when the operating voltage of certain components does not reach the expected level when the product is working. For example, if the intelligent power module is powered by a 15V power supply, if the power supply voltage is lower than 12.5V (typical value) and the time exceeds the pre-defined time, undervoltage protection will occur. At this time, the gate drive circuit will be blocked, and the fault terminal of the module will output a fault signal to cause the peripheral main control board to cut off the module operation. In related technologies, the undervoltage comparison threshold set by the intelligent power module is often relatively simple and can only detect a fixed voltage level. It is difficult to adapt to more complex application environments, and setting up multiple undervoltage protection circuits will increase the overall cost of the module.

[0004] In summary, the technical problems existing in the relevant technologies need to be solved urgently. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to solve a series of problems caused by the fact that the undervoltage comparison threshold in the existing semiconductor circuit is often relatively simple and can only detect a fixed voltage level, making it difficult to adapt to more complex application environments.

[0006] Specifically, the present invention discloses a semiconductor circuit, including a high-voltage integrated circuit and a switch tube; the high-voltage integrated circuit includes a drive circuit, an undervoltage protection circuit and a fault logic control circuit, and the drive circuit is connected to the switch tube;

[0007] The undervoltage protection circuit includes multiple voltage comparison circuits and undervoltage comparators, the positive input end of the undervoltage comparator is connected to the undervoltage monitoring point, and the output end of the undervoltage comparator is connected to the fault logic control circuit; each voltage comparison circuit includes a pull-down resistor, a reference resistor and a detection comparator, the first end of the pull-down resistor is connected to the reference power supply, the second end of the pull-down resistor is grounded through the reference resistor, the second end of the pull-down resistor is also connected to the positive input end of the detection comparator, the negative input end of the detection comparator is used to connect to the external processor of the semiconductor circuit, and the output end of the detection comparator is connected to the negative input end of the undervoltage comparator; wherein, the resistance ratio of the pull-down resistor and the reference resistor in at least two of the voltage comparison circuits is different.

[0008] Optionally, the driving circuit includes a high-voltage side driving circuit and a low-voltage side driving circuit, and the high-voltage side driving circuit and the low-voltage side driving circuit are connected.

[0009] Optionally, the high-voltage side drive circuit includes three identical high-voltage drive units, each of the high-voltage drive units includes an upper bridge arm signal input terminal, two high-voltage side power supply terminals and a high-voltage side control output terminal; wherein, the upper bridge arm signal input terminal is used to receive the upper bridge arm PWM control signal output by the peripheral main control board, the two high-voltage side power supply terminals are used to input two control signals corresponding to the upper and lower bridge arm switching tubes of one phase respectively, and the high-voltage side control output terminal is used to output a drive signal for driving the upper bridge arm switching tube of one phase.

[0010] Optionally, the high-voltage driving unit includes a first Schmitt trigger, a first filtering circuit, a first potential shifting circuit, a first dead zone interlocking unit, a pulse generating circuit, a DV / DT filter circuit, a latch, a NOR logic gate, a UV filtering circuit, a first MOS transistor, a second MOS transistor, a first current limiting resistor, a second current limiting resistor and a first output driving circuit;

[0011] The input end of the first Schmitt trigger is the upper bridge arm signal input end, the output end of the first Schmitt trigger is connected to the input end of the first filter circuit; the output end of the first filter circuit is connected to the input end of the first potential shift circuit; the output end of the potential shift circuit is connected to the input end of the first dead zone interlock unit; the output end of the first dead zone interlock unit is connected to the input end of the pulse generation circuit; the output end of the pulse generation circuit is connected to the gate of the first MOS transistor and the second MOS transistor, and the drain of the first MOS transistor and the second MOS transistor is connected to the input end of the DV / DT filter circuit. , the drain of the first MOS tube is connected to the positive terminal of the high-voltage side power supply terminal through the first current limiting resistor, and the drain of the second MOS tube is connected to the positive terminal of the high-voltage side power supply terminal through the second current limiting resistor; the output end of the DV / DT filter circuit is connected to the first input end of the latch, and the output end of the UV filter circuit is connected to the second input end of the latch; the output end of the DV / DT filter circuit is connected to the first input end of the NOR logic gate, and the output end of the latch is connected to the second input end of the NOR logic gate; the output end of the NOR logic gate is connected to the input end of the first output drive circuit.

[0012] Optionally, the first output driving circuit includes:

[0013] A third MOS tube and a fourth MOS tube;

[0014] The gate of the third MOS transistor and the gate of the fourth MOS transistor are commonly connected to the input end of the first output drive circuit, the drain of the third MOS transistor is connected to the positive end of the high-voltage side power supply end, the source of the third MOS transistor and the drain of the fourth MOS transistor are commonly connected to the output end of the first output drive circuit, and the source of the fourth MOS transistor is connected to the negative end of the high-voltage side power supply end.

[0015] Optionally, the low-voltage side drive circuit includes three identical low-voltage drive units, each of the low-voltage drive units includes a lower bridge arm signal input terminal, a low-voltage side power supply terminal, a low voltage reference terminal and a low-voltage side control output terminal; wherein, the lower bridge arm signal input terminal is used to receive the lower bridge arm PWM control signal output by the peripheral main control board, and the low-voltage side control output terminal is used to output a drive signal for driving a single-phase lower bridge arm switch tube.

[0016] Optionally, the low-voltage driving unit includes a second Schmitt trigger, a second filtering circuit, a second potential shift circuit, a second dead zone interlocking unit, a delay circuit, a comparator and a second output driving circuit;

[0017] Among them, the input end of the second Schmitt trigger is the lower bridge arm signal input end, the output end of the second Schmitt trigger is connected to the input end of the second filtering circuit; the output end of the second filtering circuit is connected to the input end of the second potential shift circuit; the output end of the second potential shift circuit is connected to the input end of the second dead zone interlocking unit; the output end of the second dead zone interlocking unit is connected to the input end of the delay circuit; the output ends of the pulse generating circuit and the delay circuit are connected to the input end of the comparator, and the output end of the comparator is connected to the input end of the second output driving circuit.

[0018] Optionally, the second output driving circuit includes:

[0019] a fifth MOS tube and a sixth MOS tube;

[0020] The gate of the fifth MOS transistor and the gate of the sixth MOS transistor are commonly connected to the input end of the second output drive circuit, the drain of the fifth MOS transistor is connected to the low-voltage side power supply end, the source of the fifth MOS transistor and the drain of the sixth MOS transistor are commonly connected to the output end of the second output drive circuit, and the source of the sixth MOS transistor is grounded.

[0021] Optionally, the undervoltage protection circuit further includes an encoder;

[0022] The input end of the encoder is used to connect to the external processor of the semiconductor circuit;

[0023] The encoder includes multiple outputs, and each output is connected to a negative input terminal of a detection comparator of a different voltage comparison circuit.

[0024] Optionally, the high-voltage integrated circuit further includes an over-temperature protection circuit, a short-circuit protection circuit and an over-current protection circuit.

[0025] A semiconductor circuit of the present invention comprises a high-voltage integrated circuit and a switching transistor; the high-voltage integrated circuit comprises a drive circuit, an undervoltage protection circuit, and a fault logic control circuit, the drive circuit being connected to the switching transistor; the undervoltage protection circuit comprising multiple voltage comparison circuits and undervoltage comparators, the positive input of each undervoltage comparator being connected to an undervoltage monitoring point, and the output of each undervoltage comparator being connected to the fault logic control circuit; each of the voltage comparison circuits comprises a pull-down resistor, a reference resistor, and a detection comparator, the first end of the pull-down resistor being connected to a reference power supply, the second end of the pull-down resistor being grounded via the reference resistor, the second end of the pull-down resistor being further connected to the positive input of the detection comparator, the negative input of the detection comparator being used to connect to an external processor of the semiconductor circuit, the output of the detection comparator being connected to the negative input of the undervoltage comparator, and the output of the undervoltage comparator being connected to the fault logic control circuit; wherein the resistance ratio of the pull-down resistor to the reference resistor in at least two of the voltage comparison circuits is different. The semiconductor circuit provided by the present invention can realize flexible adjustment of the undervoltage threshold, can adapt to complex undervoltage protection requirements in the semiconductor circuit at a relatively low cost, and improve the stability and reliability of the circuit operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of an interface of a semiconductor circuit according to an embodiment of the present invention;

[0027] Figure 2 A simplified circuit diagram of a semiconductor circuit according to an embodiment of the present invention;

[0028] Figure 3 is a circuit schematic diagram of a driving circuit in an embodiment of the present invention;

[0029] Figure 4 1 is a circuit schematic diagram of an undervoltage protection circuit according to an embodiment of the present invention;

[0030] Figure 5 FIG. 4 is a circuit schematic diagram of another undervoltage protection circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of structural or functional conflicts, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below based on examples.

[0032] The semiconductor circuit referred to in this invention is a circuit module that integrates power switching devices and high-voltage drive circuits in a sealed package. It has a wide range of applications in power electronics, such as motor drive inverters, various voltage inverters, variable frequency speed regulation, metallurgical machinery, electric traction, and variable frequency home appliances. The semiconductor circuit is also known by various other names, such as Modular Intelligent Power System (MIPS), Intelligent Power Module (IPM), hybrid integrated circuit, power semiconductor module, power module, and so on.

[0033] Reference Figure 1 First, combine Figure 1The various interface functions of a semiconductor circuit proposed in this application are described. The semiconductor circuit includes an HVIC (High Voltage Integrated Circuit) chip. The power supply terminal VCC of the HVIC chip can serve as the positive power supply terminal VDD on the low-voltage side of the semiconductor circuit. The voltage at VDD is generally 15V. The HVIC chip generally includes six signal input terminals for receiving the upper and lower bridge arm PWM control signals output by the peripheral main control board. Among them, the first upper bridge arm signal input terminal HIN1, the second upper bridge arm signal input terminal HIN2 and the third upper bridge arm signal input terminal HIN3 can respectively serve as the U-phase upper bridge arm signal input terminal UHIN, the V-phase upper bridge arm signal input terminal VHIN and the W-phase upper bridge arm signal input terminal WHIN of the semiconductor circuit; similarly, the first lower bridge arm signal input terminal LIN1, the second lower bridge arm signal input terminal LIN2 and the third lower bridge arm signal input terminal LIN3 of the HVIC chip can respectively serve as the U-phase lower bridge arm signal input terminal ULIN, the V-phase lower bridge arm signal input terminal VLIN and the W-phase lower bridge arm input terminal WLIN of the semiconductor circuit.Generally speaking, the voltage range of the input signals of the first upper bridge arm signal input terminal HIN1, the second upper bridge arm signal input terminal HIN2, the third upper bridge arm signal input terminal HIN3, the first lower bridge arm signal input terminal LIN1, the second lower bridge arm signal input terminal LIN2 and the third lower bridge arm signal input terminal LIN3 of the semiconductor circuit can be 0~5V; the ground terminal GND of the HVIC chip serves as the low-voltage side power supply negative terminal COM of the semiconductor circuit; the first power supply positive terminal VB1 of the HVIC chip serves as the positive terminal UVB of the U-phase high-voltage side power supply terminal of the semiconductor circuit, the high-voltage side control output terminal HO1 of the HVIC chip is used to output the driving signal for driving the U-phase upper bridge arm switch tube, the first power supply negative terminal VS1 of the HVIC chip serves as the negative terminal UVS of the U-phase high-voltage side power supply terminal of the semiconductor circuit, and the filter capacitor can be connected between the positive terminal UVB of the U-phase high-voltage side power supply terminal of the semiconductor circuit and the negative terminal UVS of the U-phase high-voltage side power supply terminal; the second The positive power supply terminal VB2 serves as the positive terminal VVB of the V-phase high-voltage side power supply terminal of the semiconductor circuit. The high-voltage side control output terminal HO2 of the HVIC chip is used to output a driving signal for driving the V-phase upper bridge arm switch tube. The second negative power supply terminal VS2 of the HVIC chip serves as the negative terminal VVS of the V-phase high-voltage side power supply terminal of the semiconductor circuit. The filter capacitor can be connected between the positive terminal VVB of the V-phase high-voltage side power supply terminal and the negative terminal VVS of the V-phase high-voltage side power supply terminal of the semiconductor circuit. The third positive power supply terminal VB3 of the HVIC chip serves as the positive terminal WVB of the W-phase high-voltage side power supply terminal of the semiconductor circuit. The high-voltage side control output terminal HO3 of the HVIC chip is used to output a driving signal for driving the W-phase upper bridge arm switch tube. The third negative power supply terminal VS3 of the HVIC chip serves as the negative terminal WVS of the W-phase high-voltage side power supply terminal of the semiconductor circuit. The filter capacitor can be connected between the positive terminal WVB of the W-phase high-voltage side power supply terminal and the negative terminal WVS of the W-phase high-voltage side power supply terminal of the semiconductor circuit. The semiconductor circuit also includes a U-phase low voltage reference terminal UN, a V-phase low voltage reference terminal VN, and a W-phase low voltage reference terminal WN; the high voltage input terminal of the semiconductor circuit is generally connected to a 300V voltage.

[0034] The HVIC chip's function is to transmit the 0-5V logic signals received by HIN1, HIN2, HIN3, LIN1, LIN2, and LIN3 to HO1, HO2, HO3, LO1, LO2, and LO3, respectively, to control the operation of the switch components and achieve the driving purpose. HO1, HO2, and HO3 output logic signals from VS to VS+15V, while LO1, LO2, and LO3 output logic signals from 0 to 15V. Input signals of the same phase cannot be simultaneously high. This means that the input signals from the first upper-arm signal input terminal HIN1 and the first lower-arm signal input terminal LIN1 cannot be simultaneously high, the input signals from the second upper-arm signal input terminal HIN2 and the second lower-arm signal input terminal LIN2 cannot be simultaneously high, and the input signals from the third upper-arm signal input terminal HIN3 and the third lower-arm signal input terminal LIN3 cannot be simultaneously high.

[0035] Next, a semiconductor circuit proposed by the present invention is described. Figure 2 As shown, the semiconductor circuit 33 provided in the present application includes a high-voltage integrated circuit 10 and a switch tube 56, wherein the high-voltage integrated circuit 10 includes a drive circuit, an undervoltage protection circuit and a fault logic control circuit 16, and the drive circuit is connected to the switch tube 56.

[0036] More specifically, the high-voltage integrated circuit 10 provided in the present application may also include a cache circuit 11, which is used to receive the upper and lower arm PWM control signals output by the peripheral main control board. After receiving the PWM control signal of the corresponding MCU, it can be processed by filtering, amplification, etc., and then output to the subsequent drive circuit, thereby achieving relatively smooth signal reception and improving the stability of the drive.

[0037] In an embodiment of the present application, the drive circuit of the high-voltage integrated circuit 10 may include an upper-arm drive circuit 100 and a lower-arm drive circuit 13, wherein the upper-arm drive circuit 100 may include a bootstrap circuit, a high-side undervoltage protection circuit, and three identical high-voltage drive units. Each high-voltage drive unit includes an upper-arm signal input terminal for receiving an upper-arm PWM control signal output by a peripheral main control board, which may be a signal pre-processed by a buffer circuit 11. Each high-voltage drive unit also includes a high-side control output terminal for outputting a drive signal for driving a single-phase upper-arm switch tube to the three-phase upper-arm switch tube. Similarly, the lower-arm drive circuit 13 may include three identical low-voltage drive units, each low-voltage drive unit including a lower-arm signal input terminal for receiving a lower-arm PWM control signal output by a peripheral main control board, which may also be a signal pre-processed by a buffer circuit 11. Each low-voltage drive unit also includes a low-voltage side control output terminal for outputting a drive signal for driving a single-phase lower-arm switch tube to the three-phase lower-arm switch tube. It is understandable that the high-voltage side driving circuit in the driving circuit can be powered by high-voltage direct current, and the low-voltage side driving circuit can be powered by low-voltage direct current, and the specific voltage level is not limited here.

[0038] The semiconductor circuit in the embodiment of the present application achieves the purpose of motor driving by dividing the drive circuit therein into a high-voltage side drive circuit and a low-voltage side drive circuit, respectively outputting drive signals to drive the upper bridge arm switch tube and the lower bridge arm switch tube to operate. The high-voltage side drive circuit and the low-voltage side drive circuit can be powered by separate high-voltage direct current and low-voltage direct current, respectively, and transmit multiple pulse signals to drive the switch tube to operate. This can effectively avoid the problem of false triggering caused by the low-voltage side drive circuit being easily interfered with by the current in the high-voltage side drive circuit. At the same time, the design and construction of each part of the drive circuit can be carried out independently, thereby reducing the overall complexity, thereby improving the working reliability of the drive circuit and reducing costs.

[0039] In some embodiments, the high-voltage integrated circuit 10 of the present application may further include an over-temperature protection circuit, a short-circuit protection circuit, and an over-current protection circuit. The specific structures of these circuits can be implemented with reference to the prior art and will not be described in detail here. In the embodiment of the present application, under-voltage protection, over-temperature protection, over-current protection, and short-circuit protection are provided inside the high-voltage integrated circuit 10 at the same time. When a fault occurs during the operation of the circuit, the upper and lower bridges can be interlocked, the power supply signal can be cut off, and other actions can be implemented to avoid product burnout and ensure the stability and reliability of the circuit operation. Specifically, these protection circuits can be integrated into the working protection circuit 14. When the circuit detects a certain fault, the signal can be fed back to the peripheral main control board. For example, the FAULT signal can be converted from a high level to a low level state, so that the corresponding action can be taken immediately to achieve the function of the protection circuit. In some embodiments, when the peripheral main control board performs a protection action, it can implement protection for the semiconductor circuit 33 based on the drive enable circuit 15. The drive enable circuit 15 can be set to be valid at a high level and is responsible for turning on and off the semiconductor circuit 33. When the peripheral main control board monitors the changes in the FAULT signal transmitted by the working protection circuit 14 through the fault logic control circuit 16, it can output a corresponding control signal to keep the drive enable circuit 15 in a low level state and disconnect the power supply of the semiconductor circuit 33 to protect the entire semiconductor circuit from fire or damage due to overcurrent, overheating, short circuit and other factors; when the fault disappears or is resolved after investigation, the drive enable circuit 15 can be restored to a high level state again, the semiconductor circuit 33 is powered on, and re-enters the working ready state.

[0040] Reference Figure 2 , Figure 2 The semiconductor circuit 33 in the circuit has six integrated three-phase full-bridge drivers, and realizes the driving output through the working state of six switching tubes. The semiconductor circuit 33 is loaded with low-voltage DC power VCC (usually 15V voltage) and high-voltage DC power. The positive end of the high-voltage DC power includes three ports VB1 to VB3, and the negative end includes three ports VS1 to VS3 (usually 300-315V voltage). Figure 2 The circuit is divided into a high-voltage side driving circuit 100 and a low-voltage side driving circuit 13 to respectively drive the three switching tubes Q1-Q3 of the upper bridge arm and the three switching tubes Q4-Q6 of the lower bridge arm to work.

[0041] Reference Figure 3In the high-side driving circuit 100, each high-voltage driving unit includes a first Schmitt trigger 300, a first filtering circuit 301, a first potential shift circuit 302, a first dead zone interlocking unit, a pulse generating circuit 304, a DV / DT filter circuit 305, a latch 306, a NOR logic gate 307, a UV filtering circuit 311, a first MOS transistor, a second MOS transistor, a first current limiting resistor RS1, a second current limiting resistor RS2, and a first output driving circuit; the first dead zone interlocking unit includes a first NAND logic gate 303 and a second NAND logic gate 308;

[0042] Among them, the input end of the first Schmitt trigger 300 is the upper bridge arm signal input end, the output end of the first Schmitt trigger 300 is connected to the input end of the first filter circuit 301; the output end of the first filter circuit 301 is connected to the input end of the first potential shift circuit 302; the output end of the first potential shift circuit 302 is connected to the first input terminal of the first NAND logic gate 303, the output end of the first potential shift circuit is connected to the first input terminal of the second NAND logic gate 308, and the output end of the second NAND logic gate 308 is connected to the second input terminal of the first NAND logic gate 303; the output end of the first NAND logic gate 303 is connected to the input end of the pulse generating circuit 304; the output end of the pulse generating circuit 304 is connected to the gates of the first MOS transistor and the second MOS transistor, and the first The drains of the MOS transistor and the second MOS transistor are connected to the input end of the DV / DT filter circuit 305, the drain of the first MOS transistor is connected to the positive end of the high-voltage side power supply end through the first current limiting resistor RS1, and the drain of the second MOS transistor is connected to the positive end of the high-voltage side power supply end through the second current limiting resistor RS2; the output end of the DV / DT filter circuit 305 is connected to the first input end of the latch 306, and the output end of the UV filter circuit 311 is connected to the second input end of the latch 306; the output end of the DV / DT filter circuit 305 is connected to the first input end of the NOR logic gate 307, and the output end of the latch 306 is connected to the second input end of the NOR logic gate 307; the output end of the NOR logic gate 307 is connected to the input end of the first output drive circuit.

[0043] In this embodiment of the present invention, the first Schmitt trigger 300 is used to filter the PWM control signal output by the peripheral main control board and then stably output it to the first filtering circuit 301 in the subsequent stage. The first filtering circuit 301 is used to perform high-frequency, narrow-band filtering on the received control signal, invert the control signal, and output it to the first potential shift circuit 302. When the amplitude of the coupled signal is large, this DC variation can interfere with the interface voltage. The first potential shift circuit 302 is used to compensate for the coupled signal and add a DC level adjustment function, thereby achieving stable signal output to the first dead-band interlock unit. The pulse generation circuit 304 is used to output a high-level signal output from the output end of the first NAND logic gate 303 to the gate of the first MOS transistor and the second MOS transistor to drive them to conduct. The gate and source of the MOS transistor are short-circuited to achieve unidirectional conduction, and the voltage is output to the positive terminal VB of the high-voltage side power supply end through the first bootstrap resistor current limiting resistor RS1 and the second bootstrap resistor current limiting resistor RS2. The DV / DT filter circuit 305 is used to receive the drain voltage of the first MOS transistor and the second MOS transistor, filter and rectify it, thereby stabilizing the voltage. The UV filter circuit 311 receives the level signal after the bootstrap resistor voltage is divided, filters and rectify it. The latch 306 is used to receive and temporarily store the signals from the DV / DT filter circuit 305 and the UV filter circuit 311, ultimately synchronizing the output of the level signals. The NOR logic gate 307 is used to receive the signal from the latch 306 and compare the high and low levels of the input to control the drive and opening status of the MOS transistor in the first output drive circuit.

[0044] In some embodiments of the present invention, the first output driving circuit includes:

[0045] a third MOS transistor and a fourth MOS transistor; the gate of the third MOS transistor and the gate of the fourth MOS transistor are commonly connected to the input end of the first output drive circuit, the drain of the third MOS transistor is connected to the positive end of the high-voltage side power supply end, the source of the third MOS transistor and the drain of the fourth MOS transistor are commonly connected to the output end of the first output drive circuit, and the source of the fourth MOS transistor is connected to the negative end of the high-voltage side power supply end.

[0046] In the embodiment of the present application, in the low-voltage side driving circuit, the low-voltage driving unit includes a second Schmitt trigger 312, a second filtering circuit 313, a second potential shift circuit 314, a second dead zone interlocking unit, a delay circuit 310, a comparator 315 and a second output driving circuit; the second dead zone interlocking unit includes a third NAND logic gate 309;

[0047] Among them, the input end of the second Schmitt trigger 312 is the lower bridge arm signal input end, and the output end of the second Schmitt trigger 312 is connected to the input end of the second filtering circuit 313; the output end of the second filtering circuit 313 is connected to the input end of the second potential shift circuit 314; the output end of the second potential shift circuit 314 is connected to the second input terminal of the third NAND logic gate 309, the output end of the second potential shift circuit 314 is connected to the second input terminal of the second NAND logic gate 308, and the output end of the second NAND logic gate 308 is connected to the first input terminal of the third NAND logic gate 309; the output end of the third NAND logic gate 309 is connected to the input end of the delay circuit 310; the output ends of the pulse generating circuit 304 and the delay circuit 310 are connected to the input end of the comparator 315, and the output end of the comparator 315 is connected to the input end of the second output driving circuit.

[0048] In some embodiments, the second output driver circuit includes:

[0049] a fifth MOS tube and a sixth MOS tube;

[0050] The gate of the fifth MOS transistor and the gate of the sixth MOS transistor are commonly connected to the input end of the second output drive circuit, the drain of the fifth MOS transistor is connected to the low-voltage side power supply end, the source of the fifth MOS transistor and the drain of the sixth MOS transistor are commonly connected to the output end of the second output drive circuit, and the source of the sixth MOS transistor is grounded.

[0051] In the embodiment of the present application, the second Schmitt trigger 312 is used to filter the PWM control signal output by the peripheral main control board and output it stably to the second filter circuit 313 of the subsequent stage. The second filter circuit 313 is used to perform high-frequency, narrow-band filtering on the received control signal, invert the control signal, and output it to the second potential shift circuit 314, and then to the second dead-band interlock unit. The delay unit is used to delay the output of the control signal output by the second dead-band interlock unit to avoid a short circuit fault in the power inverter bridge circuit caused by the simultaneous conduction of the lower-arm power transistor and the upper-arm power transistor of the high-voltage side drive circuit.

[0052] Reference Figure 4In an embodiment of the present application, the undervoltage protection circuit includes multiple voltage comparison circuits and an undervoltage comparator 104, the positive input terminal of the undervoltage comparator 104 is connected to the undervoltage monitoring point, and the output terminal of the undervoltage comparator 104 is connected to the fault logic control circuit 105; each of the voltage comparison circuits includes a pull-down resistor, a reference resistor and a detection comparator, the first end of the pull-down resistor is connected to the reference power supply, the second end of the pull-down resistor is grounded through the reference resistor, the second end of the pull-down resistor is also connected to the positive input terminal of the detection comparator, the negative input terminal of the detection comparator is used to connect to the external processor of the semiconductor circuit, the output terminal of the detection comparator is connected to the negative input terminal of the undervoltage comparator 104, and the output terminal of the undervoltage comparator 104 is connected to the fault logic control circuit 105; wherein, the resistance ratio of the pull-down resistor to the reference resistor in at least two of the voltage comparison circuits is different.

[0053] In the embodiment of the present application, the undervoltage protection circuit includes multiple voltage comparison circuits and an undervoltage comparator 104. For these voltage comparison circuits, they can obtain different undervoltage thresholds from the reference voltage through different resistance values ​​to perform undervoltage protection. Figure 4 For example, the undervoltage protection circuit includes a power input terminal VCC, an undervoltage comparator 104 and three voltage comparison circuits, wherein the first voltage comparison circuit includes a first pull-down resistor R1, a first reference resistor R2 and a first detection comparator 400, the second voltage comparison circuit includes a second pull-down resistor R3, a second reference resistor R4 and a second detection comparator 401, and the third voltage comparison circuit includes a third pull-down resistor R5, a third reference resistor R6 and a third detection comparator 402. Of course, it should be noted that the number of voltage comparison circuits in this application can be any integer greater than or equal to 2, and is not fixed to Figure 4 The situation shown. For each voltage comparison circuit, the potential at the positive input of its detection comparator is determined by the ratio of the pull-down resistor and the reference resistor. Among them, the resistance ratio of the pull-down resistor and the reference resistor in at least two different voltage comparison circuits is different. In other words, the undervoltage thresholds monitored by at least two different voltage comparison circuits are different. The negative input of the detection comparator can be selected by an external processor. When the negative input of the detection comparator is selected, its output outputs a corresponding high level, forming a loop with the undervoltage comparator 104, so that the negative input of the undervoltage comparator 104 can be pulled to the specified undervoltage threshold. The undervoltage comparator 104 can output a level signal based on whether undervoltage occurs. If undervoltage occurs, the level signal is output from the output of the current limiting resistor R12 to the fault logic control circuit 105, triggering undervoltage protection.

[0054] It is understood that in the above embodiments, the undervoltage protection circuit can implement undervoltage protection at different voltage levels. Figure 5 The undervoltage protection circuit in this application may further include an encoder 106; the encoder 106 may include multiple outputs, each output being connected to the negative input of a detection comparator of a different voltage comparison circuit. By integrating the encoder 106 into the HIVC chip, N encoding pin inputs may be provided, enabling selection of switching modes in 2N powers. Figure 5 As shown in the figure, based on the logic input and output control, the undervoltage protection circuit has eight undervoltage value selection channels, namely 1#INPUT to 8#INPUT. In actual application, the undervoltage value can be freely selected through the encoder output channel, thus achieving multi-level adjustable undervoltage value.

[0055] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0056] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0058] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0059] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0060] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A semiconductor circuit, characterized in that: The semiconductor circuit comprises: A high-voltage integrated circuit and a switch tube; the high-voltage integrated circuit includes a drive circuit, an undervoltage protection circuit, and a fault logic control circuit, and the drive circuit is connected to the switch tube; The undervoltage protection circuit includes multiple voltage comparison circuits and undervoltage comparators, the positive input end of the undervoltage comparator is connected to the undervoltage monitoring point, and the output end of the undervoltage comparator is connected to the fault logic control circuit; each of the voltage comparison circuits includes a pull-down resistor, a reference resistor and a detection comparator, the first end of the pull-down resistor is connected to the reference power supply, the second end of the pull-down resistor is grounded through the reference resistor, the second end of the pull-down resistor is also connected to the positive input end of the detection comparator, the negative input end of the detection comparator is used to connect to the external processor of the semiconductor circuit, and the output end of the detection comparator is connected to the negative input end of the undervoltage comparator; wherein, the resistance ratio of the pull-down resistor to the reference resistor in at least two of the voltage comparison circuits is different, and when the negative input end of the detection comparator is selected, its output end outputs a corresponding high level, forming a loop with the undervoltage comparator.

2. The semiconductor circuit according to claim 1, wherein: The driving circuit includes a high-voltage side driving circuit and a low-voltage side driving circuit, and the high-voltage side driving circuit is connected to the low-voltage side driving circuit.

3. The semiconductor circuit according to claim 2, wherein: The high-voltage side drive circuit includes three identical high-voltage drive units, each of which includes an upper bridge arm signal input terminal, two high-voltage side power supply terminals and a high-voltage side control output terminal; wherein, the upper bridge arm signal input terminal is used to receive the upper bridge arm PWM control signal output by the peripheral main control board, the two high-voltage side power supply terminals are used to input two control signals corresponding to the upper and lower bridge arm switching tubes of one phase respectively, and the high-voltage side control output terminal is used to output a drive signal for driving the upper bridge arm switching tube of one phase.

4. The semiconductor circuit according to claim 3, wherein: The high-voltage driving unit includes a first Schmitt trigger, a first filtering circuit, a first potential shifting circuit, a first dead zone interlocking unit, a pulse generating circuit, a DV / DT filter circuit, a latch, a NOR logic gate, a UV filtering circuit, a first MOS transistor, a second MOS transistor, a first current limiting resistor, a second current limiting resistor and a first output driving circuit; Among them, the input end of the first Schmitt trigger is the upper bridge arm signal input end, the output end of the first Schmitt trigger is connected to the input end of the first filtering circuit; the output end of the first filtering circuit is connected to the input end of the first potential shift circuit; the output end of the first potential shift circuit is connected to the input end of the first dead zone interlocking unit; the output end of the first dead zone interlocking unit is connected to the input end of the pulse generating circuit; the output end of the pulse generating circuit is connected to the gate of the first MOS tube and the second MOS tube, the drain of the first MOS tube and the second MOS tube is connected to the input end of the DV / DT filter circuit, the drain of the first MOS tube is connected to the positive end of the high-voltage side power supply end through the first current limiting resistor, and the drain of the second MOS tube is connected to the positive end of the high-voltage side power supply end through the first current limiting resistor. The drain of the transistor is connected to the positive terminal of the high-voltage side power supply terminal through the second current limiting resistor, and the source of the first MOS transistor and the source of the second MOS transistor are commonly connected to the negative terminal of the high-voltage side power supply terminal; the output end of the DV / DT filter circuit is connected to the first input end of the latch, the output end of the UV filter circuit is connected to the second input end of the latch, and the input end of the UV filter circuit is connected to the positive terminal of the high-voltage side power supply terminal; the output end of the DV / DT filter circuit is connected to the first input end of the NOR logic gate, and the output end of the latch is connected to the second input end of the NOR logic gate; the output end of the NOR logic gate is connected to the input end of the first output drive circuit, and the output end of the first output drive circuit is the output end of the high-voltage drive unit.

5. The semiconductor circuit according to claim 4, wherein: The first output driving circuit includes: A third MOS tube and a fourth MOS tube; The gate of the third MOS transistor and the gate of the fourth MOS transistor are commonly connected to the input end of the first output drive circuit, the drain of the third MOS transistor is connected to the positive end of the high-voltage side power supply end, the source of the third MOS transistor and the drain of the fourth MOS transistor are commonly connected to the output end of the first output drive circuit, and the source of the fourth MOS transistor is connected to the negative end of the high-voltage side power supply end.

6. The semiconductor circuit according to claim 4, wherein: The low-voltage side drive circuit includes three identical low-voltage drive units, each of which includes a lower bridge arm signal input terminal, a low-voltage side power supply terminal, a low voltage reference terminal and a low-voltage side control output terminal; wherein, the lower bridge arm signal input terminal is used to receive the lower bridge arm PWM control signal output by the peripheral main control board, and the low-voltage side control output terminal is used to output a drive signal for driving a single-phase lower bridge arm switch tube.

7. The semiconductor circuit according to claim 6, wherein: The low-voltage driving unit includes a second Schmitt trigger, a second filtering circuit, a second potential shift circuit, a second dead zone interlocking unit, a delay circuit, a comparator, and a second output driving circuit; Among them, the input end of the second Schmitt trigger is the lower bridge arm signal input end, the output end of the second Schmitt trigger is connected to the input end of the second filtering circuit; the output end of the second filtering circuit is connected to the input end of the second potential shift circuit; the output end of the second potential shift circuit is connected to the input end of the second dead zone interlocking unit; the output end of the second dead zone interlocking unit is connected to the input end of the delay circuit; the output end of the pulse generating circuit and the delay circuit are connected to the input end of the comparator, the output end of the comparator is connected to the input end of the second output driving circuit, and the output end of the second output driving circuit is the output end of the low-voltage driving unit.

8. The semiconductor circuit according to claim 7, wherein: The second output driving circuit includes: a fifth MOS tube and a sixth MOS tube; The gate of the fifth MOS transistor and the gate of the sixth MOS transistor are commonly connected to the input end of the second output drive circuit, the drain of the fifth MOS transistor is connected to the low-voltage side power supply end, the source of the fifth MOS transistor and the drain of the sixth MOS transistor are commonly connected to the output end of the second output drive circuit, and the source of the sixth MOS transistor is grounded.

9. The semiconductor circuit according to claim 1, wherein: The undervoltage protection circuit further includes an encoder; The input end of the encoder is used to connect to the external processor of the semiconductor circuit; The encoder includes multiple outputs, and each output is connected to a negative input terminal of a detection comparator of a different voltage comparison circuit.

10. The semiconductor circuit according to claim 1, wherein The high-voltage integrated circuit further includes an over-temperature protection circuit, a short-circuit protection circuit and an over-current protection circuit.

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