Implementation methods and systems for L2 early wake-up of L1

Abstract

This invention relates to the field of CPU technology, specifically to a method and system for implementing L2 early wake-up of L1, comprising the following steps: allocating a load miss request to the CRQ, and having the load miss request participate in and win arbitration to be added to the pipeline; determining the specific situation of hit L2 or miss L2 in the pipeline, and generating a relevant allocation scheme; updating the L2 tag_ram data_ram and returning the data to the core; finally, dealing with the entry item corresponding to the outstanding request queue and ending the process. This invention allows L2 to wake up the LSU to the pipeline earlier. When a load instruction needs data in the pipeline, L2 has already sent the data to the LSU, meaning the load instruction can obtain the data when it needs it. This allows the load instruction to be added to the pipeline 4 cycles earlier, thereby effectively improving the overall performance of the CPU.

Description

TECHNICAL FIELD

[0001] The present application relates to the CPU technical field, specifically relates to a kind of L2 early wake-up L1 implementation method and system. BACKGROUND

[0002] In prior art, when L2 returns data to the reload request of lsu, if it is waited until the data has been returned to LSU, then go wakeup load instruction to re-enter the pipeline of lsu, it is very late, seriously affect the overall performance of CPU.

[0003] Since the data returned by reload does not improve the load instruction through bypass, it occupies the resource of accessing D_cache, and also affects the performance of CPU; At the same time, due to multiple accesses to D_cache, it causes unnecessary power consumption.

[0004] Therefore, the present application provides an L2 early wake-up L1 implementation method and system, which can early wakeup lsu pipeline, when load instruction needs data in pipeline, L2 can send data to LSU, that is, load instruction can get data when it needs, so that load instruction can be early several cycles in pipeline, thereby effectively improving the overall performance of CPU.

[0005] Since load is early in pipeline, load instruction obtains data through bypass at this time, thereby reducing the access to L1_cache, which can effectively access L1_cache for other pipeline, effectively improving the overall performance of CPU; At the same time, since D_cache does not need to be accessed, power consumption can be effectively reduced. SUMMARY

[0006] In view of the deficiencies of the prior art, the present application discloses an L2 early wake-up L1 implementation method and system to solve the above problems.

[0007] The present application is implemented by the following technical solutions:

[0008] In the first aspect, the present application provides an L2 early wake-up L1 implementation method, comprising the following steps:

[0009] S1 initialization is completed, and the load miss request is distributed to CRQ, and the load miss request is involved and won in arbitration, and is in pipeline;

[0010] S2 judges the specific case of hit L2 or miss L2 in the pipeline, and generates a relevant allocation scheme;

[0011] S3 updates the L2 tag_ram data_ram and returns data to the core;

[0012] S4 finally deallocates the entry item corresponding to the outstanding request queue, and ends the process;

[0013] If L2 is hit, the data is directly returned to the core, and the load instruction pipeline is awakened in advance a few beats, and L2 can provide data when the load instruction in L1 needs data.

[0014] If L2 is missed in the pipeline, allocate outstanding request queue, and deallocate the corresponding entry item in the core read queue, that is, if L2 is missed in the pipeline, outstanding request queue sends a reload request to the next level memory, and waits for the refill data.

[0015] After the lower level memory refills the data, it participates in and obtains the pipeline arbitration, at which time the data can be returned to the core, and the load instruction pipeline is awakened in advance a few beats, and L2 can provide data when the load instruction in L1 needs data.

[0016] Further, in the method, the L2 working includes the following steps:

[0017] T1 receives requests from the core and external extension, and receives requests from CRQ, CWQ, EPQ, ORQ, EFQ and CPQ, and selects one of them to enter the pipeline;

[0018] T2 generates a relevant allocation scheme according to the type of the request and the TAG information and MESI state information in the current L2;

[0019] T3 sends a read request or a write request to the downstream memory through L2, and returns reload data to refill the EFQ by the downstream memory;

[0020] T4 writes the data back from reload to L2$ through L2 de pipeline, and returns the data to the requesting core.

[0021] Further, in the method, L2 receives requests from cores and external extensions, including receiving read requests from cores and placing them in CRQs, receiving write requests from cores and placing them in CWQs, and receiving probe requests from external extensions and placing them in EPQs.

[0022] Further, in the method, in the pipeline, according to the type of the request, and the TAG information and the MESI state information in the current L2, it is determined whether the data can be directly written to L2, whether the data can be directly returned to the requester, whether the data or the authority needs to be reloaded to the downstream memory, whether eviction needs to be generated, whether the data needs to be written to the downstream memory, whether the core needs to be probed, if it is determined that the data or the authority needs to be reloaded to the downstream memory, an ORQ is allocated, if it is determined that the data needs to be written to the downstream memory, a WRQ is allocated, and if it is determined that the core needs to be probed, a CPQ is allocated, and the L2 sends a probe request to the core through the CPQ.

[0023] Further, in the method, a read request is sent to the downstream memory through the L2, and the data is read from the downstream memory through an ORQ, and the authority corresponding to the data is obtained, and a write request is sent to the downstream memory through the L2, and the data is written from the L2 to the next memory through a WRQ.

[0024] In a second aspect, the application provides an implementation system of L2 early wake-up L1, which is used for implementing the implementation method of L2 early wake-up L1 in the first aspect, and includes a probe, an eviction, a TAG RAM, a DATA RAM, a CRQ, a CWQ, an EPQ, an ORQ, a WRQ, an EFQ, and a CPQ.

[0025] Further, the probe is used for peeking and monitoring, and dirty data in the core is probed down or the MESI state information in the core is modified in order to obtain E authority.

[0026] The eviction is used for keeping the data saved in the cache relatively new, and is generated when the data needs to be replaced in the cache.

[0027] The TAG RAM is used for recording the addr of the cacheline and the MESI state information of the cacheline in L2 and all L2 COREs;

[0028] The DATA RAM is used for recording the data information of the cacheline;

[0029] The CRQ is a queue used for receiving read request from the core;

[0030] The CWQ is a queue used for receiving write request from the core;

[0031] The EPQ is a queue used for receiving probe request from the outside;

[0032] The ORQ is used for applying an ORQ to reload data from the next level memory and get the corresponding permission when a request in L2 is found to be not in the cache or the access permission of the cacheline in the cache is not enough after the L2 pipeline;

[0033] The WRQ is used for applying a WRQ to write data into the next level memory when L2 needs to write a cacheline to the next level memory;

[0034] The EFQ is used for writing data into the EFQ when reloading data to refill L2, and then writing the data into L2 through the pipeline of L2 and returning the data to the request module;

[0035] The CPQ is used for probing the corresponding core, and the probe request is first stored in the CPQ, and then the probe request is sent to the corresponding core through the CPQ.

[0036] The present application has the following advantages:

[0037] The L2 of the present application can wake up the pipeline of the LSU in advance, and when the load instruction needs data in the pipeline, the L2 has already sent the data to the LSU, that is, the load instruction can get the data when it needs, so that the load instruction can be pipelined several cycles in advance, thereby effectively improving the overall performance of the CPU.

[0038] The application reduces the access to L1_cache, effectively improves the access to L1_cache for other pipeline, and effectively improves the overall performance of CPU; meanwhile, since D_cache is not accessed, power consumption is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0040] Figure 1 is a basic block diagram of the L2 of the embodiment of the present application;

[0041] Figure 2 is a flow chart of an implementation method of the L2 early wake-up L1 of the embodiment of the present application;

[0042] Figure 3 is a timing chart of the load miss request, hit L2 of the embodiment of the present application;

[0043] Figure 4 is a timing chart of the load instruction not early wake-up lsu pipeline of the embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present application.

[0045] Embodiment 1

[0046] Referring to Figure 2 The embodiment provides an implementation method of L2 early wake-up L1, and the specific implementation is as follows:

[0047] The load miss request is distributed to the CRQ (core read queue);

[0048] CRQ (core read queue) will participate in the load miss request and win arbitration, and go up the pipeline;

[0049] In this embodiment, if L2 is hit, data can be returned directly to the core. Since reading data takes more than two cycles to complete, as long as it is confirmed that data can be returned to the core in the following cycles, the load instruction is woken up in advance and goes up the pipeline. When the load instruction in L1 needs data, L2 can provide the data.

[0050] In this embodiment, if L2 is missed in the pipeline, an outstanding request queue is allocated, and the corresponding entry in the core read queue is deallocated.

[0051] In this embodiment, the outstanding request queue sends a reload request to the next level memory and waits for the refill data.

[0052] In this embodiment, after the lower level memory refills the data, it participates in and wins the arbitration of the pipeline. At this time, data can be returned to the core. Similarly, the load instruction can be woken up in advance and go up the pipeline. When the load instruction in L1 needs data, L2 can provide the data.

[0053] The L2 tag_ram data_ram is updated to return data to the core, and the corresponding entry in the outstanding request queue is deallocated.

[0054] In this embodiment, L2 can wake up the lsu and go up the pipeline in advance. When the load instruction needs data in the pipeline, L2 has already sent the data to the LSU. That is, the load instruction can get the data when it needs it. In this way, the load instruction can go up the pipeline 4 cycles in advance, thereby effectively improving the overall performance of the CPU.

[0055] Embodiment 2

[0056] On other levels, the embodiment provides an L2 working mode, a block diagram of which is shown in Figure 1 The basic function is described as follows:

[0057] Receive requests from the core and external extensions, including:

[0058] Receive read request from core, put it in CRQ (core read queue);

[0059] Receive write request from core, put it in CWQ (core write queue);

[0060] Receive probe request from core, put it in EPQ (extend probe queue);

[0061] Arbitration module receives request from CRQ, CWQ, EPQ, ORQ, EFQ, CPQ, and selects one of them to enter the pipeline;

[0062] In the pipeline, according to the type of request, and the TAG information and MESI state information in the current L2, it is determined:

[0063] Whether it can be directly written into L2; whether it can directly return data to the requester; whether it needs to reload data or authority to the downstream memory; whether it needs to generate evict; whether it needs to write data to the downstream memory; whether it needs to probe the core, etc.

[0064] In this embodiment, if it is judged that data or authority needs to be reloaded to the downstream memory, an ORQ (outstanding request queue) is allocated.

[0065] In this embodiment, if it is judged that data needs to be written to the downstream memory, a WRQ (write request queue) is allocated.

[0066] In this embodiment, if it is judged that the core needs to be probed, a CPQ (core probe queue) is allocated, and the L2 sends a probe request to the core, which is completed through the CPQ (core probe queue).

[0067] L2 sends a request to the downstream memory:

[0068] Read request, send it through ORQ (outstanding request queue), read data from the downstream memory and get the authority corresponding to the data.

[0069] Write request, send it through WRQ (write request queue), write data from L2 to the next level of memory.

[0070] L downstream memory returns reload data to EFQ (Extend fill queue)

[0071] Then the EFQ (Extend fill queue) on L2de pipeline, write reload data back to L2$, and the core data return request.

[0072] Embodiment 3

[0073] This embodiment provides a protocol for maintaining data consistency in a memory system, indicating how the current core has the right to the cacheline, as follows:

[0074] M: modify, indicating that the core has modified the cacheline, and the cacheline only exists in the cache. If other caches need to access the cacheline, they need to get the latest dirty data and the corresponding rights through the probe.

[0075] E: Exclusive indicates that the cacheline only exists in the cache. If other caches need to access the cacheline, they need to get the corresponding data and rights through the probe.

[0076] S: Shared indicates that the cacheline not only exists in the cache, but also in other caches. If other caches need to access the cacheline and get E / M mode, they need to get the corresponding data and rights through the probe.

[0077] I: Invalid indicates that the cacheline does not exist in the cache.

[0078] Embodiment 4

[0079] In terms of specific implementation, this embodiment provides a load miss request, hit L2 timing, as shown in Figure 3 From the figure, we can see that:

[0080] (1) At T4, it is determined that the tag hit.

[0081] (2) Since the T4 tag hit, data will be returned to the core in the following, so at T5, the core can be awakened in advance with the missq_ldq_wakeup signal.

[0082] According to the pipeline of L2, it can be known that at T7, L2 can return data to the fill buffer of the lsu, at T8, the pipeline of the lsu can bypass data from the fill buffer, and according to the pipeline information of the load instruction in the lsu, it is determined that the awakened load instruction is pipelined at T6, and the bypass data is obtained at T9.

[0083] As shown in Figure 4 the timing diagram of not waking up the load instruction on the lsu pipeline in advance, it can be known from the diagram that:

[0084] (4) The tag hit is determined at T4.

[0085] (5) According to the pipeline of L2, it can be known that at T7, L2 can return data to the fill buffer of the lsu, at T8, the pipeline of the lsu can bypass data from the fill buffer.

[0086] (6) The load instruction on the lsu pipeline is awakened at T8, and according to the pipeline information of the load instruction in the lsu, the bypass data is obtained at T13.

[0087] Therefore, it can be seen that the load instruction on the lsu pipeline is awakened in advance in the scheme, which is 4 cycles earlier than awakening the load instruction on the lsu pipeline after obtaining the data.

[0088] Embodiment 5

[0089] The embodiment provides an implementation system for L2 waking up L1 in advance, and specifically comprises:

[0090] probe: probe, in a multi-core environment, for maintaining data consistency, dirty data in the core needs to be probed down through the probe, or the MESI state information in the core needs to be modified in order to obtain E permission.

[0091] eviction: due to the limited capacity of the cache, in order to keep the data saved in the cache relatively new, when the data in the cache needs to be replaced, eviction occurs.

[0092] TAG RAM: records the addr of the cacheline and the MESI state information of the cacheline in L2 and all L2 COREs.

[0093] DATA RAM: record data information of cacheline.

[0094] CRQ (core read queue): queue for receiving read request from core.

[0095] CWQ (core write queue): queue for receiving write request from core.

[0096] EPQ (extend probe queue): queue for receiving probe request from outside.

[0097] ORQ (outstanding request queue): when a request in L2 is found to be not in the cache or the access right of the cacheline in the cache is not enough after going through L2 pipeline, an ORQ is needed to reload data from lower level memory and get the corresponding right.

[0098] WRQ (write request queue): when L2 needs to write a cacheline to lower level memory, a WRQ is needed to write data into lower level memory.

[0099] EFQ (extend fill queue): when reloading data into L2, data is first written into EFQ, and then data is written into L2 through L2 pipeline and returned to the request module.

[0100] CPQ (core probe queue): since L2 is connected with multiple cores, the latest data required by a core may be in other cores or a core needs to get E / M right, at this time, the corresponding core needs to be probed, and the probe request is first stored in CPQ, and then the probe request is sent to the corresponding core through CPQ.

[0101] In summary, the present application can wake up the pipeline on the lsu in advance, when the load instruction needs data in the pipeline, L2 has already sent the data to the LSU, that is, the load instruction can get the data when it needs, so that the load instruction can be pipelined several cycles in advance, thereby effectively improving the overall performance of the CPU.

[0102] The application reduces the access to L1_cache and effectively improves the overall performance of CPU by advancing the load to the pipeline and obtaining data by bypassing the load instruction.

[0103] The above examples are only used to illustrate the technical solutions of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for implementing L2 early wake up of L1, the method comprising: The method comprises the following steps: S1 initialization is completed, a load miss request is allocated to a CRQ, and the load miss request participates in and wins arbitration, and is pipelined; S2 the specific situation of a hit L2 or a miss L2 in the pipeline is judged, and a related allocation scheme is generated; S3 L2 tag_ram data_ram is updated, and data is returned to the core; S4 finally, an entry item corresponding to an outstanding request queue is deallocated, and the process is ended; If the L2 is hit, the data is directly returned to the core, it is confirmed that the data can be returned to the core in the following several beats, the load instruction is woken up in advance for several beats, and the L2 can provide data when the load instruction of the L1 needs data; If the L2 is missed in the pipeline, an outstanding request queue is allocated, and a corresponding entry item in a core read queue is deallocated, that is, if the L2 is missed in the pipeline, the outstanding request queue sends a reload request to a next-level memory, and waits for refilling data; After the next-level memory refills the data, the data is returned to the core, the load instruction is woken up in advance for several beats, and the L2 can provide data when the load instruction of the L1 needs data.

2. The method of claim 1, wherein the L2 layer is configured to wake up the L1 layer in advance, and the L1 layer is configured to wake up the L2 layer in advance. In the method, when the L2 works, the following steps are included: T1 receives a request from a core and an external extension, receives a request from a CRQ, a CWQ, an EPQ, an ORQ, an EFQ and a CPQ, and selects one of the requests to enter a pipeline; T2 generates a related allocation scheme according to the type of the request, and TAG information and MESI state information in the current L2; T3 sends a read request or a write request to a downstream memory through the L2, and reload data is returned to the EFQ by the downstream memory; T4 writes the data returned by the reload into the L2$ through the de pipeline of the EFQ, and returns the data to the requesting core.

3. The method of claim 2, wherein the L2 layer is configured to send a message to the L1 layer to wake up the L1 layer before the L2 layer is scheduled to wake up. In the method, the L2 receives a request from a core and an external extension, which comprises receiving a read request from the core and placing the read request in a CRQ, receiving a write request from the core and placing the write request in a CWQ, and receiving a probe request from the outside and placing the probe request in an EPQ.

4. The implementation method of L2 early wake up L1 according to claim 2, characterized in that, In the method, in the pipeline, according to the type of the request, and the TAG information and the MESI state information in the current L2, it is determined whether the L2 can be directly written into the L2; Whether to return data directly to the requester; whether to reload data or permissions to the downstream memory; whether to generate eviction; whether to write data to the downstream memory; Whether to probe the core; if it is determined to reload data or permissions to the downstream memory, an ORQ is allocated; if it is determined to write data to the downstream memory, a WRQ is allocated; if it is determined to probe the core, a CPQ is allocated, and the L2 sends a probe request to the core, which is completed through the CPQ.

5. The method of claim 2, wherein the L2 early wake-up of the L1 is implemented by, In the method, when the L2 sends a read request to the downstream memory, the ORQ is used to read data from the downstream memory and obtain the permissions corresponding to the data; when the L2 sends a write request to the downstream memory, the WRQ is used to write data from the L2 to the next-level memory.

6. A system for implementing the L2-early-wakeup-Ll implementation method according to any one of claims 1-5, wherein The probe, eviction, TAG RAM, DATA RAM, CRQ, CWQ, EPQ, ORQ, WRQ, EFQ and CPQ are included.

7. The system for implementing L2 early wake up L1 according to claim 6, wherein, The probe is used for peeking and monitoring, and the dirty data in the core is probed down or the MESI state information in the core is modified to obtain E permissions. The eviction is used to keep the data stored in the cache relatively new, and is generated when the data needs to be replaced in the cache. The TAG RAM is used to record the addr of the cacheline and the MESI state information of the cacheline in the L2 and all L2 COREs. The DATA RAM is used to record the data information of the cacheline. The CRQ is a queue used to receive read requests from the core. The CWQ is a queue used to receive write requests from the core. The EPQ is a queue used to receive probe requests from the outside. The ORQ is used to apply for an ORQ when a request in the L2 is found to be not in the cache or the access permissions of the cacheline in the cache are not enough after the L2 pipeline is sent, and reload data from the next-level memory and obtain the corresponding permissions through the ORQ. The WRQ is used to apply for a WRQ when the L2 needs to write a cacheline to the next-level memory, and write data into the next-level memory through the WRQ. The EFQ is used to write data into the EFQ when the data is backfilled into the L2, and then write the data into the L2 through the pipeline of the L2 and return the data to the request module. The CPQ is used to probe the corresponding core, and the probe request is first stored in the CPQ, and then the probe request is sent to the corresponding core through the CPQ.

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