Speculative instruction wake up to tolerate drain delay of memory violation ordering check buffer

Abstract

A technique for speculatively executing load-dependent instructions includes detecting that a memory sorting consistency queue is full for a completed load instruction. The technique further includes storing data loaded by the completed load instruction into a storage location when the memory sorting consistency queue is full. The technique also includes speculatively executing instructions dependent on the completed load instruction. The technique further includes replaying the load instruction in response to a time slot becoming available in the memory sorting consistency queue. The technique further includes testing for incorrect speculation of data by comparing the load data for the replayed load instruction with the data loaded by the completed load instruction stored in the storage location in response to receiving load data for the replayed load instruction.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. non-provisional application No. 16 / 671,097, filed October 31, 2019, and U.S. provisional patent application serial number 62 / 828,861, filed April 3, 2019, the contents of which are incorporated herein by reference.

[0003] Statement on Government Interests

[0004] This invention was made with government support under the PathForward project (primary contract number DE-AC52-07NA27344, subcontract number B620717) granted by the DOE to the Lawrence Livermore National Security Agency of the United States. The government enjoys certain rights in this invention. Background Technology

[0005] Out-of-order processors execute instructions out of order, but adhere to certain constraints to ensure execution occurs as specified by the program. One type of constraint involves ensuring adherence to certain memory ordering semantics. While relaxing constraints related to memory ordering semantics can improve performance, additional steps are required to ensure correct execution. Attached Figure Description

[0006] A more detailed understanding can be obtained from the following description, which is given by way of example in conjunction with the accompanying drawings:

[0007] Figure 1 It is a block diagram of an exemplary apparatus in which one or more of the disclosed embodiments may be implemented;

[0008] Figure 2 It is based on an example located at Figure 1 A block diagram of the instruction execution pipeline within the processor;

[0009] Figure 3A An exemplary operation is shown for triggering speculative execution of instructions that depend on load instructions that are eligible to be placed in a full memory consistency sorting queue;

[0010] Figure 3B Exemplary operations are shown in response to a load instruction that was previously full in such a queue, when the time slot becomes idle in the memory ordering consistency queue; and

[0011] Figure 4 This is a flowchart of a method for speculatively executing load instructions that depend on a full memory sorting consistency queue, based on an example. Detailed Implementation

[0012] A technique is provided for speculatively executing load-dependent instructions. The technique includes detecting that a memory sorting consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location when the memory sorting consistency queue is full. The technique further includes speculatively executing instructions that depend on the completed load instruction. The technique also includes replaying the load instruction in response to a time slot becoming available in the memory sorting consistency queue. The technique further includes testing for incorrect speculation of data by comparing the load data for the replayed load instruction with the data loaded by the completed load instruction stored in the storage location in response to receiving load data for the replayed load instruction.

[0013] A processor subsystem is provided for speculatively executing load-dependent instructions. The processor subsystem includes a memory sorting consistency queue and a load / store unit. The load / store unit detects that the memory sorting consistency queue is full for a completed load instruction; when the memory sorting consistency queue is full, it writes data loaded by the completed load instruction to a storage location for storing the data; it allows speculative execution of instructions dependent on the completed load instruction; in response to a time slot becoming available in the memory sorting consistency queue, it replays the load instruction; and in response to receiving load data for the replayed load instruction, it tests for incorrect speculation of the data by comparing the load data for the replayed load instruction with the data loaded by the completed load instruction stored in the storage location.

[0014] A processor is provided for speculatively executing load-dependent instructions. The processor includes a memory sorting consistency queue, a load / store unit, and one or more functional units. The load / store unit detects that the memory sorting consistency queue is full for a completed load instruction; when the memory sorting consistency queue is full, it writes data loaded by the completed load instruction to a storage location for storing the data; allows speculative execution of instructions dependent on the completed load instruction; replays the load instruction in response to a time slot becoming available in the memory sorting consistency queue; and tests for data error speculation by comparing the load data for the replayed load instruction with the data loaded by the completed load instruction stored in the storage location in response to receiving load data for the replayed load instruction. The one or more functional units speculatively execute the instructions dependent on the completed load instruction.

[0015] Figure 1This is a block diagram of an exemplary device 100 that implements various aspects of the present disclosure. Device 100 includes, for example, a computer, gaming device, handheld device, set-top box, television, mobile phone, or tablet computer. Device 100 includes a processor 102, memory 104, storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 may also optionally include an input driver 112 and an output driver 114. It should be understood that device 100 may include... Figure 1 Additional components not shown.

[0016] Processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU on the same die, or one or more processor cores, wherein each processor core is a CPU or a GPU. Memory 104 may be located on the same die as processor 102 or may be located separately from processor 102. Memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or cache.

[0017] Storage device 106 includes fixed or removable storage devices, such as hard disk drives, solid-state drives, optical disk drives, or flash drives. Input device 108 includes a keyboard, keypad, touchscreen, touchpad, detector, microphone, accelerometer, gyroscope, biometric scanner, or network connectivity (e.g., a wireless LAN card for transmitting and / or receiving wireless IEEE 802 signals). Output device 110 includes a display, speaker, printer, haptic feedback device, one or more lights, antenna, or network connectivity (e.g., a wireless LAN card for transmitting and / or receiving wireless IEEE 802 signals).

[0018] Input driver 112 communicates with processor 102 and input device 108, and allows processor 102 to receive input from input device 108. Output driver 114 communicates with processor 102 and output device 110, and allows processor 102 to send output to output device 110. It should be noted that input driver 112 and output driver 114 are optional components, and device 100 will operate in the same manner even without input driver 112 and output driver 114.

[0019] Figure 2 It is based on an example located at Figure 1 A block diagram of the instruction execution pipeline 200 within the processor 102. The instruction execution pipeline 200 retrieves instructions from memory and executes them, outputs data to memory, and modifies the state of elements within the instruction execution pipeline 200, such as registers in register file 218.

[0020] The instruction execution pipeline 200 includes an instruction fetch unit 204 that fetches instructions from system memory (such as memory 104) via an instruction cache 202; a decoder 208 that decodes the fetched instructions; a function unit 216 that performs computations to process the instructions; a load / store unit 214 that loads data from system memory or stores data to system memory via a data cache 220; and a register file 218 that includes registers storing working data for the instructions. A reordering buffer 210 tracks currently in-process instructions and, while allowing out-of-order execution in flight, also ensures that instructions are retired in order. "In-flight" instructions refer to those that have been received by the reordering buffer 210 but whose architectural state (e.g., writing non-speculatory results to the register file, etc.) has not yet been committed to the processor. A reservation station 212 maintains instructions waiting to be executed on function unit 216 and tracks instruction operands. When all operands are ready to execute a specific instruction, the reservation station 212 sends the instruction to function unit 216 or load / store unit 214 for execution. Completed instructions are marked as retired in reorder buffer 210 and retired when they are at the beginning of reorder buffer queue 210. Retirement refers to the act of committing the result of an instruction to the processor's architectural state. Examples of instruction retirement include writing the result of an addition instruction to the latest non-speculative copy of the architectural register via an addition instruction; writing the loaded value to the latest non-speculative copy of the architectural register via a load instruction; or non-speculatively jumping the instruction flow to a new location via a branch instruction.

[0021] The various components of the instruction execution pipeline 200 communicate via a common data bus 222. For example, functional unit 216 and load / store unit 214 write results to the common data bus 222, which can be read by the reservation station 212 to execute dependent instructions; and read by the reordering buffer 210 as the final processing result of an ongoing instruction that has been completed. Load / store unit 214 also reads data from the common data bus 222. For example, load / store unit 214 reads the result of a completed instruction originating from the common data bus 222 and writes the result to memory via data cache 220 for storing instructions.

[0022] Instruction execution pipeline 200 is capable of executing load instructions and store instructions (as well as other instructions). Load instructions load data from memory and place that data into registers in register file 218. Store instructions store data from registers to memory locations. For both store and load, the specified address is calculated based on the contents of one or more registers and / or one or more values ​​specified in the instruction itself. Furthermore, for loads or stores specifying virtual memory addresses, those addresses are translated into physical addresses.

[0023] Load / store unit 214 supports a memory consistency model that specifies the relative order of execution of loads and stores as observed by the software. In the example, load / store unit 214 implements a load order consistency model, where load instructions appear to the software as being executed sequentially with respect to load instructions from other threads. Specifically, this load order memory consistency model operates as follows: Reservation station 212 issues load instructions to functional unit 216 to generate virtual addresses (e.g., computes virtual addresses in the manner specified by the load instructions). Functional unit 216 then transmits the load instructions to load / store unit 214, which executes the load instructions to fetch translations to physical addresses from data translation back buffer (“TLB”) 226 and fetch data based on physical addresses from data cache 220. In some implementations, load / store unit 214 stores loads in load queue 224 in response to dispatching load instructions from decoder 208 to reorder buffer 210. In other implementations, loads are placed in load queue 224 at any other technically feasible time.

[0024] A load instruction is considered complete when the data requested by it is returned. However, the reordering buffer 210 will not mark a load instruction as eligible for retirement until a memory consistency violation has been detected. If a memory consistency model violation occurs for a load instruction, the load / store unit 214 flushes the load instruction (and in various cases, instructions newer than the load instruction) from the instruction pipeline 200 and replays the load instruction. In some implementations, two types of violations are possible: violations of load-to-load ordering and violations of store-to-load ordering.

[0025] The definition of load-to-load ordering depends on the ordering rules imposed by the memory coherence model. In some implementations, memory ordering requires all loads to appear to be executed in program order, regardless of whether the loads access the same address. Load-to-load ordering is enforced by checking whether loads observe the same values ​​as each other when they become eligible to be deselected in program order. This enforcement is achieved by monitoring external probes to data cache 220 and evicting from data cache 220. If an external probe to address (“A”) reaches data cache 220 and there is an instruction to read from address A in load ordering queue 228, then the oldest such instruction in load ordering queue 228 is determined to have experienced a load-to-load ordering violation. If the load instruction at address A is evicted from data cache 220 before becoming the oldest load in reordering buffer 210, then that instruction has experienced a load-to-load ordering violation. In the event of a load-to-load order violation for a load instruction, the load / store unit 214 flushes and replays the load instruction from the instruction execution pipeline 200.

[0026] Store-to-load ordering is a memory ordering rule that requires all loads to receive data from store operations in a manner specified by program order (i.e., the order in which instructions are assumed to be executed based on the control flow of the software executing those instructions). Because the instruction execution pipeline 200 can execute instructions, including load and store instructions, out of order, store-to-load ordering is enforced among instructions in the same thread to prevent load instructions from consuming stale data.

[0027] To enforce memory ordering rules in an out-of-order processor (e.g., processor 102), instruction pipeline 200 is allowed, and sometimes does execute, load and store instructions out of order. When a load instruction completes but is not yet ready to retire, instruction pipeline 200 monitors the load instruction for violations of one or more memory ordering rules. When a memory ordering violation is unlikely for that load instruction, the load instruction is ready to retire. It is also possible for a load instruction to complete and be ready to retire simultaneously; in this case, no memory ordering rule violation is checked. In the event of a violation, the load instruction is flushed and replayed from pipeline 200. Depending on the replay mechanism, other instructions, such as those newer than the load instruction, are also flushed. In the event of no violation, the load instruction is allowed to retire, meaning the result of the load instruction is committed to the architectural state of instruction pipeline 200. Some exemplary techniques for checking for violations are as follows.

[0028] In some examples, violations of the load-to-load order are checked as follows: In response to a load instruction completing and that load instruction is not the oldest load instruction to be placed in the load order queue 228, the load / store unit 214 removes the instruction from the load queue 224 and places it in the load order queue 228. If, when the load instruction completes, it is the oldest load instruction to be placed in the load order queue 228, then the load / store unit 214 removes the instruction from the load queue 224 and does not place it in the load order queue 228.

[0029] When a load instruction is in load sorting queue 228, load / store unit 214 monitors cache lines in the lowest-level cache (e.g., L1 cache) storing the load data. Load / store unit 214 determines a load-to-load order violation has occurred if either a cache line is evicted from the cache (e.g., due to replacement by a different cache line) or a cache line is accessed by a thread different from the thread executing the load instruction (wherein the access is identified by a probe received at the cache). If the violation occurs before load instructions are no longer monitored in load sorting queue 228, load / store unit 214 removes the load instruction from load sorting queue 228. If the load instruction is the oldest load instruction for that thread in both load sorting queue 228 and load queue 224, load instructions are no longer monitored in load sorting queue 228.

[0030] In some examples, violations of the store-to-load ordering are checked as follows: In response to a load instruction completing and being eligible for placement in the out-of-order buffer 230, the load / store unit 214 places the load instruction in the out-of-order buffer 230. The load instruction is eligible for placement in the out-of-order buffer 230 if it is likely to commit a violation of the store-to-load ordering rules. This violation can occur if there is at least one older store instruction than the load instruction, where the load / store unit 214 has not yet determined the physical address for that older store instruction. If the load instruction is eligible for placement in the out-of-order buffer 230, the load / store unit 214 will not place the load instruction in the out-of-order buffer 230.

[0031] While in the out-of-order buffer 230, the load / store unit 214 checks for violations of the store-to-load ordering rules as follows: When determining the physical address for a store instruction older than the load instruction, the load / store unit 214 compares that physical address with the physical address of the load instruction. If a match is found, the load / store unit 214 determines that a violation has occurred; if no match is found, the load / store unit 214 determines that no violation will occur for that store instruction. In response to the absence of any more store instructions older than the load instruction whose physical address has not yet been determined, the load / store unit 214 determines that no further violation is possible for that load instruction and removes the load instruction from the out-of-order buffer 230.

[0032] If both load-to-load and store-to-load ordering are to be enforced, a load instruction will not be deprecated even if it is removed from one of the load ordering queues 228 or out-of-order buffer 230 if it is still in one of those queues. In this case, the load instruction is deprecated if it is no longer in either queue. Alternative or additional memory ordering rules, each with its own queue, can also be used. In this case, the load instruction is deprecated in response to the fact that it is not present in all such queues. The load ordering queue, out-of-order buffer, and / or any other queue used for memory consistency model verification are referred to herein as memory consistency ordering queue 232.

[0033] In some cases, one or more of the memory consistency sorting queues 232 become full. If a load instruction completes and is eligible to be placed in the memory consistency sorting queue 232, but that queue is full, the load instruction will not be placed in that queue. In that case, the load instruction remains in the load queue 224 until a time slot becomes available in the full memory consistency sorting queue 232. Such load instructions are sometimes referred to herein as load instructions waiting for a time slot in the memory consistency sorting queue 232 to become available.

[0034] In one technique, when a load instruction is waiting for a slot in the memory coherence queue to become idle, no load-dependent instructions are issued for execution. If an instruction consumes data loaded by the load instruction (as an operand), then that instruction depends on the load instruction. This technique is "simple" because it does not require special steps to identify whether a memory ordering violation has occurred for load-dependent instructions. More specifically, such instructions are not executed at all, meaning there is no need to detect such violations. However, performance improvements can be achieved by speculatively executing such dependent instructions and using mechanisms for detecting memory ordering violations.

[0035] Figure 3A An exemplary operation is shown for triggering speculative execution of an instruction that depends on a load instruction eligible to be placed in a full memory consistency sorting queue 232. Load / store unit 214 receives a load instruction 301 for execution and places it in load queue 224. Load / store unit 214 performs address calculation 302 as specified by load instruction 301. Address calculation 302 involves calculating an address from which data is to be loaded based on an operation or operand explicitly or implicitly specified by load instruction 301. If load instruction 301 requires address translation (e.g., because load instruction 301 specifies a virtual address), then at operation 304, load / store unit 214 requests address translation from data TLB 226, and at operation 306, data TLB 226 returns the translated address. In operation 308, load / store unit 214 requests data at the address from data cache 220, and in operation 310, data cache 220 returns the requested data. At this point, the load instruction is considered complete. However, because load / store unit 214 executes memory instructions out of order, it checks for violations of memory sorting rules. As described elsewhere in this document, if a load instruction is eligible to be placed in at least one memory sorting consistency queue 232, load / store unit 214 attempts to place the load instruction in such a queue.

[0036] However, in Figure 3A During the operation, queue 232 is full. Therefore, at operation 312, load / store unit 214 detects that at least one of the memory sorting queues 232 where load instructions are to be placed is full. As described elsewhere in this document, not all load instructions are placed in every memory sorting queue 232. Discussions regarding when to place or not place load instructions in memory sorting queues 232 are provided elsewhere in this document. Generally, load instructions are placed in memory sorting queues 232 when there is a possibility of violating the type associated with that queue. Load instructions are not placed in memory sorting queues 232 when it is no longer possible to violate that type. Operation 312 involves load / store unit 214 detecting that at least one memory sorting queue 232 where load instructions are to be placed is full.

[0037] In response to detection 312, load / store unit 214 retains load instruction 301 in load queue 214, and in operation 314, stores the data retrieved from data cache 220 to a storage location used for retrieving the data. In one example, the storage location is register file 218. In another example, the storage location is memory 320 used for temporary storage of such loaded data. Load / store unit 214 then uses the data stored at the storage location used for retrieving the data to check for violations of data speculation for load dependency instructions used for speculative execution. Using register file 218 as the storage location provides the following advantages: no additional cost (in terms of chip area) is incurred in checking for data speculation violations, and additionally, if the port of register file 218 allocated to the load instruction to be placed in memory ordering consistency queue 232 is read / write, the port can be used "freely" for checking for violations.

[0038] Figure 3B An exemplary operation is shown in response to a load instruction whose queue 232 was previously full, when the time slot becomes idle in the memory sorting queue 232. In some implementations, an event occurs in response to the time slot becoming idle in all memory sorting queues 232 where the load instruction is waiting. Figure 3B The operation. In other implementations, each time slot becomes idle in one of the memory sorted consistency queues 232 where load instructions are waiting. Figure 3B Then the operation will occur. Typically, Figure 3B The operation demonstrates a check for data error speculation in load-dependent instructions that are held in load queue 224 because memory sorting consistency queue 232 is full.

[0039] At operation 330, load / store unit 214 replays load instruction 301. This replay involves fetching data from data cache 220. At operation 332, load / store unit 214 compares the data retrieved for the replayed load instruction with the data stored in the memory location used to retrieve the data from the original load instruction. If the data are the same, no data error guessing has occurred for instructions that depend on the load instruction, and load / store unit 214 does not flush the pipeline or replay the load instruction. If the data are different, a data error guessing has occurred, and load / store unit 214 flushes the instruction pipeline 200 for at least the load instruction and load-dependent instructions, and replays the load instruction.

[0040] If the data is identical in operation 332, and it is still necessary to check whether the load instruction violates the memory sorting rules, then the load / store unit 214 stores the load instruction in a now-idle time slot in the memory sorting consistency queue 232. The load / store unit 214 uses this time slot to check for such a violation at a later time, as described elsewhere herein. The violation checked is a violation of the type of load instruction associated with a queue 232 that has become idle. For example, if a load instruction is waiting for a time slot in the load sorting queue 228, the violation to be checked is a violation of the load-to-load sorting.

[0041] It is possible that when comparison 332 completes, it is not necessary to check whether the load instruction violates the memory ordering rules for queue 232, and the time slot becomes idle for queue 232 (e.g., because the load instruction will be the oldest load instruction in queue 232, or all older memory instructions already have their calculated physical addresses and none of them conflict with the load instruction). In that case, the load instruction is not placed in queue 232. If the load instruction is not residing in load queue 224 or any memory ordering consistency queue 232 at this time, the load instruction is ready to retire.

[0042] Figure 4 This is a flowchart of a method 400 for speculatively executing load instructions that depend on a full memory sorting consistency queue, based on an example. Although related to... Figures 1 to 3B The system described herein, however, will be understood by those skilled in the art that any system configured to perform the steps of method 400 in any technically feasible order falls within the scope of this disclosure.

[0043] Method 400 begins at step 402, where a load instruction completes and the memory sorting consistency queue 232, which is eligible for the load instruction to be placed, is full. The load instruction completes when the data requested by the load instruction has been returned to the load / store unit 214. Load instructions already in the load queue 224 remain there. In step 404, the load / store unit 214 places the loaded data in the storage location used for loading data when the memory sorting consistency queue 232 is full. As described elsewhere herein, in one example, this storage location is register file 218, and in another example, it is temporary load data storage memory 320.

[0044] In step 406, instruction pipeline 200 speculatively executes load-dependent instructions that depend on the load instructions discussed in step 402. Load-dependent instructions are instructions that consume values ​​loaded by load instructions (as operands) or that depend on other load-dependent instructions. These instructions are executed speculatively because it cannot be determined that the values ​​they consume are correct; this is because the load instructions may be determined to have violated memory ordering rules.

[0045] In step 408, in response to a time slot becoming available in a full memory sorting consistency queue 232, load / store unit 214 replays the load instruction to fetch data again. In step 410, load / store unit 214 tests for data error speculation against speculatively executed load-dependent instructions by comparing the data loaded by the replayed load instruction with the data from the original executed load instruction stored in a storage location for data loaded when memory sorting consistency queue 232 was full. This test includes comparing the value used for the replayed load with the value in the storage location. If the values ​​are different, an error speculation occurs, and the load instruction, load-dependent instructions, and replayed load instruction are refreshed. If the values ​​are the same, no error speculation occurs.

[0046] If no data error speculation occurs, load / store unit 214 moves the load instruction to a previously full and now available memory sorting consistency queue 232. While in this memory sorting consistency queue 232, load / store unit 214 monitors whether the load instruction violates the memory sorting rules associated with that queue 232. Several exemplary techniques for testing such violations are described herein. If no violation occurred while the load instruction was in queue 232 and if it is determined that no violation will occur, the load instruction leaves the queue (e.g., the load instruction becomes the oldest load instruction in queue 232 or there are no longer any memory instructions older than the load instruction whose physical address has not yet been determined). If the load instruction is no longer in any memory sorting consistency queue 232, the load instruction becomes ready to retire.

[0047] As used herein, the term "instruction" can refer to architectural instructions or micro-operations generated by decoder stage 208 or other stages of instruction pipeline 200. It is well known that architectural instructions specified by the instruction set architecture are sometimes executed by the instruction pipeline as multiple separate micro-operations.

[0048] When declaring that data is being retrieved from the cache, it should be understood that the data may not exist in the cache at the time of the request, and in response to such a request, the cache may request the data from a higher level in the hierarchy, which ultimately provides the data to the original cache.

[0049] It should be understood that many variations are possible based on the disclosure herein. Although features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements.

[0050] The various elements described herein are implemented as circuits performing the functions described herein, software executing on a processor, or a combination thereof. Figure 1 In this document, processor 102 is a computer processor that performs the operations described herein. Input driver 112, output driver 114, input device 108, and output device 110 are software, hardware, or a combination thereof that execute on one or more processors. The various elements of instruction pipeline 200 are hardware circuits.

[0051] The provided method can be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, for example, general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), any other type of integrated circuit (IC), and / or state machines. Such processors can be manufactured by configuring the manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data, including netlists (such instructions can be stored on a computer-readable medium). The result of such processing can be a mask, which is then used in the semiconductor manufacturing process to manufacture processors that implement various aspects of the implementation scheme.

[0052] The methods or flowcharts provided herein can be implemented in a computer program, software, or firmware incorporated in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media, and optical media (such as CD-ROMs and DVDs).

[0053] ***

Claims

1. A method for speculatively executing load dependency instructions, comprising: The detection indicates that the memory sorting consistency queue is full for the completed load instruction; When the memory sorting consistency queue is full, the data loaded by the completed load instruction will be stored in the storage location used for storing data. Speculatively execute instructions that depend on the completed load instructions; In response to a time slot becoming available in the memory ordering consistency queue, the load instruction is replayed; as well as In response to receiving load data for replay of the load instruction, error speculation of the data is tested by comparing the load data for replay of the load instruction with the data loaded by the completed load instruction stored in the storage location.

2. The method of claim 1, further comprising: In response to determining that the load data for the load instruction used for replay is the same as the data loaded by the completed load instruction, it is determined that no violation of the memory sorting rule has occurred.

3. The method of claim 2, further comprising: Remove the load instruction from the load queue; The load instruction is stored in the memory sorting consistency queue; as well as For each load instruction in the memory order consistency queue, test whether it violates the memory order consistency rule.

4. The method of claim 1, further comprising: In response to determining that the load data for the load instruction used for replay is different from the data loaded by the completed load instruction, a violation of the memory order consistency semantics is determined.

5. The method of claim 4, further comprising: In response to the aforementioned violation, the loading instruction is refreshed and replayed.

6. The method of claim 1, wherein the instructions dependent on the completed load instruction include instructions that consume the data loaded by the completed load instruction.

7. The method of claim 1, wherein the memory sorting rule includes a load-to-load sorting rule.

8. The method of claim 1, wherein the memory sorting rule includes a sorting rule for storage to loading.

9. The method of claim 1, wherein: The storage location includes one of the following: a register in a register file, which is the destination register of the completed load instruction; and a memory dedicated to storing load data for testing whether memory ordering consistency semantics are violated for load-dependent instructions.

10. A processor subsystem for speculatively executing load-dependent instructions, the processor subsystem comprising: Memory-ordered consistency queue; as well as Load / store unit, the load / store unit being configured as follows: The detection indicates that the memory sorting consistency queue is full for the completed load instruction; If the memory sorting consistency queue is full, the data loaded by the completed load instruction will be stored in the storage location used for storing the data. Allows speculative execution of instructions that depend on the completed load instructions; In response to a time slot becoming available in the memory ordering consistency queue, the load instruction is replayed; as well as In response to receiving load data for replay of the load instruction, error speculation of the data is tested by comparing the load data for replay of the load instruction with the data loaded by the completed load instruction stored in the storage location.

11. The processor subsystem of claim 10, wherein the load / store unit is further configured to: In response to determining that the load data for the load instruction used for replay is the same as the data loaded by the completed load instruction, it is determined that no violation of the memory sorting rule has occurred.

12. The processor subsystem of claim 11, wherein the load / store unit is further configured to: Remove the load instruction from the load queue; The load instruction is stored in the memory sorting consistency queue; and For each load instruction in the memory order consistency queue, test whether it violates the memory order consistency rule.

13. The processor subsystem of claim 10, wherein the load / store unit is further configured to: In response to determining that the load data for the load instruction used for replay is different from the data loaded by the completed load instruction, a violation of the memory order consistency semantics is determined.

14. The processor subsystem of claim 13, wherein the load / store unit is further configured to: In response to the aforementioned violation, the loading instruction is refreshed and replayed.

15. The processor subsystem of claim 10, wherein the instructions dependent on the completed load instruction include instructions that consume the data loaded by the completed load instruction.

16. The processor subsystem of claim 10, wherein the memory sorting rule includes a load-to-load sorting rule.

17. The processor subsystem of claim 10, wherein the memory sorting rule includes a storage-to-load sorting rule.

18. The processor subsystem of claim 10, wherein: The storage location includes one of the following: a register in a register file, which is the destination register of the completed load instruction; and a memory dedicated to storing load data for testing whether memory ordering consistency semantics are violated for load-dependent instructions.

19. A processor for speculatively executing load-dependent instructions, the processor comprising: Memory-ordered consistency queue; Load / store unit, the load / store unit being configured as follows: The detection indicates that the memory sorting consistency queue is full for the completed load instruction; When the memory sorting consistency queue is full, the data loaded by the completed load instruction will be stored in the storage location used for storing data. Allows speculative execution of instructions that depend on the completed load instructions; In response to a time slot becoming available in the memory ordering consistency queue, the load instruction is replayed; as well as In response to receiving load data for replay of the load instruction, error speculation of the data is tested by comparing the load data for replay of the load instruction with the data loaded by the completed load instruction stored in the storage location. as well as One or more functional units, the one or more functional units being configured to speculatively execute the instructions that depend on the completed load instructions.

20. The processor of claim 19, wherein the memory sorting rule includes one of a load-to-load sorting rule and a storage-to-load sorting rule.

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