Semiconductor structure with bulk contact region embedded in polycrystalline semiconductor material

Abstract

This invention relates to a semiconductor structure having a main contact region embedded in a polycrystalline semiconductor material, and discloses a main contact semiconductor structure and a method for forming the main contact semiconductor structure. A semiconductor substrate comprising a single-crystal semiconductor material includes a device region and a plurality of main contact regions, each main contact region being composed of a single-crystal semiconductor material. A polycrystalline layer and polycrystalline regions are formed in the semiconductor substrate. The polycrystalline regions are located between the polycrystalline layer and the device region, and the polycrystalline regions are arranged with lateral spacing, with gaps between adjacent pairs of polycrystalline regions. One of the plurality of main contact regions is disposed in the gap between adjacent pairs of polycrystalline regions.

Description

Technical Field

[0001] This invention relates to semiconductor device manufacturing and integrated circuits, and more specifically, to a body contact semiconductor structure and a method for forming a body contact semiconductor structure. Background Technology

[0002] Semiconductor device structures, such as high-voltage power electronic devices, are susceptible to high capacitance and body-to-body leakage when formed using bulk semiconductor wafers. One possible measure to reduce sensitivity is to provide triple-well isolation around the active regions containing the device structure within the bulk semiconductor wafer. Another measure to reduce sensitivity is to replace the bulk wafer with a silicon-on-insulator (SiI) wafer, where a thin silicon layer provides the active regions, and a buried oxide layer is disposed between the active regions and the substrate beneath the buried oxide layer.

[0003] Due to the requirements of maximum power handling capability (Pmax) and linearity specifications for the body contact, groups or stacks of switch field-effect transistors may encounter limitations in scaling up their width. As the width increases, the body voltage may become unevenly distributed across the switch field-effect transistors in the group.

[0004] There is a need for improved host contact semiconductor structures and methods for forming host contact semiconductor structures. Summary of the Invention

[0005] In one embodiment of the present invention, a structure includes a semiconductor substrate made of a single-crystal semiconductor material. The semiconductor substrate includes a device region and a plurality of body contact regions, each of the body contact regions being made of the single-crystal semiconductor material. The structure includes a polycrystalline layer and a plurality of polycrystalline regions in the semiconductor substrate. The plurality of polycrystalline regions are located between the polycrystalline layer and the device region, and the plurality of polycrystalline regions are arranged with lateral spacing, with gaps between adjacent pairs of the plurality of polycrystalline regions. One of the plurality of body contact regions is disposed in the gap between adjacent pairs of the plurality of polycrystalline regions.

[0006] In one embodiment of the present invention, a method includes forming a polycrystalline layer in a semiconductor substrate made of a single-crystal semiconductor material, and forming a plurality of polycrystalline regions in the semiconductor substrate. The semiconductor substrate includes a device region and a plurality of body contact regions, each of the body contact regions being made of the single-crystal semiconductor material. The plurality of polycrystalline regions are located between the polycrystalline layer and the device region, the plurality of polycrystalline regions being laterally spaced, with gaps between adjacent pairs of the plurality of polycrystalline regions, and one of the plurality of body contact regions being disposed in the gap between the adjacent pairs of the plurality of polycrystalline regions. Attached Figure Description

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the respective embodiments of the invention. In the drawings, the same reference numerals denote the same features in various views.

[0008] Figures 1 to 3 This is a cross-sectional view of the structure of the continuous manufacturing stage of the processing method according to an embodiment of the present invention.

[0009] Figure 4 for Figure 3 A top-down view of the structure during the subsequent manufacturing phase.

[0010] Figure 5 For along Figure 4 5-5 is a cross-sectional view.

[0011] Figure 5A For along Figure 4 Cross-sectional view of 5A-5A.

[0012] Figure 5B For along Figure 4 Cross-sectional view of 5B-5B.

[0013] Figure 6 , Figure 6A , Figure 6B for Figure 5 , Figure 5A , Figure 5B Cross-sectional view of the structure during the subsequent manufacturing stage.

[0014] Figure 7 , Figure 7A , Figure 7B for Figure 6 , Figure 6A , Figure 6B Cross-sectional view of the structure during the subsequent manufacturing stage.

[0015] Figure 8 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention.

[0016] Explanation of main component symbols

[0017] 10 Semiconductor substrate

[0018] 12 Top surface

[0019] 14 Injection Layer

[0020] 15 Lower Boundary

[0021] 16 Undamaged areas

[0022] 18 polycrystalline layers

[0023] 20 Upper Boundary

[0024] 22 Lower Boundary

[0025] 24 Recrystallized single crystal layer

[0026] 25 Shallow trench isolation area

[0027] 26 Shallow trench isolation area

[0028] 28 Injection Area

[0029] 30 Injection Mask

[0030] 32 Non-injection region

[0031] 34 Non-injection region

[0032] 36 Non-injection regions

[0033] Polycrystalline regions 38, 39, 40

[0034] 42 Main contact area

[0035] 44 Main contact area

[0036] 45 gap

[0037] 46 Equipment Area

[0038] 48 Main contact area

[0039] 49 Upper boundary

[0040] 50 Field-Effect Transistors

[0041] 52 Gate electrode

[0042] 53 Gate dielectric

[0043] 54 Source / Drain Region

[0044] 56 contacts

[0045] 72 Embedded oxide layer

[0046] 74 Processing substrate. Detailed Implementation

[0047] refer to Figure 1 According to embodiments of the present invention, a semiconductor substrate 10 comprising a single-crystal semiconductor material (e.g., single-crystal silicon) is provided. The semiconductor substrate 10 may be a bulk substrate comprising a single-crystal semiconductor material (e.g., single-crystal silicon). In one embodiment, the semiconductor substrate 10 may be a high-resistivity bulk substrate comprising single-crystal silicon with a resistivity greater than or equal to 1,000 ohm-cm. In another embodiment, the semiconductor substrate 10 may be a high-resistivity bulk substrate comprising single-crystal silicon with a resistivity greater than or equal to 1,000 ohm-cm to 50,000 ohm-cm. In an alternative embodiment, the semiconductor substrate 10 may be a low-resistivity bulk substrate comprising single-crystal silicon with a resistivity less than 1,000 ohm-cm.

[0048] An implantation layer 14 containing damaged or amorphous semiconductor material is formed in the semiconductor substrate 10 below the top surface 12. The implantation layer 14 may be formed by an ion implantation process that introduces high-energy ions with ionic trajectories that impact the top surface 12 and travel within the semiconductor substrate 10. These high-energy ions lose energy along their path through random scattering events with atomic nuclei and electrons in the semiconductor material they pass through. The energy lost in nuclear collisions causes target atoms in the semiconductor substrate 10 to displace from their original lattice positions, which disrupts the lattice structure of the semiconductor substrate 10 and creates point defects. The lattice structure of the semiconductor substrate 10 is damaged or amorphized within the implantation layer 14 compared to an undamaged region 16 of the single-crystal semiconductor material located below the lower boundary 15 of the implantation layer 14. In one embodiment, the implantation layer 14 may extend from the lower boundary 15 to the top surface 12. Due to the use of high-dose implantation, the implantation layer 14 of the semiconductor substrate 10 can be changed from a crystalline semiconductor material (e.g., monocrystalline silicon) to a damaged or amorphous semiconductor material (e.g., amorphous silicon).

[0049] Ions can be generated by a suitable source gas and implanted into the semiconductor substrate 10 under one or more implantation conditions using an ion implantation tool. Implantation conditions (e.g., ion type, dose, energy) for the ion implantation process can be selected to tune the characteristics of the implanted layer 14. In one embodiment, ions can be generated by an inert gas (e.g., argon or xenon). In embodiments where the semiconductor substrate 10 will remain crystallized at the top surface 12, the ion dose can be selected to be less than a threshold ion dose, exceeding which it is impossible for the damaged semiconductor material in the implanted layer 14 to recrystallize by subsequent annealing. In one embodiment, the argon ion dose can be greater than 1 x 10⁻⁶. 14 ions / cm 2In one embodiment, the dose of argon ions can be 1x10⁻⁶. 14 ions / cm 2 Up to 5x10 15 ions / cm 2 Within a certain range. In one embodiment, the energy of the argon ions can be in the range of about 30 keV to about 1000 keV. The dose and energy of other implanted inert gas ion species may be similar to or different from those of argon. Ion implantation conditions may include single implantation, multiple implantations performed at different energies, segmented implantation, etc. A thin silicon dioxide layer (not shown) may be deposited on the top surface 12 of the semiconductor substrate 10 before performing the ion implantation process and may be removed after all ion implantation processes are completed.

[0050] refer to Figure 2 In which the same reference numerals indicate Figure 1 The same characteristics are present in the subsequent manufacturing stage of the processing method, whereby a portion of the damaged semiconductor material in the implanted layer 14 is transformed into a polycrystalline layer 18 in the semiconductor substrate 10 by performing a heat treatment (i.e., an annealing process). In one embodiment, the heat treatment for heat-treating the implanted layer 14 of the semiconductor substrate 10 and forming the polycrystalline layer 18 can be rapid thermal annealing. In one embodiment, rapid thermal annealing can be performed using, for example, a set of flash lamps that heats the semiconductor substrate 10 to a peak temperature in the range of 900°C to 1125°C and holds the peak temperature for 30 milliseconds to 5 seconds, and in a particular embodiment, the peak temperature can be maintained at 1000°C for a holding time not exceeding or equal to 1 second.

[0051] Polycrystalline layer 18 contains particles of polycrystalline semiconductor material (e.g., polycrystalline silicon). In addition to the polycrystalline particles, polycrystalline layer 18 may also contain defects as residual damage, and these defects may contain trapped atoms of the implantation type (e.g., argon or xenon). The heat treatment also recrystallizes the damaged semiconductor material of the implantation layer 14 between polycrystalline layer 18 and top surface 12 into layer 24 of the semiconductor substrate 10, which comprises a single-crystal semiconductor material (e.g., single-crystal silicon). Compared to polycrystalline layer 18, the recrystallized single-crystal semiconductor material in layer 24 lacks polycrystalline particles and defects, and may also lack implantation-type atoms.

[0052] A recrystallized single-crystal layer 24 is located between the upper boundary 20 of the polycrystalline layer 18 and the top surface 12 of the semiconductor substrate 10. The semiconductor substrate 10 also includes single-crystal semiconductor material in an undamaged region 16 located below the lower boundary 22 of the polycrystalline layer 18. Therefore, the polycrystalline layer 18 is buried below the top surface 12 and embedded in the single-crystal semiconductor material of the semiconductor substrate 10. The polycrystalline layer 18 has a thickness t1 in the vertical direction between the boundaries 20 and 22. In one embodiment, the thickness t1 of the polycrystalline layer 18 may be less than the thickness of the implanted layer 14 ( Figure 1 ).

[0053] The polycrystalline layer 18 can be characterized as a trap-rich material having a resistivity greater than or equal to that of the single-crystal semiconductor material of the semiconductor substrate 10. In one embodiment, the polycrystalline layer 18 may have a resistivity greater than or equal to 1,000 ohm-cm. In another embodiment, the resistivity of the polycrystalline layer 18 may be in the range of 10,000 ohm-cm to 1,000,000 ohm-cm. In yet another embodiment, the single-crystal semiconductor material of the substrate may have a resistivity of 1,000 to 10,000 ohm-cm, and the polycrystalline layer 18 may have a resistivity 10 to 100 times greater (i.e., in the range of 10,000 to 1,000,000 ohm-cm).

[0054] refer to Figure 3 In which similar reference numerals indicate Figure 2 Similar features are found in the process, where, in subsequent manufacturing stages, shallow trench isolation regions 25 and 26 are formed extending from the top surface 12 of the semiconductor substrate 10 to a shallow depth within the semiconductor substrate 10. The shallow trench isolation regions 25 and 26 may contain dielectric material deposited by chemical vapor deposition into trenches etched into the semiconductor substrate 10 by a mask etching process, polished, and deglazed. The dielectric material contained in the shallow trench isolation regions 25 and 26 may be silicon dioxide, silicon nitride, silicon carbide, silicon-rich silicon dioxide, or a combination of two or more of these materials.

[0055] The shallow trench isolation regions 25 and 26 extend to a depth in the semiconductor substrate 10 that is shallower than the upper boundary 20 of the polycrystalline layer 18. Therefore, a portion of the recrystallized single-crystal layer 24 of the semiconductor substrate 10 lies between the shallow trench isolation regions 25 and 26 and the polycrystalline layer 18. The shallow trench isolation regions 25 and 26 surround and isolate the active regions of the semiconductor substrate 10.

[0056] refer to Figure 4 , Figure 5 , Figure 5A , Figure 5B Similar reference numerals indicate Figure 3 Similar features are present in the subsequent manufacturing stages of the processing method, where implantation regions 28 are formed in the semiconductor substrate 10. For this purpose, a patterned implantation mask 30 is formed to define selected areas on the top surface 12 exposed for ion implantation to form the implantation regions 28. The implantation mask covers different areas on the top surface 12 to at least partially define the location and horizontal dimensions of the implanted implantation regions 28. The implantation mask may include a material layer, such as an organic photoresist, which is laid out and patterned such that non-selected areas on the top surface 12 are covered and masked. The implantation mask has sufficient thickness and blocking power to prevent the masked areas of the top surface 12 from receiving a dose of implanted ions.

[0057] An implantation region 28 containing damaged or amorphous semiconductor material is formed in the semiconductor substrate 10 below the top surface 12. The implantation region 28 can be formed by an ion implantation process that introduces high-energy ions with ion trajectories that impact the top surface 12 of the mask and travel within the semiconductor substrate 10. The high-energy ions lose energy along their path through random scattering events with atomic nuclei and electrons in the semiconductor material they pass through. The energy lost in nuclear collisions causes target atoms of the semiconductor substrate 10 to displace from their original lattice positions, which disrupts the lattice structure of the semiconductor substrate 10 and creates point defects. The lattice structure of the semiconductor substrate 10 is damaged or amorphized within the implantation region 28 compared to undamaged areas of the single-crystal semiconductor material laterally disposed between the implantation regions 28. Due to the use of a high dose of implantation type, the implantation region 28 of the semiconductor substrate 10 can be changed from a crystalline semiconductor material (e.g., single-crystal silicon) to a damaged or amorphous semiconductor material (e.g., amorphous silicon).

[0058] Ions can be generated by a suitable source gas and implanted into the semiconductor substrate 10 under one or more implantation conditions using an ion implantation tool. Implantation conditions (e.g., ion type, dose, energy) for the ion implantation process can be selected to tune the characteristics of the implantation region 28. In one embodiment, ions can be generated by an inert gas (e.g., argon or xenon). In one embodiment, the dose of argon ions can be greater than 1 x 10⁻⁶. 14 ions / cm 2 In one embodiment, the dose of argon ions can be 1x10⁻⁶. 14 Ion cm 2 Up to 5x10 15 ions / cm 2 Within a certain range. In one embodiment, the energy of the argon ions can range from about 30 keV to about 1000 keV. The dose and energy of other inert gas ion implantations may be similar to or different from those of argon ion implantations. Ion implantation conditions may include single implantation, multiple implantations performed at different energies, segmented implantation, etc.

[0059] The implantation region 28 in the active region can extend from the top surface 12 of the semiconductor substrate 10 to the polycrystalline layer 18. In one embodiment, the implantation region 28 may overlap with the polycrystalline layer 18 at its upper boundary 20. The implantation region 28 located at the periphery of the active region may also partially overlap with the shallow trench isolation regions 25, 26. The implantation mask 30 partially covers the non-implanted region 32 located between adjacent implantation regions 28. The implantation mask 30 partially covers the non-implanted region 34 extending around the entire outer periphery or circumference of the active region. The non-implanted region is laterally located between the shallow trench isolation regions 25 and 26. A portion of the implantation mask 30 covers the non-implanted region 36 extending laterally to the non-implanted region 32. The non-implanted region 36 may be located at the center of the active region between different groups of implantation regions 28. The non-implanted regions 32, 34, 36 contain the single-crystal semiconductor material of the recrystallized single-crystal layer 24 of the semiconductor substrate 10.

[0060] refer to Figure 6 , Figure 6A , Figure 6B Similar reference numerals indicate Figure 5 , 5A Similar to features in 5B, in a subsequent manufacturing stage of the processing method, the implanted region 28 is transformed into polycrystalline regions 38, 39, and 40 in the semiconductor substrate 10 by performing a heat treatment (i.e., an annealing process). In one embodiment, the heat treatment for heat-treating the implanted region 28 of the semiconductor substrate 10 to form polycrystalline regions 38, 39, and 40 can be rapid thermal annealing. In one embodiment, rapid thermal annealing can be performed using, for example, a set of flash lamps that heats the semiconductor substrate 10 to a peak temperature in the range of 900°C to 1125°C and holds the peak temperature for 30 milliseconds to 5 seconds, and in a particular embodiment, the peak temperature can be maintained at 1000°C for a holding time not exceeding or equal to 1 second.

[0061] Polycrystalline regions 38, 39, and 40 contain particles of polycrystalline semiconductor material (e.g., polycrystalline silicon). In addition to the polycrystalline particles, polycrystalline regions 38, 39, and 40 may also contain defects as residual damage, and these defects may contain trapped atoms of an implantation type (e.g., argon or xenon). The heat treatment also recrystallizes the damaged semiconductor material in the implantation region 28 between the polycrystalline region 38 and the top surface 12 into a single-crystal semiconductor material (e.g., single-crystal silicon) belonging to the recrystallization layer 24 of the semiconductor substrate 10.

[0062] Polycrystalline region 38 is located between the upper boundary 20 of polycrystalline layer 18 and the top surface 12 of semiconductor substrate 10. A portion of the single-crystal semiconductor material of layer 24 is located between each polycrystalline region 38 and the top surface 12. Polycrystalline region 39 is partially located between the upper boundary 20 of polycrystalline layer 18 and shallow trench isolation region 25, and partially located between the upper boundary 20 of polycrystalline layer 18 and the top surface 12. Polycrystalline region 40 is located between the upper boundary 20 of polycrystalline layer 18 and shallow trench isolation region 26. Shallow trench isolation regions 25 and 26 are located between polycrystalline regions 39 and 40 and the top surface 12. The lower portion of each polycrystalline region 38, 39, and 40 may intersect with and / or extend with polycrystalline layer 18 at its upper boundary 20.

[0063] Similar to polycrystalline layer 18, polycrystalline regions 38, 39, and 40 can be characterized as trap-rich materials having a resistivity greater than or equal to that of the monocrystalline semiconductor material of semiconductor substrate 10. In one embodiment, the resistivity of polycrystalline regions 38, 39, and 40 may be greater than or equal to 1,000 ohm-cm. In one embodiment, the resistivity of polycrystalline layer 18 may be in the range of 10,000 ohm-cm to 1,000,000 ohm-cm. In one embodiment, the monocrystalline semiconductor material of the substrate may have a resistivity of 1,000 to 10,000 ohm-cm, and polycrystalline layer 18 may have a resistivity 10 to 100 times greater (i.e., in the range of 10,000 to 1,000,000 ohm-cm).

[0064] The recrystallized single-crystal layer 24 includes a body contact region 42 laterally located between shallow trench isolation regions 25 and 26. The recrystallized single-crystal layer 24 includes a body contact region 44 located in a gap G between adjacent pairs of polycrystalline regions 38, 39, a body contact region 48 laterally extending to the body contact region 44, and a device region 46 located above the polycrystalline regions 38, 39 and the body contact region 44. The device region 46 is located between the body contact region 44 and the top surface 12. The body contact region 42 of layer 24 extends completely around the entire perimeter or circumference of the device region 46 (i.e., completely surrounds it). The body contact region 48 extends through a fracture or gap 45 in the polycrystalline region 39 to provide a connection between the single-crystal semiconductor material in the body contact region 42 and the single-crystal semiconductor material in the body contact region 44. The fracture in the polycrystalline semiconductor material is located below a section or portion of the shallow trench isolation region 25. The polycrystalline layer 18 is located below all regions 42, 44, 46, and 48. Shallow trench isolation area 25 completely surrounds equipment area 46, and shallow trench isolation area 26 completely surrounds shallow trench isolation area 25.

[0065] One of the main contact regions 44 is located in each gap G between adjacent pairs of polycrystalline regions 38, 39, and in one embodiment, may completely fill each gap G. The main contact region 44 may be located at and below the upper boundary 49 of the polycrystalline regions 38, 39, as shown by the horizontal dashed line. The polycrystalline regions 38, 39, 40 have a thickness t2 in the vertical direction, and the main contact region 44 may have a thickness equal to the thickness t2. In one embodiment, the thickness of the polycrystalline regions 38, 39, 40 may be less than that of the implantation region 28 (…). Figure 3 The thickness of the high-resistivity trap-rich material in polycrystalline regions 38, 39, and 40 is such that only the lower portion of each injection region 28 is converted into polycrystalline semiconductor material. The total thickness of the high-resistivity trap-rich material in polycrystalline regions 38, 39, and 40 is actually equal to the sum of thicknesses t1 and t2, while the total thickness of the high-resistivity trap-rich material in the main contact regions 42, 44, and 48 is equal to thickness t1. The combination of high-resistivity trap-rich material of varying thicknesses gives the corrugated shape.

[0066] The device region 46 can be doped to form a well with a given type of conductivity. The well can be formed, for example, by introducing a dopant into the device region 46 through ion implantation under given implantation conditions. Implantation conditions (e.g., ion type, dose, kinetic energy) can be selected to tune the electrical and physical properties of the well in the device region 46. In one embodiment, the well may comprise a semiconductor material doped with a p-type dopant (e.g., boron) to provide p-type conductivity.

[0067] After a well is formed in device region 46, device region 46 has higher conductivity (i.e., lower resistivity) than the body contact regions 44, 48. In one embodiment, body contact regions 44, 48 may be undoped, unlike device region 46. In another embodiment, body contact region 44 may be doped to have the same conductivity type as device region 46, but with a significantly reduced dopant concentration.

[0068] refer to Figure 7 , Figure 7A , Figure 7B Similar reference numerals indicate Figure 6 , Figure 6A , Figure 6BSimilar to the features described in the previous process, in subsequent manufacturing stages of the process, the field-effect transistor 50 can be fabricated via front-end process (FEOL) processing, which serves as a device structure in the device region 46 of the semiconductor substrate 10. The field-effect transistor 50 may include a gate electrode 52 composed of a conductor (e.g., doped polysilicon, or a work function metal) and a gate dielectric 53 composed of an electrically insulating material (e.g., silicon dioxide or hafnium oxide). The gate electrode 52 and the associated gate dielectric 53 can be formed by depositing layers and patterning the layer stack using photolithography and etching processes. The field-effect transistor 50 may include other elements such as a halo region, a lightly doped drain extension, a source / drain region 54 in a well, a trench region as part of the well between the source / drain regions 54, and sidewall spacers on the gate electrode 52.

[0069] In one embodiment, the field-effect transistor 50 may provide a switching field-effect transistor in a radio frequency circuit, and the field-effect transistor 50 may be connected in series with other similar field-effect transistors in a group or stack.

[0070] Middle-of-line and back-end-of-line processing follow, including contacts, vias, and wiring to form interconnect structures for coupling with the field-effect transistor 50. The interconnect structures include contacts 56 coupled to the body contact region 42, which provide body bias to the body contact region 44. Additional body contacts (not shown) may also be coupled to the body contact region 42 at other locations.

[0071] The structure, including polycrystalline layer 18 and polycrystalline regions 38, 39, and 40, can alleviate the limitation on upward width scaling of the switch bank caused by body contact requirements by increasing maximum power handling capability (Pmax) and improving linearity. The structure can provide a more uniform distribution of body voltage across the switch bank.

[0072] refer to Figure 8 According to an alternative embodiment, the semiconductor substrate 10 may be a silicon-on-insulator substrate, comprising a buried oxide layer 72 and a handle substrate 74. By controlling the implantation conditions of the implantation layer 14, a polycrystalline layer 18 formed by the heat treatment of the implantation layer 14 can overlap with the buried oxide layer 72, such that a portion of the polycrystalline layer 18 lies within the handle substrate 74 below the buried oxide layer 72, while another portion of the polycrystalline layer 18 lies above the buried oxide layer 72 and between the buried oxide layer 72 and the top surface 12. Therefore, the buried oxide layer 72 is located between the upper and lower boundaries 20, 22 of the polycrystalline layer 18. The recrystallized single crystal layer 24 is provided by the device layer of the silicon-on-insulator substrate. The processing is combined... Figure 3-7 , Figure 7A, Figure 7B Continue as described.

[0073] The methods described above are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare chips, or in packages. In the latter case, the chips are mounted in a single-chip package (e.g., a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with one or both surface interconnects or buried interconnects). In any case, the chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product.

[0074] Terms used in this document that are modified from approximate language, such as “about,” “approximately,” and “substantially,” are not limited to specified exact values. Approximate language may correspond to the accuracy of the instrument used to measure the value and may represent + / - 10% of the specified value unless otherwise dependent on the accuracy of the instrument.

[0075] The use of terms such as “vertical” and “horizontal” in this document is illustrative and not restrictive, serving to establish a framework for reference. As used herein, the term “horizontal” is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional orientation. The terms “vertical” and “normal” refer to directions perpendicular to the horizontal plane, as defined above. The term “lateral” refers to a direction within the horizontal plane.

[0076] A feature that is "connected" or "coupled" to another feature can be directly connected or coupled to another feature, or there can be one or more intermediate features. If no intermediate features exist, a feature can be "directly connected" or "directly coupled" to another feature or together with another feature. If at least one intermediate feature exists, a feature can be "indirectly connected" or "indirectly coupled" to another feature. A feature that is "on" or "in contact" with another feature can be directly on or in direct contact with another feature, or conversely, there can be one or more intermediate features. If no intermediate features exist, a feature can be "directly" on or in direct contact with another feature. If at least one intermediate feature exists, a feature can be "indirectly" on or indirectly in contact with another feature.

[0077] The description of various embodiments of the present invention is given for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application or improvement relative to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A body contact semiconductor structure, comprising: a semiconductor substrate composed of a single crystalline semiconductor material, the semiconductor substrate including a device region and a plurality of first body contact regions, each of the first body contact regions being composed of the single crystalline semiconductor material; a polycrystalline layer located in the semiconductor substrate; and a plurality of polycrystalline regions located in the semiconductor substrate, the plurality of polycrystalline regions being located between the polycrystalline layer and the device region, and the plurality of polycrystalline regions having a lateral spaced apart arrangement with a first gap between each adjacent pair of the plurality of polycrystalline regions, wherein one of the plurality of first body contact regions is disposed in the first gap between each adjacent pair of the plurality of polycrystalline regions, the polycrystalline layer has a first overall thickness, and each of the plurality of polycrystalline regions has a second overall thickness that is greater than the first overall thickness. the semiconductor substrate includes a top surface, and the device region is entirely located between the plurality of polycrystalline regions and the top surface.

2. The body contact semiconductor structure of claim 1, wherein, the polycrystalline layer and the plurality of polycrystalline regions have a resistivity in a range of 10,000 ohm-cm to 1,000,000 ohm-cm.

3. The body contact semiconductor structure of claim 1, wherein, the semiconductor substrate includes a second body contact region composed of the single crystalline semiconductor material, and the second body contact region is disposed to entirely surround the device region.

4. The body contact semiconductor structure of claim 1, wherein, the semiconductor substrate includes a third body contact region composed of the single crystalline semiconductor material, and the third body contact region connects the second body contact region with the plurality of first body contact regions.

5. The body contact semiconductor structure of claim 4, wherein, the third body contact region is laterally aligned with the plurality of first body contact regions.

6. The body contact semiconductor structure of claim 5, wherein, the third body contact region extends through a second gap in the plurality of polycrystalline regions to provide a connection between the second body contact region and the plurality of first body contact regions.

7. The body contact semiconductor structure of claim 5, wherein, 8. The body contact semiconductor structure of claim 4, further comprising: a first shallow trench isolation region located in the semiconductor substrate, the first shallow trench isolation region entirely surrounding the device region, and the first shallow trench isolation region being located between the second body contact region and the device region. the semiconductor substrate includes a third body contact region composed of the single crystalline semiconductor material, and the third body contact region extends through a second gap in the plurality of polycrystalline regions and under a portion of the first shallow trench isolation region to provide a connection between the second body contact region and the plurality of first body contact regions.

9. The bulk contact semiconductor structure of claim 8, wherein, 10. The body contact semiconductor structure of claim 8, further comprising: a second shallow trench isolation region located in the semiconductor substrate, the second shallow trench isolation region entirely surrounding the first shallow trench isolation region, wherein the second body contact region is laterally located between the first shallow trench isolation region and the second shallow trench isolation region.

11. The body contact semiconductor structure of claim 1, further comprising: a plurality of gate electrodes located over the device region; and a plurality of source / drain regions located in the device region. ​ ​ 12. The bulk contact semiconductor structure of claim 1, wherein, The polycrystalline layer has an upper boundary, the semiconductor substrate includes a top surface, and the plurality of polycrystalline regions are located between the upper boundary of the polycrystalline layer and the top surface of the semiconductor substrate.

13. The body-contacted semiconductor structure of claim 1, further comprising: a shallow trench isolation region located in the semiconductor substrate, the shallow trench isolation region surrounding the device region, wherein at least one of the plurality of polycrystalline regions extends from the polycrystalline layer to the shallow trench isolation region.

14. The body contact semiconductor structure of claim 1, wherein, The semiconductor substrate includes a buried oxide layer, and the polycrystalline layer includes a first portion above the buried oxide layer and a second portion below the buried oxide layer.

15. The bulk contact semiconductor structure of claim 1, wherein, The first gap between each adjacent pair of the plurality of polycrystalline regions is completely filled by one of the plurality of first body-contacted regions.

16. A method of forming a body-contacted semiconductor structure, the method comprising: forming a polycrystalline layer in a semiconductor substrate composed of a single crystalline semiconductor material; and forming a plurality of polycrystalline regions in the semiconductor substrate, wherein the semiconductor substrate includes a device region and a plurality of first body-contacted regions each composed of the single crystalline semiconductor material, the plurality of polycrystalline regions are located between the polycrystalline layer and the device region, the plurality of polycrystalline regions have a lateral spaced-apart arrangement with a first gap between each adjacent pair of the plurality of polycrystalline regions, one of the plurality of first body-contacted regions is disposed in the first gap between each adjacent pair of the plurality of polycrystalline regions, the polycrystalline layer has a first total thickness, and each of the plurality of polycrystalline regions has a second total thickness greater than the first total thickness.

17. The method of claim 16, wherein, Forming the polycrystalline layer in the semiconductor substrate composed of the single crystalline semiconductor material includes: implanting ions into the semiconductor substrate with a first ion implantation process to amorphize a crystalline structure of the single crystalline semiconductor material in an implanted layer; and annealing the semiconductor substrate with a first anneal process to convert the amorphized semiconductor material to form the polycrystalline layer.

18. The method of claim 17, wherein, Forming the plurality of polycrystalline regions in the semiconductor substrate includes: forming a patterned mask on the semiconductor substrate; implanting ions into the semiconductor substrate with a second ion implantation process to amorphize the crystalline structure of the single crystalline semiconductor material in a plurality of implanted regions associated with the patterned mask; and annealing the semiconductor substrate with a second anneal process to convert the amorphized semiconductor material to form the plurality of polycrystalline regions.

19. The method of claim 16, wherein, The semiconductor substrate includes a second body-contacted region composed of the single crystalline semiconductor material, and the second body-contacted region completely surrounds the device region.

20. The method of claim 19, wherein, The semiconductor substrate includes a third body contact region composed of the single crystalline semiconductor material, the third body contact region coupling the second body contact region with the plurality of first body contact regions, the third body contact region laterally aligned with the plurality of first body contact regions, and the third body contact region extending to the second body contact region through a second gap in the plurality of polycrystalline regions.

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