Phase change memory device and method of forming the same

Abstract

In a particular aspect, a three-dimensional (3D) phase change memory (PCM) device includes a first PCM cell, a first shrinkage PCM cell on the first PCM cell, a second shrinkage PCM cell on the first shrinkage PCM cell, and a second PCM cell on the second shrinkage PCM cell. The first PCM cell includes a first PCM element, the first shrinkage PCM cell includes a first shrinkage PCM element, the second shrinkage PCM cell includes a second shrinkage PCM element, and the second PCM cell includes a second PCM element. The width of the first PCM element is greater than the width of the first shrinkage PCM element, and the width of the second PCM element is greater than the width of the second shrinkage PCM element.

Description

Technical Field

[0001] The present disclosure relates to phase-change memory (PCM) devices and methods of manufacturing the same. Background Art

[0002] Planar memory cells are shrunk to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral devices for controlling signals in and out of the memory array. For example, PCM can exploit the difference between the resistivity of the amorphous and crystalline phases in a phase change material based on electrothermal heating and quenching of the phase change material. PCM array cells can be stacked vertically in 3D to form a 3D PCM device. Summary of the invention

[0004] In one aspect, a three-dimensional (3D) phase change memory (PCM) device includes a first PCM cell, a first shrunken PCM cell on the first PCM cell, a second shrunken PCM cell on the first shrunken PCM cell, and a second PCM cell on the second shrunken PCM cell. The first PCM cell includes a first PCM element, the first shrunken PCM cell includes a first shrunken PCM element, the second shrunken PCM cell includes a second shrunken PCM element, and the second PCM cell includes a second PCM element. A width of the first PCM element is greater than a width of the first shrunken PCM element, and a width of the second PCM element is greater than a width of the second shrunken PCM element.

[0005] In another aspect, a three-dimensional (3D) phase change memory (PCM) device includes: one or more first PCM cells, each of which includes a first PCM element; one or more first systolic PCM cells on the corresponding one or more first PCM cells, each of which includes a first systolic PCM element; one or more second systolic PCM cells on the corresponding one or more first systolic PCM cells, each of which includes a second systolic PCM element; and one or more second PCM cells on the corresponding one or more second systolic PCM cells, each of which includes a second PCM element. A width of the first PCM element is greater than a width of the first systolic PCM element, and a width of the second PCM element is greater than a width of the second systolic PCM element.

[0006] In yet another aspect, a method for forming a three-dimensional (3D) phase change memory (PCM) device includes: depositing one or more first PCM cells on one or more first bit lines, each first PCM cell including a first PCM element; sequentially depositing one or more first word lines and one or more first systolic PCM cells on the corresponding one or more first PCM cells, each first systolic PCM cell including a first systolic PCM element; sequentially depositing one or more second bit lines and one or more second systolic PCM cells on the corresponding one or more first systolic PCM cells, each second systolic PCM cell including a second systolic PCM element; sequentially depositing one or more second word lines and one or more second PCM cells on the corresponding one or more second systolic PCM cells, each second PCM cell including a second PCM element; and depositing one or more third bit lines on the corresponding one or more second PCM cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable one skilled in the relevant art to make and use the present disclosure.

[0008] Figure 1 A perspective view of an exemplary 3D phase change memory (PCM) memory device according to some aspects of the present disclosure is shown.

[0009] Figure 2 A side view showing a cross section of a 3D PCM memory device according to some aspects of the present disclosure is shown.

[0010] Figure 3 A perspective view of an exemplary 3D PCM device with stacked PCM cells according to some aspects of the present disclosure is shown.

[0011] Figure 4 A side view of a cross section of an exemplary 3D PCM device with shrunken PCM cells according to some aspects of the present disclosure is shown.

[0012] Figure 5 Comparison results of resistance variation over operating time between a 3D PCM device with the same cell size and a 3D PCM device with a modified cell size according to some aspects of the present disclosure are shown.

[0013] Figures 6A-6D An exemplary fabrication process for forming an exemplary 3D PCM device having shrunken PCM cells according to some aspects of the present disclosure is shown.

[0014] Figure 7 A flow chart illustrating an exemplary method for forming an exemplary 3DPCM device having a shrink PCM cell according to some aspects of the present disclosure.

[0015] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0016] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Therefore, those skilled in the relevant art will appreciate that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

[0017] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a person skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0018] Typically, a term can be understood at least in part from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one", "an" or "the" can also be understood to express singular usage or to express plural usage. In addition, the term "based on" can be understood to not necessarily express an exclusive set of factors, but can allow for the presence of other factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0019] It should be easily understood that the meaning of “on,” “over,” and “above” in the present disclosure should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “on” or “above” not only means “on something” or “above something,” but also includes the meaning of “it is on something” or “it is over something” without intervening features or layers therebetween (i.e., directly on something).

[0020] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0021] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0022] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire lower or upper structure, or may have a range that is less than the range of the lower or upper structure. In addition, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top surface and the bottom surface of a continuous structure or between any pair of horizontal planes at the top surface and the bottom surface. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (where interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0023] As used herein, the term "3D" memory device or PCM device refers to a semiconductor device having memory cells that can be arranged vertically on a laterally oriented substrate, so that the number of memory cells can be increased in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" refers to a lateral surface that is nominally perpendicular to the substrate.

[0024] Based on electrothermal heating and quenching of phase change materials (such as chalcogenide alloys), PCM can exploit the difference between the resistivity of the amorphous phase and the crystalline phase in the phase change material. The phase change material in the PCM cell can be located between two electrodes, and a current can be applied to cause the material (or at least a portion of the material that blocks the current path) to repeatedly switch between the two phases to store data. PCM cells can be stacked vertically in 3D to form a 3D PCM device. 3D PCM devices store data based on the resistance change of bulk material properties (e.g., in a high resistance state or a low resistance state) and in combination with a stackable cross-point data access array capable of bit addressing.

[0025] With the development of 3D memory devices (e.g., 3D PCM devices), more cells (e.g., PCM cells) are stacked to increase the density of 3D memory devices. However, high power consumption, cell-to-cell variation, and data retention loss are the main limitations of more memory cell stacks. With regard to power consumption, especially in PCM arrays, when a selected memory cell is programmed by a programming voltage, thermal crosstalk between adjacent memory cells undesirably increases the temperature of nearby unselected memory cells. After multiple consecutive programming operations, the programming voltage may increase the threshold voltage of nearby unselected memory cells in a cumulative manner. This leads to the adverse effect of requiring a higher programming voltage to program these affected unselected memory cells. In particular, when more than two memory cell stacks (e.g., four memory cell stacks) are involved, the internal cell is capped between two external cells. The capped internal cell may retain and accumulate more heat internally, and thus may cause more thermal crosstalk effects and reduce power performance. In addition, with regard to cell-to-cell variation, especially variation in the vertical direction, the temperature between the external cell and the internal cell varies in the vertical direction due to heat dissipation as described above. That is, the characteristics of the cells may change due to the temperature they are exposed to. Finally, data retention time is also affected by the thermally activated crystallization of the amorphous PCM material. The more amorphous volume retained in the PCM element, the longer the array-level data retention time can be achieved. That is, high temperatures of amorphous PCM materials create the possibility of crystallization, which reduces the stability of data retention.

[0026] In order to solve one or more of the above problems, the present disclosure introduces a solution, wherein the thickness and / or width of the internal cells of the PCM device can be reduced so that the thermal crosstalk is reduced laterally. In addition, by reducing the thickness of the PCM cell, the amorphous volume can be maintained, thereby increasing the data retention time at the array level. In addition, by reducing the thickness of the internal cell while maintaining the thickness of the external cell, the temperature variation is reduced, thereby minimizing the cell-to-cell variation affected by temperature. In addition, as the thickness of the PCM cell is reduced, the resistance-capacitance (RC) delay can also be improved during the reset operation. Finally, as the thickness of the PCM cell is reduced, the crystallization temperature increases, and the thermal boundary resistance (TBR) is more prominent. It has been found that the TBR will achieve the following temperature distribution, which minimizes the overheating of the center of the active area of ​​the PCM cell while also facilitating the formation of the amorphous volume. This phase distribution (phase distribution) contributes to the minimum reset current, which is very desirable for power consumption and data retention. The present disclosure also provides a method of stacking a plurality of PCM cells and connecting these PCM cells to a common bit line or word line, wherein the plurality of PCM cells include a shrink PCM cell.

[0027] Figure 1 A perspective view of an exemplary 3D PCM device 100 according to some embodiments of the present disclosure is shown. According to some embodiments, the 3D PCM device 100 has a transistor-free crosspoint architecture that positions memory cells at the intersection of vertical conductors. The 3D PCM device 100 includes one or more parallel lower bitlines 102 in the same plane and one or more parallel upper bitlines 104 in the same plane above the lower bitlines 102. The 3D PCM device 100 also includes one or more parallel wordlines 106 located vertically between the lower bitlines 102 and the upper bitlines 104 in the same plane. Figure 1 As shown, in a plan view, each lower bit line 102 and each upper bit line 104 extend laterally along a bit line direction (parallel to the wafer plane), and in a plan view, each word line 106 extends laterally along a word line direction. In a plan view, each word line 106 crosses each lower bit line 102 and each upper bit line 104. In some embodiments, each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

[0028] It should be noted that Figure 1 The x and y axes are included in FIG. 1 to illustrate two orthogonal directions in the wafer plane. The x direction is the word line direction, while the y direction is the bit line direction. It should be noted that Figure 1The z-axis is also included in the 3D PCM device 100 to further illustrate the spatial relationship of the components in the 3D PCM device 100. The substrate (not shown) of the 3D PCM device 100 includes two lateral surfaces extending laterally in the xy plane: a top surface on the front side of the wafer, and a bottom surface on the back side opposite to the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, when the substrate is located in the lowest plane of the semiconductor device (e.g., 3D PCM device 100) in the z-direction (perpendicular to the vertical direction of the xy plane), it is determined in the z-direction relative to the substrate of the semiconductor device whether a component (e.g., a layer or device) of the semiconductor device is "on", "above" or "below" another component (e.g., a layer or device). Throughout this disclosure, the same concept is applied to describe spatial relationships.

[0029] like Figure 1 As shown, the 3D PCM device 100 includes one or more PCM cells 108, each of which is arranged at the intersection of the lower bit line 102 or the upper bit line 104 and the corresponding word line 106. Each PCM cell 108 has a vertical square column shape. Each PCM cell 108 includes at least a vertically stacked PCM element 110 and a selector 112. Each PCM cell 108 stores a single data bit and can be written or read by changing the voltage applied to the corresponding selector 112, which replaces the need for transistors. Each PCM cell 108 is individually accessed by a current applied through a top conductor and a bottom conductor (e.g., a corresponding word line 106 and a lower bit line 102 or an upper bit line 104) in contact with each PCM cell 108. The PCM cells 108 in the 3D PCM device 100 are arranged in a memory array.

[0030] Figure 2 A side view of a cross section of an exemplary 3D PCM memory device 200 is shown according to some aspects of the present disclosure. Figure 2 , a 3D PCM memory device 200 includes a substrate 202, one or more parallel bit lines 211 formed on the substrate 202, and one or more parallel word lines 221 formed above the bit lines 211. The substrate 202 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. The bit lines 211 and the word lines 221 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of the bit lines 211 and the word lines 221 includes a metal, such as tungsten.

[0031] The 3D PCM memory device 200 can be divided by an isolation layer 218 to form one or more separated pillar-shaped PCM cells 201. In some embodiments, each pillar-shaped PCM cell 201 is disposed at the intersection of a corresponding bit line 211 and a corresponding word line 221. Each pillar-shaped PCM cell 201 can be individually accessed by a current applied through a corresponding word line 221 and a corresponding bit line 211 in contact with the pillar-shaped PCM cell 201. Each pillar-shaped PCM cell 201 has a vertical pillar shape (e.g., similar to Figure 1 The isolation layer 218 may extend laterally in the x-direction and the y-direction to separate the columnar PCM cells 201 .

[0032] Each columnar PCM cell 201 includes a first electrode 2071 formed on a bit line 211, a selector 205 formed on the first electrode 2071, and a second electrode 2072 formed on the selector 205. The columnar PCM cell 201 also includes a PCM element 203 formed on the second electrode 2072, and a third electrode 2073 formed on the PCM element 203. The first electrode 2071, the selector 205, and the second electrode 2072 are functionally modularized and used as a selection device in the columnar PCM cell 201. The second electrode 2072, the PCM element 203, and the third electrode 2073 are functionally modularized and used as a storage element in the columnar PCM cell 201. It can be understood that the second electrode 2072 is used as a common electrode in the selection device and the storage element.

[0033] The first electrode 2071 is formed on the bit line 211 and contacts the selector 205, so that the first electrode 2071 serves as a current path and may be formed of a conductive material. In some embodiments, the first electrode 2071 may be a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, the first electrode 2071 may be a titanium nitride (TiN) layer, but the present disclosure is not limited thereto.

[0034] The selector 205 is formed on the first electrode 2071, and the resistance of the selector 205 changes in response to the selection voltage applied between the first electrode 2071 and the second electrode 2072. In some embodiments, the selector 205 may be an ovonic threshold switch (OTS) device made of at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), antimony (Sb), silicon (Si), or arsenic (As). The OTS device is formed of an OTS material having an OTS property. Regarding the function of the selector 205 including the OTS material, when a voltage lower than the threshold voltage Vth is applied between the first electrode 2071 and the second electrode 2072, the selector 205 may be in a high resistance state that prevents current from flowing, and when a voltage higher than the threshold voltage Vth is applied between the first electrode 2071 and the second electrode 2072, the selector 205 may be in a low resistance state that allows current to flow.

[0035] The second electrode 2072 is formed between the selector and the storage element and serves as an electrode for both the selector and the storage element, so the second electrode 2072 should be formed of a thermally insulating and electrically insulating material to reduce temperature interference and electrical interference from the selector and the storage element. The second electrode 2072 can be formed of, for example, a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof, or can include, for example, a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, the second electrode 2072 can be a titanium nitride (TiN) layer or any suitable conductive layer. In some embodiments, the second electrode 2072 can be formed of amorphous carbon.

[0036] The PCM element 203 is formed on the second electrode 2072. The PCM element 203 is a material whose phase can be reversibly switched between an amorphous state and a crystalline state according to a heating time. Generally, the PCM element 203 can exist in the form of an amorphous phase and a crystalline phase, or the PCM element 203 can sometimes exist in the form of an amorphous phase and several crystalline phases, and can be quickly and repeatedly switched between these phases. In some embodiments, the PCM element 203 may include a material whose phase can be reversibly changed using Joule heat, which is generated when a voltage is applied between the second electrode 2072 and the third electrode 2073, and the resistance of the PCM element 203 can be changed by this phase change. In some embodiments, the PCM element 203 may include a chalcogenide component, and the chalcogenide component includes at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga). In some embodiments, PCM element 203 may be a binary (two-element) compound such as GaSb, InSb, InSe, SbTe, or GeTe; a ternary (three-element) compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, or InSbGe; or a quaternary (four-element) compound such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), or TeGeSbS. In some embodiments, PCM element 203 may be GeSbTe.

[0037] The third electrode 2073 is formed on the PCM element 203. In some embodiments, the material of the third electrode 2073 may be similar to that of the first electrode 2071 or the second electrode 2072. In some embodiments, the material of the third electrode 2073 may be similar to that of the second electrode 2072. Then, the word line 221 is formed on the third electrode 2073.

[0038] It should be understood that the positions of the bit line 211 and the word line 221 corresponding to the pillar-shaped PCM unit 201 may be exchanged according to different memory designs. That is, the first electrode 2071 may be formed on the word line, and the bit line may be formed on the third electrode 2073 .

[0039] Figure 3 A perspective view of an exemplary 3D PCM device 300 having stacked PCM cells according to some aspects of the present disclosure is shown. The 3D PCM device 300 includes a lower bit line 321, an intermediate bit line 323 above the lower bit line 321, and an upper bit line 325 above the intermediate bit line 323.3. The PCM device 300 also includes a lower word line 341 vertically located between the lower bit line 321 and the intermediate bit line 323, and an upper word line 343 vertically located between the intermediate bit line 323 and the upper bit line 325. Figure 3As shown, in a plan view, each of the bit lines 321, 323, and 325 extends laterally along a bit line direction (e.g., in an x-direction); and in a plan view, each of the word lines 341 and 343 extends laterally along a word line direction (e.g., in a y-direction). In a plan view, each of the word lines 341 and 343 crosses each of the bit lines 321, 323, and 325. In some embodiments, each of the word lines 341 and 343 is perpendicular to each of the bit lines 321, 323, and 325.

[0040] like Figure 3 As shown, the 3D PCM device 300 also includes a first PCM cell 311 disposed at the intersection of a lower bit line 321 and a lower word line 341, a second PCM cell 331 disposed at the intersection of the lower word line 341 and the middle bit line 323, a third PCM cell 351 disposed at the intersection of the middle bit line 323 and the upper word line 343, and a fourth PCM cell 371 disposed at the intersection of the upper word line 343 and the upper bit line 325. Each of the PCM cells 311, 331, 351 and 371 has a vertical column shape. Each of the PCM cells 311, 331, 351 and 371 includes at least a vertically stacked PCM element and a selector. Each of the PCM cells 311, 331, 351 and 371 stores a single data bit and can be written or read by changing the voltage applied to the corresponding selector, which replaces the need for a transistor. The first PCM cell 311 is individually accessed by a current applied through a top conductor and a bottom conductor (e.g., a lower word line 341 and a lower bit line 321) in contact with the first PCM cell 311. The second PCM cell 331 is individually accessed by a current applied through, for example, a middle bit line 323 and a lower word line 341. The third PCM cell 351 is individually accessed by a current applied through, for example, an upper word line 343 and a middle bit line 323. The fourth PCM cell 371 is individually accessed by a current applied through, for example, an upper bit line 325 and an upper word line 343. Each of the PCM cells 311, 331, 351, and 371 in the 3D PCM device 300 is arranged in a memory array. In some embodiments, the first PCM cell 311 and the fourth PCM cell 371 are external PCM cells, for example, a first external PCM cell and a second external PCM cell. The second PCM cell 331 and the third PCM cell 351 are internal PCM cells, for example, a first internal PCM cell and a second internal PCM cell. In some embodiments, each of the first inner PCM cell and the second inner PCM cell may include a shrink PCM cell to be discussed later.

[0041] Figure 4A side view of a cross section of an exemplary 3D PCM device 400 with a shrink PCM cell according to some aspects of the present disclosure is shown. The 3D PCM device 400 includes a lower bit line 421, an intermediate bit line 423 above the lower bit line 421, and an upper bit line 425 above the intermediate bit line 423. The 3D PCM device 400 also includes a lower word line 441 vertically located between the lower bit line 421 and the intermediate bit line 423, and an upper word line 443 vertically located between the intermediate bit line 423 and the upper bit line 425. Figure 4 As shown, each of the bit lines 421, 423, and 425 extends laterally along the bit line direction (e.g., in the x direction), and each of the word lines 441 and 443 extends laterally along the word line direction (e.g., in the y direction). Each of the word lines 441 and 443 intersects each of the bit lines 421, 423, and 425. In some embodiments, each of the word lines 441 and 443 is perpendicular to each of the bit lines 421, 423, and 425. In some embodiments, the bit lines 421, 423, and 425 and the word lines 441 and 443 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the bit lines 421, 423, and 425 and each of the word lines 441 and 443 include a metal, such as tungsten.

[0042] like Figure 4As shown, the 3D PCM device 400 also includes a first external PCM cell 411 disposed at the intersection of a lower bit line 421 and a lower word line 441, a first contraction PCM cell 431 disposed at the intersection of the lower word line 441 and the middle bit line 423, a second contraction PCM cell 451 disposed at the intersection of the middle bit line 423 and the upper word line 443, and a second external PCM cell 471 disposed at the intersection of the upper word line 443 and the upper bit line 425. Each of the PCM cells 411, 431, 451, and 471 has a vertical column shape. Each of the PCM cells 411, 431, 451, and 471 includes at least a vertically stacked PCM element and a selector. Each of the PCM cells 411, 431, 451, and 471 stores a single data bit and can be written or read by changing a voltage applied to a corresponding selector, which replaces the need for a transistor. The first external PCM cell 411 is individually accessed by a current applied through a top conductor and a bottom conductor (e.g., a lower word line 441 and a lower bit line 421) in contact with the first external PCM cell 411. The first shrinkage PCM cell 431 is individually accessed by a current applied through, for example, a middle bit line 423 and a lower word line 441. The second shrinkage PCM cell 451 is individually accessed by a current applied through, for example, an upper word line 443 and a middle bit line 423. The second external PCM cell 471 is individually accessed by a current applied through, for example, an upper bit line 425 and an upper word line 443. Each of the PCM cells 411, 431, 451, and 471 in the 3D PCM device 400 is arranged in a memory array. In some embodiments, the 3D PCM device 400 may include a plurality of internal shrinkage PCM cells (e.g., a first shrinkage PCM cell 431 and a second shrinkage PCM cell 451) between two external PCM cells (e.g., a first external PCM cell 411 and a second external PCM cell 471). For example, the 3D PCM device 400 may include four inner shrink PCM cells between two outer PCM cells. In some embodiments, the size of the outer PCM cells may be a baseline for all PCM cells, and the size of the shrink PCM cells is smaller than the size of the outer PCM cells. It should be noted that each shrink PCM cell may be smaller in the size of both the PCM element and the selector (i.e., including two elements), or it may be smaller in the size of the PCM element only. It should also be noted that a shrink PCM cell may refer to a PCM cell having a reduced thickness, width, or both.

[0043] Specifically, the first external PCM cell 411 includes a first bottom electrode 4171 formed on the lower bit line 421, a first selector 415 formed on the first bottom electrode 4171, a first intermediate electrode 4172 formed on the first selector 415, a first PCM element 413 formed on the first intermediate electrode 4172, and a first top electrode 4173 formed on the first PCM element 413. In some embodiments, a first adhesive layer or a pair of first adhesive layers 419 may be formed on, under, or on and under the first PCM element 413 to increase electrical contact between the PCM element and the electrode or reduce stress between the PCM element and the electrode. The first constriction PCM cell 431 includes a second bottom electrode 4371 formed on the lower word line 441, a second selector 435 formed on the second bottom electrode 4371, a second intermediate electrode 4372 formed on the second selector 435, a first constriction PCM element 433 formed on the second intermediate electrode 4372, and a second top electrode 4373 formed on the first constriction PCM element 433. In some embodiments, a second adhesive layer or a pair of second adhesive layers 439 may be formed on, under, or on and under the first shrink PCM element 433 to increase electrical contact between the PCM element and the electrode or reduce stress between the PCM element and the electrode. In some embodiments, the thickness of the first PCM element 413 is greater than the thickness of the first shrink PCM element 433. In some embodiments, the thickness of the first PCM element 413 may be 5% to 20%, for example, 10%, greater than the thickness of the first shrink PCM element 433. In some embodiments, the width of the first PCM element 413 is greater than the width of the first shrink PCM element 433. In some embodiments, the width of the first PCM element 413 may be 5% to 20%, for example, 10% greater than the width of the first shrink PCM element 433. In some embodiments, the thickness of the second PCM element of the second PCM unit 471 may be the same as the thickness of the first PCM element 413. In some embodiments, the width of the second shrink PCM element of the second shrink PCM unit 451 may be the same as the width of the first shrink PCM element 433. Therefore, the width of the first PCM element 413 is greater than the width of the first shrink PCM element 433, and the width of the second PCM element of the second PCM unit 471 is greater than the width of the second shrink PCM element of the second shrink PCM unit 451. In addition, the thickness of the first PCM element 413 is greater than the thickness of the first shrink PCM element 433, and the thickness of the second PCM element of the second PCM unit 471 is greater than the thickness of the second shrink PCM element of the second shrink PCM unit 451.

[0044] In some embodiments, electrodes 4171, 4172, 4173, 4371, 4372, and 4373 may include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, electrodes 4171, 4172, 4173, 4371, 4372, and 4373 may include a titanium nitride (TiN) layer. In some embodiments, the first intermediate electrode 4172 and the second intermediate electrode 4372 may be formed of amorphous carbon. Other electrodes in PCM units 411, 431, 451, and 471 may include the same or similar materials as electrodes 4171, 4172, 4173, 4371, 4372, and 4373.

[0045] In some embodiments, the selectors 415 and 435 may be bidirectional threshold switch (OTS) devices made of at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), antimony (Sb), silicon (Si), or arsenic (As). The OTS device is formed of an OTS material having OTS properties. Other selectors in the PCM units 411, 431, 451, and 471 may include the same or similar materials as the first selector 415 and the second selector 435.

[0046] In some embodiments, the first PCM element 413 and the first constricted PCM element 433 may include a chalcogenide component including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga). In some embodiments, the first PCM element 413 and the first constricted PCM element 433 may be a binary (two-element) compound, such as GaSb, InSb, InSe, SbTe, or GeTe; the first PCM element 413 and the first constricted PCM element 433 may be a ternary (three-element) compound, such as GeSbTe, GaSeTe, InSbTe, SnSbTe, or InSbGe; or the first PCM element 413 and the first constricted PCM element 433 may be a quaternary (four-element) compound, such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), or TeGeSbS. In some embodiments, the first PCM element 413 and the first constricted PCM element 433 may be GeSbTe. Other PCM elements and the shrinkage PCM elements in PCM cells 411, 431, 451, and 471 may include the same or similar materials as first PCM element 413 and first shrinkage PCM element 433. In some embodiments, the crystallization temperature of the PCM element of the inner cell (e.g., first shrinkage PCM element 433 of first shrinkage PCM cell 431) may be higher than the crystallization temperature of first PCM element 433. In some embodiments, during a programming operation, the crystallization temperature of the PCM element of the inner cell (e.g., first shrinkage PCM element 433 of first shrinkage PCM cell 431) may be maintained between 800K-900K. In some embodiments, the PCM element of the inner unit (e.g., the first shrinkage PCM element 433 of the first shrinkage PCM unit 431) may be further doped with carbon (C), while the PCM element of the outer unit (e.g., the first PCM element 413 of the first outer PCM unit 411) may not be doped with carbon or may be doped with less carbon than the first shrinkage PCM element 433, so that the crystallization temperature of the first shrinkage PCM element 433 may be higher than the crystallization temperature of the first PCM element 433.

[0047] It should be understood that the positions of the bit lines 421, 423, and 425 and the word lines 441 and 443 corresponding to the PCM cells 411, 431, 451, and 471 may be swapped according to different memory designs. In other words, the first bottom electrode 4171 may be formed on the word line, and the bit line may be formed on the first top electrode 4173.

[0048] In addition, the first isolation layer 418 may be formed on the sidewalls of the first outer PCM cell 411, and the second isolation layer 438 may be formed on the sidewalls of the first shrink PCM cell 431. Since the width of the first shrink PCM cell 431 may be reduced, the width of the second isolation layer 438 may be greater than the width of the first isolation layer 418. In some embodiments, the lateral distance between the shrink PCM cells (e.g., the first shrink PCM cell 431 and its laterally adjacent shrink PCM cells) is greater than the lateral distance between the outer PCM cells (e.g., the first outer PCM cell 411 and its laterally adjacent PCM cells). In some embodiments, the material of the isolation layers 418 and 438 may include at least one of silicon nitride (Si3N4), silicon dioxide (SiO2), aluminum nitride (AlN), or aluminum oxide (Al2O3).

[0049] Figure 5 A comparison of the resistance variation over operation time between a 3D PCM device with the same cell size and a 3D PCM device with a modified cell size according to some aspects of the present disclosure is shown. Figure 5 , the resistance of a 3D PCM device comprising a stack of four PCM cells having the same cell size may decrease over time due to thermal crosstalk and data retention issues. Crystallization in the amorphous phase accumulated during continuous operation causes the resistance to decrease over time. On the other hand, with the modified cell size as provided in the present disclosure, the decrease in resistance over time has been significantly reduced. In particular, since the internal cell with reduced thickness reduces the reset programming pulse amplitude requirement for reaching the amorphous temperature, there is less thermal crosstalk transmitted to adjacent cells, and thus the retention margin is increased. At the same time, the crystallization temperature of the internal cell increases with the reduction in thickness, and thus the inherent retention time is increased.

[0050] Figures 6A-6D An exemplary manufacturing process for forming an exemplary 3D PCM device having a shrunken PCM cell according to some aspects of the present disclosure is shown. And, Figure 7 A flow chart illustrating an exemplary method for forming an exemplary 3D PCM device having shrunken PCM cells according to some aspects of the present disclosure is shown. Figures 6A-6D and Figure 7 Examples of 3DPCM devices shown include Figure 4 The 3D PCM device 400 shown will be described together Figures 6A-6D and Figure 7 It should be understood that the operations shown in method 700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 7 The different orders shown are executed.

[0051] refer to Figure 7 , method 700 begins at operation 702, wherein one or more first PCM cells are deposited on one or more first bit lines, and each of the one or more first PCM cells includes a first PCM element. Fig. 6A In some embodiments, one or more first PCM cells (eg, first PCM cells 611) are deposited on one or more first bit lines (eg, first bit lines 621). Figure 2 One or more first bit lines (eg, first bit line 621, which may correspond to Figure 4 421) and one or more first PCM cells (eg, first PCM cell 611, which may correspond to Figure 4 To form a first PCM cell 611 having a first PCM element 613 on a first bit line 621, a first bottom electrode (eg, corresponding to Figure 4 A first bottom electrode 4171 in the embodiment of the present invention is deposited on the first bottom electrode, and a first selector (eg, corresponding to Figure 4 A first selector 415 in the embodiment of the present invention is deposited on the first selector, and a first intermediate electrode (eg, corresponding to Figure 4 A first intermediate electrode 4172 in the embodiment of the present invention is deposited on the first intermediate electrode, and a first PCM element 613 (eg, corresponding to Figure 4 4), depositing a first top electrode (eg, corresponding to the first PCM element 413 in FIG. 6 ) on the first PCM element 613. Figure 4 In some embodiments, the deposition may include using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, any other suitable deposition process, or any combination thereof. In some embodiments, the first PCM unit 611 is formed by depositing a first PCM stack (not shown) and etching the first PCM stack in a vertical direction (e.g., z-direction) to form one or more first PCM units (e.g., first PCM unit 611). The etching process includes wet etching, dry etching, or a combination thereof.

[0052] refer to Figure 7, the method 700 proceeds to operation 704, wherein one or more first word lines and one or more first systolic PCM cells are sequentially deposited on the corresponding one or more first PCM cells, each of which includes a first systolic PCM element. Figure 6B As shown, one or more first word lines (e.g., first word line 641) and one or more first shrinkage PCM cells (e.g., first shrinkage PCM cell 631) are sequentially deposited on corresponding one or more first PCM cells (including first PCM cell 611). Each of the one or more first shrinkage PCM cells (e.g., first shrinkage PCM cell 631) includes a first shrinkage PCM element 633. In order to form first shrinkage PCM cell 631 having first shrinkage PCM element 633 on first word line 641, a second bottom electrode (e.g., corresponding to first word line 641) is deposited on first word line 641. Figure 4 A second bottom electrode 4371 in the embodiment of the present invention is deposited on the second bottom electrode, and a second selector (eg, corresponding to Figure 4 A second selector 435 in the embodiment of the present invention is deposited on the second selector, and a second intermediate electrode (eg, corresponding to Figure 4 A second intermediate electrode 4372 in the embodiment of the present invention is deposited on the second intermediate electrode, and a first constricted PCM element 633 (eg, corresponding to Figure 4 A second top electrode (eg, corresponding to the first constricted PCM element 433 in FIG. 4 ) is deposited on the first constricted PCM element 633. Figure 4 In some embodiments, the deposition may include using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof. In some embodiments, the first shrink PCM unit 631 is formed by depositing a second PCM stack (not shown) and etching the second PCM stack in a vertical direction (e.g., z-direction) to form one or more first shrink PCM units (e.g., first shrink PCM unit 631). The etching process includes wet etching, dry etching, or a combination thereof.

[0053] In some embodiments, the width of each second trench 663 etched through the second PCM stack is greater than the width of each first trench 661 etched through the first PCM stack. Thus, the first shrink PCM cell 631 has a smaller width than the first PCM cell 611 .

[0054] refer to Figure 7 , the method 700 proceeds to operation 706, where one or more second bit lines and one or more second systolic PCM cells are sequentially deposited on the corresponding one or more first systolic PCM cells. Figure 6CAs shown, one or more second bit lines (e.g., second bit lines 623) and one or more second shrink PCM cells (e.g., second shrink PCM cells 651) are sequentially deposited on corresponding one or more first shrink PCM cells (e.g., first shrink PCM cells 631). Forming the second shrink PCM cell 651 having the second shrink PCM element 653 is similar to forming the first shrink PCM cell 631 having the first shrink PCM element 633. In some embodiments, the deposition may include using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof. In some embodiments, the second shrink PCM cell 651 is formed by depositing a third PCM stack (not shown) and etching the third PCM stack in a vertical direction (e.g., z-direction) to form one or more second shrink PCM cells (e.g., second shrink PCM cells 651). The etching process includes wet etching, dry etching, or a combination thereof.

[0055] In some embodiments, the width of each third groove 665 etched through the third PCM stack is greater than the width of each first groove 661 etched through the first PCM stack. Thus, the second shrink PCM unit 651 has a smaller width than the first PCM unit 611. In some embodiments, the width of each third groove 665 etched through the third PCM stack is the same as the width of each second groove 663 etched through the second PCM stack. Thus, the second shrink PCM unit 651 has the same width as the first shrink PCM unit 631.

[0056] refer to Figure 7 , the method 700 proceeds to operation 708, where one or more second word lines and one or more second PCM cells are sequentially formed on the corresponding one or more second shrinkage PCM cells. Fig.6DAs shown, one or more second word lines (e.g., second word lines 643) and one or more second PCM cells (e.g., second PCM cells 671) are sequentially deposited on corresponding one or more second shrinkage PCM cells (e.g., second shrinkage PCM cells 651). Forming the second PCM cell 671 having the second PCM element 673 is similar to forming the first PCM cell 611 having the first PCM element 613. In some embodiments, the deposition may include using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof. In some embodiments, the second PCM cell 671 is formed by depositing a fourth PCM stack (not shown) and etching the fourth PCM stack in a vertical direction (e.g., z-direction) to form one or more second PCM cells (e.g., second PCM cells 671). The etching process includes wet etching, dry etching, or a combination thereof.

[0057] In some embodiments, the width of each fourth groove 667 etched through the fourth PCM stack is smaller than the width of each third groove 665 etched through the third PCM stack. Thus, the second PCM cell 671 has a width greater than the second shrink PCM cell 651. In some embodiments, the width of each fourth groove 667 etched through the fourth PCM stack is the same as the width of each first groove 661 etched through the first PCM stack. Thus, the second PCM cell 671 has the same width as the first PCM cell 611.

[0058] refer to Figure 7 , method 700 proceeds to operation 710, where one or more third bit lines are formed on one or more second PCM cells. Fig.6D As shown, one or more third bit lines (e.g., third bit line 625) are deposited on corresponding one or more second PCM cells (e.g., second PCM cell 671). In some embodiments, deposition may include using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof.

[0059] According to one aspect of the present disclosure, a three-dimensional (3D) phase change memory (PCM) device includes a first PCM cell, a first shrinkage PCM cell on the first PCM cell, a second shrinkage PCM cell on the first shrinkage PCM cell, and a second PCM cell on the second shrinkage PCM cell. The first PCM cell includes a first PCM element, the first shrinkage PCM cell includes a first shrinkage PCM element, the second shrinkage PCM cell includes a second shrinkage PCM element, and the second PCM cell includes a second PCM element. The width of the first PCM element is greater than the width of the first shrinkage PCM element, and the width of the second PCM element is greater than the width of the second shrinkage PCM element.

[0060] In some embodiments, the width of the first PCM element is 5% to 20% greater than the width of the first constricted PCM element, and the width of the second PCM element is 5% to 20% greater than the width of the second constricted PCM element.

[0061] In some embodiments, the thickness of the first PCM element is greater than the thickness of the first constricted PCM element, and the thickness of the second PCM element is greater than the thickness of the second constricted PCM element.

[0062] In some embodiments, the thickness of the first PCM element is 5% to 20% greater than the thickness of the first shrink PCM element, and the thickness of the second PCM element is 5% to 20% greater than the thickness of the second shrink PCM element.

[0063] In some embodiments, the width of the first PCM cell is greater than the width of the first shrink PCM cell, and the width of the second PCM cell is greater than the width of the second shrink PCM cell.

[0064] In some embodiments, the width of the first shrink PCM cell is the same as the width of the second shrink PCM cell, and the width of the second PCM cell is the same as the width of the first PCM cell.

[0065] In some embodiments, the crystallization temperature of the first shrinkage PCM element is higher than the crystallization temperature of the first PCM element.

[0066] In some embodiments, the material of the first PCM element and the first constriction PCM element includes a chalcogenide component including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga).

[0067] In some embodiments, the first constrictive PCM element is doped with carbon (C), and the first PCM element is not doped with carbon, or is doped with less carbon than the first constrictive PCM element.

[0068] In some embodiments, the 3D PCM device further comprises a lower bit line, a lower word line, a middle bit line, an upper word line, an upper bit line, a first PCM cell is formed between the lower bit line and the lower word line, a first systolic PCM cell is formed between the lower word line and the middle bit line, a second systolic PCM cell is formed between the middle bit line and the upper word line, and a second PCM cell is formed between the upper word line and the upper bit line.

[0069] In some embodiments, in a plan view, the lower bit line intersects the lower word line, the lower word line intersects the middle bit line, the middle bit line intersects the upper word line, and the upper word line intersects the upper bit line.

[0070] In some embodiments, the first PCM cell includes a first bottom electrode formed on the lower bit line, a first selector formed on the first bottom electrode, a first middle electrode formed on the first selector, a first PCM element formed on the first middle electrode, and a first top electrode formed on the first PCM element. The first constricted PCM cell includes a second bottom electrode formed on the lower word line, a second selector formed on the second bottom electrode, a second middle electrode formed on the second selector, a first constricted PCM element formed on the second middle electrode, and a second top electrode formed on the first constricted PCM element.

[0071] In some embodiments, the 3D PCM device further includes a pair of first adhesive layers formed above and below the first PCM element, and a pair of second adhesive layers formed above and below the first shrink PCM element.

[0072] In some embodiments, the 3D PCM device further includes a first isolation layer formed on a sidewall of the first PCM cell, and a second isolation layer formed on a sidewall of the first shrink PCM cell.

[0073] According to another aspect of the present disclosure, a three-dimensional (3D) phase change memory (PCM) device includes: one or more first PCM cells, each of which includes a first PCM element; one or more first shrinkage PCM cells on the corresponding one or more first PCM cells, each of which includes a first shrinkage PCM element; one or more second shrinkage PCM cells on the corresponding one or more first shrinkage PCM cells, each of which includes a second shrinkage PCM element; and one or more second PCM cells on the corresponding one or more second shrinkage PCM cells, each of which includes a second PCM element. The width of the first PCM element is greater than the width of the first shrinkage PCM element, and the width of the second PCM element is greater than the width of the second shrinkage PCM element.

[0074] In some embodiments, the width of the first PCM element is 5% to 20% greater than the width of the first constricted PCM element, and the width of the second PCM element is 5% to 20% greater than the width of the second constricted PCM element.

[0075] In some embodiments, the thickness of the first PCM element is greater than the thickness of the first constricted PCM element, and the thickness of the second PCM element is greater than the thickness of the second constricted PCM element.

[0076] In some embodiments, the thickness of the first PCM element is 5% to 20% greater than the thickness of the first shrink PCM element, and the thickness of the second PCM element is 5% to 20% greater than the thickness of the second shrink PCM element.

[0077] In some embodiments, the width of the first PCM cell is greater than the width of the first shrink PCM cell, and the width of the second PCM cell is greater than the width of the second shrink PCM cell.

[0078] In some embodiments, the width of the first shrink PCM cell is the same as the width of the second shrink PCM cell, and the width of the second PCM cell is the same as the width of the first PCM cell.

[0079] In some embodiments, the crystallization temperature of the first shrinkage PCM element is higher than the crystallization temperature of the first PCM element.

[0080] In some embodiments, the material of the first PCM element and the first constriction PCM element includes a chalcogenide component including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga).

[0081] In some embodiments, the first constrictive PCM element is doped with carbon (C), and the first PCM element is not doped with carbon, or is doped with less carbon than the first constrictive PCM element.

[0082] In some embodiments, the 3D PCM device further includes one or more lower bit lines, one or more lower word lines, one or more middle bit lines, one or more upper word lines, and one or more upper bit lines. A first PCM cell is formed between a corresponding lower bit line of the one or more lower bit lines and a corresponding lower word line of the one or more lower word lines, a first systolic PCM cell is formed between a corresponding lower word line of the one or more lower word lines and a corresponding middle bit line of the one or more middle bit lines, a second systolic PCM cell is formed between a corresponding middle bit line of the one or more middle bit lines and a corresponding upper word line of the one or more upper word lines, and a second PCM cell is formed between a corresponding upper word line of the one or more upper word lines and a corresponding upper bit line of the one or more upper bit lines.

[0083] In some embodiments, in a plan view, one or more lower bit lines intersect with corresponding one or more lower word lines, one or more lower word lines intersect with corresponding one or more middle bit lines, one or more middle bit lines intersect with corresponding one or more upper word lines, and one or more upper word lines intersect with corresponding one or more upper bit lines.

[0084] In some embodiments, the 3D PCM device further includes one or more first isolation layers separating the one or more first PCM cells, and one or more second isolation layers separating the one or more first shrinkage PCM cells.

[0085] According to yet another aspect of the present disclosure, a method for forming a three-dimensional (3D) phase change memory (PCM) device includes: depositing one or more first PCM cells on corresponding one or more first bit lines, each first PCM cell including a first PCM element; sequentially depositing one or more first word lines and one or more first systolic PCM cells on corresponding one or more first PCM cells, each first systolic PCM cell including a first systolic PCM element; sequentially depositing one or more second bit lines and one or more second systolic PCM cells on corresponding one or more first systolic PCM cells, each second systolic PCM cell including a second systolic PCM element; sequentially depositing one or more second word lines and one or more second PCM cells on corresponding one or more second systolic PCM cells, each second PCM cell including a second PCM element; and depositing one or more third bit lines on corresponding one or more second PCM cells.

[0086] In some embodiments, the method further comprises depositing the one or more first bit lines on the substrate before depositing the one or more first PCM cells on the one or more first bit lines.

[0087] In some embodiments, depositing one or more first PCM cells comprises: depositing a first PCM stack; and etching the first PCM stack in a vertical direction to form one or more first PCM cells. Depositing one or more first shrinking PCM cells comprises: depositing a second PCM stack; and etching the second PCM stack in a vertical direction to form one or more first shrinking PCM cells. Depositing one or more second shrinking PCM cells comprises: depositing a third PCM stack; and etching the third PCM stack in a vertical direction to form one or more second shrinking PCM cells. Depositing one or more second shrinking PCM cells comprises: depositing a fourth PCM stack; and etching the fourth PCM stack in a vertical direction to form one or more second PCM cells.

[0088] In some embodiments, the width of each second groove etched through the second PCM stack is greater than the width of each first groove etched through the first PCM stack, and the width of each third groove etched through the third PCM stack is greater than the width of each fourth groove etched through the fourth PCM stack.

[0089] In some embodiments, the width of each third groove etched through the third PCM stack is the same as the width of each second groove etched through the second PCM stack, and the width of each first groove etched through the first PCM stack is the same as the width of each fourth groove etched through the fourth PCM stack.

[0090] The above description of the specific embodiments will fully reveal the overall nature of the present disclosure, so that others can easily modify and / or change the various applications of these specific embodiments by applying the knowledge in the art, but without excessive experimentation, and without departing from the overall concept of the present disclosure. Therefore, based on the teachings and guidance given herein, these changes and modifications are intended to be within the meaning and scope of the equivalent transformations of the disclosed embodiments. It should be understood that the wording or terminology herein is for the purpose of description rather than limitation, so that the terms or wording of this specification will be interpreted by those skilled in the art based on the teachings and guidance.

[0091] The embodiments of the present disclosure have been described above with the aid of functional building blocks, which illustrate the embodiments of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. As long as the specific functions and their relationships are properly performed, replaceable boundaries can be defined.

[0092] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by one or more inventors, and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0093] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) phase change memory (PCM) device, comprising: A first PCM unit; a first contraction PCM unit on the first PCM unit; a second shrinkage PCM unit on the first shrinkage PCM unit; as well as a second PCM cell on the second shrink PCM cell, wherein the first PCM cell comprises a first PCM element, the first shrink PCM cell comprises a first shrink PCM element, the second shrink PCM cell comprises a second shrink PCM element, and the second PCM cell comprises a second PCM element, and wherein a width of the first PCM element is greater than a width of the first shrink PCM element, and a width of the second PCM element is greater than a width of the second shrink PCM element.

2. The three-dimensional phase change memory device according to claim 1, wherein: The width of the first PCM element is 5% to 20% greater than the width of the first constricted PCM element, and the width of the second PCM element is 5% to 20% greater than the width of the second constricted PCM element.

3. The three-dimensional phase change memory device according to claim 1, wherein: The thickness of the first PCM element is greater than the thickness of the first shrinkage PCM element, and the thickness of the second PCM element is greater than the thickness of the second shrinkage PCM element.

4. The three-dimensional phase change memory device according to claim 3, wherein: The thickness of the first PCM element is 5% to 20% greater than the thickness of the first shrinkage PCM element, and the thickness of the second PCM element is 5% to 20% greater than the thickness of the second shrinkage PCM element.

5. The three-dimensional phase change memory device according to any one of claims 1 to 4, wherein: The width of the first PCM cell is greater than the width of the first shrinkage PCM cell, and the width of the second PCM cell is greater than the width of the second shrinkage PCM cell.

6. The three-dimensional phase change memory device according to any one of claims 1 to 4, wherein: A width of the first shrinkage PCM cell is the same as a width of the second shrinkage PCM cell, and a width of the second PCM cell is the same as a width of the first PCM cell.

7. The three-dimensional phase change memory device according to any one of claims 1 to 4, wherein: The crystallization temperature of the first shrinkage PCM element is higher than the crystallization temperature of the first PCM element.

8. The three-dimensional phase change memory device according to any one of claims 1 to 4, wherein: The material of the first PCM element and the first constriction PCM element includes a chalcogenide component including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga).

9. The three-dimensional phase change memory device according to any one of claims 1 to 4, wherein: The first constrictive PCM element is doped with carbon (C), and the first PCM element is not doped with carbon or is doped with less carbon than the first constrictive PCM element.

10. The three-dimensional phase change memory device according to any one of claims 1 to 4, further comprising: Lower line; Lower word line; Middle bit line; Upper word line; as well as an upper bit line, wherein the first PCM cell is formed between the lower bit line and the lower word line, the first systolic PCM cell is formed between the lower word line and the middle bit line, the second systolic PCM cell is formed between the middle bit line and the upper word line, and the second PCM cell is formed between the upper word line and the upper bit line.

11. The three-dimensional phase change memory device according to claim 10, wherein: In a plan view, the lower bit line intersects the lower word line, the lower word line intersects the middle bit line, the middle bit line intersects the upper word line, and the upper word line intersects the upper bit line.

12. The three-dimensional phase change memory device according to claim 11, wherein: The first PCM unit comprises: a first bottom electrode formed on the lower bit line, a first selector formed on the first bottom electrode, a first intermediate electrode formed on the first selector, the first PCM element formed on the first intermediate electrode, and a first top electrode formed on the first PCM element, and wherein the first constricted PCM cell comprises: A second bottom electrode formed on the lower word line, a second selector formed on the second bottom electrode, a second intermediate electrode formed on the second selector, the first constricted PCM element formed on the second intermediate electrode, and A second top electrode is formed on the first constrictive PCM element.

13. The three-dimensional phase change memory device according to any one of claims 1 to 4 and 11 to 12, further comprising: a pair of first adhesive layers formed above and below the first PCM element; as well as A pair of second adhesive layers are formed above and below the first shrink PCM element.

14. The three-dimensional phase change memory device according to any one of claims 1 to 4 and 11 to 12, further comprising: a first isolation layer formed on a sidewall of the first PCM unit; as well as A second isolation layer is formed on the sidewalls of the first constricted PCM unit.

15. A three-dimensional (3D) phase change memory (PCM) device, comprising: one or more first PCM cells, each first PCM cell comprising a first PCM element; one or more first contraction PCM units on corresponding said one or more first PCM units, each first contraction PCM unit comprising a first contraction PCM element; one or more second shrink PCM units on the corresponding one or more first shrink PCM units, each second shrink PCM unit comprising a second shrink PCM element; as well as One or more second PCM cells on the corresponding one or more second constricted PCM cells, each second PCM cell comprising a second PCM element, wherein a width of the first PCM element is greater than a width of the first constricted PCM element, and a width of the second PCM element is greater than a width of the second constricted PCM element.

16. The three-dimensional phase change memory device according to claim 15, wherein: The width of the first PCM element is 5% to 20% greater than the width of the first constricted PCM element, and the width of the second PCM element is 5% to 20% greater than the width of the second constricted PCM element.

17. The three-dimensional phase change memory device according to claim 15, wherein: The thickness of the first PCM element is greater than the thickness of the first shrinkage PCM element, and the thickness of the second PCM element is greater than the thickness of the second shrinkage PCM element.

18. The three-dimensional phase change memory device according to claim 17, wherein: The thickness of the first PCM element is 5% to 20% greater than the thickness of the first shrinkage PCM element, and the thickness of the second PCM element is 5% to 20% greater than the thickness of the second shrinkage PCM element.

19. The three-dimensional phase change memory device according to any one of claims 15 to 18, wherein: The width of the first PCM cell is greater than the width of the first shrinkage PCM cell, and the width of the second PCM cell is greater than the width of the second shrinkage PCM cell.

20. The three-dimensional phase change memory device according to any one of claims 15 to 18, wherein: A width of the first shrinkage PCM cell is the same as a width of the second shrinkage PCM cell, and a width of the second PCM cell is the same as a width of the first PCM cell.

21. The three-dimensional phase change memory device according to any one of claims 15 to 18, wherein: The crystallization temperature of the first shrinkage PCM element is higher than the crystallization temperature of the first PCM element.

22. The three-dimensional phase change memory device according to any one of claims 15 to 18, wherein: The material of the first PCM element and the first constriction PCM element includes a chalcogenide component including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga).

23. The three-dimensional phase change memory device according to any one of claims 15 to 18, wherein: The first constrictive PCM element is doped with carbon (C), and the first PCM element is not doped with carbon or is doped with less carbon than the first constrictive PCM element.

24. The three-dimensional phase change memory device according to any one of claims 15 to 18, further comprising: one or more hyponyms; one or more underline; one or more intermediate bit lines; one or more upper character lines; as well as one or more upper bit lines, wherein the first PCM cell is formed between a corresponding lower bit line of the one or more lower bit lines and a corresponding lower word line of the one or more lower word lines, the first systolic PCM cell is formed between the corresponding lower word line of the one or more lower word lines and a corresponding middle bit line of the one or more middle bit lines, the second systolic PCM cell is formed between the corresponding middle bit line of the one or more middle bit lines and a corresponding upper word line of the one or more upper word lines, and the second PCM cell is formed between the corresponding upper word line of the one or more upper word lines and a corresponding upper bit line of the one or more upper bit lines.

25. The three-dimensional phase change memory device according to claim 24, wherein: In a plan view, the one or more lower bit lines intersect with the corresponding one or more lower word lines, the one or more lower word lines intersect with the corresponding one or more middle bit lines, the one or more middle bit lines intersect with the corresponding one or more upper word lines, and the one or more upper word lines intersect with the corresponding one or more upper bit lines.

26. The three-dimensional phase change memory device according to any one of claims 15 to 18 and 25, further comprising: one or more first isolation layers separating the one or more first PCM cells; as well as One or more second isolation layers separating the one or more first shrinkage PCM cells.

27. A method for forming a three-dimensional (3D) phase change memory (PCM) device, comprising: depositing one or more first PCM cells on the one or more first bit lines, each first PCM cell comprising a first PCM element; depositing one or more first word lines and one or more first systolic PCM cells in sequence on the corresponding one or more first PCM cells, each first systolic PCM cell comprising a first systolic PCM element; sequentially depositing one or more second bit lines and one or more second systolic PCM cells on the corresponding one or more first systolic PCM cells, each second systolic PCM cell comprising a second systolic PCM element; sequentially depositing one or more second word lines and one or more second PCM cells on the corresponding one or more second shrinkage PCM cells, each second PCM cell comprising a second PCM element; as well as depositing one or more third bit lines on corresponding said one or more second PCM cells, Wherein, the width of the first PCM element is greater than the width of the first shrinkage PCM element, and the width of the second PCM element is greater than the width of the second shrinkage PCM element.

28. The method according to claim 27, further comprising: The one or more first bit lines are deposited on the substrate before depositing the one or more first PCM cells on the corresponding one or more first bit lines.

29. The method according to claim 27 or 28, wherein: Depositing the one or more first PCM units includes: depositing a first PCM stack and etching the first PCM stack in a vertical direction to form the one or more first PCM units, Wherein, depositing the one or more first shrink PCM units comprises: depositing a second PCM stack and etching the second PCM stack in the vertical direction to form the one or more first shrink PCM units, wherein depositing the one or more second shrinkage PCM units comprises: depositing a third PCM stack and etching the third PCM stack in the vertical direction to form the one or more second shrinkage PCM units, and Wherein, depositing the one or more second shrink PCM units comprises: depositing a fourth PCM stack and etching the fourth PCM stack in the vertical direction to form the one or more second PCM units.

30. The method of claim 29, wherein: Each second groove etched through the second PCM stack has a width greater than each first groove etched through the first PCM stack, and each third groove etched through the third PCM stack has a width greater than each fourth groove etched through the fourth PCM stack.

31. The method according to claim 30, wherein: Each third groove etched through the third PCM stack has the same width as each second groove etched through the second PCM stack, and wherein each first groove etched through the first PCM stack has the same width as each fourth groove etched through the fourth PCM stack.

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