Power-on reset circuit and electronic equipment

Abstract

The present invention discloses a power-on reset circuit and electronic device. The power-on reset circuit includes first, second, and third voltage-dividing resistors, a PNP transistor, a comparator, and a first inverter. The first voltage-dividing resistor, a power supply end of the comparator, and a power supply end of the first inverter are all connected to an input power supply. The first voltage-dividing resistor is connected to the second and third voltage-dividing resistors and the first input end of the comparator. The second voltage-dividing resistor is connected to the second input end of the comparator and the emitter of the PNP transistor. The third voltage-dividing resistor, the base and collector of the PNP transistor, the ground end of the comparator, and the ground end of the first inverter are all grounded. The output end of the comparator is connected to the input end of the first inverter. The output end of the first inverter outputs a reset signal. The present invention uses a structure similar to a bandgap reference to achieve variable reset levels. The PNP transistor does not require an additional mask layer, making process transplantation easier, thereby achieving a low-cost design.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a power-on reset circuit and electronic equipment. Background Art

[0002] The power-on reset circuit is a critical component of integrated circuits. Its primary function is to provide a reset signal to the system, allowing the integrated circuit to enter a defined state. In addition to using RC delay to generate the reset signal, existing power-on reset circuits primarily generate the reset signal through voltage level detection. Based on the principle of a bandgap reference, NPN transistors are used in power-on reset circuits to minimize the impact of process fluctuations on the reset level. However, in such power-on reset circuits, the reset level is fixed to the bandgap reference voltage, making it immutable. Furthermore, the NPN transistor requires additional mask layers, increasing circuit design costs. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the defects of the prior art power-on reset circuit, such as high cost and unchangeable reset level, and to provide a power-on reset circuit and electronic equipment.

[0004] The present invention solves the above technical problems through the following technical solutions:

[0005] According to a first aspect of the present invention, a power-on reset circuit is provided, comprising a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, a PNP transistor, a comparator, and a first inverter:

[0006] One end of the first voltage-dividing resistor, the power supply end of the comparator, and the power supply end of the first inverter are all connected to an input power supply; the other end of the first voltage-dividing resistor is respectively connected to one end of the second voltage-dividing resistor, one end of the third voltage-dividing resistor, and the first input end of the comparator; the other end of the second voltage-dividing resistor is respectively connected to the second input end of the comparator and the emitter of the PNP transistor;

[0007] The other end of the third voltage-dividing resistor, the base and collector of the PNP transistor, the grounding end of the comparator and the grounding end of the first inverter are all grounded;

[0008] The output end of the comparator is connected to the input end of the first inverter; the output end of the first inverter is used to output a reset signal.

[0009] Preferably, the comparator includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor:

[0010] The source of the first PMOS transistor and the source of the second PMOS transistor are connected to form a power supply terminal of the comparator;

[0011] The gate of the second NMOS transistor is connected to the other end of the first voltage-dividing resistor to form a first input end of the comparator;

[0012] The gate of the first NMOS transistor is connected to the other end of the second voltage-dividing resistor to form a second input end of the comparator;

[0013] The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor to form an output end of the comparator;

[0014] The source of the first NMOS transistor and the source of the second NMOS transistor are connected to form a ground terminal of the comparator;

[0015] The drain of the first PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the first NMOS transistor respectively.

[0016] Preferably, the power-on reset circuit includes a current limiting resistor:

[0017] The ground terminal of the comparator is grounded through the current limiting resistor.

[0018] Preferably, the first inverter includes a third PMOS transistor and a third NMOS transistor:

[0019] The source of the third PMOS transistor is connected to one end of the first voltage-dividing resistor to form a power supply end of the first inverter;

[0020] The gate of the third PMOS transistor is connected to the gate of the third NMOS transistor to form an input end of the first inverter;

[0021] The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor to form an output end of the first inverter;

[0022] The source of the third NMOS transistor is connected to the other end of the third voltage-dividing resistor to form a ground terminal of the first inverter.

[0023] Preferably, the power-on reset circuit further includes a filter circuit:

[0024] The input end of the filter circuit is connected to the output end of the first inverter, and the output end of the filter circuit is used to output a reset signal.

[0025] Preferably, the power-on reset circuit further includes a driving circuit:

[0026] The power supply terminal of the driving circuit is connected to the input power supply; the ground terminal of the driving circuit is grounded;

[0027] The input end of the driving circuit is connected to the output end of the filtering circuit;

[0028] The output end of the driving circuit is used to output a reset signal.

[0029] Preferably, the driving circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor:

[0030] The gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor to form an input end of the driving circuit;

[0031] The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor to form an output end of the driving circuit;

[0032] The source of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor to form a power supply end of the driving circuit;

[0033] The source of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor to form a ground terminal of the driving circuit;

[0034] The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fifth PMOS transistor, and the gate of the fifth NMOS transistor respectively.

[0035] According to a second aspect of the present invention, an electronic device is provided. The electronic device includes an integrated circuit and the power-on reset circuit of the present invention. The reset signal output by the power-on reset circuit is used to power-on reset the integrated circuit.

[0036] The positive progress effect of the present invention is:

[0037] The bandgap reference-like structure not only reduces process fluctuations in the reset level, but also allows for adjustment of the reset level by varying the resistor ratio, achieving variable reset levels. Furthermore, the present invention primarily utilizes MOS transistors and PNP transistors to design a power-on reset circuit. PNP transistors do not require additional mask layers, making them easier to transplant, thus achieving a low-cost design. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic diagram of the circuit structure of a power-on reset circuit provided in Example 1 of the present invention.

[0039] Figure 2 This is a schematic diagram of the circuit structure of another power-on reset circuit provided in Example 1 of the present invention.

[0040] Figure 3 A schematic diagram of the circuit structure of a power-on reset circuit provided in Example 2 of the present invention.

[0041] Figure 4 This is a schematic diagram of the circuit structure of a power-on reset circuit provided in Example 3 of the present invention. DETAILED DESCRIPTION

[0042] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.

[0043] Example 1

[0044] This embodiment provides a power-on reset circuit, such as Figure 1 As shown, it includes a first voltage-dividing resistor R1, a second voltage-dividing resistor R2, a third voltage-dividing resistor R3, a PNP transistor Q, a comparator CM and a first inverter F1:

[0045] One end of the first voltage-dividing resistor R1, the power supply end of the comparator CM, and the power supply end of the first inverter F1 are all connected to the input power supply VDD; the other end of the first voltage-dividing resistor R1 is respectively connected to one end of the second voltage-dividing resistor R2, one end of the third voltage-dividing resistor R3, and the first input end of the comparator F1; the other end of the second voltage-dividing resistor R2 is respectively connected to the second input end of the comparator CM and the emitter of the PNP transistor Q; the other end of the third voltage-dividing resistor R3, the base and collector of the PNP transistor Q, the ground end of the comparator CM, and the ground end of the first inverter F1 are all connected to ground VSS; the output end of the comparator CM is connected to the input end of the first inverter F1; and the output end of the first inverter F1 is used to output a reset signal RST1.

[0046] As an optional implementation, the comparator includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, and a second NMOS transistor NM2:

[0047] The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are connected to form a power supply terminal of the comparator CM; the gate of the second NMOS transistor NM2 is connected to the other end of the first voltage-dividing resistor R1, forming a first input terminal of the comparator CM; the gate of the first NMOS transistor NM1 is connected to the other end of the second voltage-dividing resistor R2, forming a second input terminal of the comparator CM; the drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2, forming an output terminal of the comparator CM; the source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2 are connected to form a ground terminal of the comparator CM; the drain of the first PMOS transistor PM1 is connected to the gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, and the drain of the first NMOS transistor NM1, respectively.

[0048] As an optional implementation, Figure 2 As shown, the power-on reset circuit includes a current-limiting resistor R4 , and the ground terminal of the comparator CM is grounded through the current-limiting resistor R4 , and the current-limiting resistor R4 is used to limit the power consumption of the comparator.

[0049] As an optional implementation, Figure 2 As shown, the first inverter F1 includes a third PMOS transistor PM1 and a third NMOS transistor NM2:

[0050] The source of the third PMOS transistor PM3 is connected to one end of the first voltage-dividing resistor R1, forming a power supply terminal of the first inverter F1; the gate of the third PMOS transistor PM3 is connected to the gate of the third NMOS transistor NM3, forming an input terminal of the first inverter F1; the drain of the third PMOS transistor PM3 is connected to the drain of the third NMOS transistor NM3, forming an output terminal of the first inverter F1; and the source of the third NMOS transistor NM3 is connected to the other end of the third voltage-dividing resistor R3, forming a ground terminal of the first inverter F1.

[0051] According to an analysis of the circuit of this embodiment, when power is initially applied, the input power supply voltage VDD is low, and the current flowing through the second voltage-divider resistor R2 is very small. At this point, the voltage difference between points A and B is approximately zero. By setting the first NMOS transistor NM1 to be larger than the second NMOS transistor NM2, the first NMOS transistor NM1 is ensured to conduct first, and the second NMOS transistor NM2 is turned on later. The current flowing through the first NMOS transistor NM1 is greater than the current flowing through the second NMOS transistor NM2, causing the voltage output at the output terminal VOUT of the comparator CM to approach the supply voltage. As the supply voltage gradually increases, the voltage difference between points A and B gradually increases, thereby gradually reducing the current difference between the current flowing through the first NMOS transistor NM1 and the current flowing through the second NMOS transistor NM2. The first PMOS transistor PM1 and the second PMOS transistor PM2 form a current mirror structure, performing a 1:1 replication of the current flowing through the first NMOS transistor NM1 and the current flowing through the second NMOS transistor NM2, respectively.

[0052] When the power supply voltage rises to a certain level, the current flowing through the first NMOS transistor NM1 and the current flowing through the second NMOS transistor NM2 are equal. At this time, the power supply voltage VDD of the input power supply is equal to the reset level, and the voltage output by the output terminal VOUT of the comparator is close to the ground voltage VSS. The voltage level is converted by the first inverter F1, and the output terminal of the inverter F1 outputs the reset signal RST1 from low level to high level.

[0053] When the power supply voltage VDD of the input power supply rises to the reset level, the first voltage divider resistor R1, the second voltage divider resistor R2, the third voltage divider resistor R3, the first NMOS transistor NM1, the second NMOS transistor NM2, and the PNP transistor Q actually form a bandgap reference structure. Among them, the first NMOS transistor NM1, the second NMOS transistor NM2 and the second voltage divider resistor R2 are used to realize the positive temperature coefficient PTAT current; the PNP transistor Q is used to realize the negative temperature coefficient voltage V BE The third voltage divider resistor R3 is used to change the reset level to achieve variable reset level. Set the reset level to V RST , based on the analysis of the above circuit principle, its reset level is V RST The formula is as follows:

[0054]

[0055] Among them, V BE is the voltage difference between the base and emitter of the PNP transistor Q, which has a negative temperature coefficient; is a positive temperature coefficient, where K is the Boltzmann constant, T is the thermodynamic temperature, q is the electron load, and ζ n is a process parameter of the MOS transistor, N is a ratio of the width to length of the first NMOS transistor NM1 to the second NMOS transistor NM2, and as an optional implementation manner, N is set to be ≥2.

[0056] In the above formula, based on the principle of bandgap reference, the positive temperature coefficient is adjusted by adjusting the ratio of the first voltage divider resistor R1, the second voltage divider resistor R2 and the third voltage divider resistor R3, so that the negative temperature coefficient voltage VBE and the positive temperature coefficient voltage The reset level V is adjusted by adjusting the ratio of the first voltage divider resistor R1 to the third voltage divider resistor R3. RST , to achieve variable reset level.

[0057] In this embodiment, a structure similar to a bandgap reference is used to reduce process fluctuations in the reset level. Furthermore, the reset level can be adjusted by varying the resistor ratio, achieving variable reset levels. Furthermore, this embodiment primarily utilizes MOS transistors and PNP transistors to design the power-on reset circuit. PNP transistors do not require additional mask layers, making them easier to migrate to other processes and thus achieving a low-cost design.

[0058] Example 2

[0059] This embodiment is a further improvement on embodiment 1. Figure 3As shown, in order to improve the reliability of the entire power-on reset circuit, a filter circuit is added after the output end of the first inverter. The filter circuit is used to filter out possible glitch signals in the reset signal RST1 and then output the reset signal RST2.

[0060] Example 3

[0061] This embodiment is a further improvement on embodiment 2. Figure 4 As shown, a driving circuit F2 is added after the output end of the filter circuit. The driving circuit F2 is used to improve the driving capability of the reset signal RST2 to drive subsequent digital circuits and output the final reset signal RST3.

[0062] As an optional implementation, Figure 3 As shown, the driving circuit F2 includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a fourth NMOS transistor NM4 and a fifth NMOS transistor NM5:

[0063] The gate of the fourth PMOS transistor PM4 is connected to the gate of the fourth NMOS transistor NM4, forming an input terminal of the drive circuit F2; the drain of the fifth PMOS transistor PM5 is connected to the drain of the fifth NMOS transistor NM5, forming an output terminal of the drive circuit F2; the source of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5, forming a power supply terminal of the drive circuit F2; the source of the fourth NMOS transistor NM4 is connected to the source of the fifth NMOS transistor NM5, forming a ground terminal of the drive circuit F2; and the drain of the fourth PMOS transistor PM4 is connected to the drain of the fourth NMOS transistor NM4, the gate of the fifth PMOS transistor PM5, and the gate of the fifth NMOS transistor NM5, respectively.

[0064] Example 4

[0065] This embodiment provides an electronic device, which includes an integrated circuit and the power-on reset circuit of Example 1, Example 2, or Example 3. The integrated circuit is powered on and reset by the reset signal output by the power-on reset circuit of Example 1, Example 2, or Example 3. The selection can be based on the cost and other requirements of the actual electronic device.

[0066] Since the power-on reset circuits in Examples 1, 2, and 3 have the advantages of variable reset level, low cost, low power consumption, and small size, electronic devices only need to provide a smaller layout area for the power-on reset circuit to have a power-on reset function, which not only ensures the high reliability of the electronic device but also reduces the circuit design cost of the entire electronic device.

[0067] Although specific embodiments of the present invention have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, and such changes and modifications are intended to fall within the scope of the present invention.

Claims

1. A power-on reset circuit, characterized in that: The power-on reset circuit includes a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, a PNP transistor, a comparator and a first inverter: One end of the first voltage-dividing resistor, the power supply end of the comparator, and the power supply end of the first inverter are all connected to the input power supply; the other end of the first voltage-dividing resistor is respectively connected to one end of the second voltage-dividing resistor, one end of the third voltage-dividing resistor, and the first input end of the comparator; The other end of the second voltage-dividing resistor is connected to the second input end of the comparator and the emitter of the PNP transistor respectively; The other end of the third voltage-dividing resistor, the base and collector of the PNP transistor, the grounding end of the comparator and the grounding end of the first inverter are all grounded; The output end of the comparator is connected to the input end of the first inverter; the output end of the first inverter is used to output a reset signal; The comparator includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor: The source of the first PMOS transistor and the source of the second PMOS transistor are connected to form a power supply terminal of the comparator; The gate of the second NMOS transistor is connected to the other end of the first voltage-dividing resistor to form a first input end of the comparator; The gate of the first NMOS transistor is connected to the other end of the second voltage-dividing resistor to form a second input end of the comparator; The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor to form an output end of the comparator; The source of the first NMOS transistor and the source of the second NMOS transistor are connected to form a ground terminal of the comparator; The drain of the first PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the first NMOS transistor respectively; The reset signal corresponds to the reset level V RST The formula is: Among them, R1 is the first voltage divider resistor, R2 is the second voltage divider resistor, R3 is the third voltage divider resistor, V BE is the voltage difference between the base and emitter of the PNP transistor Q, and the voltage difference has a negative temperature coefficient; is a positive temperature coefficient, where K is the Boltzmann constant, T is the thermodynamic temperature, q is the electron load, and ζ n is the process parameter of the MOS tube, and N is the ratio of the width to length of the first NMOS tube NM1 to the second NMOS tube NM2; The power-on reset circuit further includes a filter circuit: The input end of the filter circuit is connected to the output end of the first inverter, and the output end of the filter circuit is used to output a reset signal.

2. The power-on reset circuit according to claim 1, wherein: The power-on reset circuit includes a current limiting resistor: The ground terminal of the comparator is grounded through the current limiting resistor.

3. The power-on reset circuit according to claim 1, wherein: The first inverter includes a third PMOS transistor and a third NMOS transistor: The source of the third PMOS transistor is connected to one end of the first voltage-dividing resistor to form a power supply end of the first inverter; The gate of the third PMOS transistor is connected to the gate of the third NMOS transistor to form an input end of the first inverter; The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor to form an output end of the first inverter; The source of the third NMOS transistor is connected to the other end of the third voltage-dividing resistor to form a ground terminal of the first inverter.

4. The power-on reset circuit according to claim 1, wherein: The power-on reset circuit further includes a driving circuit: The power supply terminal of the driving circuit is connected to the input power supply; the ground terminal of the driving circuit is grounded; The input end of the driving circuit is connected to the output end of the filtering circuit; The output end of the driving circuit is used to output a reset signal.

5. The power-on reset circuit according to claim 4, wherein: The driving circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor: The gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor to form an input end of the driving circuit; The drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor to form an output end of the driving circuit; The source of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor to form a power supply end of the driving circuit; The source of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor to form a ground terminal of the driving circuit; The drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fifth PMOS transistor, and the gate of the fifth NMOS transistor respectively.

6. An electronic device, characterized in that: The electronic device includes an integrated circuit and a power-on reset circuit according to any one of claims 1 to 5, wherein the reset signal output by the power-on reset circuit is used to power-on reset the integrated circuit.

Images