Methods, systems, storage media, and devices for sharing an ldpc decoding engine

Abstract

The application provides a method for sharing LDPC hard decoding and soft decoding engines of a solid state disk, comprising the following steps: configuring N hard decoding nodes and L soft decoding nodes for a solid state disk comprising N channels; the N channels share the N hard decoding nodes and L soft decoding nodes; and the N hard decoding nodes and L soft decoding nodes share M decoders. N, L and M are all natural numbers greater than or equal to 1, and M < N. The application also provides a system for sharing LDPC hard decoding and soft decoding engines of a solid state disk. Through the above method and system, LDPC can be fully utilized in the working cycle of the SSD, and has a relatively ideal resource occupancy rate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer hardware, and in particular to a method, system, storage medium and device for sharing LDPC hard decoding and soft decoding engines of a solid state disk. BACKGROUND

[0002] A solid state disk (SSD) is composed of a controller, a storage medium and modules such as NAND. With the factors such as smaller and smaller units and thinner and thinner oxide layers, the noise of NAND Flash increases, and the original bit error rate of NAND is relatively high. Therefore, a powerful ECC (Error Correcting Code) engine is needed, and the reliability requirement of enterprise-level SSDs is higher.

[0003] LDPC (Low Density Parity Check Cod) soft decoding has strong error correction capability and can meet the requirements of enterprise-level SSDs. Therefore, in addition to hard decoding, soft decoding is also applied. However, the number of device gate circuits required for minimizing LDPC is a big challenge for SSDs. Therefore, leading SSD manufacturers can make full use of limited LDPC decoding engines to obtain more business value.

[0004] Generally, a multi-channel NAND Flash controller contains several large-area soft decoding and hard decoding engines. In the present application, in order to optimize the device resources and circuit area occupied by the LDPC decoding engine, a structure for sharing LDPC soft decoding and hard decoding engines is proposed. This structure makes LDPC fully utilized in the working cycle of SSD and has a relatively ideal resource occupancy rate. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a method, system, storage medium and device for sharing LDPC hard decoding and soft decoding engines of a solid state disk, so as to optimize the ECC structure of the SSD.

[0006] In order to achieve the above purpose, the present application provides a method for sharing LDPC hard decoding and soft decoding engines of a solid state disk, comprising the following steps:

[0007] N hard decoding nodes and L soft decoding nodes are configured for a solid state disk comprising N channels;

[0008] The N channels share the N hard decoding nodes and L soft decoding nodes; and

[0009] The N hard decoding nodes and L soft decoding nodes share M decoders,

[0010] Wherein, N, L, M are natural numbers greater than or equal to 1, and M < N.

[0011] In some embodiments, the decoder is an IP core of the same architecture.

[0012] In some embodiments, in the beginning stage of the Nand Flash life cycle of the solid state disk, the soft decoding node is not used, and the decoder is not allocated to the soft decoding node, and each of the N hard decoding nodes to be decoded selects to use one of the M decoders by detecting the working state of the decoder. In the middle stage of the Nand Flash life cycle of the solid state disk, each of the N hard decoding nodes to be decoded selects to use one of the M decoders by detecting the working state of the decoder, and each of the L soft decoding nodes to be decoded selects to use the decoder in the idle state among the M decoders by detecting the working state of the decoder. In the end stage of the Nand Flash life cycle of the solid state disk, each of the L soft decoding nodes to be decoded selects to use one of the M decoders, and the decoder is no longer allocated to the hard decoding node.

[0013] In some embodiments, when the throughput of the decoder is x MB / s, and the throughput of each channel is y MB / s, the number of decoders M satisfies the following formula at the same time:

[0014] M = [Ny / x].

[0015] Another aspect of the present application also provides a system for sharing LDPC hard decoding and soft decoding engines of a solid state disk, comprising:

[0016] a decoder module comprising M decoders for decoding;

[0017] a hard decoding node module comprising N hard decoding nodes; and

[0018] a soft decoding node module comprising L soft decoding nodes,

[0019] Wherein, the N channels of the solid state disk share the N hard decoding nodes and the L soft decoding nodes,

[0020] The N hard decoding nodes and the L soft decoding nodes share M decoders, and

[0021] Wherein, M, N, L are natural numbers greater than or equal to 1, and M < N.

[0022] In some embodiments of the system of shared LDPC hard-decoding and soft-decoding engine for solid state drive, in the beginning stage of the Nand Flash life cycle of the solid state drive, the soft-decoding module is not used, the decoders are not allocated to the soft-decoding nodes in the soft-decoding module, and each of the N hard-decoding nodes in the hard-decoding node module to be decoded selects to use one of the M decoders by detecting the working state of the decoders. In the middle stage of the Nand Flash life cycle of the solid state drive, each of the N hard-decoding nodes to be decoded selects to use one of the M decoders by detecting the working state of the decoders, and each of the L soft-decoding nodes to be decoded selects to use the decoder in the idle state of the M decoders by detecting the working state of the decoders. In the end stage of the Nand Flash life cycle of the solid state drive, each of the L soft-decoding nodes to be decoded selects to use one of the M decoders, and the decoders are no longer allocated to the hard-decoding nodes.

[0023] In still another aspect of the present application, a computer readable storage medium is provided, which stores computer program instructions, and the computer program instructions, when executed, implement any of the above methods.

[0024] In yet another aspect of the present application, a computer device is provided, which comprises a memory and a processor, and the memory stores a computer program, and the computer program, when executed by the processor, implements any of the above methods.

[0025] In an SSD, one LDPC decoding engine needs to occupy many circuit resources, which greatly increases the area of the controller. The present application provides a shared LDPC hard-decoding and soft-decoding engine method and system for a solid state drive, which can optimize the ECC structure of the LDPC area occupation. The main innovation of the design is a multi-channel shared LDPC hard-decoding and soft-decoding engine, and the required decoding core resources are allocated to the hard-decoding and soft-decoding nodes according to the stage of the Nand Flash life cycle and the P / E (Program / Erase) cycle. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other embodiments can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0027] Figure 1 FIG. 1 shows a schematic diagram of a method for shared LDPC hard-decoding and soft-decoding engine for solid state drive according to an embodiment of the present application;

[0028] Figure 2 FIG. 2 shows a schematic diagram of a system for shared LDPC hard-decoding and soft-decoding engine for solid state drive according to an embodiment of the present application;

[0029] Figure 3 FIG. 3 shows an ECC structure diagram of one example of a system for shared LDPC hard-decoding and soft-decoding engine for solid state drive according to an embodiment of the present application;

[0030] Figure 4 FIG. 4 shows a conventional 4-channel ECC structure diagram in prior art;

[0031] Figure 5 FIG. 5 shows a schematic diagram of a computer readable storage medium for implementing a method for shared LDPC hard-decoding and soft-decoding engine for solid state drive according to an embodiment of the present application;

[0032] Figure 6 FIG. 6 shows a hardware structure schematic diagram of a computer device for executing a method for shared LDPC hard-decoding and soft-decoding engine for solid state drive according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the objects, technical solutions and advantages of the present application clearer, the embodiments of the present application are further described in detail below with reference to the drawings.

[0034] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same-named non-identical entities or non-identical parameters, and it can be seen that "first" and "second" are only for the convenience of description, and should not be understood as a limitation on the embodiments of the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, the process, method, system, product or device inherently includes other steps or units.

[0035] Based on the above purpose, in a first aspect, an embodiment of a method for shared LDPC hard-decoding and soft-decoding engine for solid state drive is provided. Figure 1 FIG. 1 shows a schematic diagram of a method for shared LDPC hard-decoding and soft-decoding engine for solid state drive according to an embodiment of the present application. As shown in FIG. 1, the embodiment of the present application includes the following steps: Figure 1

[0036] Step S10, configuring N hard-decoding nodes and L soft-decoding nodes for a solid state drive including N channels;​

[0037] Step S20, the N channels share the N hard decoding nodes and L soft decoding nodes;

[0038] Step S30, the N hard decoding nodes and L soft decoding nodes share M decoders.

[0039] Wherein, N, L, M are all natural numbers greater than or equal to 1, and M < N.

[0040] The decoders can be IP cores of the same architecture.

[0041] In the beginning stage of the Nand Flash life cycle (BOL, Begin of Life) of the solid state disk, no soft decoding node is used, and no decoder is allocated for the soft decoding node, and each hard decoding node to be decoded in the N hard decoding nodes respectively selects to use one of the M decoders by detecting the working state of the decoder.

[0042] In the middle stage of the Nand Flash life cycle (MOL, Middle of Life) of the solid state disk, each hard decoding node to be decoded in the N hard decoding nodes respectively selects to use one of the M decoders by detecting the working state of the decoder, and each soft decoding node to be decoded in the L soft decoding nodes respectively selects to use the decoder in the idle state in the M decoders by detecting the working state of the decoder.

[0043] In the end stage of the Nand Flash life cycle (EOL, End of Life) of the solid state disk, each soft decoding node to be decoded in the L soft decoding nodes respectively selects to use one of the M decoders, and no decoder is allocated for the hard decoding node.

[0044] According to the preferred embodiment, when the throughput of the decoder is x MB / s and the throughput of each channel is y MB / s, the number of decoders M satisfies the following formula at the same time:

[0045] M = "Ny / x]".

[0046] The shared LDPC hard decoding and soft decoding engine method for the solid state disk can optimize the ECC structure of the LDPC occupied area. The main innovation of the design is that the multi-channel shares the LDPC hard decoding and soft decoding engine, and the required decoding core resources are allocated to the hard decoding and soft decoding nodes according to the stage of the Nand Flash life cycle and the P / E (Program / Erase, erase / write) cycle.

[0047] The second aspect of the embodiment of the present application also provides a system for sharing LDPC hard decoding and soft decoding engines of a solid state disk. Figure 2 An embodiment of the system for sharing LDPC hard decoding and soft decoding engines of a solid state disk provided by the present application is shown. As shown in Figure 2 The system for sharing LDPC hard decoding and soft decoding engines of a solid state disk includes a decoder module 10 including M decoders for decoding, a hard decoding node module 20 including N hard decoding nodes, and a soft decoding node module 30 including L soft decoding nodes. N channels of the solid state disk share the N hard decoding nodes and the L soft decoding nodes. The N hard decoding nodes and the L soft decoding nodes share the M decoders. Wherein, M, N, L are natural numbers greater than or equal to 1, and M < N.

[0048] The system for sharing LDPC hard decoding and soft decoding engines of a solid state disk provided by the present application can optimize the ECC structure of the LDPC occupied area. The main innovation of the design is that the multi-channel shares the LDPC hard decoding and soft decoding engine, and the hard decoding and soft decoding nodes are allocated with the required decoding core resources according to the stage of the Nand Flash life cycle and the P / E (Program / Erase, erase / write) cycle.

[0049] Figure 3 An ECC structure diagram of one example of the system for sharing LDPC hard decoding and soft decoding engines of a solid state disk provided by the embodiment of the present application is shown. Figure 4 A conventional 4-channel ECC structure diagram in the prior art is shown.

[0050] First, the conventional 4-channel ECC structure in the prior art is introduced.

[0051] As shown in Figure 4 In the ECC structure of the conventional 4-channel NAND Flash controller, each channel has an exclusive hard decoding node, and the four channels share two soft decoding nodes, so the structure needs at least four decoding IP cores, and occupies a large circuit area.

[0052] Figure 3 An ECC structure of a solid state disk also for 4 channels according to the present application is shown. As shown in FIG. 3, core0, core1 and core2 in the figure are three IP cores (i.e. decoders) for decoding and having the same architecture. The four channels share four hard decoding nodes and two soft decoding nodes, and these nodes share the three decoders core0-core2, so that they can be switched with each other without complete initialization and reloading of the matrix, and the consumption of circuit resources and area is reduced.

[0053] In the case ofFigure 3 In the BOL phase, i.e. the beginning phase of the Nand Flash life cycle, the original bit error is less, so two shared soft decoding (SD) nodes are not used, and there is no need to allocate decoding IP cores for them. Each hard decoding (HD) node can select one of the three shared cores by detecting the working state of the decoding IP core.

[0054] In the MOL phase, i.e. the middle phase of the Nand Flash life cycle, as the P / E cycle increases, the original bit error rate will increase, at which time a combination of soft decoding and hard decoding is adopted. Not only are shared IP cores allocated for HD nodes, but also shared IP cores are allocated for SD nodes. For example, core0~core2 decoders are allocated for three HD nodes, and three idle state decoders are allocated for SD nodes. Figure 3 In the EOL phase, i.e. the end phase of the Nand Flash life cycle, the original bit error rate is larger. At this time, the SD node uses three shared IP cores, and no decoding core is allocated for the HD node.

[0055] Figure 3 Through the ECC structure example of the shared LDPC hard decoding and soft decoding engine system for a solid state disk according to the present application, 4 channels share the hard decoding and soft decoding nodes, only 3 decoding IP cores are needed, and resource consumption and circuit area are reduced. Moreover, compared with the traditional 4-channel ECC structure, the more the number of channels in the SSD, the more obvious the area saving effect.

[0056] The third aspect of the embodiment of the present application also provides a computer readable storage medium, The computer readable storage medium 3 stores computer program instructions 31, which can be executed by a processor. The computer program instructions 31 are executed to implement the method of any one of the above embodiments.

[0057] Figure 5 It should be understood that, in the case of not conflicting with each other, all the embodiments, features and advantages described above for the method of the shared LDPC hard decoding and soft decoding engine for a solid state disk according to the present application are equally applicable to the system and storage medium of the shared LDPC hard decoding and soft decoding engine for a solid state disk according to the present application. Figure 5

[0058] It should be understood that, in the case of not conflicting with each other, all the embodiments, features and advantages described above for the method of the shared LDPC hard decoding and soft decoding engine for a solid state disk according to the present application are equally applicable to the system and storage medium of the shared LDPC hard decoding and soft decoding engine for a solid state disk according to the present application.

[0059] ​​The fourth aspect of the embodiments of the present application also provides a computer device including a memory 402 and a processor 401, the memory storing a computer program, and the computer program is executed by the processor to implement the method of any one of the above embodiments.

[0060] As shown in Figure 6 , it is a hardware structure diagram of an embodiment of a computer device provided by the present application to execute the method of the shared LDPC hard decoding and soft decoding engine for solid state disks. Taking the computer device as shown in Figure 6 , as an example, the computer device includes a processor 401 and a memory 402, and can also include an input device 403 and an output device 404. The processor 401, the memory 402, the input device 403 and the output device 404 can be connected by a bus or other means, Figure 6 , taking the bus connection as an example. The input device 403 can receive input digital or character information, and generate key signal input related to user settings and function control of the system of the shared LDPC hard decoding and soft decoding engine for solid state disks. The output device 404 can include a display device such as a display screen.

[0061] The memory 402 as a non-volatile computer readable storage medium can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules corresponding to the method of the shared LDPC hard decoding and soft decoding engine for solid state disks in the embodiments of the present application. The memory 402 can include a program storage area and a data storage area, wherein the program storage area can store an operating system, application programs required by at least one function; the data storage area can store data created by use of the method of the shared LDPC hard decoding and soft decoding engine for solid state disks, etc. In addition, the memory 402 can include a high-speed random access memory, and can also include a non-volatile memory, for example, at least one magnetic disk storage device, a flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory 402 can optionally include a memory remotely arranged with respect to the processor 401, and these remote memories can be connected to the local modules through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0062] The processor 401 executes various function applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 402, that is, implements the method of the shared LDPC hard decoding and soft decoding engine for solid state disks of the above method embodiments.

[0063] Finally, it is to be appreciated that the computer readable storage media (e.g., memory) of the subject innovation can be external or internal to the subject innovation. As an example, and not by way of limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM), which can act as external cache memory. By way of example, and not by way of limitation, RAM is available in many forms such as Static RAM (DRAM), Dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The memory of the subject innovation is intended to include, without being limited to including, these and any other suitable types of memory.

[0064] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0065] The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein can be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0066] The above are exemplary embodiments disclosed by the present application, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present application as defined by the claims. The functions, steps and / or actions of the method claims described herein need not be performed in any particular order. Furthermore, although elements of the embodiments disclosed by the present application can be described or claimed in individual form, unless explicitly restricted, they can also be implemented in multiple forms.

[0067] It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The embodiment number of the embodiments disclosed by the present application is only for description, and does not represent the advantages and disadvantages of the embodiments.

[0068] Those skilled in the art should understand that the above discussion of any embodiment is only exemplary, and is not intended to imply that the scope of the embodiments disclosed by the present application (including the claims) is limited to these examples; the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes of the different aspects of the embodiments disclosed by the present application as described above. In order to be brief, they are not provided in detail. Therefore, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principles of the embodiments disclosed by the present application shall be included in the scope of protection of the embodiments disclosed by the present application.

Claims

1. A method of sharing LDPC decoding engines, the method comprising: The method comprises the following steps: N hard decoding nodes and L soft decoding nodes are configured for a solid state disk comprising N channels; The N channels share the N hard decoding nodes and L soft decoding nodes; and The N hard decoding nodes and L soft decoding nodes share M decoders, wherein N, L, M are all natural numbers greater than or equal to 1, and M < N; In the beginning stage of the Nand Flash life cycle of the solid state disk, the soft decoding nodes are not used, the soft decoding nodes are not allocated the decoders, and each hard decoding node to be decoded in the N hard decoding nodes selects to use one of the M decoders by detecting the working state of the decoders; In the middle stage of the Nand Flash life cycle of the solid state disk, each hard decoding node to be decoded in the N hard decoding nodes selects to use one of the M decoders by detecting the working state of the decoders, and each soft decoding node to be decoded in the L soft decoding nodes selects to use a decoder in the idle state of the M decoders by detecting the working state of the decoders; In the end stage of the Nand Flash life cycle of the solid state disk, the hard decoding nodes are not used, the hard decoding nodes are not allocated the decoders, and each soft decoding node to be decoded in the L soft decoding nodes selects to use one of the M decoders.

2. The method of claim 1, wherein The decoders are IP cores of the same architecture.

3. The method of claim 1, wherein When the throughput of the decoders is x MB / s and the throughput of each channel is y MB / s, the number of decoders M satisfies the following formula simultaneously: M = ⌈Ny / x⌉.

4. A system sharing LDPC decoding engines, characterized in that, comprises: a decoder module comprising M decoders for decoding; a hard decoding node module comprising N hard decoding nodes; and a soft decoding node module comprising L soft decoding nodes, wherein N channels of a solid state disk share the N hard decoding nodes and L soft decoding nodes, the N hard decoding nodes and L soft decoding nodes share M decoders, and wherein M, N, L are all natural numbers greater than or equal to 1, and M < N; wherein in the beginning stage of the Nand Flash life cycle of the solid state disk, the soft decoding node module is not used, the soft decoding nodes in the soft decoding node module are not allocated the decoders, and each hard decoding node to be decoded in the N hard decoding nodes in the hard decoding node module selects to use one of the M decoders by detecting the working state of the decoders; ​ In the middle stage of the Nand Flash life cycle of the solid state disk, each hard decoding node to be decoded in the N hard decoding nodes respectively selects to use one of the M decoders by detecting the working state of the decoder, and each soft decoding node to be decoded in the L soft decoding nodes respectively selects to use the decoder in the idle state in the M decoders by detecting the working state of the decoder; and In the end stage of the Nand Flash life cycle of the solid state disk, each soft decoding node to be decoded in the L soft decoding nodes respectively selects to use one of the M decoders.

5. A computer readable storage medium, characterized in that, Computer program instructions are stored in the memory, and the computer program instructions are executed to implement the method of any one of claims 1-3. 6.A computer device, comprising a memory and a processor, and characterized in that, The memory stores a computer program, and the computer program is executed by the processor to execute the method of any one of claims 1-3.

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