Power saving techniques in the isolated state for usb power delivery with integrated synchronous rectifier controller

Abstract

A secondary side controller for an AC-DC converter, the secondary side controller having a single synchronous rectifier sense (SR_SNS) terminal coupled to a synchronous rectifier (SR) of the AC-DC converter, and a voltage divider circuit coupled to the single SR_SNS terminal, the voltage divider circuit configured to provide a signal to a sense circuit. The voltage divider includes an active diode, an internal resistive element, and a switch, wherein the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison of a voltage at the single SR_SNS terminal to a reference voltage.

Description

[0001] priority

[0002] This application is an international application of U.S. Nonprovisional Application No. 16 / 705,509, filed on December 6, 2019, which claims priority and benefit to U.S. Provisional Application No. 62 / 904,026, filed on September 23, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to AC-DC power converters, and more specifically to secondary-side controlled converters including synchronous rectifier sensing architectures and methods of operation thereof. Background Technology

[0004] An AC-DC converter converts electrical power from an alternating current (AC) source to direct current (DC) at a specified voltage level. For a given size, AC-DC converters with secondary-side control can deliver power more efficiently and are therefore widely used in portable electronic devices. Typically, an AC-DC converter transfers power from an AC input connected to or coupled to the primary side of a transformer to a DC output coupled to the secondary side of the transformer.

[0005] Figure 1 A simplified schematic block diagram of such an AC-DC converter, including a synchronous rectifier (SR) sensing architecture, is shown. (Refer to...) Figure 1 The AC-DC converter 100 typically includes a transformer 102, an active rectifier element or power switch (PS) (e.g., a PS field-effect transistor (PS_FET 104) on the primary side of the transformer), a synchronous rectifier (SR) (e.g., an SR field-effect transistor (SR_FET 106) on the secondary side of the transformer), and an output filter or capacitor 108. In operation, the PS_FET 104 turns on or off power to the primary side in response to a signal from the primary-side controller 110. In a secondary-side controlled converter, the secondary-side controller 112, coupled to the drain node (SR_DRAIN 114) and gate of the SR_FET 106, senses the voltage on the SR_DRAIN and turns the SR_FET on and off in response to sensed voltage peaks, negative crossovers, and zero crossings.

[0006] In a flyback converter, the primary-side controller 110 receives signals from either the SR_FET 106 or the secondary-side controller 112 via feedback or flyback path 116. During the period when the PS_FET 104 is on or off and the SR_FET 106 is off or open, the AC-DC converter 100 is considered to operate in flyback mode, and a magnetic field is established in the transformer 102 while the current on the primary side increases linearly. When the PS_FET 104 is off or open and the SR_FET 106 is on or off, the AC-DC converter 100 transfers power to the secondary side, where the magnetic field begins to decay and the secondary current gradually decreases as power is supplied to Cout 108 connected to the output and stabilizes, until a point is reached where there is essentially zero current flow on the secondary side.

[0007] One problem with previous generations of AC-DC converters using the SR sensing architecture was that, depending on the turns ratio (N:1) of transformer 102 (typically 4:1), the voltage at the drain node 114 of SR_FET 106 could exceed 1 / N of the rectified AC input voltage, typically as high as 115V for a 230V AC input. This, in turn, necessitated the use of a relatively large and expensive high-voltage FET at the SR_DRAIN node 114, and additional electrostatic discharge (ESD) circuitry in the secondary-side controller 112 to safely couple this voltage from the drain node 114 to the secondary-side controller.

[0008] Existing methods that at least partially address the aforementioned problems rely on using a large, high-power FET manufactured with fault-tolerant technology greater than 150V within the secondary controller 112 to sense the SR_DRAIN node 114, or on using an external clamping circuit 118 to limit the input to the secondary-side controller 112. These methods are not entirely satisfactory because the secondary-side controller 112 is typically implemented as an integrated circuit (IC), and using an external clamping circuit 118 to limit the input to the IC requires additional package pins and external components for peak detection and feed-forward (fwd) sensing, as external voltage limiting on the SR_DRAIN node 114 interferes with these detections. Therefore, using an external clamping circuit 118 increases the size and complexity of the IC, as well as the number of package pins for the IC dedicated to SR sensing. This further increases the bill of materials (BOM) required to manufacture the AC-DC converter 100 and the size of the IC on which the secondary-side controller 112 is manufactured, both of which tend to increase costs while reducing the yield and utility of the AC-DC converter 100 in applications that require compact power converters.

[0009] Another problem with previous generations of AC-DC converters 100, and especially with secondary-side controlled flyback converters, arises from the need to detect valley or minimum voltage on the primary side. In the AC-DC converter 100, the PS_FET 104 should be turned on at the valley to minimize switching losses and thus achieve optimal efficiency. However, in the secondary-side controlled flyback converter 100, for example... Figure 1 As shown, because the valley on the primary side is detected as the peak on the secondary side (which corresponds to the peak on the secondary side), accurate peak detection is required. Since the external clamping circuit 118 will not allow accurate sensing of the peak on SR_DRAIN, this additional requirement for peak detection necessitates additional components on SR_DRAIN node 114. Therefore, additional components are needed on SR_DRAIN 114, such as... Figure 1 As shown, a capacitor function Cpd is added to the AC-DC converter 100. Therefore, the use of an external peak detection component (Cpd) increases the size and complexity of the IC, as well as the number of package pins for the IC dedicated to SR sensing. This, in turn, increases the bill of materials (BOM) required to manufacture the AC-DC converter 100 and the size of the IC on which the secondary-side controller 112 is manufactured, both of which tend to increase cost while reducing the yield and utility of the AC-DC converter 100 in applications requiring a compact power converter. Consequently, previous generations of flyback converters 100 were unable to accurately hit the valley, resulting in efficiency losses.

[0010] Therefore, there is a need for AC-DC converters with secondary-side control and SR sensing architectures, and their operating methods, that reduce cost and complexity without negatively impacting performance. There is also a need for flyback converters with secondary-side control and SR sensing architectures, and their operating methods, that provide accurate valley detection to improve efficiency. Attached Figure Description

[0011] Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, wherein corresponding reference numerals indicate corresponding parts. Furthermore, the accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the invention and, together with the description, further serve to explain the principles of the invention and enable those skilled in the art to make and use the invention.

[0012] Figure 1 This is a schematic block diagram illustrating an AC-DC converter, and the secondary-side controller and synchronous rectifier (SR) architecture of this disclosure are particularly useful for this AC-DC converter;

[0013] Figure 2AThis is a schematic block diagram depicting an implementation of an AC-DC converter including a secondary-side controller and an SR architecture according to the present disclosure;

[0014] Figure 2B It is a description of the content of this disclosure. Figure 2A Detailed block diagram of the implementation of the secondary-side controller;

[0015] Figure 2C This describes an optical isolator according to the present disclosure. Figure 2A A schematic block diagram illustrating an implementation of the isolation barrier.

[0016] Figure 2D This describes a pulse transformer according to the present disclosure. Figure 2A A schematic block diagram of another embodiment of the isolation and barrier section;

[0017] Figure 2E It is a description Figure 2B A schematic block diagram of a portion of the secondary-side controller. Figure 2E An implementation of an SR sensing block according to this disclosure is described;

[0018] Figure 3 This is a flowchart illustrating an implementation of a method for operating an AC-DC converter including a secondary-side controller and an SR architecture according to the present disclosure;

[0019] Figure 4 It is shown in passing Figure 3 When operating the method Figure 2A The graphs showing the changes of primary current (I_primary) and secondary current (I_secondary) over time in the circuit.

[0020] Figure 5 It shows when passing Figure 3 When operating the method Figure 2A The graph of the voltage across the drain node of SR in the circuit as a function of time;

[0021] Figure 6 It shows when passing Figure 3 When operating the method Figure 2E The graph shows the time-varying signals at the gate, NSN_OUT node, and ZCD_OUT node of the SR sensing block in the circuit.

[0022] Figure 7A It is a description Figure 2B A schematic block diagram of a portion of the secondary-side controller. Figure 7A An implementation of the SR sensing block and voltage divider according to this disclosure is described;

[0023] Figure 7BIt is a schematic block diagram depicting a portion of a voltage divider according to this disclosure;

[0024] Figure 8 It is a description Figure 2B A schematic block diagram of a portion of the secondary-side controller. Figure 8 An implementation of the SR sensing block and voltage divider according to this disclosure is described;

[0025] Figure 9 These are schematic block diagrams depicting two alternative embodiments of a voltage divider according to this disclosure; and

[0026] Figure 10 This is a flowchart illustrating an implementation of a method for operating an AC-DC converter including a secondary-side controller and an SR architecture according to the present disclosure. Detailed Implementation

[0027] An AC-DC converter with a secondary-side control and synchronous rectifier (SR) architecture, including a single SR sensing (SR_SNS) pin or terminal, and its operation method are disclosed to reduce the cost, complexity, and size of the converter while improving efficiency. The systems and methods of this disclosure are particularly useful in AC-DC flyback converters or in situations where AC-DC flyback converters are available, to improve valley detection, thereby improving the control of the secondary-side controller over the primary-side power switch or primary FET, and thus improving the converter's efficiency.

[0028] Overview of the implementation method:

[0029] Examples, implementations, and methods described herein include voltage dividers with active diodes for secondary-side controlled AC-DC converters, systems, and their operation methods, to provide undivided sensing signals during a disconnected state for improving sensing efficiency and reducing power loss.

[0030] According to one embodiment, the secondary-side controller for an AC-DC converter of this subject matter may have a single synchronous rectifier sensing (SR_SNS) terminal coupled to the synchronous rectifier (SR) of the AC-DC converter, having a maximum input voltage significantly smaller than the SR drain voltage. The secondary-side controller may also have a voltage divider circuit coupled to the single SR_SNS terminal, the voltage divider circuit being configured to provide a signal to the sensing circuit. In one embodiment, the voltage divider may include an active diode, an internal resistive element, and a switch. In this embodiment, the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison of the voltage at the single SR_SNS terminal with a reference voltage.

[0031] In one implementation, the active diode of the aforementioned secondary-side controller can also be configured to disable the internal resistive element when the AC-DC converter is in a disconnected state and the AC-DC converter is not electrically coupled to any load via a USB Type-C connector.

[0032] In one implementation, the active diode may have comparator and NOR logic functions, wherein the inverted output signal and the decoupled signal of the comparator are coupled to the two inputs of the NOR logic function, and the output signal of the NOR logic function is configured to control the operation of the switch.

[0033] In one implementation, the active diode may have a comparator configured to provide an enable signal to the switch when the voltage at a single SR_SNS terminal is greater than Vref, and to provide a disable signal to the switch when the voltage at a single SR_SNS terminal is less than Vref.

[0034] In one embodiment, the sensing circuit may have a zero-crossing detection (ZCD) block, a negative sensing (NSN) block, a peak detection (PKD) block, and a line feedforward (LFF) block integrally formed on the sensing circuit. The ZCD block, PKD block, NSN block, and LFF block can be coupled to the drain of the SR via a single SR_SNS terminal.

[0035] In one implementation, the voltage divider circuit may not include any passive diodes that include PN junction diodes.

[0036] In one embodiment, the voltage divider circuit may also have an external resistor element coupled between a single SR_SNS terminal and the drain of the SR, wherein the external resistor element may be arranged outside the secondary-side controller.

[0037] In one implementation, the external resistive element may have a resistance value based on the following: the AC input voltage to the primary side of the transformer of the AC-DC converter, the turns ratio of the transformer, and a maximum input voltage of less than 20V to a single SR_SNS terminal.

[0038] In one implementation, the internal resistive element can be coupled to ground in series via a switch, wherein the switch can be controlled by an active diode and can be configured to disable voltage division during negative sensing and zero-crossing detection in the secondary-side controller.

[0039] In one embodiment, the secondary-side controller for the AC-DC converter may also have a terminal arranged between the SR_SNS terminal and the V... BUS_INA passive diode between the terminals, wherein the passive diode can be configured to limit the voltage at the SR_SNS terminals during power-up of the AC-DC converter. In an embodiment, the reference voltage can be predetermined or programmable.

[0040] In one embodiment, the PKD block may include a PKD comparator coupled to the SR_SNS terminal via an internal capacitor to detect the peak voltage without any limiting on the peak voltage at the SR_SNS terminal, and may be configured to generate a PKD_OUT signal, which is processed and sent to the primary-side controller to turn on the power switch (PS) coupled between the AC input and the primary side of the transformer to enable a valley-switching operating mode. The sensing circuit may also have a ZCD block with a ZCD comparator coupled between the SR_SNS terminal and the negative terminal of the DC output of the AC-DC converter, the comparator being configured to generate a zero-current signal to turn off the SR when a zero-crossing voltage is sensed at the SR_SNS terminal without any voltage division. In one embodiment, the sensing circuit may also have an NSN block with an NSN comparator coupled to the SR_SNS terminal to detect a negative voltage crossover without any voltage division, wherein the NSN comparator is configured to generate a signal for turning on the SR. In one embodiment, the sensing circuit may also have an LFF block with a voltage-current (V2I) block coupled to the SR_SNS terminal to detect a proportional AC line input voltage in the presence of a voltage divider, and the line input voltage information is used to change the parameters of the AC-DC converter to improve efficiency and performance.

[0041] According to one embodiment, a method of operating a secondary-side controlled AC-DC converter may include the following steps: sensing a voltage on the drain of a synchronous rectifier (SR) coupled to the secondary side of a transformer using a secondary-side controller, the secondary-side controller including an integrated circuit (IC) including a single synchronous rectifier sensing (SR_SNS) terminal, the IC being coupled to the drain of the SR via the single SR_SNS terminal; sensing the voltage on the drain of the SR via the single SR_SNS terminal; coupling the single SR_SNS terminal to ground via a voltage divider circuit including an active diode, an internal resistive element, and a switch; disabling the internal resistive element using the active diode and the switch when the voltage at the SR_SNS terminal is determined to be less than a reference voltage; and disabling the internal resistive element using the active diode and the switch when the AC-DC converter is in a disconnected state.

[0042] In one implementation, the previously mentioned method may also include the following steps: when the voltage at the SR_SNS terminal is determined to be greater than the reference voltage and the AC-DC converter is in the attached state, an active diode and a switch are used to enable the internal resistive element.

[0043] In one implementation, the step of disabling the internal resistive element may include sensing the undivided voltage during negative sensing and zero-crossing detection operations without attenuation.

[0044] In one implementation, enabling the internal resistive element may include sensing the voltage divider at the SR_SNS terminal during online feedforward sensing operation.

[0045] In this implementation, the reference voltage used for voltage comparison can be predetermined or programmable.

[0046] According to one embodiment, the USB system of this subject may include a transformer having a primary side coupled to receive a rectified AC input and a secondary side coupled to a DC output via a USB connector, and a synchronous rectifier (SR) coupled between the DC output and the secondary side. In one embodiment, the aforementioned USB system may also include a secondary-side controller having an integrated circuit (IC) and multiple terminals coupled to the secondary side of the transformer via the multiple terminals, including a single synchronous rectifier sensing (SR_SNS) terminal. The IC is coupled to the drain of the SR via the single SR_SNS terminal to sense the voltage at the drain of the SR. In one embodiment, the single SR_SNS terminal may be coupled to the drain of the SR and the sensing circuit via a voltage divider circuit, wherein the voltage divider circuit may have an active diode, an internal resistive element, and a switch. In one embodiment, the active diode may be configured to control the switch to enable or disable the internal resistive element based on a comparison of the voltage at the single SR_SNS terminal with a reference voltage.

[0047] In one implementation, the active diode can also be configured to disable the internal resistive element when the AC-DC converter is in a disconnected state, wherein, in the disconnected state, the AC-DC converter is not electrically coupled to any load via the USB Type-C connector.

[0048] In one implementation, the voltage divider circuit may also have an external resistive element that couples a single SR_SNS terminal to the drain of the SR.

[0049] In one implementation, the sensing circuit may have a zero-crossing detection (ZCD) block, a negative sensing (NSN) block, a peak detection (PKD) block, and a line feedforward (LFF) block integrally formed on the IC.

[0050] Other features and advantages of embodiments of the present invention, as well as the structure and operation of various embodiments of the present invention, will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to those skilled in the art based on the teachings contained herein.

[0051] Now refer to Figures 2A to 2E This disclosure describes an implementation of an AC-DC converter including a secondary-side controller and an SR architecture according to the present disclosure. Figure 2A This is a schematic block diagram of an AC-DC converter 200 having an SR architecture, including a secondary-side controller 202, according to an embodiment of this disclosure. (Refer to...) Figure 2A An AC-DC converter 200 typically includes a transformer 204 having a primary winding (NP) electrically connected or coupled to a primary side 206 of an AC input and a secondary winding (NS) coupled to a secondary side 208 of a DC output.

[0052] On the primary side 206, a rectifier circuit, such as a bridge rectifier 210, coupled to the first terminal 204a of the transformer 204, and one or more input filters 212, 214 rectify the AC input voltage and provide input power to the primary winding of the transformer 204. The input filters may include: a first input filter 212 having a capacitor (C1) coupled to the output of the rectifier 210 or across the output terminals of the rectifier 210; and a second RC filter 214 including a resistor or resistive element (R2) and a capacitor (C2) coupled in parallel between the first terminal 204a of the transformer 204 and the cathode of a diode or rectifier (D2), the diode or rectifier (D2) having an anode coupled to the second terminal 204b of the transformer. Typically, as in the illustrated embodiment, the AC-DC converter 200 also includes a power switch (PS 216), such as a primary field-effect transistor (PR_FET), the power switch (PS 216) having a first or drain node coupled to a second terminal 204b of the transformer 204, a second or gate node coupled to a primary-side controller 218, and a third or source node coupled to the primary-side controller and grounded via a current sensing element (e.g., a resistive element (RCS)) to sense the primary current (I_primary) flowing through the primary winding when PS 216 is closed or conducting. Typically, as in the illustrated embodiment, the primary-side controller 218 is also coupled to a first terminal 204a of the transformer 204 via a resistive element (Rin) to receive a voltage or signal equal to or proportional to the rectified AC input voltage.

[0053] On the secondary side 208, the AC-DC converter 200 includes a filter capacitor 221 coupled between the third terminal 204c of the transformer 204 and electrical ground or a ground terminal, and an output capacitor 220 coupled between the third terminal 204c of the transformer 204 and electrical ground to provide a DC output voltage to the output interface or connector 222. Typically, as in the illustrated embodiment, the output connector 222 is also coupled to the secondary-side controller 202 via multiple communication channels 224 to support various charging protocols. Suitable output connectors 222 may include connectors compatible with and supporting the following standards and proprietary charging protocols: including Universal Serial Bus Power Delivery (USB PD2.0) and USB PD3 ​​with Programmable Power Supply (PPS). Quick Charge AFC and Charging protocol. For example, the connector may include a Universal Serial Bus Type-C (USB-C) compatible connector, wherein the AC-DC converter 200 conforms to the USB protocol to provide a DC output voltage of approximately 3.3VDC to approximately 21.5VDC at a current of approximately 0 mA to approximately 3000 mA.

[0054] According to this disclosure, the AC-DC converter 200 also includes a synchronous rectifier (SR 226), such as a synchronous rectifier field-effect transistor (SR_FET), on the secondary side 208. The synchronous rectifier (SR 226) is coupled between the fourth terminal 204d of the transformer 204 and the ground terminal of the DC output. SR 226 includes: a first or drain node 226a coupled to the fourth terminal 204d of the transformer 204 and the secondary-side controller 202 to sense the voltage on the drain of the SR; a second or gate node 226b coupled to the secondary-side controller to drive or control the SR; and a third or source node 226c coupled to the secondary-side controller and the ground terminal of the DC output.

[0055] In some implementations, for example, as shown, the secondary-side controller 202 is implemented or carried out as a single integrated circuit (IC), or as multiple ICs packaged in a single IC package, and the drain node 226a is coupled to a single SR_SNS pin or terminal 228 of the IC via a voltage divider 230, which includes internal and external circuitry elements of the secondary-side controller IC. The gate node 226b of SR 226 is coupled to the secondary-side controller 202 via an SR-G drive (SR_GDRV) pin or terminal 232, and the source node 226c of SR 226 is coupled to the secondary-side controller via an SR_Vss (ground voltage level) pin or terminal 234.

[0056] Optionally, as in the illustrated embodiment, the secondary side further includes an additional or secondary switch (SS) 236, such as an NFET, coupled between the third terminal 204c of the transformer 204 and the positive DC output, enabling the secondary-side controller 202 to shut off the DC output to prevent overvoltage and / or undervoltage conditions. SS 236 includes a drain node coupled to a voltage bus input pin or terminal (V) of the secondary-side controller 202. BUS_IN )238; Gate node, which is coupled to the voltage bus control pin or terminal (V BUS_CTRL )240 to drive or control SS; and source node, which is coupled to the voltage bus output pin or terminal (V BUS_OUT )242 and the positive terminal of DC output.

[0057] Voltage divider 230 includes an external resistive element 244, an internal resistive element 246, and an internal rectifier 248. Although schematically shown as a diode, it should be understood that this is not necessarily the case in every embodiment, and the internal rectifier 248 may be a PN diode (as shown), or alternatively a synchronous diode or a FET configured or connected to function as a diode. The configuration or placement of the internal rectifier 248—i.e., a cathode-grounded connection—ensures that substantially no current flows through voltage divider 230 during negative sensing or zero-crossing operation, thereby allowing a full, undivided negative voltage on drain node 226a to be coupled to SR_SNS pin 228. The resistance value of external resistive element 244 is typically fixed by the manufacturer of AC-DC converter 200 and selected based on the expected maximum voltage on drain node 226a based on the maximum AC voltage input and the turns ratio of transformer 204, to limit the maximum voltage on SR_SEN node 228, enabling the secondary-side controller 202 to be manufactured using non-high-voltage devices manufactured using standard low-voltage techniques. A suitable resistance value for resistor element 244 is approximately 4 kΩ to approximately 10 kΩ. For example, in one embodiment (where the maximum input voltage after bridge rectifier 210 is 380 V and the turns ratio of transformer 204 is 4:1), the voltage on VBUS_IN 238 is 21.5 V DC, and the voltage on SR_DRAIN 226a may be 116.5 V. The secondary-side controller 202 is manufactured using 20 V fault-tolerant technology, and the external resistor element 244 has a resistance of approximately 10 kΩ and an internal resistance of approximately 2 kΩ to limit the maximum voltage on SR_SNS node 228 to no more than approximately 21.5 V.

[0058] exist Figure 2AThe internal resistive element 246, schematically shown as a variable resistor, may have a resistance value set by the manufacturer when manufacturing the AC-DC converter 200 based on a desired input or output voltage, or a resistance value used to compensate for parameter variations in ICs or other components within the AC-DC converter. Alternatively, the resistance value of the internal resistive element 246 may be dynamically adjusted by calibration circuitry in the AC-DC converter 200 or the secondary-side controller 202 during AC-DC converter startup or power-on, or periodically adjusted after AC-DC converter startup or power-on.

[0059] Optionally, as in the illustrated embodiment, the voltage divider 230 further includes a bypass switching element or switch 252 connected in parallel with the internal rectifier 248. In response to the detection of a rising or non-zero positive voltage at drain node 226a (indicating feedforward operation), a ff signal (ff_enable) generated in the secondary-side controller 202, switch 252 closes during feedforward (ff) sensing. Note that although in Figure 2A In the illustrated embodiment, the internal rectifier 248 and the switch 252 are schematically shown as two separate and distinct elements, but this is not required in every embodiment, and the rectifier and switch may alternatively comprise a single device such as a FET, wherein the switch is formed by the FET and the rectifier is formed by an intrinsic body diode between the source and drain of the FET.

[0060] like Figure 2A As shown, the AC-DC converter 200 also includes an isolation circuit or barrier 254 for electrically isolating the secondary side 208 from the high AC input voltage appearing on the primary side 206. Because the transformer 204 is a step-down transformer, it is generally considered part of the isolation barrier 254. Furthermore, as in the illustrated embodiment, the AC-DC converter 200 is a flyback converter, where the signal 256 is provided from a pin on the secondary-side controller 202 (e.g., feedback pin 243 or pulse width modulation (PWM) drive pin 258) to the primary-side controller 218. The isolation barrier 254 may also include additional circuitry or components between the secondary-side controller and the primary-side controller 218 or PS 216. (Refer to below...) Figure 2C and Figure 2D This describes the details of these additional circuits or components according to various implementation methods.

[0061] Figure 2B It is a description Figure 2A A detailed block diagram of an implementation of the secondary-side controller 202. (Refer to...) Figure 2BIn addition to voltage divider 230, secondary-side controller 202 typically includes SR sensing circuitry or block 260 and SR gate driver circuitry or block 262 coupled to gate node 226b of SR 226 via SR-G drive pin 232. SR sensing block 260 is coupled to drain node 226a of SR 226 via a single SR_SNS pin 228 and voltage divider 230, and to source node 226c of SR via SR-Vss pin 234. SR sensing block 260 typically includes a zero-crossing detection (ZCD) block, a negative sensing (NSN) block, a peak detection (PKD) block, and a line feedforward (LFF) block for sensing the voltage on drain 226a of SR 226 to sense or detect zero-crossing, negative voltage, peak (positive) voltage, and feedforward operation. One or more outputs of the SR sensing block 260 are coupled to the SR gate driver block 262 to control the SR 226, and to the pulse width modulation (PWM) circuit 264 to provide a signal 256 to the primary-side controller 218 via the PWM drive pin 258 to control the PS 216. The PWM circuit 264 includes a ramp generator and a PWM for generating a signal with a modulated pulse width, and a PWM driver for boosting the voltage or power of the signal to the voltage or power required to drive the primary-side controller 218 or the PS 216.

[0062] like Figure 2B As shown, the secondary-side controller 202 also includes a secondary switch (SS) circuit 266. The SS circuit 266 includes an OV-UV circuit or block for detecting V. BUS_IN 238 and V BUS_OUT Overvoltage (OV) and undervoltage (UV) conditions on 242; low voltage drop (LDO) and high voltage (HV) regulators; and for making V BUS_IN and V BUS_OUT A circuit or block that discharges electricity.

[0063] The interface circuit 268 switch includes circuitry or blocks for communicating with devices powered or charged by the AC-DC converter 200 to support various charging protocols. These circuitry or blocks may include a two-phase marker code (BMC) physical layer (PHY) for communicating with the device using a specific charging protocol, a charger detection block, and a power-on reset (POR) block for resetting the device (placing the device in a known state when charging begins by the AC-DC converter 200).

[0064] The secondary-side controller 202 also includes a microcontroller unit (MCU) subsystem 270, which includes: a logic microprocessor or controller for executing a program stored in the memory of the MCU subsystem; an analog-to-digital converter (ADC); a multi-purpose timer-counter pulse-width modulator (TCPWM) capable of performing multiple functions required for the operation of the MCU; and multiple general-purpose input / output (GPIO) devices (only one of which is shown).

[0065] Finally, the secondary-side controller 202 also includes a feedback circuit or circuit 272 coupled to the feedback pin 243 to provide error correction to the PWM circuit 264 and, in some embodiments of the isolation barrier section 254, to provide a feedback signal to the primary-side controller 218. Typically, as in the illustrated embodiment, circuit 272 includes a constant voltage (CV) reference, a constant current (CC) reference, one or more error amplifiers and an analog-to-digital converter (IDAC), a low-side current sensing amplifier (LSCSA), and a short-circuit protection (SCP) block.

[0066] Now refer to Figure 2C and Figure 2D describe Figure 2A An embodiment of the isolation barrier section 254 of the AC-DC converter 200. It should be noted that... Figure 2C and Figure 2D Each figure shows an exemplary embodiment of the isolation barrier 254, and other embodiments of the isolation barrier can be implemented, which may or may not include all the elements and components shown in these figures. Therefore, Figure 2C and Figure 2D The implementation methods described herein are not intended to limit the invention and the appended claims in any way.

[0067] Reference Figure 2CIn a first embodiment, the isolation barrier 254 includes an opto-isolator 274 to provide electrical isolation between the feedback pin 243 of the secondary-side controller 200 and the primary-side controller 218. Typically, the opto-isolator includes a light-emitting element (e.g., a light-emitting diode (LED) 274a) and a photosensitive element (e.g., a photosensitive or phototransistor 274b). The LED 274a has a cathode directly coupled to the error amplifier output pin (EA_OUT) and an anode coupled to the third terminal 204c of the transformer 204 via a voltage divider including a first resistive element (R3) and a second resistive element (R4). The cathode of the LED 274a is also coupled to the FB pin 243 and the constant current compensated general-purpose input / output (CC_COMP_GPIO) via resistor-capacitor filters or networks 276 and 278. The phototransistor 274b may include a bipolar NPN transistor and is coupled to the primary-side controller 218 via the FB_input pin 280. In this implementation, the secondary-side controller 202 uses the output from the error amplifier 272 to acquire feedback from the secondary side and transmits it to the primary controller via the opto-isolator 274. This architecture provides three key features: secondary-side sensing and regulation, synchronous rectification, and a charging port controller.

[0068] Figure 2D It is a description Figure 2A A schematic block diagram of another embodiment of the isolation barrier includes a pulse transformer 282 coupled between a PWM drive pin 258 of the secondary-side controller 202 and a pulse_in pin 284 and a soft-start (SS) pin 273. The PWM drive pin 258 of the primary-side controller 218 modulates the pulse width of the primary MOSFET in voltage-mode control. In this architecture, the primary-side controller 218 combines an error amplifier 272 with a programmable ramp generator of a PWM circuit 264 to determine the pulse width of the PWM signal. This PWM signal is transmitted from the secondary-side controller 202 to the primary-side controller 218 via the pulse transformer 282. This architecture is similar to... Figure 2CThe architecture also provides three key features: secondary-side sensing and regulation, synchronous rectification, and a charging port controller. The isolation barrier also includes an auxiliary coil for transformer 204, which serves as a flyback buck transformer 204e to provide power to the primary-side controller 218 via the Aux pin. The buck transformer 204e, along with diode D1 and subsequently grounded capacitor C1, stores the buck voltage, which is then limited by a bipolar junction transistor (BJT) structure and then coupled to the auxiliary pin. This additional circuitry helps reduce the overall power consumption of the AC-DC converter 200 because the primary-side controller 218 is powered via the Aux pin, rather than by a separate power supply via another pin of the first terminal 204a on the primary side 206 of transformer 204 coupled via Rin. A resistor divider R1 and R2 connected to the overvoltage protection (OVP)_AUX pin 284 of the primary-side controller 218 is used to sense the reflected voltage VBUS_IN on the secondary side 208 via the buck transformer 204e. Using the VBUS_IN signal, the primary-side controller 218 can disable PS 216, shown here as PR_FET, using the internal circuitry of the primary-side controller.

[0069] Figure 2E yes Figure 2B A schematic block diagram of a portion of the secondary-side controller. Figure 2E An embodiment of the SR sensing block 260 according to this disclosure is described. For example... Figure 2E As shown, the SR sensing block includes a zero-crossing detection (ZCD) block 286, a negative sensing (NSN) block 288, a peak detection (PKD) block 290, and a line feedforward (LFF) block 292, all of which are integrally formed on a single IC together with other components and elements of the secondary-side controller 202.

[0070] ZCD block 286 may include a comparator having a first inverting input coupled to the source node 226c of SR 226 via SR_Vss pin 234, and a second non-inverting input coupled to the drain node 226a of SR via SR_SNS pin 228 and voltage divider 230. During the ZCD sensing phase, in which SR_DRAIN 226a is negative and tilted towards 0V, rectifier 248 remains enabled while switch 252 is disabled, so that there is no voltage division in voltage divider 230. This achieves a direct voltage of SR_DRAIN 226a at the non-inverting input of ZCD comparator 286. The comparator of ZCD block 286 can be configured to generate a zero-current signal (ZCD_OUT) to turn off SR 226 when a zero-crossing voltage is sensed on SR_SNS pin 228 and SR_DRAIN pin 226a without any voltage division. The absence of a voltage divider allows for precise detection of the zero-crossing current (or voltage) of the SR_DRAIN 226a, which improves the efficiency of the AC-DC converter 200.

[0071] NSN block 288 may also include a comparator having a first inverting input coupled to SR_SNS pin 228 and coupled to the drain node 226a of SR 226 via voltage divider 230, and a second non-inverting input coupled to a negative reference voltage (Vtnesn), which may be between -700mV and +200mV. This reference voltage Vtnesn can be defined as a desired negative voltage or low-voltage trigger point at which the controller needs to turn on SR_GDRV 226b. An alternative method for the negative reference voltage could be, for example, connecting the non-inverting input coupled via SR-Vss pin 234 to the source node 226c of SR 226, and the comparator could have a built-in offset to trigger when SR_SNS pin 228 is at a negative voltage. During the NSN detection phase when SR_DRAIN 226a changes from a positive to a negative voltage, rectifier 248 remains enabled while switch 252 is disabled, resulting in no voltage division in voltage divider 230. This achieves a direct voltage of SR_DRAIN 226a at the inverting input 228 of NSN comparator 288. NSN comparator 288 generates a negative voltage signal (NSN_OUT) to turn on SR 226.

[0072] During power delivery on the secondary side, when SR 226 is off, and because PS 216 is not yet on, an LC sinusoidal oscillation occurs on SR_DRAIN 226a, and a reverse sinusoidal oscillation occurs at the PR drain 204b terminal of the flyback transformer 204. To improve the efficiency of the AC-DC converter, the primary switch 216 must be turned on when there are valleys in these sinusoidal oscillations (which correspond to peaks on the secondary SR_DRAIN 226a node). PKD block 290 is a peak sensing block on the secondary side. PKD block 290 may also include a comparator having a first inverting input coupled to SR_SNS pin 228 via switch 294 and internal capacitor 295 and coupled from SR_SNS pin to the drain node 226a of SR226 via voltage divider 230, and a second non-inverting input coupled to ground. Typically, as in the illustrated embodiment, the PKD block 290 also includes a diode circuit 296 connected back-to-back between the first and second inputs of the comparator to detect the peak value of the sine wave seen on SR_SEN 228. The comparator is configured to generate a peak voltage detection signal (PKD_OUT), which can be coupled to the primary-side controller 218 to turn on PS 216 to enable valley switching operation mode. Switch 294 remains off during the NSN and ZCD detection phases to avoid capacitive load provided by the PKD block at the SR_SEN 228 node, which reduces the delay in sensing NSN and ZCD and improves the performance and efficiency of the AC-DC converter 200. Switch 294 is turned on during the peak detection function by using the derived signal of ZCD_OUT when ZCD_OUT determines the turn-off of SR FET 226, after which the LC sine oscillation begins.

[0073] Finally, the AC line feedforward (LFF) block 292 may include a voltage-current (V2I) block, which is coupled to the SR_SNS pin 228 via a sampling and holding arrangement using switch 297, diode element 298, and charge storage element (capacitor 299), and coupled to the drain node 226a of SR 226 via voltage divider 230. During the phase when the primary switch 216 is on, the difference between nodes 204d and 204c of the flyback transformer forms a reflected voltage proportional to the rectified line input voltage at node 204a of transformer 204, based on the turns ratio (N) of the flyback transformer 204. Since node 204d is also coupled to SR_DRAIN 226a, which serves as a sensing node within the secondary-side controller 202 after resistor divider 230, node SR_SEN 228 also carries the line input voltage information derived using LFF block 292. Secondary-side controller 202 can use line input information to change valley switching or PWM pulse width to optimize the efficiency of AC-DC converter 200 on variable AC line inputs. The phase in which primary switch 216 is turned on and SR_DRAIN 226a receives a reflected proportional voltage is defined as the feedforward sensing phase, during which switch 297 is turned on to begin sensing the line input voltage via the SR_SEN 228 pin. Simultaneously, switch 252 is also turned on to bypass rectifier element 248 to allow a precise resistive divider version of SR_DRAIN 226a to reach the input of LFF block 292. Switch 297 remains off during the NSN and ZCD sensing phases to avoid capacitive loads provided by the LFF block at the SR_SEN 228 node, which helps reduce the sensing delay of NSN and ZCD and improves the performance and efficiency of AC-DC converter 200. LFF block 292 is configured to generate a current signal (IFF_OUT) when AC-DC converter 200 operates in feedforward sensing mode. The IFF_OUT current can then be used to adjust the PWM pulse width based on the line AC voltage, which improves the performance and efficiency of the AC-DC converter over a wide range of AC input voltages. The IFF_OUT current can also be converted to a voltage proportional to the line AC input voltage and can be used for any function required on the secondary-side controller, such as changing the valley value at which the primary FET 216 should be turned on based on the line AC voltage to improve the performance of the AC-DC converter 200 for the same output power requirements.

[0074] Now refer to Figure 3 Flowcharts and Figure 4 and Figure 5The diagram illustrates a method of operating an AC-DC converter with a secondary-side controller, which includes an IC with a single SR_SNS pin, through which the IC is coupled to the drain of the SR via a voltage divider. Figure 4 It shows when passing Figure 3 When operating the method, Figures 2A to 2E The graphs of the primary current (I_primary402) and secondary current (I_secondary404) in the circuit. Figure 5 It shows when passing Figure 3 The graph of the voltage 502 obtained at the drain node of SR during the operation of the method.

[0075] Reference Figure 3 as well as Figure 2A and Figure 2E The method begins with the receipt of a rectified AC input to the primary side 206 of transformer 204 (302). The voltage across the drain 226a of SR 226 is sensed via a single SR_SNS pin 228 (304). Next, it is determined whether a negative sense is detected (306). Typically, the determination of whether the AC-DC converter is operating in negative sense mode is accomplished by sensing an increased negative voltage across the SR_SNS pin 228. If no negative sense is detected, step or block 304 is repeated, and the voltage across the drain 226a of SR 226 continues to be sensed via the single SR_SNS pin 228. If a negative sense is detected, SR 226 is turned on, while the power switch or PS 216 on the primary side 206 of transformer 204 remains off (308).

[0076] Next, a zero-crossing check is performed on the SR_SNS pin 228 using the ZCD block 286 in the secondary-side controller 202 (310), and it is determined whether a zero-crossing is detected (312). If no zero-crossing is detected, step or block 310 is repeated to continue checking for zero-crossings on the SR_SNS pin 228. If a zero-crossing is detected, SR 226 is turned off, and PS 216 remains off (314).

[0077] Then, the PKD block 290 in the secondary-side controller 202 performs a check (316) on a predetermined or desired number of peak values ​​detected on the SR_SNS pin 228 for a predetermined or desired number of peak values, and determines whether the desired number of peak values ​​is detected (318). If the desired number of peak values ​​is not detected, step or block 316 is repeated to continue checking for the desired number of peak values. If the desired number of peak values ​​is detected, SR 226 remains off, PS 216 is on (320), and bypass switch 252 is closed to apply a voltage divider to the SR_SNS pin 228.

[0078] Next, a check is performed to sense whether the AC-DC converter 200 is operating in line-fed forward (LFF) sensing mode (322), and a determination is made as to whether LFF is sensed (324). Typically, the determination of whether the AC-DC converter 200 is operating in LFF sensing mode is accomplished by sensing the rising or stable positive voltage on the drain 226a of SR 226 applied through a single SR_SNS pin 228 using LFF block 292. If the AC-DC converter 200 is not operating in LFF sensing mode, step or block 322 is repeated to continue checking for LFF sensing. If it is determined that the AC-DC converter is operating in LFF sensing mode, bypass switch 252 is opened so that the voltage applied to the secondary-side controller 202 through a single SR_SNS pin 228 is not divided by voltage divider 230 (326), and step or block 304 is repeated to sense the voltage on the drain 226a of SR 226 through a single SR_SNS pin 228.

[0079] Reference Figure 2A and Figure 2E In the voltage divider 230, current can flow from the drain node 226a of SR 226 to ground whenever the voltage at the drain node 226a is above or close to 0V. Even when the AC-DC converter 200 is not attached to any device or load (disconnected state) (possibly via a USB Type-C connector), continuous power consumption may occur between the drain node 226a of SR 226 and ground through the internal resistive element 246 and the internal rectifier or diode 248. USB power adapter regulatory guidelines may require any power adapter to consume less than 75mW in the disconnected state. During the disconnected state, where the AC-DC converter 200 is not electrically attached to any device or load via the output connector 222 or otherwise, the power consumption through the voltage divider 230 to ground may cause certain problems, such as the power adapter continuously drawing current even when no device is connected, resulting in power adapter heating and constant power consumption. In some embodiments, due to power loss, during the disconnected state, at V BUS_IN With pin 238 at approximately 5V, the power adapter may draw up to 700μA of current.

[0080] Figure 6 It shows when passing Figure 3 When the described method or similar method is operated Figure 2EThe graph shows the signal variations over time at the gate 226b, NSN_OUT node, and ZCD_OUT node of SR 226 in the AC-DC converter 200. As previously explained, during the NSN detection phase, the reference voltage (Vtnesn) can be defined as the desired negative or low voltage trigger point at which the controller needs to turn on SR 226 via the SR_GDRV pin 226b (at t1). Once the voltage at the SR_SNS pin 228 drops below Vtensn, the NSN block 288 can generate the NSN_OUT signal (detected by the NSN) at t1 to turn on SR 226. Accordingly, the voltage at the SR drain node 226a can reach a negative or low trigger voltage, for example, as... Figure 5 The voltage is -0.7V. In one implementation, SR 226 should be turned on immediately to avoid any delay. Once the voltage at the drain node 226a of SR drops toward a negative voltage (e.g., -0.7V) at or near t1, the circuitry in the secondary side 208 of the AC-DC converter 200 carries a high current. Any delay in turning on SR 226 can result in efficiency losses in the AC-DC converter 200. (Refer to...) Figure 6 During the ZCD detection phase, when zero current or zero voltage is detected on SR226, ZCD block 286 can generate a ZCD_OUT signal. The ZCD_OUT signal can then turn off SR 226 by disabling the SR_GDRV signal. In one embodiment, SR226 is preferably disabled rapidly or almost instantly at or near t2 to avoid cross-conduction of the AC-DC adapter 200. In one embodiment, as... Figure 2E The internal rectifier 248 shown can be a passive diode, such as a PN junction diode. When the voltage at the SR drain node 226a drops below or near 0V, or to the threshold voltage of the passive diode, such as 0.7V (in... Figure 5 At or near time 504, the internal rectifier 248 can block the path including the internal resistive element 246 to ground. Disabling the internal rectifier 248 or disconnecting the internal rectifier 248 from ground may cause a delay between the signal at the SR drain node 226a and the signal at the SR_SNS pin 228, because subsequent discharge of the SR_SNS pin 228 may be required through a path with high resistance. As a result, this may cause delays in turning on and / or turning off SR226 at or near t1 and / or t2, respectively. In one embodiment, adding as Figure 2EThe voltage divider 230, including the internal rectifier 248, along with its chip parasitic capacitance, may further adversely affect the turn-on and / or turn-off delay of SR 226, resulting in efficiency losses and potential cross-conduction in the AC-DC converter 200. Therefore, it is necessary to address the aforementioned power losses during the disconnected state, as well as the efficiency losses and cross-conduction caused by the SR226 switching delay.

[0081] Figure 7A This is a schematic block diagram depicting a portion of a secondary-side controller, illustrating an implementation of the SR sensing circuit 260 and voltage divider 704 according to this disclosure. In one implementation, the connection between the voltage divider 704 on the secondary side 208 and the SR sensing circuit 260 is similar to... Figure 2E As described in its corresponding description, the SR sensing circuit 260 includes a ZCD block 286, an NSN block 288, a PKD block 290, and an LFF block 292. The voltage divider 704 includes an external resistive element 244, an internal resistive element 702, an active diode 710, and a switch 706. The resistance value of the external resistive element 244 can be fixed by the manufacturer of the AC-DC converter 200 and selected based on the expected maximum voltage at the drain node 226a of the transformer 204, according to the maximum AC voltage input and the turns ratio of the transformer 204, to enable the secondary-side controller 202 to be manufactured using a non-high-voltage device manufactured using standard low-voltage technology. A suitable resistance value for the external resistive element 244 is approximately 4 kΩ to approximately 10 kΩ (e.g., 5 kΩ) to ensure that the voltage at the SR_SNS pin 228 is limited to below 20V to 22V to protect the secondary-side controller 202 from potentially high voltages from the SR drain node 226a.

[0082] In one implementation, voltage divider 704 may not include any passive or PN junction diodes, for example... Figure 2EThe internal rectifier 248 is included. In one embodiment, the implementation of the PN junction diode in the CMOS process can create a parasitic BJT junction with the substrate, which may lead to latch-up problems. Alternatively, the active diode 710, including comparator 708, can be coupled to the SR_SNS pin 228 to ensure that during negative sensing or zero-crossing sensing operation, when the voltage at the SR drain node 226a is close to ground or 0V, essentially no current flows through the voltage divider 704, allowing the full, undivided voltage at the drain node 226a to be coupled to the SR_SNS pin 228 and sensed without any attenuation. Since there is no passive diode in this embodiment, the threshold voltage drop of the diode is not shown in the figure. Alternatively, the switch can be turned off whenever the voltage on the SR_SNS pin reaches a programmable reference threshold (Vref). This threshold voltage can be very close to ground compared to a passive diode, which helps the SR_SNS pin discharge quickly, thus contributing to improved efficiency. In one embodiment, the active diode 710 may include a comparator 708 having a non-inverting input coupled via the SR_SNS pin 228 and an inverting input coupled to a programmable reference voltage (Vref). The comparator 708 may be configured to generate a switch control signal by comparing the voltage at the SR_SNS pin 228 with Vref. In one embodiment, the switch control signal may be coupled to directly control the operation of the switch 706. When the SR_SNS voltage is greater than Vref, the switch control signal may turn on the switch 706, enabling (conducting) the internal resistive element 702 to ensure that the voltage at the SR_SNS pin 228 is limited to approximately 20V to 22V. When the voltage at the SR drain node 226a is higher than 0V, it may enable LFF sensing operation (e.g., ...). Figure 5 A voltage divider is provided at t3 to t4 or at the beginning of the NSN sensing operation. When the voltage at SR_SNS 228 drops below Vref, the switch control signal can turn off switch 706, disabling or blocking the internal resistive element 702. In one embodiment, when the voltage at the drain 226a of SR is close to ground or 0V, a full, undivided voltage can be provided for ZCD sensing or NSN sensing, resulting in a good signal-to-noise ratio (SNR) and sensing accuracy. In one embodiment, Vref can be determined and fixed by the manufacturer based on design and operational requirements, as well as other parameters. Alternatively or additionally, the user can program Vref. Typically, Vref can be determined such that when the voltage at the SR_SNS pin 228 is close to 0V, switch 706 is turned off or disabled to allow undiminished NSN sensing and ZCD sensing operation. As a result, the possible delay in turning on SR 226 (at or near t1) can be reduced or eliminated.

[0083] Figure 7BThis is a schematic block diagram depicting an implementation of the voltage divider 800 according to the present disclosure. The connection between the voltage divider 800 and the SR sensing circuit 260 is similar to... Figure 2E and Figure 7A As described in their respective descriptions, the SR sensing circuit 260 includes a ZCD block 286, an NSN block 288, a PKD block 290, and an LFF block 292. In one embodiment, the voltage divider 800 includes a reference generator 804, a comparator 708, a logic gate 808, a switch 706, a mux (multiplexer) 802, and a resistor ladder including resistors 812a to 812l.

[0084] exist Figure 2A and Figure 7A The internal resistive element 246 or 702, schematically shown as a variable resistor, may have a resistance value set by the manufacturer during the manufacture of the AC-DC converter based on the desired input or output voltage, or a resistance value, such as 2KΩ, to compensate for parameter variations in the IC or other components in the AC-DC converter. Alternatively or additionally, the resistance value of the internal resistive element 702 may be dynamically adjusted by calibration circuitry in the AC-DC converter or secondary-side controller during AC-DC converter startup or power-on, or periodically adjusted after AC-DC converter startup or power-on. Figure 7B As best shown, one implementation of the internal resistive element 702 with a variable resistance value can be achieved using a resistor ladder and a mux circuit. In one embodiment, the mux 802 may include a plurality of multiplexers connected to one or more resistors 812a to 812l to adjust the total resistance of the internal resistive element 702. In one embodiment, a control signal ( Figure 7B (Not shown) Coupled to mux802 to adjust the total resistance of the internal resistive element 702. It will be understood that the resistor ladder may include any number of resistors 812a to 812l with variable resistance values, depending on design and operational requirements.

[0085] In one implementation, the output of mux 802 can be coupled to the non-inverting input of comparator 708, and the inverting input of comparator 708 can be coupled to reference generator 804 to receive Vref. Figure 7A The described implementation is similar; Vref can be fixed by the manufacturer or programmed via reference generator 804. Alternatively, with Figure 7A Similar to the configuration described herein, the non-inverting input of comparator 708 can instead be grounded to pin 228 (SR_SNS). Figure 7B(Not shown in the diagram). When the non-inverting input of comparator 806 (the voltage via mux 802 or SR_SNS pin 228) is greater than Vref, it will output an enable signal to turn on switch 706. When Vref is greater and the comparison result is opposite, comparator 708 can output a disable signal to turn off switch 706, in contrast to... Figure 7A The implementation methods described herein are similar. Alternatively, as... Figure 7B As best shown, the active diode 810 may further include a logic gate 808. A comparator 708 may be coupled to one of the inputs of the logic gate 808, which may be in the form of an AND gate. In one embodiment, the other input of the logic gate 808 may be coupled to receive NSN_EN (NSN enable signal), such that the output signal of the comparator 708 is coupled only during NSN sensing operation to control the switch 706. In one embodiment, the switch 810 may be configured to be turned on or closed during LFF sensing operation and turned off or open during ZCD sensing operation.

[0086] Figure 7A and Figure 7B The voltage divider scheme described herein, which uses active diodes 710 and 810 instead of passive diodes, can help reduce the sensing delay between the SR_drain node 226a and the SR_SNS pin 228 by activating a lower resistance path for discharge when Vref, used to operate switch 706, can be programmed. This reduction in delay in NSN detection can be up to 50%, which in turn can significantly reduce the efficiency losses of the AC-DC converter 200.

[0087] Figure 8 This is a schematic block diagram depicting a portion of the secondary-side controller, illustrating an implementation of the SR sensing circuit 260 and voltage divider 902 according to this disclosure. As previously mentioned, in addition to reducing efficiency losses and cross-conduction due to sensing delay, reducing power losses when the AC-DC converter (e.g., AC-DC converter 200) is in a disconnected state may also be crucial. (Refer to...) Figure 8 Voltage divider 902 can have the same characteristics as... Figure 7A Voltage divider 704 or Figure 7BA similar configuration to the voltage divider 800 is used, where active diodes are used instead of passive diodes. In one embodiment, the inverted output of comparator 708 is coupled to one of the inputs of logic gate 906 using inverter 904, which may be in the form of a NOR gate. The other input of logic gate 906 may be coupled to receive a disconnect signal, which may indicate that the AC-DC converter 200 is not electrically connected to any device or load (disconnected). In one embodiment, the logic operation of NOR gate 904 ensures that switch 706 is turned on only when the voltage at SR_SNS pin 228 is greater than Vref (inverted logic value of comparator 708: 0) and the AC-DC converter is not in a disconnected state (logic value: 0) (logic value: 1). In other words, regardless of the voltage at SR drain node 226a, switch 706 is always off (logic value: 0) as long as the AC-DC converter 200 is in a disconnected state (logic value: 1). In one embodiment, the internal resistive element 702 is activated only when the SR 226 function is required (i.e., during the attached state) to avoid quiescent current consumption to ground during the disconnected state. In one embodiment, it can be achieved through, as... Figure 2B The depicted AC-DC converter 200 provides a separation signal to the NOR gate 904. In one embodiment, one of the cc pins (CC1 or CC2) at its USB Type-C receptacle senses a specified resistance to ground, and then the USB-PD controller senses the attachment state. As a result, a separation signal can be generated accordingly. It will be understood that the illustrated combination of the inverting comparator and the NOR gate is merely one example of implementing the aforementioned logical result to operate the switch 706 and should not be construed as limiting.

[0088] like Figure 7A , Figure 7B and Figure 8 As explained, using a voltage divider without any passive diodes helps limit the maximum voltage at the SR_SNS pin 228 to 20V to 22V, or approximately 20V to 22V, to protect the secondary-side controller 202 of the AC-DC converter 200. This also protects the IC from high voltage during power-up of the AC-DC converter 200 when no circuitry is active. Figure 7A , Figure 7B and Figure 8 In the depicted implementation, a switch and an active diode are used instead of a passive diode. In one implementation, switch 706 can be turned on or off during power-up. To protect the IC from higher voltages during power-up, diode 705 is coupled to the SR_SNS pin 228 (anode of diode 705) and V. BUS_INBetween pin 238 (cathode of diode 705). Diode 705 helps limit the voltage on pin 228 of SR_SNS during power-up, as the maximum allowable voltage on Vbus is 21V or approximately 21V. During power-up and / or fault conditions, the current may also be limited by external resistor element 244 between pin 228 of SR_SNS and drain node 226a of SR 226.

[0089] Figure 9 A pair of schematic block diagrams depicting two alternative embodiments of a voltage divider according to this disclosure are shown. In one embodiment, the voltage divider 900 includes an external resistive element 244 connected in series with ground, an internal resistive element 702, a passive diode 912, and a switch 706. Figure 7A , Figure 7B and Figure 8 Similar to the implementation disclosed herein, switch 706 can be controlled by active diode 710 based on a comparison between Vref and the voltage at SR_SNS pin 228. In another embodiment, voltage divider 950 does not include any active or passive diodes. Figure 9 As best illustrated, the voltage divider 950 includes an external resistive element 244, an internal resistive element 702, and a switch 706 connected in series to ground. In one embodiment, the switch 706 can be controlled by a control signal received via another part of the secondary-side controller 202. One possibility for the control signal is a disconnect signal to avoid power loss during disconnection.

[0090] Now refer to Figure 10 Flowchart and Figure 7A , Figure 7B and Figure 8 The following describes a method for operating a voltage divider in an AC-DC converter having a secondary-side controller, the secondary-side controller including an IC with a single SR_SNS pin, through which the IC is coupled to the drain of the SR via the voltage divider. (Refer to...) Figure 10 The method of operating voltage divider 1000 begins with step 1002, in which ( Figure 7A and Figure 8 The voltage / signal at pin 228 of the SR_SNS module is coupled to the non-inverting input of comparator 708, which may be part of an active diode. Alternatively, the non-inverting input of comparator 708 may be coupled to an internal resistive element, such as... Figure 7B The resistors in the series are stepped up from 812a to 812l and the output node of mux 802. Next, a reference generator (e.g., Figure 7BThe reference voltage Vref generated in the reference generator 804 is coupled to the inverting input of the comparator 708 with an active diode. As previously mentioned, Vref can be fixed or programmable by the manufacturer. Next, in step 1004, the voltage at the SR_SNS pin 228 is compared with Vref.

[0091] Next, refer to Figure 10 , Figure 7A and Figure 7B The operation of switch 706 can be directly controlled using the output signal of active diode 710. (In step 1006) A check is performed to determine whether the voltage at SR_SNS pin 228 is greater than Vref. In step 1008, switch 706 can be turned on to enable the voltage division of internal resistor element 702. In one embodiment, a voltage divider can be provided for a portion of LFF sensing or NSN sensing, wherein the voltage at SR drain node 226a can be significantly higher than 0V. (In step 1006) It is also determined whether the voltage at SR_SNS pin 228 is less than Vref. A control signal from active diode 710 can be coupled to switch 706 to turn it off or on. In one embodiment, in step 1014, internal resistor element 702 can be disabled, and the full undivided voltage from SR_SNS pin 228 can be provided for ZCD and / or NSN sensing without attenuation.

[0092] Optionally or additionally, operating method 100 can solve the power loss problem during the disconnection state of AC-DC converter 200. Next, refer to... Figure 10 and Figure 8 In step 1010, the inverted output signal from comparator 708 can be coupled to the input of NOR gate 904. In one embodiment, in step 1010, a separation signal verifying that the AC-DC converter is in a separated state is provided to another input of NOR gate 904. In one embodiment, the separation signal can be generated by, for example... Figure 2B The secondary-side controller 202, as shown in the optimal embodiment, generates this signal. In one implementation, one of the cc pins (CC1 or CC2) at its USB Type-C receptacle senses a specified resistance to ground, and then the USB-PD controller senses the attachment state. As a result, a disconnect signal can be generated accordingly.

[0093] Next, a check for the presence of a disconnected state is performed using the disconnect signal. In step 1008, it is determined that if the AC-DC converter is "not in a disconnected state" (i.e., the AC-DC converter is attached and requires the SR function) and the voltage at the SR-SNS pin 228 is greater than Vref, then switch 706 is turned on or closed to enable the internal resistor element 702. In step 1014, it is also determined that regardless of the result of comparing the SR_SNS voltage with Vref, if the AC-DC converter is in a disconnected state, switch 706 will be turned off or open to disable the internal resistor element 702 and reduce power consumption.

[0094] Therefore, an AC-DC converter with secondary-side control and an SR structure, and its operation method are disclosed. Embodiments of the invention have been described above with the aid of functional and schematic block diagrams illustrating the implementation of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

[0095] The foregoing description of specific embodiments so fully reveals the general nature of the invention that, without departing from the general conception of the invention, others can readily modify and / or adapt it to various applications, such as the specific embodiments, by applying knowledge within the art, without excessive experimentation. Therefore, based on the teachings and guidance set forth herein, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limitation, and that the terminology or terminology of this specification will be interpreted by those skilled in the art based on the teachings and guidance.

[0096] It should be understood that the Detailed Description section (rather than the Summary and Abstract sections) is intended to interpret the claims. The Summary and Abstract sections may set forth one or more exemplary embodiments of the invention as conceived by the inventors, but not all exemplary embodiments, and are therefore not intended to limit the invention or the appended claims in any way.

[0097] The breadth and scope of this invention should not be limited by any of the exemplary embodiments described above, but should be defined only by the appended claims and their equivalents.

Claims

1. A secondary side controller for an AC-DC converter, comprising: a single synchronous rectifier sense terminal (SR_SNS terminal) coupled to a synchronous rectifier (SR) of the AC-DC converter, having a maximum input voltage that is significantly less than a SR drain voltage; and a voltage divider circuit coupled to the single SR_SNS terminal, the voltage divider circuit configured to provide a signal to a sense circuit, the voltage divider comprising an active diode, an internal resistive element, and a switch, wherein the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison of a voltage at the single SR_SNS terminal to a reference voltage, wherein the internal resistive element is coupled in series to ground through the switch, and wherein the switch is configured to disable voltage division during negative sensing and zero crossing detection in the secondary side controller, wherein the active diode comprises a comparator and a NOR logic function, wherein an output signal of the comparator after use of an inverter and a split signal are coupled to two inputs of the NOR logic function, and wherein an output signal of the NOR logic function is configured to control operation of the switch.

2. The secondary side controller of claim 1, wherein, the active diode is further configured to disable the internal resistive element when the AC-DC converter is in a disconnected state, wherein in the disconnected state the AC-DC converter is not electrically coupled to any load through a universal serial bus (USB) Type-C connector.

3. The secondary side controller of claim 1, wherein, the active diode comprises a comparator, and wherein: the comparator is configured to provide an enable signal to the switch when the voltage at the single SR_SNS terminal is greater than the reference voltage; and the comparator is configured to provide a disable signal to the switch when the voltage at the single SR_SNS terminal is less than the reference voltage.

4. The secondary side controller of claim 1, wherein, the sense circuit comprises a zero crossing detection (ZCD) block, a negative sense (NSN) block, a peak detection (PKD) block, and a line feed forward (LFF) block integrally formed on the sense circuit, and wherein the ZCD block, the PKD block, the NSN block, and the LFF block are coupled to a drain of the SR through the single SR_SNS terminal, wherein the NSN block is used to detect negative voltage crossings without any voltage division, and the LFF block detects scaled AC line input voltage with voltage division.

5. The secondary side controller of claim 1, wherein, the voltage divider circuit does not comprise any passive diode comprising a P-N junction diode.

6. The secondary side controller of claim 1, wherein, the voltage divider circuit further comprises an external resistive element coupled between the single SR_SNS terminal and the drain of the SR, wherein the external resistive element is disposed external to the secondary side controller.

7. The secondary side controller of claim 6, wherein, the external resistive element has a resistance value based on an AC input voltage to a primary side of a transformer of the AC-DC converter, a turns ratio of the transformer, and the maximum input voltage to the single SR_SNS terminal being less than 20V.

8. The secondary side controller of claim 1, wherein, A passive diode is arranged between the single SR SNS terminal and V BUS_IN terminal, wherein the passive diode is configured to limit a voltage at the single SR SNS terminal during power-up of the AC-DC converter.

9. The secondary side controller of claim 1, wherein, the reference voltage is programmable.

10. The secondary side controller of claim 4, wherein: The PKD block includes a PKD comparator coupled to the single SR_SNS terminal through an internal capacitor to detect a peak voltage on the single SR_SNS terminal without any clipping of the peak voltage and is configured to generate a PKD_OUT signal that is processed and sent to a primary side controller to turn on a power switch PS coupled between an AC input and a primary side of a transformer to enable a valley switching mode of operation; The ZCD block includes a ZCD comparator coupled between the single SR_SNS terminal and a negative terminal of a DC output of the AC-DC converter, the ZCD comparator configured to generate a zero current signal to turn off the SR when a zero voltage is sensed on the single SR_SNS terminal without any voltage division; The NSN block includes a NSN comparator coupled to the single SR_SNS terminal, the NSN comparator configured to generate a signal to turn on the SR; and The LFF block includes a voltage-to-current V2I block coupled to the single SR_SNS terminal and the scaled AC line input voltage is used to vary parameters of the AC-DC converter to improve efficiency and performance.

11. A method of operating a secondary side controlled AC-DC converter, comprising: sensing, with a secondary side controller, a voltage on a drain of a synchronous rectifier SR coupled to a secondary side of a transformer, the secondary side controller including an integrated circuit IC, the IC including a single synchronous rectifier sense terminal, single SR_SNS terminal, the IC coupled to the drain of the SR through the single SR_SNS terminal; sensing, through the single SR_SNS terminal, the voltage on the drain of the SR; coupling, through a voltage divider circuit including an active diode, an internal resistive element, and a switch, the single SR_SNS terminal to ground; when a voltage at the single SR_SNS terminal is determined to be less than a reference voltage, disabling the internal resistive element using the active diode and the switch, wherein disabling the internal resistive element includes sensing an un-divided voltage during negative sense and zero detection sense operations without attenuation; and when the AC-DC converter is in a detached state, disabling the internal resistive element using the active diode and the switch, wherein the active diode includes a comparator and a NOR logic function, wherein an output signal of the comparator after an inverter and a detached signal are coupled to two inputs of the NOR logic function, and wherein an output signal of the NOR logic function is configured to control operation of the switch.

12. The method of claim 11, further comprising: when a voltage at the single SR_SNS terminal is determined to be greater than the reference voltage and the AC-DC converter is in an attached state, enabling the internal resistive element using the active diode and the switch.

13. The method of claim 12, wherein, Enabling the internal resistive element includes sensing a divided voltage at the single SR_SNS terminal during line feed forward sense operations.

14. The method of claim 11, wherein, The reference voltage is programmable.

15. A system for an AC-DC converter, comprising: a transformer including a primary side coupled to receive a rectified AC input and a secondary side coupled to a DC output, and having a synchronous rectifier (SR) coupled between the DC output and the secondary side; and a secondary side controller including an integrated circuit (IC) and a plurality of terminals, the IC coupled to the secondary side of the transformer through the plurality of terminals, the plurality of terminals including a single synchronous rectifier sense terminal (SR_SNS terminal), the IC coupled to a drain of the SR through the single SR_SNS terminal to sense a voltage on the drain of the SR, wherein the single SR_SNS terminal is coupled to the drain of the SR and a sensing circuit through a voltage divider circuit, the voltage divider circuit including an active diode, an internal resistive element, and a switch, wherein the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison of the voltage at the single SR_SNS terminal and a reference voltage, wherein the internal resistive element is coupled in series to ground through the switch, and wherein the switch is configured to disable voltage division during negative sensing and zero-crossing detection in the secondary side controller, wherein the active diode includes a comparator and a NOR logic function, wherein an output signal of the comparator after use of an inverter and an isolated signal are coupled to two inputs of the NOR logic function, and wherein an output signal of the NOR logic function is configured to control operation of the switch. the active diode is further configured to disable the internal resistive element when the system is in an isolated state, wherein in the isolated state the system is not electrically coupled to any load through a USB Type-C connector.

16. The system of claim 15, wherein, the voltage divider circuit further includes an external resistive element coupling the single SR_SNS terminal to the drain of the SR.

17. The system of claim 15, wherein, the sensing circuit includes a zero-crossing detection (ZCD) block, a negative sensing (NSN) block, a peak detection (PKD) block, and a line feed forward (LFF) block integrally formed on the IC, wherein the NSN block is used to detect negative voltage crossings without any voltage division, and the LFF block detects scaled AC line input voltage with voltage division.

18. The system of claim 15, wherein, ​

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