A radiation-resistant SRAM storage circuit based on polarity reinforcement technology

Abstract

The invention discloses an anti-radiation SRAM storage circuit based on polarity reinforcement technology, comprising eight NMOS transistors and six PMOS transistors, PMOS transistors P3 and P4 are cross-coupled, NMOS transistors N3, N4 and PMOS transistors P1, P2 are used as pull-up tubes, and NMOS transistors N1, N2, N5, N6 are used as pull-down tubes; two main storage nodes Q and QN are respectively connected to bit lines BL and BLB through NMOS transistors N8 and N7, two redundant storage nodes S1 and S0 are respectively connected to bit lines BL and BLB through PMOS transistors P6 and P5, NMOS transistors N7 and N8 are controlled by word lines WL, and PMOS transistors P5 and P6 are controlled by word lines WLB. The above circuit can improve the stability of SRAM storage cells and improve the single particle upset resistance of the cells.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit design, and in particular to a radiation-resistant SRAM storage circuit based on polarity reinforcement technology. Background Art

[0002] With the advancement of science and technology, static random access memory (SRAM) has been widely used in various aerospace electronic fields, and radiation-resistant design has become the only way for the further development of the aerospace integrated circuit field. With the increase in the complexity of aerospace missions, it is required to design and manufacture integrated circuits with lower power consumption, higher integration, and higher radiation resistance. With the increasing integration, SRAM is affected by single event effects (SET), resulting in a higher probability of single event upset (SEU). Single event effect means that a single high-energy particle (proton, neutron, alpha particle, heavy ion, etc.) hits the sensitive part of the microelectronic device, and then the induced charge along its path is effectively collected and accumulated through the drift process. Once the transient voltage pulse generated by the accumulated charge is higher than the switching threshold of the circuit, the storage value in the sensitive node will change, causing temporary or permanent damage to the circuit. Therefore, SEU resistance has become an issue that cannot be ignored by scientific researchers. Summary of the invention

[0003] The object of the present invention is to provide a radiation-resistant SRAM storage circuit based on polarity reinforcement technology, which can improve the stability of SRAM storage cells and improve the cell's ability to resist single event upset (abbreviated as SEU).

[0004] The objective of the present invention is achieved through the following technical solutions:

[0005] A radiation-resistant SRAM storage circuit based on polarity reinforcement technology, the circuit includes eight NMOS transistors and six PMOS transistors, the eight NMOS transistors are sequentially recorded as N1 to N8, and the six PMOS transistors are sequentially recorded as P1 to P6, wherein:

[0006] The PMOS transistors P3 and P4 have a cross-coupling structure, that is, the gate of the PMOS transistor P3 is electrically connected to the drain of the PMOS transistor P4, and the gate of the PMOS transistor P4 is electrically connected to the drain of the PMOS transistor P3, so that the data of the main storage nodes Q and QN are latched; the NMOS transistors N3 and N4 act as pull-up transistors to open the redundant storage nodes S0 and S1 nodes to the power supply path; the NMOS transistors N1, N2, N5, and N6 act as pull-down transistors, wherein the NMOS transistors N1 and N2 open the main storage nodes Q and QN to the ground path, and the NMOS transistors N5 and N6 open the redundant storage nodes S0 and S1 to the ground path;

[0007] The two main storage nodes Q and QN are connected to the bit lines BL and BLB respectively through NMOS transistors N8 and N7, and the two redundant storage nodes S1 and S0 are connected to the bit lines BL and BLB respectively through PMOS transistors P6 and P5, wherein:

[0008] NMOS transistors N7 and N8 are controlled by word line WL, and PMOS transistors P5 and P6 are controlled by word line WLB;

[0009] The bit line BL is electrically connected to the source of the NMOS transistor N8 and the PMOS transistor P6, and the bit line BLB is electrically connected to the source of the NMOS transistor N7 and the PMOS transistor P5;

[0010] The word line WL is electrically connected to the gates of the NMOS transistors N7 and N8, and the word line WLB is electrically connected to the gates of the PMOS transistors P5 and P6;

[0011] The drain of the NMOS transistor N7 is electrically connected to the drain of the NMOS transistor N2, and the drain of the NMOS transistor N8 is electrically connected to the drain of the NMOS transistor N1; the source of the PMOS transistor P5 is electrically connected to the gate of the NMOS transistor N1, and the source of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N2;

[0012] The power supply VDD is electrically connected to the sources of the PMOS transistors P1 and P2 and the drains of the NMOS transistors N3 and N4;

[0013] Sources of the NMOS transistors N1 , N2 , N5 , and N6 are all grounded.

[0014] It can be seen from the technical solution provided by the present invention that the above circuit can improve the stability of the SRAM storage unit and improve the unit's ability to resist single-particle upset. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0016] Figure 1 A schematic diagram of the structure of a radiation-resistant SRAM storage circuit based on polarity reinforcement technology provided in an embodiment of the present invention;

[0017] Figure 2 A timing waveform diagram of the SRAM storage circuit provided by an embodiment of the present invention;

[0018] Figure 3 This is a transient waveform simulation diagram of the SRAM storage circuit provided by the embodiment of the present invention when different nodes are injected with double exponential current source pulses at different times. DETAILED DESCRIPTION

[0019] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] like Figure 1 The figure shows a schematic diagram of the structure of a radiation-resistant SRAM storage circuit based on polarity reinforcement technology provided by an embodiment of the present invention. The circuit includes eight NMOS transistors and six PMOS transistors. The eight NMOS transistors are sequentially recorded as N1 to N8, and the six PMOS transistors are sequentially recorded as P1 to P6, wherein:

[0021] The PMOS transistors P3 and P4 have a cross-coupling structure, that is, the gate of the PMOS transistor P3 is electrically connected to the drain of the PMOS transistor P4, and the gate of the PMOS transistor P4 is electrically connected to the drain of the PMOS transistor P3, so that the data of the main storage nodes Q and QN are latched; the NMOS transistors N3 and N4 act as pull-up transistors to open the redundant storage nodes S0 and S1 nodes to the power supply path; the NMOS transistors N1, N2, N5, and N6 act as pull-down transistors, wherein the NMOS transistors N1 and N2 open the main storage nodes Q and QN to the ground path, and the NMOS transistors N5 and N6 open the redundant storage nodes S0 and S1 to the ground path;

[0022] The two main storage nodes Q and QN are connected to the bit lines BL and BLB respectively through NMOS transistors N8 and N7, and the two redundant storage nodes S1 and S0 are connected to the bit lines BL and BLB respectively through PMOS transistors P6 and P5, wherein:

[0023] NMOS transistors N7 and N8 are controlled by word line WL, and PMOS transistors P5 and P6 are controlled by word line WLB;

[0024] The bit line BL is electrically connected to the source of the NMOS transistor N8 and the PMOS transistor P6, and the bit line BLB is electrically connected to the source of the NMOS transistor N7 and the PMOS transistor P5;

[0025] The word line WL is electrically connected to the gates of the NMOS transistors N7 and N8, and the word line WLB is electrically connected to the gates of the PMOS transistors P5 and P6;

[0026] The drain of the NMOS transistor N7 is electrically connected to the drain of the NMOS transistor N2, and the drain of the NMOS transistor N8 is electrically connected to the drain of the NMOS transistor N1; the source of the PMOS transistor P5 is electrically connected to the gate of the NMOS transistor N1, and the source of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N2;

[0027] The power supply VDD is electrically connected to the sources of the PMOS transistors P1 and P2 and the drains of the NMOS transistors N3 and N4;

[0028] Sources of the NMOS transistors N1 , N2 , N5 , and N6 are all grounded.

[0029] In the specific implementation, the specific connection relationship of each transistor is:

[0030] The drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P3, and the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N1 and the source of the PMOS transistor P5;

[0031] The drain of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P4, and the gate of the PMOS transistor P2 is electrically connected to the gate of the NMOS transistor N2 and the source of the PMOS transistor P6;

[0032] The drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N1, and the gate of the PMOS transistor P3 is electrically connected to the gate of the NMOS transistor N3, the drain of the NMOS transistor N7, and the drain of the PMOS transistor P4;

[0033] The drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2, and the gate of the PMOS transistor P4 is electrically connected to the gate of the NMOS transistor N4, the drain of the PMOS transistor P3, and the drain of the NMOS transistor N8;

[0034] The source of the PMOS transistor P5 is electrically connected to the gate of the NMOS transistor N1, the gate of the PMOS transistor P1, the drain of the NMOS transistor N5, and the gate of the NMOS transistor N6;

[0035] The source of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N2, the gate of the PMOS transistor P2, the drain of the NMOS transistor N6, and the gate of the NMOS transistor N5;

[0036] The drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P3, the gate of the PMOS transistor P4, the gate of the NMOS transistor N4, and the drain of the NMOS transistor N8, and the gate of the NMOS transistor N1 is electrically connected to the gate of the PMOS transistor P1, the source of the PMOS transistor P5, the gate of the NMOS transistor N6, and the drain of the NMOS transistor N5;

[0037] The drain of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P3, the gate of the NMOS transistor N3, and the drain of the NMOS transistor N7, and the gate of the NMOS transistor N2 is electrically connected to the gate of the PMOS transistor P2, the source of the PMOS transistor P6, the gate of the NMOS transistor N5, and the drain of the NMOS transistor N6;

[0038] The source of the NMOS transistor N3 is electrically connected to the gate of the NMOS transistor N1, the drain of the NMOS transistor N5, and the source of the PMOS transistor P5, and the gate of the NMOS transistor N3 is electrically connected to the gate of the PMOS transistor P3, the drain of the NMOS transistor N2, and the drain of the NMOS transistor N6;

[0039] The source of the NMOS transistor N4 is electrically connected to the gate of the NMOS transistor N2, the drain of the NMOS transistor N6, and the source of the PMOS transistor P6, and the gate of the NMOS transistor N4 is electrically connected to the gate of the PMOS transistor P4, the drain of the NMOS transistor N1, and the drain of the NMOS transistor N8;

[0040] The drain of the NMOS transistor N5 is electrically connected to the source of the NMOS transistor N3, the gate of the NMOS transistor N1, and the source of the PMOS transistor P5, and the gate of the NMOS transistor N5 is electrically connected to the gate of the PMOS transistor P2, the gate of the NMOS transistor N2, the source of the PMOS transistor P6, and the drain of the NMOS transistor N6;

[0041] The drain of the NMOS transistor N6 is electrically connected to the source of the NMOS transistor N4, the gate of the NMOS transistor N2, and the source of the PMOS transistor P6, and the gate of the NMOS transistor N6 is electrically connected to the gate of the PMOS transistor P1, the gate of the NMOS transistor N1, the source of the PMOS transistor P5, and the drain of the NMOS transistor N5;

[0042] The drain of the NMOS transistor N7 is electrically connected to the drain of the NMOS transistor N2, the gate of the NMOS transistor N3, and the gate of the PMOS transistor P3;

[0043] The drain of the NMOS transistor N8 is electrically connected to the drain of the NMOS transistor N1 , the gate of the NMOS transistor N4 , and the gate of the PMOS transistor P4 .

[0044] Based on the structure of the above circuit:

[0045] In the holding phase, the bit lines BL and BLB are both precharged to a high level, the word line WL is at a low level, the word line WLB is at a high level, the circuit remains in its initial state, and the circuit does not work;

[0046] In the data reading stage, both bit lines BL and BLB are precharged to a high level, word line WL is a high level, word line WLB is a low level, and P5, P6, N7 and N8 as transmission transistors are turned on; if the data stored in the circuit is '0', then "Q = S1 = 0, QN = S0 = 1", then the bit line BL is discharged to the ground through transistors P6 and N6, and transistors N8 and N1, so that a voltage difference is generated in the bit line BL, and then the data is read out through the sense amplifier; if the data stored in the circuit is '1', then "Q = S1 = 1, QN = S0 = 0", then the bit line BLB is discharged to the ground through transistors P5 and N5, and transistors N7, N2 and N4, so that a voltage difference is generated in the bit line BLB, and then the data is read out through the sense amplifier;

[0047] In the data writing stage, the word line WL is at a high level and the word line WLB is at a low level. If the bit line BL is at a high level and the bit line BLB is at a low level, then '1' is written to the storage nodes Q and S1 respectively through transistors N8 and P6; if the bit line BL is at a low level and the bit line BLB is at a high level, then '1' is written to the storage nodes QN and S0 respectively through transistors N7 and P5.

[0048] In the specific implementation, in the data writing stage, because data is written to the internal nodes Q\S1 and QN\S0 simultaneously through the transmission transistors N8 and P6, N7 and P5, the storage node is easier to be written with data, so the writing speed is greatly improved. At the same time, the power consumption of the circuit is reduced due to the increase in the writing speed.

[0049] In addition, the gate length of all transistors is 65nm, where:

[0050] The gate width of PMOS transistors P1, P2, P3, and P4 is 150nm;

[0051] The gate width of NMOS transistors N1, N2, N5, and N6 is 200 nm, and the gate width of NMOS transistors N3 and N4 is 75 nm;

[0052] The gate width of the remaining transistors is 140nm.

[0053] like Figure 2 The timing waveform diagram of the SRAM storage circuit provided by the embodiment of the present invention is shown in FIG. 1 . The specific simulation conditions are: Corner: TT; Temperature: 27°C; VDD: 1.2V. Figure 2 It can be seen that before the word line WL is turned on, the bit lines BL and BLB maintain a high level to achieve the bit line precharge signal retention; after the word line WL is turned on, the bit lines BL and BLB become high and low levels alternately. It can be seen intuitively from the waveform that the signals of the word lines WL and WLB are reverse signals. At the same time, it can be observed that the storage information of the Q and S1 nodes is consistent, and the storage information of the QN and S0 nodes is consistent.

[0054] like Figure 3 The figure shows the transient waveform simulation diagram of the SRAM storage circuit provided by the embodiment of the present invention when different nodes are injected with double exponential current source pulses at different times. The specific simulation conditions are: VDD: 1.2V, Figure 3 It can be seen that: read and write operation settings and Figure 2 The settings remain consistent, and the main storage nodes Q and QN are bombarded with double exponential current source pulses at 10ns. It is observed that the Q and QN nodes quickly recover to the original storage data, and the levels are also at the levels before the bombardment. At 20ns, the redundant storage nodes S0, S1 and QN are bombarded respectively, and it is observed that the circuit can still resist the interference of the bombardment current, and during the two bombardment processes, the storage information stored in Q and QN is not leaked or flipped. It can be concluded that the circuit described in the embodiment of the present invention can meet the requirements of radiation-resistant design.

[0055] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to professional and technical personnel in the field.

[0056] To summarize, based on the structure of the circuit described in the embodiment of the present application, when only considering the improvement of the circuit structure's anti-irradiation performance, if the storage node of the circuit is bombarded by particles, since the storage nodes S0 and S1 are surrounded by PMOS transistors, according to the polarity reinforcement principle, the space particles bombard the sensitive node PMOS tube, and only generate a "0-1" voltage pulse at the node, and this pulse cannot affect the state of other transistors due to the existence of the gate capacitor, which effectively prevents the external storage nodes S0 and S1 from flipping. At the same time, the stability of the data of the S0 and S1 nodes ensures that the internal storage nodes Q and QN can be restored to the initial state after the flip, thereby improving the circuit's ability to resist SEU. If other non-critical nodes are bombarded by particles, the storage unit will be less susceptible to being affected.

[0057] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A radiation-resistant SRAM storage circuit based on polarity reinforcement technology, characterized in that: The circuit includes eight NMOS transistors and six PMOS transistors, the eight NMOS transistors are sequentially denoted as N1 to N8, and the six PMOS transistors are sequentially denoted as P1 to P6, wherein: The PMOS transistors P3 and P4 have a cross-coupling structure, that is, the gate of the PMOS transistor P3 is electrically connected to the drain of the PMOS transistor P4, and the gate of the PMOS transistor P4 is electrically connected to the drain of the PMOS transistor P3, so that the data of the main storage nodes Q and QN are latched; the NMOS transistors N3 and N4 act as pull-up transistors to open the redundant storage nodes S0 and S1 nodes to the power supply path; the NMOS transistors N1, N2, N5, and N6 act as pull-down transistors, wherein the NMOS transistors N1 and N2 open the main storage nodes Q and QN to the ground path, and the NMOS transistors N5 and N6 open the redundant storage nodes S0 and S1 to the ground path; The two main storage nodes Q and QN are connected to the bit lines BL and BLB respectively through NMOS transistors N8 and N7, and the two redundant storage nodes S1 and S0 are connected to the bit lines BL and BLB respectively through PMOS transistors P6 and P5, wherein: NMOS transistors N7 and N8 are controlled by word line WL, and PMOS transistors P5 and P6 are controlled by word line WLB; The bit line BL is electrically connected to the source of the NMOS transistor N8 and the PMOS transistor P6, and the bit line BLB is electrically connected to the source of the NMOS transistor N7 and the PMOS transistor P5; The word line WL is electrically connected to the gates of the NMOS transistors N7 and N8, and the word line WLB is electrically connected to the gates of the PMOS transistors P5 and P6; The drain of the NMOS transistor N7 is electrically connected to the drain of the NMOS transistor N2, and the drain of the NMOS transistor N8 is electrically connected to the drain of the NMOS transistor N1; the source of the PMOS transistor P5 is electrically connected to the gate of the NMOS transistor N1, and the source of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N2; The power supply VDD is electrically connected to the sources of the PMOS transistors P1 and P2 and the drains of the NMOS transistors N3 and N4; The sources of NMOS transistors N1, N2, N5, and N6 are all grounded; Among them, the specific connection relationship of each transistor is: The drain of the PMOS transistor P1 is electrically connected to the source of the PMOS transistor P3, and the gate of the PMOS transistor P1 is electrically connected to the gate of the NMOS transistor N1 and the source of the PMOS transistor P5; The drain of the PMOS transistor P2 is electrically connected to the source of the PMOS transistor P4, and the gate of the PMOS transistor P2 is electrically connected to the gate of the NMOS transistor N2 and the source of the PMOS transistor P6; The drain of the PMOS transistor P3 is electrically connected to the drain of the NMOS transistor N1, and the gate of the PMOS transistor P3 is electrically connected to the gate of the NMOS transistor N3, the drain of the NMOS transistor N7, and the drain of the PMOS transistor P4; The drain of the PMOS transistor P4 is electrically connected to the drain of the NMOS transistor N2, and the gate of the PMOS transistor P4 is electrically connected to the gate of the NMOS transistor N4, the drain of the PMOS transistor P3, and the drain of the NMOS transistor N8; The source of the PMOS transistor P5 is electrically connected to the gate of the NMOS transistor N1, the gate of the PMOS transistor P1, the drain of the NMOS transistor N5, and the gate of the NMOS transistor N6; The source of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N2, the gate of the PMOS transistor P2, the drain of the NMOS transistor N6, and the gate of the NMOS transistor N5; The drain of the NMOS transistor N1 is electrically connected to the drain of the PMOS transistor P3, the gate of the PMOS transistor P4, the gate of the NMOS transistor N4, and the drain of the NMOS transistor N8, and the gate of the NMOS transistor N1 is electrically connected to the gate of the PMOS transistor P1, the source of the PMOS transistor P5, the gate of the NMOS transistor N6, and the drain of the NMOS transistor N5; The drain of the NMOS transistor N2 is electrically connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P3, the gate of the NMOS transistor N3, and the drain of the NMOS transistor N7, and the gate of the NMOS transistor N2 is electrically connected to the gate of the PMOS transistor P2, the source of the PMOS transistor P6, the gate of the NMOS transistor N5, and the drain of the NMOS transistor N6; The source of the NMOS transistor N3 is electrically connected to the gate of the NMOS transistor N1, the drain of the NMOS transistor N5, and the source of the PMOS transistor P5, and the gate of the NMOS transistor N3 is electrically connected to the gate of the PMOS transistor P3, the drain of the NMOS transistor N2, and the drain of the NMOS transistor N6; The source of the NMOS transistor N4 is electrically connected to the gate of the NMOS transistor N2, the drain of the NMOS transistor N6, and the source of the PMOS transistor P6, and the gate of the NMOS transistor N4 is electrically connected to the gate of the PMOS transistor P4, the drain of the NMOS transistor N1, and the drain of the NMOS transistor N8; The drain of the NMOS transistor N5 is electrically connected to the source of the NMOS transistor N3, the gate of the NMOS transistor N1, and the source of the PMOS transistor P5, and the gate of the NMOS transistor N5 is electrically connected to the gate of the PMOS transistor P2, the gate of the NMOS transistor N2, the source of the PMOS transistor P6, and the drain of the NMOS transistor N6; The drain of the NMOS transistor N6 is electrically connected to the source of the NMOS transistor N4, the gate of the NMOS transistor N2, and the source of the PMOS transistor P6, and the gate of the NMOS transistor N6 is electrically connected to the gate of the PMOS transistor P1, the gate of the NMOS transistor N1, the source of the PMOS transistor P5, and the drain of the NMOS transistor N5; The drain of the NMOS transistor N7 is electrically connected to the drain of the NMOS transistor N2, the gate of the NMOS transistor N3, and the gate of the PMOS transistor P3; The drain of the NMOS transistor N8 is electrically connected to the drain of the NMOS transistor N1 , the gate of the NMOS transistor N4 , and the gate of the PMOS transistor P4 .

2. The radiation-resistant SRAM storage circuit based on polarity reinforcement technology according to claim 1, characterized in that: Based on the structure of the circuit: In the holding phase, the bit lines BL and BLB are both precharged to a high level, the word line WL is at a low level, the word line WLB is at a high level, the circuit remains in its initial state, and the circuit does not work; In the data reading stage, both bit lines BL and BLB are precharged to a high level, word line WL is a high level, word line WLB is a low level, and P5, P6, N7 and N8 as transmission transistors are turned on; if the data stored in the circuit is '0', then "Q = S1 = 0, QN = S0 = 1", then the bit line BL is discharged to the ground through transistors P6 and N6, and transistors N8 and N1, so that a voltage difference is generated in the bit line BL, and then the data is read out through the sense amplifier; if the data stored in the circuit is '1', then "Q = S1 = 1, QN = S0 = 0", then the bit line BLB is discharged to the ground through transistors P5 and N5, and transistors N7, N2 and N4, so that a voltage difference is generated in the bit line BLB, and then the data is read out through the sense amplifier; In the data writing stage, the word line WL is at a high level and the word line WLB is at a low level. If the bit line BL is at a high level and the bit line BLB is at a low level, then '1' is written to the storage nodes Q and S1 respectively through transistors N8 and P6; if the bit line BL is at a low level and the bit line BLB is at a high level, then '1' is written to the storage nodes QN and S0 respectively through transistors N7 and P5.

3. The radiation-resistant SRAM storage circuit based on polarity reinforcement technology according to claim 1, characterized in that: The gate length of all transistors is 65nm, where: The gate width of PMOS transistors P1, P2, P3, and P4 is 150nm; The gate width of NMOS transistors N1, N2, N5, and N6 is 200 nm, and the gate width of NMOS transistors N3 and N4 is 75 nm; The gate width of the remaining transistors is 140nm.

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