Ringing gate input / output engineering

Abstract

A method of manufacturing a gate-all-around electronic device is described. The method includes forming a thermal oxide layer by enhancing in-situ steam generation processing in combination with atomic layer deposition of a low-K layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the gate-all-around (GAA). The passivation processing after deposition of the low-K layer reduces bulk traps and enhances the breakdown performance of the GAA transistor.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention generally relate to the fabrication of integrated circuits. More specifically, embodiments relate to materials and integration in gate engineering of wrap-around gates.

[0002] Description of the Related Art

[0003] Transistors are a key component of most integrated circuits. Since the drive current of a transistor, and thus the speed of the transistor, is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Thus, there is a tradeoff between the size and speed of a transistor, and "finFETs" have been developed to address the conflicting goals of having a transistor with maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that substantially increases the size of the transistor without significantly increasing the footprint of the transistor, and finFETs are now employed in many integrated circuits. However, finFETs have their own drawbacks.

[0004] The formation of horizontal source / drain extensions becomes increasingly difficult for narrow and tall finFETs, as the fin-shaped channel region can be simply amorphized or damaged by conventional ion implantation techniques, such as beamline ion implantation. In particular, in some finFET architectures (e.g., horizontal wrap-around gate (h-GAA)), ion implantation can cause severe intermixing between the silicon channel and the adjacent silicon germanium (SiGe) sacrificial layer. This intermixing is highly undesirable, as it can thus compromise the ability to selectively remove the sacrificial SiGe layer. Moreover, the repair of this implant damage via thermal anneal increases the thermal budget of the finFET device.

[0005] Logic gate performance is related to the properties of the materials used and the thickness and area of the structural layers. However, challenges arise when some gate features are adjusted to accommodate device scaling. Furthermore, the space confinement between pillars on horizontal wrap-around gate (hGAA) devices limits the thickness of the gate dielectric material for input / output (I / O) transistors. Thus, there is a need for material and integration choices to address this space confinement in hGAA devices. SUMMARY

[0006] One or more embodiments of the present invention relate to a method of fabricating an electronic device, the method comprising the steps of: forming alternating silicon (Si) layers and silicon germanium (SiGe) layers on a substrate; patterning and etching the alternating silicon layers and silicon germanium layers to expose at least one sidewall of a silicon layer and at least one sidewall of a silicon germanium layer; selectively etching the silicon germanium layers to form an opening; forming a thermal oxide layer on the silicon layer through the opening; passivating the thermal oxide layer to form a passivated thermal oxide layer; depositing a low-k layer on the passivated thermal oxide layer through the opening; and densifying the low-k layer to form a densified low-k layer.

[0007] Additional embodiments of the present invention relate to a processing tool for forming a semiconductor device, the processing tool comprising: a central transfer station having a plurality of processing chambers disposed about the central transfer station; a robot within the central transfer station configured to move a substrate between the plurality of processing chambers; a first processing chamber coupled to the central transfer station, the first processing chamber configured to perform an in-situ steam generation process to deposit a thermal oxide layer; a metrology station within the processing tool accessible by the robot, the metrology station configured to determine a thickness of the thermal oxide layer on the substrate; a second processing chamber coupled to the central transfer station, the second processing chamber configured to perform an atomic layer deposition process; and a controller coupled to one or more of the central transfer station, the robot, the first processing chamber, the metrology station, or the second processing chamber, the controller having a configuration selected from one or more of: a first configuration to move the substrate on the robot between the plurality of processing chambers and the metrology station; a second configuration to perform the in-situ steam generation process to deposit the thermal oxide layer on the substrate in the first processing chamber; a third configuration to perform an analysis to determine the thickness of the thermal oxide layer in the metrology station; or a fourth configuration to perform the atomic layer deposition process in the second processing chamber, the atomic layer deposition adjusted for the thickness of the thermal oxide layer.

[0008] Further embodiments of the present invention relate to a non-transitory computer readable medium comprising a plurality of instructions that, when executed by a controller of a processing tool, cause the processing tool to perform the following operations: forming alternating silicon layers and silicon germanium layers on a substrate; patterning and etching the alternating silicon layers and silicon germanium layers to expose at least one sidewall; selectively etching the silicon germanium layers; performing an enhanced in-situ steam generation process to form a thermal oxide layer on the silicon layers; passivating the thermal oxide layer; depositing a low-k layer; and densifying and / or passivating the low-k layer. BRIEF DESCRIPTION OF DRAWINGS

[0009] A more particular description of the present application, briefly summarized above, can be had by reference to certain embodiments, some of which are illustrated in the appended drawings, wherein:

[0010] Figure 1 is a process flow diagram of a fabrication process to form a gate-all-around (GAA) transistor in accordance with one or more embodiments of the present application;

[0011] Figure 2A is a cross-sectional view of a gate-all-around (GAA) transistor in accordance with one or more embodiments of the present application;

[0012] Figure 2B is a cross-sectional view of a gate-all-around (GAA) transistor in accordance with one or more embodiments of the present application;

[0013] Figure 2C is a cross-sectional view of a gate-all-around (GAA) transistor in accordance with one or more embodiments of the present application;

[0014] Figure 2D is a cross-sectional view of a gate-all-around (GAA) transistor in accordance with one or more embodiments of the present application;

[0015] Figure 2E is a cross-sectional view of a gate-all-around (GAA) transistor in accordance with one or more embodiments of the present application;

[0016] Figure 2F is a cross-sectional view of a gate-all-around (GAA) transistor in accordance with one or more embodiments of the present application;

[0017] Figure 2G is a cross-sectional view of a gate-all-around (GAA) transistor in accordance with one or more embodiments of the present application; and

[0018] Figure 3 shows a diagrammatic view of a processing system that performs a method in accordance with any embodiment of the present application. DETAILED DESCRIPTION

[0019] Before one or more embodiments of the application are explained in detail, it is to be understood that the application is not limited in its application to the details of construction or the arrangements of the components set forth in the following description or illustrated in the drawings. The application is capable of other embodiments and of being practiced or being carried out in various ways.

[0020] As used in this specification and the appended claims, the term "substrate" refers to a surface or a portion of a surface upon which processing is performed. Unless the context clearly indicates otherwise, it will be understood that references to a substrate can also be simply referring to a portion of the substrate. In addition, references to deposition on a substrate can mean both a bare substrate and a substrate with one or more films or features deposited or formed thereon.

[0021] As used herein, "substrate" refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface upon which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates can be subjected to pre-processing routines to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present application, any of the film processing steps disclosed can also be performed on an underlayer formed on the substrate, as will be explained in more detail below, and the term "substrate surface" is intended to include such underlayer as the context indicates. Thus, for example, where a film / layer or portion thereof has been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0022] As used in this specification and the appended claims, the terms "precursor", "reactant", "reactive gas", and the like are used interchangeably to mean any gaseous species capable of reacting with a substrate surface.

[0023] A transistor is an electrical circuit component or element that is typically formed on a semiconductor device. Depending on the circuit design, transistors are formed on semiconductor devices in addition to capacitors, inductors, resistors, diodes, wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is positioned over the channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0024] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Field effect transistors generally exhibit very high input impedance at low temperatures. Conduction between the drain and source terminals is controlled by the electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of a FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which terminal regulates channel conduction. Conventionally, the current entering the channel at the source (S) is designated as I S , and the current entering the channel at the drain (D) is designated as I D . The drain-to-source voltage is designated as V DS . By applying a voltage to the gate (G), the current at the drain entering the channel (i.e., I D ) can be controlled.

[0025] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). MOSFETs have an insulated gate whose voltage determines the conductivity of the device. The ability to vary the conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of the charge density of a metal-oxide-semiconductor (MOS) capacitor between a body electrode and a gate electrode that is insulated from all other device regions by a gate dielectric layer and sits above the body. In comparison to MOS capacitors, MOSFETs include two additional terminals (source and drain), each connected to a separate highly doped region separated by the body region. These regions can be either p-type or n-type, but they are all of the same type and of opposite type to the body region. The source and drain (unlike the body) are highly doped and denoted with a "+" sign after the type of doping.

[0026] If the MOSFET is an n-channel or nMOSFET, the source and drain are n+ regions and the body is a p-region. If the MOSFET is a p-channel or pMOSFET, the source and drain are p+ regions and the body is an n-region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

[0027] As used herein, the term "fin field-effect transistor" (FinFET) refers to a MOSFET transistor fabricated on a substrate in which the gate is placed on two, three, or four sides of the channel or wraps around the channel, forming a dual-gate structure. FinFET devices have been so named because the source / drain regions form "fins" on the substrate. FinFET devices have fast switching times and high current densities.

[0028] As used herein, the term "gate-all-around" (GAA) is used to refer to an electronic device such as a transistor in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor can include nanowire channels, strip channels, or any suitable channel configuration known to those of skill in the art. In one or more embodiments, the channel region of a GAA device has multiple horizontal nanowires or horizontal strips that are vertically separated, such that the GAA transistor is a stacked horizontal gate-all-around (hGAA) transistor.

[0029] In one or more embodiments, a horizontal gate all around (hGAA) transistor includes a substrate having a top surface; a source region having a source and a source contact, the source region on the top surface of the substrate; a drain region having a drain and a drain contact, the drain region on the top surface of the substrate; a channel between the source and the drain, the channel having an axis substantially normal to the top surface of the substrate; a gate surrounding the channel between the source region and the drain region; a thermal oxide layer covering and contacting one or more of the gate, the source contact, or the drain contact, and a low-K dielectric layer covering the thermal oxide layer. In one or more embodiments, the low-K dielectric layer has a thickness less than about 2 nm.

[0030] Embodiments of the present invention relate to gate all around transistors with thin thermal oxide layers combined with low-K material layers to achieve high effective oxide thickness (EOT). In one or more embodiments, the use of a thin layer of thermal oxide combined with low-K dielectric material increases the effective electrical thickness necessary for gate all around input / output (I / O) transistors. In one or more embodiments, a PME treatment is used after atomic layer deposition of the low-K material to suppress bulk defects formed in the low-K material.

[0031] One or more embodiments provide a method of fabricating a gate all around (GAA) input / output (I / O) transistor. The method includes the step of forming a thermal oxide layer by enhanced in-situ steam generation (eISSG) treatment combined with atomic layer deposition of a low-K layer. The thin thermal oxide layer passivates the interface between the silicon layer of the GAA and the low-K dielectric layer. The passivation treatment after deposition of the low-K layer reduces bulk traps and enhances the breakdown performance of the GAA transistor.

[0032] Figure 1 is a process flow diagram of a fabrication process 100 of a GAA transistor according to various embodiments of the present invention. Figures 2A-2E is a diagrammatic cross-sectional view of a GAA structure 200 corresponding to various stages of the process 100 according to embodiments of the present invention. Although the process 100 is described for forming a nanowire GAA structure, the process 100 can also be applied to form other structures on a substrate.

[0033] The process 100 begins at operation 102, where alternating silicon layers 204 and silicon germanium (SiGe) layers 206 are formed on a bulk semiconductor substrate 202, as shown in Figure 2A The bulk semiconductor substrate 202 can be formed of silicon, silicon germanium, or any other suitable bulk crystalline semiconductor material. The silicon layers 204 and the silicon germanium layers 206 can each be formed via a selective epitaxial growth (SEG) process, and generally comprise a crystalline semiconductor material.

[0034] In operation 104, the silicon layer 204 and the silicon germanium layer 206 are patterned and etched to expose vertical sidewalls 208 on the silicon layer 204 and vertical sidewalls 210 on the silicon germanium layer 206, as shown in Figure 2B In some embodiments, operation 104 includes a deep reactive ion etching (DRIE) process.

[0035] In operation 106, the silicon germanium layer 206 is selectively etched inward from the vertical sidewalls 210 to form a trench or opening 212, as shown in Figure 2C In some embodiments, a chemical vapor etching (CVE) process is used to selectively remove the silicon germanium layer 206 over the silicon layer 204. For example, a gaseous hydrochloric acid selective etch of SiGe over Si in a reduced pressure chemical vapor deposition reactor has been demonstrated. Alternatively, an ex-situ HF soak followed by a GeH4enhanced Si etch performed in-situ in an epitaxial reactor can be applied in operation 106.

[0036] In operation 108, a thermal oxide layer 214 is formed on the silicon layer 204. In one or more embodiments, the thermal oxide layer includes one or more silicon oxides. In one or more embodiments, the thermal oxide layer is formed by an enhanced in-situ steam generation (eISSG) process.

[0037] Generally, an oxide layer can be formed using a wet furnace oxidation process or a dry oxidation process. A wet furnace oxidation process exposes a silicon layer to a high temperature environment in the presence of water vapor. Water from the water vapor diffuses through the oxide layer to the oxide / silicon interface, where the water and silicon react with each other to form silicon dioxide. However, a wet furnace oxidation process causes the oxide layer to bulge outward from the silicon layer, providing a surface with a convex curvature that forms non-uniformities. These non-uniformities cause performance and reliability problems. Furthermore, a wet furnace oxidation process also provides a poor quality oxide due to dangling bonds in the non-reacted silicon. This poor quality oxide increases the roughness at the interface between the oxide layer and the silicon layer.

[0038] Accordingly, in one or more embodiments, an enhanced in-situ steam generation (eISSG) process is used to form the thermal oxide layer 214 on the silicon layer 204. As used herein, the term "in-situ steam generation (ISSG) process" refers to an oxidation technique for single wafer rapid thermal processing (RTP). ISSG is a low pressure process (typically less than about 20 Torr) in which pre-mixed hydrogen (H2) and oxygen (O2) are introduced directly into the process chamber without pre-combustion. The process gases (pure hydrogen (H2) and oxygen (O2)) are mixed in a gas chamber and then injected into the chamber, where the process gases flow across a rotating substrate heated by a lamp, such as a tungsten halogen lamp, separated by a thin quartz window. Because the hot substrate acts as an ignition source, the reaction between the hydrogen (H2) and oxygen (O2) occurs close to the substrate surface. In one or more embodiments, the thermal oxide layer 214 has a thickness of about 10-20 A. to about a thickness in the range of about about about about about about about or about

[0039] In operation 110, the one or more passivation and functionalized thermal oxide layers 214 are annealed (e.g., RTX (at RTH2 or RTN2)) or plasma treatment process (e.g., DPX (at DPHe, DPH2, DPN2, or DPNH3)), and the like, as shown in Figure 2E to form passivated and functionalized thermal oxide layers 215.

[0040] In operation 112, a low-k layer 216 is then conformally deposited on the passivated and functionalized thermal oxide layers 215, as shown in Figure 2F In one or more embodiments, the low-k layer 216 fills at least a portion of the trench 212. In one or more embodiments, the low-k layer is deposited by atomic layer deposition (ALD). In one or more embodiments, the low-k layer is deposited by plasma enhanced atomic layer deposition (PEALD). In one or more embodiments, the low-k layer 216 has a thickness of less than about 2 nm, or less than about 1.5 nm.

[0041] In one or more embodiments, the low-k layer 216 has a dielectric constant or dissipation factor or K value in the range of about 2.0 to about 6.0, including about 2.25, about 2.5, about 2.75, about 3.0, about 3.25, about 3.5, about 3.75, about 4.0, about 4.25, about 4.5, about 4.75, about 5.0, about 5.25, about 5.5, about 5.75, or about 6.0. In one or more particular embodiments, the low-k layer 216 has a dielectric constant or dissipation factor or K value of about 2.

[0042] In one or more embodiments, the low-k layer 216 includes any low-k dielectric material known to those skilled in the art. In one or more embodiments, the low-k layer 216 includes a low-k dielectric material having atoms of one or more of silicon (Si), aluminum (Al), carbon (C), oxygen (O), hydrogen (H), or nitrogen (N). For example, the low-k layer 216 includes one or more of silicon oxide, silicon oxycarbide, silicon oxynitride, SiCOH, SiCONH, aluminum oxide, and the like. Although the term "silicon oxide" can be used to describe the low-k layer 216, those skilled in the art will recognize that the present invention is not limited to a particular stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" can be used to describe a material having silicon and oxygen atoms in any suitable stoichiometric ratio. This is true for other materials listed in the present invention, such as silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and the like.

[0043] As used herein, "atomic layer deposition" or "cyclical deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or portions of the substrate are sequentially or separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay to allow each compound to adhere and / or react on the substrate surface before being purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate.

[0044] In a spatial ALD process, different portions of the substrate surface or material on the substrate surface are simultaneously exposed to two or more reactive compounds such that at any given point on the substrate is not substantially simultaneously exposed to more than one reactive compound. As used in this specification and the appended claims, the term "substantially" when used in this manner means that there is a possibility that a small portion of the substrate can be simultaneously exposed to multiple reactive gases due to diffusion, but this simultaneous exposure is not intentional.

[0045] In one aspect of the time-domain ALD process, a first reactant gas (i.e., a first precursor or compound A, such as a manganese precursor, a ruthenium precursor, or a manganese-ruthenium precursor) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B (e.g., a reducing agent) is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, can be introduced into the processing chamber to purge the reaction zone or remove any residual reaction compounds or reaction byproducts from the reaction zone. Alternatively, a purge gas can be continuously flowed throughout the deposition process, such that only the purge gas is flowed during the time delays between pulses of the reaction compounds. The reaction compounds are alternately pulsed until the desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsed compound A, purge gas, compound B, and purge gas is a cycle. A cycle can begin with compound A or compound B and continue in the respective order of this cycle until a film having a predetermined thickness is achieved.

[0046] As used herein, "pulse" or "dose" is intended to refer to the amount of source gas introduced into the processing chamber intermittently or non-continuously. The amount of a particular compound in each pulse can vary over time depending on the duration of the pulse. A particular process gas can include a single compound or a mixture / combination of two or more compounds, such as the process gases described below.

[0047] The duration of each pulse / dose can vary and can be adjusted to accommodate, for example, the volumetric capacity of the processing chamber and the ability of the vacuum system coupled to the processing chamber. Further, the dose time of the process gas can vary depending on the flow rate of the process gas, the temperature of the process gas, the type of control valve, the type of processing chamber utilized, and the ability of the constituents of the process gas to adsorb on the substrate surface. The dose time can also vary based on the type of layer being formed and the geometry of the device being formed. The dose time should be long enough to provide a volume of the compound sufficient to adsorb / chemisorb on substantially the entire surface of the substrate and form a layer of the constituents of the process gas on the surface.

[0048] The metal-containing precursor process gas can be provided in one or more pulses or continuously. The flow rate of the metal-containing precursor process gas can be any suitable flow rate, including but not limited to, a flow rate in a range from about 1 to about 5000 seem, or in a range from about 2 to about 4000 seem, or in a range from about 3 to about 3000 seem, or in a range from about 5 to about 2000 seem. The metal precursor can be provided at any suitable pressure, including but not limited to, a pressure in a range from about 5 mTorr to about 500 Torr, or in a range from about 100 mTorr to about 500 Torr, or in a range from about 5 Torr to about 500 Torr, or in a range from about 50 mTorr to about 500 Torr, or in a range from about 100 mTorr to about 500 Torr, or in a range from about 200 mTorr to about 500 Torr.

[0049] The time period during which the substrate is exposed to the one or more metal-containing precursor process gases can be any suitable amount of time necessary to allow the metal precursor to form a suitable nucleation layer on top of the conductive surface of the bottom of the opening. For example, the process gas can be flowed into the processing chamber for a period of time ranging from about 0.1 seconds to about 90 seconds. In some time-domain ALD processes, the duration of the metal-containing precursor process gas exposure of the substrate surface ranges from about 0.1 seconds to about 90 seconds, or ranges from about 0.5 seconds to about 60 seconds, or ranges from about 1 second to about 30 seconds, or ranges from about 2 seconds to about 25 seconds, or ranges from about 3 seconds to about 20 seconds, or ranges from about 4 seconds to about 15 seconds, or ranges from about 5 seconds to about 10 seconds.

[0050] In some embodiments, an inert carrier gas can additionally be provided to the processing chamber at the same time as the metal-containing precursor process gas. The carrier gas can be mixed with the metal-containing precursor process gas (e.g., as a dilution gas) or separate from the metal-containing precursor process gas, and can be pulsed or continuously flowing. In some embodiments, the carrier gas is flowed into the processing chamber at a fixed flow rate ranging from about 1 to about 10,000 seem. The carrier gas can be any inert gas, such as, for example, argon, helium, neon, combinations of the foregoing, or the like. In one or more embodiments, the metal-containing precursor process gas is mixed with argon prior to being flowed into the processing chamber.

[0051] In embodiments of spatial ALD processing, the first and second reactant gases are delivered to the reaction zone simultaneously, but separated by an inert and / or vacuum curtain. The substrate is moved relative to the gas delivery apparatus so that any given point on the substrate is exposed to the first and second reactant gases.

[0052] In operation 114, the low-K layer 216 is densified and passivated to reduce bulk defects. In one or more embodiments, the low-K layer 216 is treated with one or more of an anneal process (e.g., RTX (at RTH2 or RTN2)) or a plasma process (e.g., DPX (at DPHe, DPH2, DPN2, or DPNH3)) to form a densified / passivated low-K layer 217.

[0053] In one or more embodiments, the densified / passivated low-K layer 217 has a density ranging from greater than about 2.1 g / cc, including greater than about 2.15 g / cc, greater than about 2.2 g / cc, greater than about 2.25 g / cc, greater than about 2.3 g / cc, greater than about 2.35 g / cc, greater than about 2.4 g / cc, or greater than about 2.5 g / cc.

[0054] Referring to Figure 1In one or more embodiments, the advanced process control (APC) is integrated with operations 108, 110, 112, and 114. As used herein, the term "integrated" means that the formation of the thermal oxide, the passivation and functionalization, the ALD deposition of the low K layer 216, and the densification and passivation of the low K layer 216 are performed in the same platform (under vacuum processing). At operation 120, an integrated metrology tool can be used to determine the thickness of the thermal oxide layer 214 and the low K layer 216. In some embodiments, the integrated metrology tool is performed in-situ. Once the thickness of the layers 214, 216 has been determined by the integrated metrology tool, this measurement is fed to the tool to perform compensation (e.g., the thickness / composition of the first layer can be adjusted accordingly). In some embodiments, the advanced process control includes one or more of scatterometry (i.e., optical critical dimension (OCD) metrology), refractometry, ellipsometry, or electron beam.

[0055] After operation 114, the remaining components of the GAA transistor 200 can be completed using conventional manufacturing techniques known to those skilled in the art.

[0056] Referring to Figure 3 Additional embodiments of the application relate to processing systems 900 that perform the methods described herein. Figure 3 A system 900 that can be used to process a substrate in accordance with one or more embodiments of the application is depicted. The system 900 can be referred to as a cluster tool. The system 900 includes a central transfer station 910 having a robot 912 therein. The robot 912 is depicted as a single blade robot; however, those skilled in the art will recognize that other robot 912 configurations are within the scope of the application. The robot 912 is provided to move one or more substrates between chambers connected to the central transfer station 910.

[0057] At least one pre-clean / buffer chamber 920 is connected to the central transfer station 910. The pre-clean / buffer chamber 920 can include one or more of a heater, a source of radiation, or a plasma source. The pre-clean / buffer chamber 920 can be used as a holding area for individual semiconductor substrates or for cassettes of wafers for processing. The pre-clean / buffer chamber 920 can perform a pre-clean process or can pre-heat the substrates for processing or can simply be a staging area for a process sequence. In some embodiments, there are two pre-clean / buffer chambers 920 connected to the central transfer station 910.

[0058] In Figure 3In the illustrated embodiment, the pre-clean chamber 920 can serve as a pass-through chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 can include one or more robots 906 to move substrates from a cassette to the pre-clean / buffer chamber 920. The robot 912 can then move the substrates from the pre-clean / buffer chamber 920 to other chambers within the system 900.

[0059] The first processing chamber 930 can be connected to the central transfer station 910. The first processing chamber 930 can be configured as an ISSG chamber and can be in flow communication with one or more reactant gas sources to provide one or more reactant gas flows to the first processing chamber 930. Substrates can be moved to or from the processing chamber 930 by the robot 912 through the isolation valve 914.

[0060] The processing chamber 940 can also be connected to the central transfer station 910. In some embodiments, the processing chamber 940 comprises an ALD deposition chamber and is in fluid communication with one or more reactant gas sources to provide a flow of reactant gas to the processing chamber 940 to perform an isotropic etch process. Substrates can be moved to or from the processing chamber 940 by the robot 912 through the isolation valve 914.

[0061] The processing chamber 945 can also be connected to the central transfer station 910. In some embodiments, the processing chamber 945 is the same type as the processing chamber 940 and is configured to perform the same processing as the processing chamber 940. This arrangement can be useful in situations where the processing occurring in the processing chamber 940 takes significantly more time than the processing in the processing chamber 930.

[0062] In some embodiments, the processing chamber 960 is connected to the central transfer station 910 and is configured to serve as a densification and / or passivation chamber. The processing chamber 960 can be configured to perform one or more different epitaxial growth processes.

[0063] In some embodiments, each of the processing chambers 930, 940, 945, and 960 are configured to perform different portions of a processing method. For example, the processing chamber 930 can be configured to perform an eISSG process, the processing chamber 940 can be configured to perform an ALD deposition, the processing chamber 945 can be configured as a metrology station or to perform a densification or passivation process, and the processing chamber 960 can be configured to perform a second passivation process. Those skilled in the art will recognize that the number and arrangement of separate processing chambers on a tool can vary and that the processing chambers can be configured to perform different processes than those described above. Figure 3 The embodiment illustrated in FIG. 1 is merely representative of one possible configuration.

[0064] In some embodiments, the processing system 900 includes one or more metrology stations. For example, the metrology stations can be located within the pre-clean / buffer chamber 920, within the central transfer station 910, or within any of the individual processing chambers. The metrology stations can be located anywhere within the system 900 to allow for the measurement of the thickness of the thermal oxide layer and / or the low-K layer without exposing the substrate to an oxidizing environment.

[0065] At least one controller 950 is coupled to one or more of the central transfer station 910, the pre-clean / buffer chamber 920, the processing chambers 930, 940, 945, or 960. In some embodiments, there is more than one controller 950 connected to individual chambers or stations and a main control processor is coupled to each separate processor to control the system 900. The controller 950 can be any form of general- purpose computer processor, microcontroller, microprocessor, etc., that can be used in an industrial setting for controlling various chambers and sub-processors.

[0066] The at least one controller 950 can have a processor 952, memory 954 coupled to the processor 952, input / output (I / O) devices 956 coupled to the processor 952, and support circuits 958 for communicating with the various electronic components. The memory 954 can include one or more of a volatile memory (e.g., random access memory) and a non-volatile memory (e.g., storage).

[0067] The memory 954 or computer readable media of the processor can be one or more of readily available memory such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The memory 954 can hold a set of instructions executable by the processor 952 to control the parameters and components of the system 900. The support circuits 958 are coupled to the processor 952 for supporting the processor in a conventional manner. These circuits can include, for example, cache, power supplies, clock circuits, input / output circuits, subsystems, and the like.

[0068] The processes are typically stored as software programs in the memory and directed to the processor for execution of the processes. The software that directs the processor can also be stored and / or executed by a second processor (not shown) that is remotely located from the hardware being controlled. Some or all of the methods of the present application can also be embodied in hardware. Therefore, the processes can be implemented in software and executed using computer system, in hardware as, for example, an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by the processor, the software program transforms the general purpose computer into a specific purpose computer (controller) that controls chamber operation such that the processes are performed.

[0069] In some embodiments, the controller 950 has one or more configurations to perform individual processes or sub-processes to perform this method. The controller 950 can be connected to and configured to operate intermediate components to perform the functions of this method. For example, the controller 950 can be connected to and configured to control one or more of gas valves, actuators, motors, slit valves, vacuum controls, etc.

[0070] The controller 950 of some embodiments has one or more configurations selected from the group consisting of: a configuration to move a substrate on a robot between a plurality of process chambers and a metrology station; a configuration to load and / or unload a substrate from the system; a configuration to form a thermal oxide layer by an enhanced in-situ steam generation (eISSG) process; a configuration to functionalize and / or passivate a thermal oxide layer; a configuration to perform atomic layer deposition (ALD); or a configuration to densify and / or passivate a low-k layer.

[0071] One or more embodiments relate to a non-transitory computer readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to: form alternating silicon layers and silicon germanium layers on a substrate; pattern and etch the alternating silicon layers and silicon germanium layers to expose at least one sidewall; selectively etch the silicon germanium layers; perform an enhanced in-situ steam generation process to form a thermal oxide layer on the silicon layers; passivate the thermal oxide layer; deposit a low-k layer; and densify and / or passivate the low-k layer.

[0072] Reference throughout this specification to "one embodiment", "certain embodiments", "one or more embodiments" or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrases such as "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in an embodiment" in various places in the specification are not necessarily referring to the same embodiment of the application. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments.

[0073] While the application has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and further it is intended that the application be accorded with the full scope of the claims. Accordingly, the application is not to be limited as by the foregoing description nor in accordance with the accompanying drawings.

Claims

1. A method for manufacturing an electronic device, the method comprising the following steps: Alternating silicon (Si) layers and silicon-germanium (SiGe) layers are formed on the substrate; Patterning and etching the alternating silicon and silicon-germanium layers to expose at least one sidewall of the silicon layer and at least one sidewall of the silicon-germanium layer; Selectively etch the silicon-germanium layer to form an opening; A thermal oxide layer is formed on the silicon layer through the opening; Passivate the thermal oxide layer to form a passivated thermal oxide layer; A low-k layer is deposited on the passivated thermal oxide layer through the opening; and Densifying the low-k layer to form a dense low-k layer, The low-k layer has a dielectric constant in the range of 1 to 6, and The thermal oxide layer has in to The thickness within the range.

2. The method of claim 1, wherein the alternating silicon and silicon-germanium layers are formed by selective epitaxial growth (SEG) processing.

3. The method of claim 1, wherein the step of forming the thermal oxide layer comprises enhanced in-situ steam generation (eISSG) treatment.

4. The method of claim 1, wherein the low-k layer has a thickness of less than 2 nm.

5. The method of claim 1, wherein the low-k layer has a thickness of less than 1.5 nm.

6. The method of claim 1, wherein the thermal oxide layer comprises silicon oxide.

7. The method of claim 1, wherein the low-k layer comprises one or more of silicon oxide, silicon oxycarbide, silicon oxynitride, SiCOH, SiCONH, or aluminum oxide.

8. The method of claim 1, wherein the step of depositing the low-K layer on the passivated thermal oxide layer comprises an atomic layer deposition process.

9. The method of claim 8, wherein the atomic layer deposition process is a plasma-enhanced atomic layer deposition process.

10. The method of claim 1, wherein the step of passivating the thermal oxide layer comprises one or more annealing or plasma treatment processes.

11. The method of claim 10, wherein the step of passivating the thermal oxide layer comprises annealing the thermal oxide layer with one or more H2 or N2.

12. The method of claim 10, wherein the step of passivating the thermal oxide layer comprises a plasma treatment process using one or more of He, H2, N2, or NH3.

13. The method of claim 1, wherein the step of densifying the low-K layer comprises annealing the low-K layer with one or more H2 or N2.

14. The method of claim 1, wherein the step of densifying the low-K layer comprises a plasma treatment process using one or more of He, H2, N2, or NH3.

15. The method of claim 1, wherein the electronic device is a gate-all-around (GAA) transistor.

16. The method of claim 15, wherein the all-around gate transistor includes a source region having a source and a source contact on a top surface of the substrate; a drain region having a drain and a drain contact on the top surface of the substrate; and a channel located between the source and the drain, the channel having an axis substantially orthogonal to the top surface of the substrate. A gate that surrounds the channel between the source region and the drain region; The thermal oxide layer contacts one or more of the gate, the source contact, or the drain contact; and the low-K layer covers the thermal oxide layer.

17. A processing tool for forming a semiconductor device, the processing tool comprising: A central transfer station having multiple processing chambers arranged around the central transfer station; A robot is positioned within the central transfer station to move a substrate between the plurality of processing chambers; A first processing chamber, connected to the central transfer station, is configured to perform enhanced in-situ steam generation process (eISSG) to deposit a thermal oxide layer at a pressure below 20 Torr. A metrology station, located within the processing tool and accessible to the robot, includes one or more of a scatterometer, refractometer, elliptic apparatus, or electron beam, and is configured to determine the thickness of the thermal oxide layer on the substrate. A second processing chamber, connected to the central transfer station, is configured to perform atomic layer deposition to deposit a low-k layer. A third processing chamber, connected to the central transfer station, is configured to perform passivation and / or densification processes to form a dense low-K layer. and A controller, connected to one or more of the central transfer station, the robot, the first processing chamber, the metering station, the second processing chamber, and the third processing chamber, the controller comprising: a first configuration for moving a substrate on the robot between the plurality of processing chambers and the metering station; a second configuration for performing the enhanced in-situ vapor generation process (eISSG) to deposit a thermal oxide layer on the substrate in the first processing chamber; a third configuration for performing analysis to determine the thickness of the thermal oxide layer in the metering station; a fourth configuration for performing atomic layer deposition in the second processing chamber; and a fifth configuration for performing the passivation process and / or the densification process. The low-k layer has a dielectric constant in the range of 1 to 6, and The thermal oxide layer has in to The thickness within the range.

18. A non-transitory computer-readable medium comprising a plurality of instructions, wherein when the instructions are executed by a controller of a processing chamber, the non-transitory computer-readable medium causes the processing chamber to perform the following operations: Alternating silicon and silicon-germanium layers are formed on the substrate; Patterning and etching the alternating silicon and silicon-germanium layers to expose at least one sidewall; Selectively etch the silicon-germanium layer; An enhanced in-situ steam generation process is performed to form a thermal oxide layer on the silicon layer; Passivate the thermal oxide layer; Deposition of low-k layers; and Densification and / or passivation of the low-K layer, The low-k layer has a dielectric constant in the range of 1 to 6, and The thermal oxide layer has in to The thickness within the range.

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