An automatic identification circuit for switching power supply working mode

Abstract

The present invention discloses an automatic recognition circuit for the operating mode of a switching power supply, comprising a resonance detection circuit, a mode recognition circuit, and a PWM signal generation circuit. The present invention can automatically and accurately distinguish between continuous and discontinuous modes, providing more reliable preparation for valley-turning of MOS transistors. Furthermore, because it can more accurately distinguish between continuous and discontinuous modes, it can more promptly and accurately initiate valley-turning of the MOS transistor in discontinuous mode, thereby improving energy efficiency. Furthermore, except for the third D flip-flop in the mode recognition circuit, the remaining D flip-flops can be expanded as needed, providing strong compatibility. Furthermore, the resonant signal is detected by using gate-drain parasitic capacitance, making the system simpler and thus eliminating the resistors R1 and R2 in conventional AC / DC power supply circuits, thus saving costs.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to an automatic identification circuit for a switching power supply operating mode. Background Art

[0002] In a switching power supply, the system generally switches between continuous mode and discontinuous mode depending on the load. In general, when the load is heavy, the system works in continuous mode, and when the load is light, the system works in discontinuous mode. In order to improve the light load efficiency of the system, in discontinuous mode, it is hoped that the power tube will turn on when the drain end is at the valley, such as Figure 1 As shown in Figure 1, the waveform between the drain and source of the power tube achieves valley conduction at t1 and t2. Therefore, in actual application systems, it is very important to accurately identify the operating mode of the system.

[0003] In the known solution, the output voltage of the error amplifier is used to determine the system load status, thereby turning on the valley conduction function. In the switching power supply, the output voltage of the error amplifier is modulated into a triangular wave to achieve pulse width modulation, so that the system output is stable. Figure 2 As shown in the figure, from the PWM modulation principle, it can be seen that when the load is light, the FB voltage is low, and when the load is heavy, the FB voltage is high. The conventional method is to turn on the valley conduction when the voltage of the error amplifier is lower than a certain set value.

[0004] Therefore, the main drawback of existing solutions is that they cannot determine whether the system is operating in continuous or discontinuous mode; they can only determine the system's load status. Although the load status is related to the operating mode, and the error amplifier's output voltage can reflect the load severity, it does not necessarily accurately reflect the system's operating status. Specifically, the system's valley conduction behavior is determined based on a specific voltage point of the error amplifier. Under certain conditions, the system may be in discontinuous mode but not yet in valley conduction. For example, under a fixed load, the error amplifier's output voltage will certainly vary with different input voltages. Thus, if the system is continuous at low inputs but discontinuous at high inputs, valley conduction may not occur when it should. Summary of the Invention

[0005] The purpose of the present invention is to provide an automatic identification circuit for the operating mode of a switching power supply to solve the above problems.

[0006] In order to achieve the above objectives, the following technical solutions are adopted:

[0007] An automatic recognition circuit for a switching power supply operating mode, comprising

[0008] Resonance detection circuit: used to receive the gate signal and reference voltage signal of the MOS tube in the power circuit to detect whether the MOS tube has a resonance signal Valley that generates a high-level pulse and transmit it to the pattern recognition circuit;

[0009] Mode recognition circuit: connected to the resonance detection circuit, used to receive the resonance signal Valley, the oscillation signal osc and the power-on reset signal rst, so as to identify the current working mode signal of the chip in the power supply circuit and transmit it to the PWM signal generation circuit;

[0010] PWM signal generation circuit: used to generate PWM signal to control valley conduction of MOS tube in the power supply circuit when receiving the signal that the current working mode of the chip in the power supply circuit is discontinuous mode.

[0011] Furthermore, the mode recognition circuit includes a first D flip-flop, a second D flip-flop, and a third D flip-flop; the resonant signal Valley and the power-on reset signal rst are connected to the Reset interfaces of the first, second, and third D flip-flops respectively after passing through an AND gate, and the resonant signal Valley is also connected to the D interface of the third D flip-flop; the Q interface of the first D flip-flop and the Q interface of the second D flip-flop are connected to the Clk interface of the third D flip-flop after passing through an AND gate, and the D interface of the second D flip-flop is connected to its Q interface; the D interface of the first D flip-flop is connected to its Q interface, and the D interface of the first D flip-flop is also connected to the Clk interface of the second D flip-flop; the Clk interface of the first D flip-flop is used to receive the oscillation signal osc, and the Q interface and Q interface of the third D flip-flop are used to output a det_ccm signal and a det_dcm signal, respectively, wherein when the det_dcm signal is at a high level, it indicates that the current operating mode of the chip in the power supply circuit is a discontinuous mode, and when the det_ccm signal is at a high level, it indicates that the current operating mode of the chip in the power supply circuit is a continuous mode.

[0012] Furthermore, the resonance detection circuit includes an amplifier, a comparator and a waveform processing module; the reference voltage signal includes a first reference voltage vref1 and a second reference voltage vref2; the two input ends of the amplifier are respectively used to receive the first reference voltage vref1 and the MOS tube gate signal in the power supply circuit, one of the input ends of the comparator is connected to the output end of the amplifier, and the other input end of the comparator is used to receive the second reference voltage vref2; the waveform processing module is connected to the output end of the comparator, and is used to convert the wide pulse circuit into a narrow pulse circuit.

[0013] Furthermore, the input end of the amplifier for receiving the gate signal of the MOS tube in the power supply circuit is also connected to a resistor R1, and a resistor R2 is also connected between the input end and the output end of the amplifier, and the resistance value of the resistor R2 is 10 to 20 times the resistance value of the resistor R1.

[0014] Furthermore, the PWM signal generating circuit includes a fourth D flip-flop, a fifth D flip-flop, and a sixth D flip-flop connected to the fourth D flip-flop and the fifth D flip-flop; the Clk interface of the sixth D flip-flop is also connected to a delay module for delaying the rising edge of the oscillation signal osc.

[0015] By adopting the above scheme, the beneficial effects of the present invention are:

[0016] This circuit can automatically and accurately identify continuous mode and discontinuous mode, providing more certainty in preparation for valley-turning of the MOS tube. Furthermore, because it can more accurately distinguish between continuous mode and discontinuous mode, it can more timely and accurately initiate valley-turning of the MOS tube in discontinuous mode, thereby improving energy efficiency. Furthermore, with the exception of the third D flip-flop in the mode recognition circuit, the remaining D flip-flops can be expanded as needed, providing strong compatibility. Furthermore, the use of gate-drain parasitic capacitance to detect resonant signals simplifies the system, thereby eliminating the resistors R1 and R2 in conventional AC / DC power supply circuits and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is the waveform diagram when the MOS tube in the power circuit is valley-turned on;

[0018] Figure 2 This is the principle diagram of PWM modulation mode;

[0019] Figure 3 It is a schematic diagram of the present invention;

[0020] Figure 4 is a schematic diagram of a resonance detection circuit of the present invention;

[0021] Figure 5 is a waveform diagram of the resonance detection circuit of the present invention;

[0022] Figure 6 is a schematic diagram of a pattern recognition circuit of the present invention;

[0023] Figure 7 is a waveform diagram of the pattern recognition circuit of the present invention;

[0024] Figure 8 Schematic diagram of a PWM signal generating circuit of the present invention;

[0025] Figure 9 This is a waveform diagram of the PWM signal generating circuit of the present invention;

[0026] Figure 10 is an expanded diagram of the pattern recognition circuit of the present invention;

[0027] Figure 11 A topological diagram of an AC / DC switching power supply to which the present invention is applied;

[0028] The accompanying drawings illustrate:

[0029] 1—Resonance detection circuit; 2—Pattern recognition circuit;

[0030] 3—PWM signal generation circuit; 11—amplifier;

[0031] 12—comparator; 13—waveform processing module;

[0032] 21—first D flip-flop; 22—second D flip-flop;

[0033] 23—third D flip-flop; 31—fourth D flip-flop;

[0034] 32—fifth D flip-flop; 33—sixth D flip-flop;

[0035] 34—Delay module. DETAILED DESCRIPTION

[0036] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] Reference Figures 3 to 11 As shown, the present invention provides an automatic identification circuit for a switching power supply operating mode, comprising

[0038] Resonance detection circuit 1: used to receive the gate signal and reference voltage signal of the MOS tube in the power circuit to detect whether the MOS tube has a resonance signal Valley that generates a high-level pulse and transmit it to the pattern recognition circuit 2;

[0039] Mode recognition circuit 2: connected to the resonance detection circuit 1, used to receive the resonance signal Valley, the oscillation signal osc and the power-on reset signal rst, so as to identify the current working mode signal of the chip in the power supply circuit and transmit it to the PWM signal generation circuit 3;

[0040] PWM signal generating circuit 3: used to generate a PWM signal to control the valley conduction of the MOS tube in the power circuit when receiving a signal indicating that the current working mode of the chip in the power circuit is the discontinuous mode.

[0041] The pattern recognition circuit 2 includes a first D flip-flop 21, a second D flip-flop 22, and a third D flip-flop 23; the resonance signal Valley and the power-on reset signal rst are connected to the Reset interfaces of the first D flip-flop 21, the second D flip-flop 22, and the third D flip-flop 23 respectively after passing through an AND gate, and the resonance signal Valley is also connected to the D interface of the third D flip-flop 23; the Q interface of the first D flip-flop 21 and the Q interface of the second D flip-flop 22 are connected to the Clk interface of the third D flip-flop 23 after passing through an AND gate, and the D interface of the second D flip-flop 22 is connected to its Q interface. The D interface of the first D flip-flop 21 is connected to its Q interface, and the D interface of the first D flip-flop 21 is also connected to the Clk interface of the second D flip-flop 22; the Clk interface of the first D flip-flop 21 is used to receive the oscillation signal osc, and the Q interface and Q interface of the third D flip-flop 23 are used to output a det_ccm signal and a det_dcm signal, respectively, wherein when the det_dcm signal is at a high level, it indicates that the current operating mode of the chip in the power supply circuit is the discontinuous mode, and when the det_ccm signal is at a high level, it indicates that the current operating mode of the chip in the power supply circuit is the continuous mode.

[0042] The resonance detection circuit 1 includes an amplifier 11, a comparator 12 and a waveform processing module 13; the reference voltage signal includes a first reference voltage vref1 and a second reference voltage vref2; the two input terminals of the amplifier 11 are respectively used to receive the first reference voltage vref1 and the gate signal of the MOS tube in the power supply circuit, one input terminal of the comparator 12 is connected to the output terminal of the amplifier 11, and the other input terminal of the comparator 12 is used to receive the second reference voltage vref2; the waveform processing module 13 is connected to the output terminal of the comparator 12, and is used to convert the wide pulse circuit into a narrow pulse circuit. circuit; the input end of the amplifier 11 for receiving the gate signal of the MOS tube in the power supply circuit is further connected to a resistor R1, and a resistor R2 is further connected between the input end and the output end of the amplifier 11, and the resistance value of the resistor R2 is 10 to 20 times that of the resistor R1; the PWM signal generation circuit 3 includes a fourth D flip-flop 31, a fifth D flip-flop 32, and a sixth D flip-flop 33 connected to the fourth D flip-flop 31 and the fifth D flip-flop 32; the Clk interface of the sixth D flip-flop 33 is further connected to a delay module 34 for delaying the rising edge of the oscillation signal osc.

[0043] Working principle of the present invention:

[0044] Continue to refer to Figure 3 As shown, the circuit includes a resonance detection circuit 1, a pattern recognition circuit 2 and a PWM signal generation circuit 3. Figure 4As shown, gate_in in the resonance detection circuit 1 is the gate signal of the MOS tube in the power circuit, vref1 and vref2 are reference voltages, the resistance value of the resistor R2 is 10-20 times the resistance value of the resistor R1, valley is a high-level pulse signal indicating resonance, and the waveform processing module 13 is used to convert the wide pulse circuit into a narrow pulse circuit; its specific waveform diagram is shown in FIG. Figure 5 As shown, since the resonance detection circuit 1 utilizes the parasitic capacitance of the gate-drain of the power MOS tube, this solution can save the zero-crossing detection resistors R1 / R2 (such as Figure 11 shown).

[0045] Pattern recognition circuit 2 Figure 6 As shown, Figure 6 The number of D flip-flops other than the third D flip-flop 23 connected to the det_dcm signal can be expanded as needed, mainly based on the number of cycles required for continuous judgment; Figure 6 The osc signal in the code is the oscillator signal, and other clock frequency signals can also be set as needed; valley is a signal indicating whether the Vds on the MOS tube in the power supply circuit is resonant. If there is a resonance, a pulse is generated; rst is the power-on reset signal; if det_dcm is high, it means that the chip in the power supply circuit is currently operating in discontinuous mode; if det_ccm is high, it means that the chip is currently operating in continuous mode.

[0046] When operating in continuous mode, Figure 6 The valley signal in the circuit is always low. When the valley signal is low for three consecutive osc times, the clk signal becomes high and the det_ccm signal also becomes high, indicating that it is working in continuous mode. When a high-level pulse appears in the valley, the det_ccm signal becomes low and the det_dcm signal becomes high, indicating that it is working in discontinuous mode. Figure 7 As shown; Figure 7 Before t1, the system is working in discontinuous mode. After t1, the system enters continuous mode. After 3 OSC cycles, that is, at t2, det_ccm becomes high, indicating that it has entered continuous working mode. At t3, the valley signal has a high-level pulse. Figure 7 Upper det_dcm signal becomes high.

[0047] like Figure 8As shown, it is a PWM signal generating circuit 3, in which the det_ccm signal comes from the pattern recognition circuit 2; the delay module 34 is to delay the rising edge of osc, for example, the delay is 4us; the pwmoff signal is the result of the phase OR of the voltage comparison signal, the cycle-by-cycle overcurrent signal, the protection signal and other signals in the switching power supply chip, which determines the falling edge of the pwm signal; when working in discontinuous mode, within the delay time of the delay module 34 starting from the rising edge of osc, if a valley high level signal representing resonance appears, then Figure 8 The fourth D flip-flop 31 is triggered until its Q terminal becomes high, which is then transmitted to clk2 to become high. Figure 9 The t2 and t7 moments of the middle signal are also the high level starting moments of a cycle of the PWM signal, which is then transmitted to the gate end of the peripheral power MOSFET through the driving circuit to achieve the following Figure 1 If there is no valley high level signal representing resonance, the rising edge of osc is passed to clk2 through the delay module 34, as shown. Figure 9 At time t3; if Figure 8 The det_ccm signal in Figure 6 If the circuit is generated, then after three consecutive osc cycles, there is no valley high level pulse, then the det_ccm signal becomes high, such as Figure 9 The t4 moment in the figure indicates that the continuous mode has been entered. The rising edge of the PWM in the next cycle is consistent with the rising edge of the corresponding osc. Figure 9 At t5 in the figure, if a high level pulse appears in valley again, the system will enter discontinuous mode. Figure 9 The t6 moment in the.

[0048] This circuit can automatically and accurately identify the continuous mode and the discontinuous mode, providing more certain preparation for the valley-turning of the MOS tube. At the same time, because the continuous mode and the discontinuous mode can be more accurately distinguished, the valley-turning action of the MOS tube can be performed more timely and accurately in the discontinuous mode, thereby further improving energy efficiency. In addition, except for the third D flip-flop 23 in the mode recognition circuit 2, the remaining D flip-flops can be expanded as needed, with strong compatibility. The resonant signal is detected by using the gate-drain parasitic capacitance, making the system simpler, thereby eliminating the resistors R1 and R2 in the conventional AC / DC power supply circuit, saving costs.

[0049] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A circuit for automatically identifying the working mode of a switching power supply, characterized in that: include Resonance detection circuit: used to receive the gate signal and reference voltage signal of the MOS tube in the power circuit to detect whether the MOS tube has a resonance signal Valley that generates a high-level pulse and transmit it to the pattern recognition circuit; Mode recognition circuit: connected to the resonance detection circuit, used to receive the resonance signal Valley, the oscillation signal osc and the power-on reset signal rst, so as to identify the current working mode signal of the chip in the power supply circuit and transmit it to the PWM signal generation circuit; PWM signal generation circuit: used to generate PWM signal to control valley conduction of MOS tube in the power circuit when receiving the signal indicating that the current working mode of the chip in the power circuit is discontinuous mode; The pattern recognition circuit includes a first D flip-flop, a second D flip-flop, and a third D flip-flop; the resonance signal Valley and the power-on reset signal rst are connected to the Reset interface of the first D flip-flop, the second D flip-flop, and the third D flip-flop respectively after passing through an AND gate, and the resonance signal Valley is also connected to the D interface of the third D flip-flop; the Q interface of the first D flip-flop and the Q interface of the second D flip-flop are connected to the Clk interface of the third D flip-flop after passing through an AND gate, and the D interface of the second D flip-flop is connected to the Clk interface of the third D flip-flop. Interface connection; the D interface of the first D trigger is connected to The D interface of the first D flip-flop is connected to the Clk interface of the second D flip-flop; the Clk interface of the first D flip-flop is used to receive the oscillation signal osc, and the Q interface of the third D flip-flop is connected to the The interfaces are used to output det_ccm signal and det_dcm signal respectively. When the det_dcm signal is high, it indicates that the current working mode of the chip in the power supply circuit is discontinuous mode. When the det_ccm signal is high, it indicates that the current working mode of the chip in the power supply circuit is continuous mode.

2. The automatic identification circuit of the switching power supply working mode according to claim 1, characterized in that: The resonance detection circuit includes an amplifier, a comparator and a waveform processing module; the reference voltage signal includes a first reference voltage vref1 and a second reference voltage vref2; the two input ends of the amplifier are respectively used to receive the first reference voltage vref1 and the MOS tube gate signal in the power supply circuit, one input end of the comparator is connected to the output end of the amplifier, and the other input end of the comparator is used to receive the second reference voltage vref2; the waveform processing module is connected to the output end of the comparator and is used to convert the wide pulse circuit into a narrow pulse circuit.

3. The automatic identification circuit of the switching power supply working mode according to claim 2, characterized in that: The input end of the amplifier for receiving the gate signal of the MOS tube in the power supply circuit is also connected to a resistor R1, and a resistor R2 is also connected between the input end and the output end of the amplifier, and the resistance value of the resistor R2 is 10 to 20 times that of the resistor R1.

4. The automatic identification circuit of the switching power supply working mode according to claim 1, characterized in that: The PWM signal generating circuit includes a fourth D flip-flop, a fifth D flip-flop, and a sixth D flip-flop connected to the fourth and fifth D flip-flops; the Clk interface of the sixth D flip-flop is also connected to a delay module for delaying the rising edge of the oscillation signal osc.

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