A method for evaluating the channel interface of a polymer transistor

Abstract

A method for evaluating the channel interface of a polymer transistor, based on three parameters: total carrier concentration, free carrier concentration, and channel interface trap density, evaluates the quality of the channel interface of a polymer transistor by comparing it with a standard sample, helps to better analyze the device performance, provides theoretical guidance for evaluating the effects of the structure of thin-film transistors, fabrication processes, active layer and gate insulating layer materials, etc. on the electrical performance of the device, and further provides a reference for building an evaluation model for polymer transistor interface analysis in the future.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a method for evaluating the channel interface of a polymer transistor. Background Art

[0002] With the wide application of organic semiconductor materials, various organic semiconductor devices are constantly developing, such as organic field-effect transistors, organic light-emitting diodes, organic sensors, and organic photovoltaic cells. The charge transport property is a basic issue in the research of organic semiconductor materials, and it has a very important impact on the performance and efficiency of organic electronic devices. One of the key factors determining the charge transport of organic semiconductor materials is the density of states. The state is also called an interface trap, which is the interface trapped charge caused by the dangling bonds on the semiconductor-insulator interface. At present, the distribution function of the density of states in organic semiconductor materials is not clear, which is not conducive to the subsequent analysis of device performance. Summary of the Invention

[0003] Aiming at the problems existing in the above background art, the present invention proposes a method for evaluating the channel interface of a polymer transistor to assist in the performance analysis of transistor devices.

[0004] A method for evaluating the channel interface of a polymer transistor, the following are the specific steps:

[0005] Step 1, extracting the density of channel interface states through a quasi-static method, including the total carrier concentration P tot and the free carrier concentration P free ;

[0006] Step 2, extracting the channel interface trap density D through the charge pumping method it ;

[0007] Step 3, evaluating the channel interface of the polymer transistor based on the comparison of the above parameters with a standard sample, and analyzing the charge transport performance of the interface through the ratio of the free carrier concentration to the total carrier concentration and the interface trap density to the total carrier concentration.

[0008] Further, in Step 1, the total carrier concentration P of the MOS transistor is calculated through formula (1) tot :

[0009]

[0010] where C i is the gate oxide capacitance, q is the unit charge amount, εs is the dielectric constant of the semiconductor layer, V FB is the flat-band voltage, is the surface potential, and V GS is the gate voltage.

[0011] Further, in step 1, the free carrier concentration P in the semiconductor layer of the MOS transistor is calculated by formula (2). free :

[0012]

[0013] where P HOMO is the effective density of states of the organic semiconductor layer, E HOMO is the HOMO energy level of the semiconductor, E F0 is the equilibrium Fermi level, k is the Boltzmann constant, and T is the temperature.

[0014] Further, in step 2, the interface trap density D is calculated by formula (3). it :

[0015]

[0016] where q is the unit charge amount, k is the Boltzmann constant, A G is the gate area, f is the pulse frequency, T is the temperature, E T is the interface trap energy measured from the bottom of the conduction band, E C is the conduction band energy level, τ e is the time constant for electrons to be emitted from the interface trap, I cp is the current measured by the charge pumping method, and t step is the pulse time.

[0017] Further, in step 3, the larger the ratio of the free carrier concentration to the total carrier concentration, the more carriers participate in charge transport, that is, the better the channel interface of the device; the ratio of the interface trap density to the total carrier concentration represents the interface trap states in the total carriers, and the smaller it is, the smaller the proportion of the interface traps, and the better the interface performance.

[0018] The beneficial effects achieved by the present invention are as follows: Based on the three parameters of the total carrier concentration, free carrier concentration, and channel interface trap density, the quality of the channel interface of the polymer transistor is evaluated by comparison with the standard sample, which helps to better analyze the device performance, provides a theoretical guidance for evaluating the influence of the structure, preparation process, active layer, and gate insulating layer material of the thin film transistor on the electrical performance of the device, and further provides a reference for building an evaluation model for polymer transistor interface analysis in the future. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a top view of the structure of the N-type MOSFET in the specific embodiment of the present invention.

[0020] Figure 2 is a top view of the structure of the N-type MOSFET in the specific embodiment of the present invention.

[0021] Figure 3 It is the output characteristic curve of the N-type MOSFET in the specific embodiment of the present invention.

[0022] Figure 4 It is in the specific embodiment of the present invention Figure 3 A partially enlarged view of the output characteristic curve.

[0023] Figure 5 It is the pulse waveform diagram used in the specific embodiment of the present invention.

[0024] Figure 6 It is the schematic structural diagram of the transistor prepared in the specific embodiment of the present invention.

[0025] Figure 7 It is the output characteristic curve of the transistor prepared in the specific embodiment of the present invention.

[0026] Figure 8 It is in the specific embodiment of the present invention Figure 7 A partially enlarged view of the output characteristic curve.

[0027] Figure 9 It is the parameter table evaluated for two transistors in the specific embodiment of the present invention. Specific embodiment

[0028] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings of the specification.

[0029] Refer to Figure 1-2 , use an N-type MOSFET as a standard sample, fix the N-type MOSFET on a 1.5 cm × 1.5 cm transparent glass sheet and connect out the pins with silver glue, place it on the test bench of the semiconductor analyzer B1500A, and conduct a channel interface evaluation.

[0030] Open the SMU module of the semiconductor analyzer B1500A, select the I-V test, apply a gate voltage of -1V to 3V with a step of 0.02V to the MOS transistor, ground the source, and apply a voltage of 0.1V to 0.8V with a step of 0.1 to the drain to test its transfer characteristics.

[0031] Then conduct an output characteristic curve test. Apply a voltage of -1V to 3V with a step of 0.02V to the drain of the MOS transistor, ground the source, and apply a voltage of 0.1V to 1.2V with a step of 0.1 to the gate to test and obtain its output characteristic curve, as shown in Figure 3 and Figure 4 .

[0032] The total carrier concentration P of the MOS transistor is calculated by formula (1) tot , where C iis the gate oxide capacitance, q is the unit charge quantity, ε s is the dielectric constant of the semiconductor layer, VFB is the flat-band voltage, is the surface potential.

[0033]

[0034] The free carrier concentration P in the semiconductor layer of the MOS transistor is calculated by formula (2) free , where P HOMO is the effective density of states of the organic semiconductor layer, E HOMO is the HOMO energy level of the semiconductor, E F0 is the equilibrium Fermi level, k is the Boltzmann constant, T is the temperature, V GS is the gate voltage.

[0035]

[0036] Apply zero voltage to its source electrode using the SPGU module and the SMU module, and apply the Figure 5 shown pulse to the gate electrode, and monitor the drain current. Change the pulse period and measure again. The used pulse periods are 0.18 s, 0.24 s, 0.30 s, 0.42 s, 0.54 s, 0.60 s, 1 s respectively. The interface trap density D is calculated by formula (3) it , where q in the formula is the unit charge quantity, k is the Boltzmann constant, A G is the gate area, f is the pulse frequency, T is the temperature, E T is the interface trap energy measured from the bottom of the conduction band, E C is the conduction band energy level, τ e is the time constant for electrons to be emitted from the interface trap. I cp is the current measured by the charge pumping method, t step is Figure 5 the pulse time marked in

[0037]

[0038] The obtained standard sample data is shown in the Figure 9 table, denoted as P tot，0 , P free，0 , D it，0 .

[0039] Prepare an organic polymer transistor (as shown in Figure 6 ), and conduct channel interface evaluation.

[0040] The preparation process of the organic transistor is as follows:

[0041] a) Take out several glass slides, place them on the glass slide cleaning basket, soak them in deionized water, put them in an ultrasonic cleaner and clean for five minutes. After taking them out, soak them in alcohol, then put them back into the ultrasonic cleaner and clean for another five minutes. Repeat the cleaning steps again.

[0042] b) Use a nitrogen gun to blow them until there are no obvious water droplets on the surface, place them on a drying table at 100 °C and bake for 30 minutes, then transfer them to an ozone cleaner and clean for 30 minutes.

[0043] c) After attaching the source-drain mask template, put it into an evaporation coater and evaporate 3 nm of Ni, and then evaporate 50 nm of Au.

[0044] d) Spin-coat the organic layer (OSC layer): The organic layer is 5 mg / mL of DPPT-TT / DCB, and the spin-coating conditions are 500 rpm for 10 s and 2000 rpm for 60 s; then perform annealing: first anneal at 80 °C for 5 min, and then anneal at 200 °C for 1 h; after annealing, cool at room temperature for 40 min; the whole process is completed in a glove box.

[0045] e) Spin-coat the dielectric layer: The dielectric layer is 80 mg / mL of PMMA / n-BA, and the spin-coating conditions are 500 rpm for 3 s and 1500 rpm for 60 s; then perform annealing, anneal at 80 °C for two hours; after annealing, cool at room temperature for 30 minutes; the whole process is completed in a glove box.

[0046] f) After attaching the gate mask template, transfer it to an evaporation coater and evaporate 80 nm of Cu.

[0047] g) The device fabrication is completed.

[0048] Then, the channel interface of the transistor is evaluated, and the steps are as follows:

[0049] Turn on the SMU module of the semiconductor analyzer B1500A, select the I-V test, apply a gate voltage with a step of 0.5 V from -60 V to 20 V to the transistor, ground the source, and apply voltages of -0.5 V and -60 V to the drain to test its transfer characteristics.

[0050] Perform the output characteristic curve test. Apply a voltage with a step of 0.5 V from -60 V to 20 V to the drain of the transistor, ground the source, and apply voltages with a step of 15 from -10 V to -70 V to the gate to test and obtain its output characteristic curve, as Figure 7 and Figure 8 .

[0051] Similar to the evaluation process of the standard sample, calculate the total carrier concentration P of the transistor through formulas (1)-(2) tot and the free carrier concentration P free .

[0052] Apply zero voltage to its source using the SPGU module and the SMU module, and apply the Figure 5 pulses shown in Figure 1, and monitor the drain current. Change the pulse period and measure again. The pulse periods used are 0.54 s, 0.6 s, 0.72 s, 0.84 s, 0.9 s, 0.96 s, 1.02 s, 1.08 s, 1.2 s, and 1.5 s, and then calculate the interface trap density D of the transistor through Equation (3). it .

[0053] The obtained data are shown in the Figure 9 table, denoted as P tot，i , P free，i , D it，i .

[0054] According to Figure 9 the comparison of the data of the standard sample transistors in the table with the prepared organic polymer transistors, it can be found that the total carrier concentration, free carrier concentration, and interface trap density of the prepared organic polymer transistors are all larger than those of the standard samples.

[0055] Specifically, the ratio of the free carrier concentration to the total carrier concentration of the standard sample is about 14%, indicating that about 14% of the total carriers in the channel interface can participate in charge transport. For the same transistor, the larger this ratio, the more carriers participate in charge transport, which means the better the channel interface of the device. The ratio in the prepared organic polymer transistor is only 0.6%, indicating that only about 0.6% of the total carriers in the channel interface can participate in charge transport, and the channel interface of the device is relatively poor.

[0056] The ratio of the interface trap density to the total carrier concentration of the standard sample is about 4.6×10 -8 , indicating that about 0.000046% of the total carriers are interface trap states, which will capture a part of the carriers during charge transport, resulting in a decrease in carrier mobility and thus poor interface performance of the device. The value in the prepared organic polymer transistor is about 0.0000000225%, which is lower than that of the standard sample. The smaller this value, the smaller the proportion of interface traps, that is, fewer charges are captured during transport. From this, it can be judged that the channel of the prepared organic polymer transistor is better. This evaluation method is relative and can be selected according to needs among multiple judgments.

[0057] In summary, the evaluation method for the transistor channel interface provided by the present invention helps to better analyze the device performance, provides theoretical guidance for evaluating the effects of the structure, preparation process, active layer, and gate insulating layer materials of thin film transistors on the electrical performance of the device, and further provides a reference for building an evaluation model for polymer transistor interface analysis in the next step.

[0058] It should be noted that in the specific embodiments of extracting trap states by applying the technical solution of the present invention, the active layer material of the thin-film transistor sample is poly(3,4-ethylenedioxythiophene)-pyrrolopyrrole dione (DPPT-TT), but it is not limited to DPPT-TT, and can also be organic semiconductor materials such as IDT-BT. In addition, in the example, the gate insulating layer of the thin-film transistor is polymethyl methacrylate (PMMA), and other insulating layer materials can also be used.

[0059] In addition, the method for extracting trap states of the oxide semiconductor thin-film transistor provided by the present invention can be used not only for extracting trap states of p-type oxide semiconductor thin-film transistors, but also for extracting trap states of n-type oxide semiconductor thin-film transistors.

[0060] The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. Any equivalent modifications or changes made by those of ordinary skill in the art according to the disclosure of the present invention should be included in the protection scope recorded in the claims.

Claims

1. A method for evaluating the channel interface of a polymer transistor, characterized in that: The evaluation method includes the following specific steps: Step 1, extracting the channel interface state density through a quasi-static method, including the total carrier concentration P tot and the free carrier concentration P free ; Step 2, extracting the channel interface trap density D by the charge pumping method it ; Step 3: Evaluate the channel interface of the polymer transistor based on the comparison of the above parameters with the standard sample, and analyze the charge transport performance of the interface through the ratio of the free carrier concentration to the total carrier concentration and the ratio of the interface trap density to the total carrier concentration.

2. The method for evaluating a polymer transistor channel interface according to claim 1, characterized in that: In Step 1, the total carrier concentration P of the MOS transistor is calculated through Equation (1). tot : where C i is the gate oxide capacitance, q is the unit charge amount, εs is the semiconductor layer dielectric constant, V FB is the flat-band voltage, is the surface potential, V GS is the gate voltage.

3. The method for evaluating the channel interface of a polymer transistor according to claim 1, wherein: In step 1, the free carrier concentration P in the semiconductor layer of the MOS transistor is calculated by formula (2). free : where, P HOMO is the effective density of states of the organic semiconductor layer, E HOMO is the HOMO energy level of the semiconductor, q is the unit charge quantity, is the surface potential, E F0 is the equilibrium Fermi level, k is the Boltzmann constant, and T is the temperature.

4. A method for evaluating a polymer transistor channel interface according to claim 1, characterized in that: In step 2, the interface trap density D is calculated through formula (3). it : where q is the unit charge amount, k is the Boltzmann constant, A G is the gate area, f is the pulse frequency, T is the temperature, E T is the interface trap energy measured from the bottom of the conduction band, E C is the conduction band energy level, τ e is the time constant for electrons to be emitted from the interface trap, I cp is the current measured by the charge pumping method, t step is the pulse time.

5. A method for evaluating the channel interface of a polymer transistor according to claim 1, characterized in that: In Step 3, the larger the ratio of the free carrier concentration to the total carrier concentration, the more carriers participate in charge transport, that is, the better the channel interface of the device; the ratio of the interface trap density to the total carrier concentration represents the interface trap states among the total carriers, and the smaller it is, the smaller the proportion of the interface traps, and the better the interface performance.

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