Circuits designed and manufactured using first and second design rules

Abstract

The present disclosure relates generally to circuits designed and manufactured utilizing first and second design rules. An integrated circuit (IC) includes a plurality of finfet cells designed utilizing digital circuit design rules to provide smaller finfet cells having reduced cell height, and an analog circuit cell structure including a first finfet cell of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells having reduced cell height provide first shorter metal tracks in one direction, and the at least one cut metal layer provides second shorter metal tracks in another direction to improve maximum electromigration current in the integrated circuit.

Description

Technical Field

[0001] This disclosure generally relates to circuits designed and manufactured using first and second design rules. Background Technology

[0002] Electronic circuits are continuously being designed and manufactured to operate at ever-increasing speeds. Circuits such as serializer / deserializer (serdes) circuits currently operate in frequency ranges from 28 gigabits per second (Gbps) to 448 Gbps. Key device parameters for operating at these speeds include transconductance (GM), unity-gain frequency (UGF), and electromigration (EM) considerations. In the past, these circuits were designed using analog circuit design rules, including analog fin formation methods or boundaries. To achieve higher operating speeds, all three key device parameters are increased by using larger contact poly pitch (CPP), wider metal over diffusion [source / drain contacts] (MD), larger vias, wider metal lines, and more space. Changing these structures can reduce both resistance and capacitance, and improve GM, UGF, and maximum EM current. Summary of the Invention

[0003] According to a first embodiment of this disclosure, an integrated circuit is provided, comprising: a plurality of finfet cells designed using digital circuit design rules to provide smaller finfet cells with reduced cell height; an analog circuit cell structure including a first finfet cell of the plurality of finfet cells and including at least one diced metal layer; and a digital circuit cell structure including a second finfet cell of the plurality of finfet cells, wherein the analog circuit cell structure is directly adjacent to the digital circuit cell structure, and wherein the smaller finfet cell with reduced cell height includes a first shorter metal track in one direction, and the at least one diced metal layer includes a second shorter metal track in another direction to improve the maximum electromigration current in the integrated circuit.

[0004] According to a second embodiment of this disclosure, a semiconductor structure is provided, comprising: a plurality of finfet cells; a plurality of source / drain conductors disposed on and electrically coupled to the plurality of finfet cells, the plurality of source / drain conductors including wider source / drain conductors and narrower source / drain conductors; a plurality of gate conductors disposed on and electrically coupled to the plurality of finfet cells, and interleaved with the plurality of source / drain conductors; and a plurality of gate contacts electrically coupled to the finfet gates in the plurality of finfet cells and the plurality of source / drain conductors. Between gate conductors; and a plurality of source / drain contacts electrically coupled between the finfet source / drain regions in the plurality of finfet cells and the plurality of source / drain conductors, wherein the plurality of source / drain contacts include a first source / drain contact and a second source / drain contact, each of the first source / drain contacts having a first width and electrically coupled to at least one of the wider source / drain conductors, and each of the second source / drain contacts having a second width and electrically coupled to at least one of the narrower source / drain conductors, wherein the first width is greater than the second width.

[0005] According to a third embodiment of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: providing a plurality of finfet cells based on digital fin boundaries, wherein each of the plurality of finfet cells includes a fin having a non-uniform fin spacing; and providing a mid-stage process (MEOL) layer in at least one of the plurality of finfet cells, wherein providing the MEOL layer includes: providing a first source / drain contact having a first width; and providing a second source / drain contact having a second width, wherein the second width is wider than the first width. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced. Furthermore, the drawings are illustrative and not restrictive, serving as examples of embodiments of the invention.

[0007] Figure 1 This is a schematic top view of the first metal layer (MO) in a portion of an integrated circuit (IC) according to some embodiments and an example below, which includes a portion of serial / deserialized circuitry designed using digital circuit (logic) design rules and digital fin boundary design.

[0008] Figure 2This is a top view schematically illustrating an example of an IC according to some embodiments, with the back end of line (BEOL) layer extending up to the third metal layer (M2), which includes serial / deserialization circuitry designed using digital circuit design rules and digital fin boundaries.

[0009] Figure 3 This is a block diagram schematically illustrating an example of a serial / deserialized circuit designed and manufactured according to some embodiments using analog circuit design rules with analog fin boundaries and digital circuit design rules with digital fin boundaries.

[0010] Figure 4 This is a block diagram illustrating examples of computer systems configured to design and manufacture the units and circuits of this disclosure according to some embodiments.

[0011] Figure 5 This is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments.

[0012] Figure 6 This is a schematic illustration of a fin field-effect transistor (FINFET) cell designed according to some embodiments using digital circuit design rules and digital fin boundaries instead of analog circuit design rules and analog fin boundaries.

[0013] Figure 7 This is a schematic illustration of an analog cell device type including finfet cells according to some embodiments, which are designed using digital fin boundaries and arranged in a repeating pattern with two rows of PMOS finfet transistors followed by two rows of NMOS finfet transistors.

[0014] Figure 8 This is a schematic illustration of another analog cell device type, including finfet cells designed using digital fin boundaries, according to some embodiments.

[0015] Figure 9 This is a schematic illustration of an analog cell device type including finfet cells according to some embodiments, which are designed using digital fin boundaries and arranged in columns, and have the same type of finfet.

[0016] Figure 10A This is a schematic illustration of a finfet cell in an IC according to some embodiments, the IC having analog cells designed using digital circuit design rules and digital fin boundary design and including a middle end of line (MEOL) layer.

[0017] Figure 10BThis is an illustrative representation according to some embodiments. Figure 10A The edge of the finfet unit Figure 10A A cross-sectional view of line BB in the diagram.

[0018] Figure 11 This is a schematic illustration of multiple finfet cells in an IC according to some embodiments, the IC having analog cells designed using digital circuit design rules and digital fin boundary design and including a MEOL layer.

[0019] Figure 12 This is a table schematically illustrating the M0 lines or tracks in an analog cell designed using digital circuit design rules and digital fin boundary design according to some embodiments.

[0020] Figure 13 This is a table showing threshold voltage (Vt) levels that can be implemented in analog and digital cells using digital circuit design rules and digital fin boundary design, according to some embodiments, relative to Vt levels that can be implemented in analog cells using analog circuit design rules and analog fin boundary design.

[0021] Figure 14 The illustration schematically shows an IC according to some embodiments, which includes digital cells designed using digital circuit design rules and digital fin boundary design, and analog cells located next to the digital cells designed using digital circuit design rules and digital fin boundary design.

[0022] Figure 15 This is a schematic top view of M0 in an IC according to some embodiments and an example below, the IC including analog units designed using digital circuit design rules and digital fin boundary design.

[0023] Figure 16 This is an illustrative representation according to some embodiments. Figure 15 The example shown is a top view of the BEOL layer of the IC up to M2.

[0024] Figure 17 This illustrates some embodiments. Figure 15 and Figure 16 A diagram illustrating the temperature distribution of the IC.

[0025] Figure 18 This is a block diagram illustrating a method of manufacturing an IC according to some embodiments, the IC including analog units designed using digital circuit design rules and digital fin boundary design. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "lower than," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0028] In the past, some semiconductor structures, including some integrated circuits, were designed and manufactured using only analog circuit design rules and analog fin boundaries. These integrated circuits could include one or more analog circuits, one or more digital circuits, a mixture of analog and digital circuits, and / or one or more serial / deserialization circuits. However, as manufacturing processes shrink, the performance improvements achieved using analog fin boundaries are limited by device size.

[0029] To address the challenges of increased operating speeds and smaller device sizes, the semiconductor structures disclosed herein include circuits designed and manufactured using a combination of a first set of design rules having a first fin boundary and a second set of design rules having a second fin boundary, such as analog circuits, digital circuits, mixed analog and digital circuits, and / or serial / deserialized circuits. The first set of design rules differs from the second set of design rules, and the first fin boundary differs from the second fin boundary.

[0030] In embodiments, the first set of design rules are analog circuit design rules with analog fin boundaries, and the second set of design rules are digital circuit design rules (logic design rules) with digital fin boundaries, such as standard cell logic design rules. The performance of circuits designed and manufactured using digital circuit design rules improves as process geometry shrinks or decreases. In some embodiments, the semiconductor structures that are the subject of this disclosure include analog circuits, digital circuits, mixed-signal analog and digital circuits, and / or serial / deserialized circuits designed and manufactured using a combination of analog circuit design rules with analog fin boundaries and digital circuit design rules with digital fin boundaries.

[0031] In some embodiments, analog circuit design rules include one or more of the following: aligning the fin fins of the FinFET on the fin grid lines of the analog fin boundary, providing a via over drain / source contact (VD) within a certain size range, aligning the M0 with the fin and having a standard M0 width, providing a limited number of threshold voltages, not cutting metal layers, and having analog circuit cells that cannot be directly adjacent to digital circuit cells. In contrast, in some embodiments, digital circuit design rules include one or more of the following: not aligning finfets on the fin mesh lines of the analog fin boundary; providing vias over multiple different drain / source contacts (including VD and vias over larger drain / source contacts with resistance less than VD (VD2)); providing multiple widths of M0 and not aligning M0 with the fins; providing additional threshold voltages (including ultra-low threshold voltage (ULVTLL) and extremely low threshold voltage (ELVT) with low leakage); cutting metal lines and having shorter cell heights (which provides shorter metal track lengths); and providing analog circuit cells that can directly adjoin digital circuit cells.

[0032] In some embodiments, each of the first and second sets of design rules includes spacing requirements between each via in the layout design. In some embodiments, each of the first and second sets of design rules includes spacing requirements between via layout patterns. In some embodiments, each of the first and second sets of design rules includes spacing requirements between fin layout patterns in the layout design. In some embodiments, each of the first and second sets of design rules includes spacing requirements between via layout patterns and cut feature layout patterns. In some embodiments, each of the first and second sets of design rules includes spacing requirements between active region layout patterns and cut feature layout patterns. In some embodiments, each of the first and second sets of design rules includes spacing requirements between active region layout patterns. In some embodiments, each of the first and second sets of design rules includes one or more MD design rules. In some embodiments, each of the first and second sets of design rules includes one or more via over gate (gate contact) design rules. In some embodiments, each of the first and second sets of design rules includes one or more M0 track design rules.

[0033] Throughout this disclosure, finfet cells and circuits previously designed and manufactured using analog circuit design rules and analog fin boundaries are designed and manufactured using digital circuit design rules and digital fin boundaries. These finfet cells and circuits are referred to herein as analog cells designed using digital circuit design rules and digital fin boundaries. In embodiments, these analog cells can be used for analog circuits, digital circuits, hybrid analog and digital circuits, and serial / deserialized circuits.

[0034] In embodiments, digital fin boundaries are applied to finfet cells in circuits (e.g., analog circuits, mixed analog and digital circuits, and / or serial / deserialized circuits) such that the fins of these finfet cells are not located on the grid lines of the fin mesh structure associated with analog circuit design rules and analog fin boundaries. Instead, the fins are located between or intersect with the grid lines of the fin mesh structure. By utilizing fins located between the grid lines of the fin mesh structure, the height of the finfet cells can be reduced and the size of the device can be decreased.

[0035] Furthermore, the digital fin boundaries of the fins in these finFET cells are the same as the digital fin boundaries of the fins in the logic finFET cells, allowing these circuits to be placed directly adjacent to the logic finFET cells without any keep-out area or region between the circuits and the digital logic finFET cells. This saves space and reduces the size of the device. Additionally, the digital fin boundaries leave space between the fins in the middle of the finFET cells, which can be used for wiring. In some embodiments, using the space between the fins for wiring improves space utilization and reduces the size of the device.

[0036] In some embodiments, the circuit types that utilize digital fin boundaries instead of analog fin boundaries include row-arranged NMOS finFETs and row-arranged PMOS finFETs. In some embodiments, the arrangement of NMOS finFETs and PMOS finFETs in at least one of these circuits is the same as the arrangement of NMOS finFETs and PMOS finFETs in at least one logic circuit designed using digital fin boundaries. In some embodiments, the arrangement of NMOS finFETs and PMOS finFETs in at least one of these circuits differs from the arrangement of NMOS finFETs and PMOS finFETs in at least one logic circuit designed using digital fin boundaries.

[0037] Analog cells and circuits designed and manufactured using digital circuit design rules and digital fin boundary design can include MEOL layers that are not included in circuits designed using analog circuit design rules and analog fin boundary design. For example, a cell designed and manufactured using digital circuit design rules can include a via VD2 over a larger drain / source contact to the MD to improve performance because the resistance of VD2 is at least 50% smaller than the resistance of the via VD over a smaller drain / source contact to the MD.

[0038] Furthermore, the arrangement of M0 lines in a FINFET cell designed using digital circuit design rules can differ from that in a FINFET cell designed using analog circuit design rules. For example, the number of M0 lines or tracks in a FINFET cell designed using digital circuit design rules is optional and can range from 1 to 5 lines or more.

[0039] Furthermore, circuits designed using digital circuit design rules may include shorter MD lines to achieve higher maximum EM current, shorter M0 lines to achieve higher maximum EM current, and shorter second-layer metal (M1) lines to achieve higher maximum EM current.

[0040] The advantages of designing and manufacturing integrated circuits that utilize digital fin boundary designs instead of analog fin boundary designs include higher GM, higher UGF, and higher EM. GM is higher because of lower resistance in the MEOL and back-end process (BEOL) using digital circuit design rules. Furthermore, UGF = GM / C, so the higher the GM and the smaller the MEOL capacitance C, the higher the UGF. Additionally, shorter metal lines result in higher maximum EM current, where digital circuit design rules allow for cut-out M0 lines, and shorter cell heights produce shorter M1 lines.

[0041] Figure 1 This is a schematic top view illustrating the M0 line in a portion of IC 20 according to some embodiments and an example below, which includes a portion of a serial / deserialize circuit designed using digital circuit design rules. IC 20 includes... Figure 1 Multiple finfets 22 are positioned from left to right in the middle. Each finfet 22 includes a fin source region 24 electrically coupled to one or more MDs 25 as indicated at S, a fin drain region 26 electrically coupled to one or more MDs 27 as indicated at D, and a gate 28 located between the respective source and drain regions 24 and 26. In this example, each finfet 22 may cleave MDs 25 and 27 to provide a cleaved MD region (CMD) 29.

[0042] In this embodiment, in each finfet 22, the MD 25 of the source S is connected to M0 30 via one or more VD2 32 and one or more VD 34. Furthermore, in each finfet 22, the MD 27 of the drain D is connected to M0 30 via one or more VD 36. Each gate 28 is connected to M0 30 via a via (VG) 37 above the gate contact.

[0043] Figure 2 This is a schematic top view illustrating an example of the BEOL layer up to M2 40 in IC 20 according to some embodiments. IC 20 includes M2 40 arranged in a horizontal line or track on IC 20 and M1 42 arranged in a vertical line or track on IC 20.

[0044] like Figure 1 and Figure 2As shown, M0 30 is disposed in a horizontal line or track on IC 20 such that the vertical line of M1 42 is orthogonal to the horizontal line of M0 30 and to the horizontal line of M2 40. The track of M1 42 is connected to the respective tracks of M0 30 through a first via 44 (VIA0), and the track of M1 42 is further connected to the track of M2 40 through a second via 46 (VIA1). Therefore, the BEOL layer is electrically coupled to the source / drain regions 24 and 26 of IC 20 up to M2 40, and in this embodiment, to the gate 28 of IC 20.

[0045] The finfet 22 of IC 20 is interconnected with each other through different metal layers of M0 30, M1 42, and M2 40 to perform the functions of IC 20. In the current example embodiment, IC 20 includes a portion of serialization / deserialization circuitry that uses digital circuit design rules and digital fin boundary design (instead of analog circuit design rules and analog fin boundary design). In other example embodiments, IC 20 may include other circuitry, such as analog circuitry, digital circuitry, and / or mixed analog and digital circuitry that use digital circuit design rules and digital fin boundary design.

[0046] Figure 3 This is a block diagram schematically illustrating an example of a serial / deserialization circuit 50 designed and manufactured using both analog circuit design rules with analog fin boundaries and digital circuit design rules with digital fin boundaries, according to some embodiments. The serial / deserialization circuit 50 includes a plurality of circuit elements or blocks 52a-52i. In embodiments, at least one of the circuit blocks 52a-52i is designed and manufactured using only analog circuit design rules and analog fin boundaries, at least one of the circuit blocks 52a-52i is designed and manufactured using only digital circuit design rules and digital fin boundaries, and at least one of the circuit blocks 52a-52i is designed and manufactured using both analog circuit design rules and analog fin boundaries, and digital circuit design rules and digital fin boundaries.

[0047] Long-channel finFETs can be provided using analog circuit design rules and analog fin boundaries. Long-channel finFETs have a higher active region density, where the active regions correspond to the source and / or drain diffusion portions. Furthermore, long-channel finFETs have lower noise levels and can have thicker oxide layers, thus allowing them to withstand higher voltages and making them ideal for I / O devices. In some embodiments, the active region layout pattern is referred to as an oxide diffusion (OD) region layout pattern, where the OD region layout pattern can be used to fabricate the source and / or drain regions of one or more transistors.

[0048] Higher GM, higher UGF, and higher maximum EM current can be achieved using digital circuit design rules and digital fin boundaries. Digital fin boundaries provide MEOL and BEOL layers with lower interconnect resistance, resulting in higher GM. Furthermore, digital fin boundaries offer smaller cell sizes, leading to lower capacitance C values, where higher GM and lower capacitance C contribute to higher UGF. Additionally, due to the smaller cell size, digital fin boundaries provide shorter metal tracks, such as shorter M0 and M1 tracks, which increases the maximum EM current.

[0049] In this embodiment, circuit blocks 52a and 52b are designed and fabricated using only analog circuit design rules and analog fin boundaries. Circuit blocks 52a and 52b respectively include a long-channel phase-locked loop (LC-PLL) and a common bias generator. Long-channel finfets fabricated to simulate fin boundaries are used in the LC-VCO to minimize noise, and long-channel finfets are used in the current mirror to reduce the area used in the IC.

[0050] In this embodiment, circuit blocks 52c-52g are designed and manufactured according to digital circuit design rules and digital fin boundaries. Circuit blocks 52c-52g respectively include a quaternary clock generator (QCG) and clock distribution element, a high-speed multiplexer (MUX), a transmit (TX) driver, a high-speed limiter, and a receiver (RX) front-end (FE) equalizer. Digital fin boundaries are used on these circuits to achieve the high bandwidth of the serial / deserialization circuit 50.

[0051] In the embodiments, circuit blocks 52h and 52i are designed and manufactured using both analog fin boundaries and digital fin boundaries. Circuit blocks 52h and 52i respectively include serializer circuitry and deserializer circuitry. In these circuits, from an area perspective, analog fin boundaries have a better active area density than digital fin boundaries, such that if these circuits were designed using only digital fin boundaries, they would suffer an area loss.

[0052] The layout process can be implemented by a computer system, such as an EDA system. Figure 4 This is a block diagram illustrating various aspects of the EDA system 56 according to this disclosure. Some or all of the layout methods disclosed herein can be used as design tools (e.g., as described below regarding...). Figure 5 The design process is carried out as part of the design procedure in the design room (80) discussed in the discussion.

[0053] In some embodiments, Figure 4The illustrated EDA system 56 includes an Automated Placement and Routing (APR) system. In some embodiments, the EDA system 56 is a general-purpose computing device including a processor 58 and a non-transitory computer-readable storage medium 60. The computer-readable storage medium 60 may be encoded with (e.g., stored) computer program code, such as a set of executable instructions 62. Execution of the instructions 62 by the processor 58 (at least partially) represents EDA tools that implement some or all of the functionality of the system 56, for example, by providing placement using the analog and digital circuit design rules and processes described herein. Furthermore, manufacturing tools 64 are included to design and manufacture the placement and physically implement the placement.

[0054] Processor 58 is electrically coupled to computer-readable storage medium 60 via bus 66. Processor 58 is also electrically coupled to I / O interface 68 via bus 66. Network interface 70 is also electrically connected to processor 58 via bus 66. Network interface 70 is connected to network 72, enabling processor 58 and computer-readable storage medium 60 to be connected to external components via network 72. Processor 58 is configured to execute computer program code or instructions 62 encoded in computer-readable storage medium 60 to make system 56 available for performing some or all of the functions of system 56 (e.g., providing layout using analog and digital circuit design rules and processes described herein) and other functions of system 56. In embodiments, processor 58 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0055] In embodiments, the computer-readable storage medium 60 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system, apparatus, or device. For example, the computer-readable storage medium 60 may include semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In embodiments using optical disks, the computer-readable storage medium 60 may include an optical disc read-only memory (CD-ROM), an optical disc read / write memory (CD-R / W), and / or a digital video disc (DVD).

[0056] In some embodiments, the computer-readable storage medium 60 stores computer program code or instructions 62 configured to enable the system 56 to perform some or all of the functions of the system 56 (e.g., to provide layout using the analog and digital circuit design rules and procedures described herein) and other functions of the system 56. In some embodiments, the computer-readable storage medium 60 also stores information that helps to perform some or all of the functions of the system 56. In some embodiments, the computer-readable storage medium 60 stores a standard cell library 74 comprising standard logic cells.

[0057] EDA system 56 includes an I / O interface 68 coupled to external circuitry. In an embodiment, the I / O interface 68 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 58.

[0058] Network interface 70 is coupled to processor 58 and allows system 56 to communicate with network 72, through which one or more other computer systems can connect. Network interface 70 may include: a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In embodiments, some or all of the functions of system 56 may be performed in two or more systems 56.

[0059] System 56 is configured to receive information via I / O interface 68. The information received via I / O interface 68 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 58. The information is transmitted to processor 58 via bus 66. Furthermore, EDA system 56 is configured to receive information related to the user interface (UI) via I / O interface 68. This information can be stored as UI 76 on computer-readable medium 60.

[0060] In some embodiments, some or all of the functions of system 56 are implemented by a standalone software application for processor execution. In some embodiments, some or all of the functions of system 56 are implemented in a software application as part of an additional software application. In some embodiments, some or all of the functions of system 56 are implemented as plug-ins to a software application. In some embodiments, at least one function of system 56 is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the functions of system 56 are implemented as software applications used by EDA system 56. In some embodiments, the layout diagram including standard cells is generated using a tool such as VIRTUOSO, available from Cadence Design Systems, Inc., or other suitable layout generation tools.

[0061] In some embodiments, layout and other processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM and RAM), and memory cards, etc.

[0062] As described above, embodiments of EDA system 56 include manufacturing tools 64 for implementing the manufacturing process of system 56. For example, a design can be synthesized, wherein the desired behavior and / or functionality of the design is converted into a functionally equivalent logic gate-level circuit description by matching the design with standard cells selected from a standard cell library 74. This synthesis produces a functionally equivalent logic gate-level circuit description, such as a gate-level netlist. Based on the gate-level netlist, a photomask for fabricating an IC using manufacturing tools 64 can be generated.

[0063] Combination Figure 5 Other aspects of device manufacturing were disclosed. Figure 5 This is a block diagram of an IC manufacturing system 78 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 78 is used to manufacture at least one of the following: one or more semiconductor masks; or at least one component in a layer of a semiconductor IC.

[0064] exist Figure 5 In this IC manufacturing system 78, entities interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of ICs (such as those described herein), such as design studio 80, mask room 82, and IC manufacturer / fab 84. The entities in system 78 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design studio 80, mask room 82, and IC manufacturer / fab 84 are owned by a single, larger company. In some embodiments, two or more of design studio 80, mask room 82, and IC manufacturer / fab 84 coexist in a shared facility and use shared resources.

[0065] Design studio (or design team) 80 generates IC design layout 86. IC design layout 86 includes various geometric patterns or IC layouts designed for IC devices (e.g., devices designed using analog circuit design rules and analog fin boundaries and / or digital circuit design rules and digital fin boundaries). The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of the semiconductor structure to be manufactured. The layers are combined to form various IC features. For example, a portion of IC design layout 86 includes various IC features to be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source electrodes, drain electrodes, metal lines, partial vias, and openings for bonding pads. Design studio 80 implements a design process to form IC design layout 86. The design process includes one or more of analog circuit design, digital logic circuit design, physical layout design, and placement and routing routines. IC design layout 86 is presented in one or more data files containing geometric pattern information. For example, IC design layout 86 may be expressed in GDSII or DFII file format.

[0066] Mask chamber 82 includes data preparation 88 and mask fabrication 90. Mask chamber 82 uses an IC design layout 86 to fabricate one or more masks 92, which are used to fabricate various layers of an IC or semiconductor structure. Mask chamber 82 performs mask data preparation 88, in which the IC design layout 86 is converted into a representative data file (RDF). Mask data preparation 88 provides the RDF to mask fabrication 90. Mask fabrication 90 includes a mask writer that converts the RDF into an image on a substrate (e.g., a mask (reticle) 92 or a semiconductor wafer 94). Mask data preparation 88 processes the design layout 86 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer / manufacturer 84. Figure 5 In this embodiment, mask data preparation 88 and mask manufacturing 90 are shown as separate elements. In some embodiments, mask data preparation 88 and mask manufacturing 90 are collectively referred to as mask data preparation.

[0067] In some embodiments, mask data preparation 88 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout (Figure 86). In some embodiments, mask data preparation 88 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0068] In some embodiments, mask data preparation 88 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 86, which has already been processed in the OPC, to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 86 to compensate for constraints during mask fabrication 90, which can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0069] In some embodiments, mask data preparation 88 includes lithography process inspection (LPC), which simulates the process to be performed by the IC manufacturer / manufacturer 84. The LPC simulates the process based on the IC design layout 86 to create a simulated fabricated device. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, etc., or combinations thereof. In some embodiments, after the simulated fabricated device has been created via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 86.

[0070] For clarity, the above description of mask data preparation 88 has been simplified. In some embodiments, data preparation 88 includes additional features such as logic operations (LOPs) to modify the IC design layout 86 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 86 during data preparation 88 can be performed in various different sequences.

[0071] After mask data preparation 88 and during mask fabrication 90, a mask 92 or a set of masks 92 is fabricated based on a modified IC design layout 86. In some embodiments, mask fabrication 90 includes performing one or more photolithographic exposures based on the IC design layout 86. In some embodiments, a mechanism using an electron beam (e-beam) or multiple electron beams is used to form a pattern on the mask (photomask or intermediate mask) 92 based on the modified IC design layout 86. The mask 92 can be formed using various techniques. In some embodiments, the mask 92 is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (e.g., ultraviolet (UV) beams) used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 92 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 92 is formed using phase-shifting techniques. In the phase-shift mask (PSM) version of mask 92, the individual features in the pattern formed on the phase-shift mask are configured to have appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. One or more masks generated by mask fabrication 90 are used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 94, in etching processes to form various etched regions in semiconductor wafer 94, and / or for other suitable processes.

[0072] IC manufacturer / manufacturer 84 includes wafer fabrication 96. IC manufacturer / manufacturer 84 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturer / manufacturer 84 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (e.g., FEOL manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (e.g., BEOL manufacturing) for interconnecting and packaging of IC products, and a third manufacturing facility may provide additional services to the foundry enterprise.

[0073] IC manufacturer / manufacturer 84 uses one or more masks 92 manufactured by mask chamber 82 to manufacture the semiconductor structure or IC 98 of this disclosure. Therefore, IC manufacturer / manufacturer 84 uses IC design layout 86 at least indirectly to manufacture the semiconductor structure or IC 98 of this disclosure. In some embodiments, IC manufacturer / manufacturer 84 uses one or more masks 92 to manufacture semiconductor wafer 94 to form the semiconductor structure or IC 98 of this disclosure. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based at least indirectly on IC design layout 86. Semiconductor wafer 94 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 94 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0074] Figure 6 This is a schematic illustration of a FinFET cell 100 designed according to some embodiments using digital circuit design rules and digital fin boundaries instead of analog circuit design rules and analog fin boundaries. The FinFET cell 100 includes four fins 102a-102d located within a cell boundary 106 and a gate 104. Each of the four fins 102a-102d includes a source region 108 located on one side (e.g., the left side) of the gate 104 and a drain region 110 located on the other side (e.g., the right side) of the gate 104. In other embodiments, the source region 108 may be located on the right side of the gate 104, and the drain region 110 may be located on the left side of the gate 104. Furthermore, in other embodiments, the FinFET cell 100 may include fewer than four fins 102a-102d or more than four fins 102a-102d.

[0075] In ICs designed using analog circuit design rules and analog fin boundary design, the fins of a finfet cell are spaced at equal distances, known as fin pitch. The fins lie on equidistant grid lines 112 of an equifin grid 114 associated with the analog circuit design rules and analog fin boundaries. Each fin of the finfet cell is aligned with one of the grid lines 112 of the equifin grid 114. For example, for four fins, there is one fin on each of the four adjacent grid lines 112.

[0076] The fins 102a-102d of the finfet cell 100, designed using digital circuit design rules and digital fin boundaries, are not aligned with or located on the grid lines 112 of the equal-fin grid 114. Instead, the fins 102a-102d are located between or intersect with the grid lines 112 of the equal-fin grid 114. Furthermore, the finfet cell 100 has the same fin formation or boundary as digital logic cells designed using digital fin boundaries. The finfet cell 100 has two fins 102a and 102b located at the top 116 of the finfet cell 100, and two fins 102c and 102d located at the bottom 118 of the finfet cell 100. Between the top 116 and the bottom 118 is a middle section 120 without any fins, which allows metal wiring to pass through the finfet cell 100 or to the gate 104 of the finfet cell 100.

[0077] In this embodiment, by positioning fins 102a-102d between grid lines 112 and having a central portion 120 without any fins in the finfet cell 100, the space utilization efficiency of the finfet cell 100 and the space passing through the finfet cell 100 can be improved, allowing for a smaller device size. Furthermore, in this embodiment, by positioning fins 102a-102d between grid lines 112, the height H of the finfet cell 100 can be reduced or lowered relative to finfet cells designed using analog circuit design rules and analog fin boundary designs, further enabling a smaller device size.

[0078] Figures 7-9 The illustrations schematically depict different analog cell device types 200, 202, and 204 according to some embodiments. Analog cell device types 200, 202, and 204 respectively include finfet cells 206, 208, and 210 designed using digital circuit design rules and digital fin boundaries. In embodiments, the analog cell device types can be used for at least analog circuits, mixed analog and digital circuits, and / or serial / deserialized circuits. In embodiments, finfet cells 206, 208, and 210 are similar to... Figure 6 The finfet unit 100 shown.

[0079] Figure 7This is a schematic illustration of an analog cell device type 200 including finfet cells 206 according to some embodiments. These finfet cells 206 are designed using digital circuit design rules and digital fin boundaries and are arranged in columns to have two rows of PMOS finfets 212, followed by two rows of NMOS finfets 214, then two rows of PMOS finfets 212, then two rows of NMOS finfets 214, and so on, in a repeating pattern. In an embodiment, the analog cell device type 200 includes finfet cells 206 arranged in extended rows (not shown).

[0080] Each finfet cell 206 includes a row of PMOS finfets 216 and a row of NMOS finfets 218. The row of PMOS finfets 216 includes two fins 220, and the row of NMOS finfets 218 includes two fins 222. In an embodiment, each finfet cell 206 includes multiple pairs of finfets 224, where each pair of finfets 224 includes one PMOS finfet 216 and one NMOS finfet 218. In an embodiment, each pair of finfets 224 shares the same gate 226.

[0081] The finfet cells 206 of analog cell device type 200 are arranged such that a row of PMOS finfets 216 in one finfet cell 206 is adjacent to a row of PMOS finfets 216 in an adjacent finfet cell 206, and a row of NMOS finfets 218 in one finfet cell 206 is adjacent to a row of NMOS finfets 218 in an adjacent finfet cell 206. This makes two rows of PMOS finfets 212 adjacent to each other in a repeating pattern, followed by two rows of NMOS finfets 214 adjacent to each other. In an embodiment, this arrangement of NMOS and PMOS finfets is the same as the arrangement of NMOS and PMOS finfets in logic circuit devices (e.g., standard cell devices).

[0082] Figure 8This is a schematic illustration of an analog cell device type 202 comprising finfet cells 208 designed using digital circuit design rules and digital fin boundaries, according to some embodiments. The analog cell device type 202 is designed to have four rows of PMOS finfets 228, followed by four rows of NMOS finfets 230, then four rows of PMOS finfets 228, then four rows of NMOS finfets 230, and so on, in a repeating pattern. The finfet cells 208 in the analog cell device type 202 are arranged in columns. Of course, in embodiments, the analog cell device type 202 may include finfet cells 208 arranged in extended rows (not shown).

[0083] There are two types of finfet units 208. One type is a PMOS finfet unit 208a, which includes two rows of PMOS finfets 232, and the other type is an NMOS finfet unit 208b, which includes two rows of NMOS finfets 234. Each row of PMOS finfets 232 includes two fins 236, and each row of NMOS finfets 234 includes two fins 238.

[0084] FinFET cells 208 are arranged in analog circuit device type 202 to have two PMOS finFET cells 208a, followed by two NMOS finFET cells 208b, and so on in a repeating pattern. In an embodiment, analog cell device type 202 includes dual-height finFET groups 240, each including finFETs from two rows of PMOS finFETs 232 and two rows of NMOS finFETs 234. In an embodiment, each dual-height transistor group 240 shares the same gate 242. In an embodiment, the arrangement of NMOS finFETs 234 and PMOS finFETs 232 in analog cell device type 202 differs from the arrangement of NMOS and PMOS finFETs in logic circuit devices (e.g., standard cell devices).

[0085] Figure 9This is a schematic illustration of an analog cell device type 204 including finfet cells 210 according to some embodiments. These finfet cells 210 are designed using digital circuit design rules and digital fin boundaries and are arranged in columns, having the same type of finfet. In one embodiment, the analog cell device type 204 has finfet cells 210 arranged in columns, with all rows of that column being PMOS finfets. In another embodiment, the analog cell device type 204 has finfet cells 210 arranged in columns, with all rows of that column being NMOS finfets. In some embodiments, the analog cell device type 204 includes a column of finfet cells 210 where all rows are PMOS finfets and an adjacent column of finfet cells 210 where all rows are NMOS finfets. In this embodiment, this arrangement of the finfet cells 210 differs from the arrangement of NMOS and PMOS finfets in logic circuit devices (e.g., standard cell devices).

[0086] Figure 10A This is a schematic illustration of a FinFET cell 300 in an IC 20 according to some embodiments. The IC 20 has analog cells designed using digital circuit design rules and digital fin boundary design and includes a MEOL layer. In embodiments, these analog cells can be used for analog circuits, digital circuits, hybrid analog and digital circuits, and serial / deserialization circuits previously designed entirely using analog circuit design rules and analog fin boundary design. In embodiments, the FinFET cell 300 is similar to... Figure 6 The finfet unit 100 shown.

[0087] The finFET cell 300 includes four fins 302a-302d located within a cell boundary 306 and a gate 304. Each of the four fins 302a-302d includes a corresponding source region 308a-308d located on one side (e.g., the left side) of the gate 304 and a corresponding drain region 310a-310d located on the other side (e.g., the right side) of the gate 304. In other embodiments, the source regions 308a-308d may be located on the right side of the gate 304, and the drain regions 310a-310d may be located on the left side of the gate 304. Furthermore, in other embodiments, the finFET cell 300 may include fewer than four fins 302a-302d or more than four fins 302a-302d.

[0088] The fins 302a-302d of the FinFET cell 300, designed using digital circuit design rules and digital fin boundaries, are not aligned with or located on grid lines 312. Instead, fins 302a-302d are located between grid lines 312. Furthermore, the FinFET cell 300 has the same fin boundaries or formation as logic cells designed using digital fin boundaries. The FinFET cell 300 has two fins 302a and 302b located at the top 316 of the FinFET cell 300, and two fins 302c and 302d located at the bottom 318 of the FinFET cell 300. Between the top 316 and the bottom 318 is a middle section 320 without any fins, which allows metal wiring to pass through the FinFET cell 300 or to the gate 304 of the FinFET cell 300.

[0089] like Figure 10A As shown, the MEOL layer includes MD 322a-322d, M0 lines 324a-324g, VG 326, VD 328a-328d, and VD2 330a and 330b. The gate 304 of the FinFET cell 300 is electrically coupled to the M0 line 324d via VG 326. Source regions 308a and 308b are electrically coupled to MD 322a, and source regions 308c and 308d are electrically coupled to MD 322b. Furthermore, drain regions 310a and 310b are electrically coupled to MD 322c, and drain regions 310c and 310d are electrically coupled to MD 322d.

[0090] M0 lines 324a and 324g are wider metal lines, with a lower resistance per unit length than the narrower metal lines 324b-324f. In the embodiments, the widths of the wider metal lines M0 lines 324a and 324g range from 10 nanometers (nm) to 50 nm, while the widths of the narrower metal lines M0 lines 324b-324f range from 6 nm to 20 nm.

[0091] On the source side of the FinFET cell 300, MD 322a is electrically coupled to M0 line 324c via VD 328a and to M0 line 324a via VD2 330a. MD 322a electrically couples source regions 308a and 308b to M0 lines 324a and 324c. MD 322b is electrically coupled to M0 line 324e via VD 328b and to M0 line 324g via VD2 330b. MD 322b electrically couples source regions 308c and 308d to M0 lines 324e and 324g.

[0092] Each of VD2 330a and 330b is larger in size than each of VD 328a-328d. In some embodiments, VD2 ranges from 8 nm × 8 nm to 24 nm × 24 nm, and VD ranges from 6 nm × 6 nm to 20 nm × 20 nm. VD2 contacts the wider metal lines MO 324a and 324g, while VD contacts the narrower metal lines 324b, 324c, 324e, and 324f. In embodiments, VD2 330a and 330b are permitted only when the cell is designed using digital circuit design rules and digital fin boundaries. Therefore, analog circuits designed and manufactured using digital circuit design rules can include VD2 in contact with MD to improve performance because the resistance of VD2 is at least 50% lower than that of VD.

[0093] On the drain side of the finfet cell 300, MD 322c is electrically coupled to M0 line 324b via VD 328c to electrically couple drain regions 310a and 310b to M0 line 324b, and MD 322d is electrically coupled to M0 line 324f via VD 328d to electrically couple drain regions 310c and 310d to M0 line 324f.

[0094] Figure 10B This is an illustrative representation according to some embodiments. Figure 10A The edge of the finfet unit Figure 10A A cross-sectional view of line BB in the diagram. Figure 10B The cross-section shows fins 302a and 302b extending from substrate 332. The source regions 308a and 308b of fins 302a and 302b are electrically coupled to MD 322a, respectively.

[0095] VD2 330a electrically connects MD 322a to the wider metal line M0 line 324a, and VD 328a electrically connects MD 322a to the narrower metal line 324c. VD2 330a is larger than VD 328a. In some embodiments, VD2 is square, and in some embodiments, VD is square. Furthermore, in some embodiments, the width Wd2 of VD2 ranges from 8 nm to 24 nm, and in some embodiments, the width Wd of VD ranges from 6 nm to 20 nm.

[0096] Figure 11This is a schematic illustration of a finfet cell 348 in an IC 20 according to some embodiments. The IC 20 has analog cells designed using digital circuit design rules and digital fin boundary design and includes at least some MEOL layers. In embodiments, these analog cells can be used for analog circuits, digital circuits, a mixture of analog and digital circuits, and serial / deserialized circuits previously designed entirely using analog circuit design rules and analog fin boundary design.

[0097] exist Figure 11 At least four finfet units 348 are shown in the diagram. However, for clarity, only finfet unit 350 will be described in detail below. Of course, in this embodiment, each of the other finfet units 348 is similar to finfet unit 350. Furthermore, in this embodiment, each of the finfet units 348 is similar to... Figure 10A The finfet unit 300 is shown.

[0098] The fin unit 350 includes four fins 352 (two fins at 352a and two fins at 352b) and a gate 354. Furthermore, each fin at 352a includes a corresponding source region at 358a on one side of the gate 354 and a corresponding drain region at 360a on the other side of the gate 354, and each fin at 352b includes a corresponding source region at 358b on one side of the gate 354 and a corresponding drain region at 360b on the other side of the gate 354. In other embodiments, the source and drain regions 358 and 360 can be switched to the other side of the gate 354.

[0099] like Figure 11 As shown, the MEOL layer includes MD 362a-362d, cleaved MD regions (CMD) 364a-364c, VG 366, VD368a-368d, and VD2 370a and 370b. The gate 354 of the finfet cell 350 is electrically coupled to VG 366. The source region at 358a is electrically coupled to MD 362a, and the source region at 358b is electrically coupled to MD 362b. The drain region at 360a is electrically coupled to MD 362c, and the drain region at 360b is electrically coupled to MD 362d.

[0100] On the source side of the FinFET cell 350, MD 362a is electrically coupled to VD 368a and VD2 370a, and MD 362b is electrically coupled to VD 368b and VD2 370b. Each of VD2 370a and 370b is larger in size than each of VD 368a-368d. In some embodiments, VD2 ranges from 8 nm × 8 nm to 24 nm × 24 nm, and VD ranges from 6 nm × 6 nm to 20 nm × 20 nm. In some embodiments, VD2 370a and 370b are permitted only when using digital circuit design rules. Therefore, analog circuits designed and manufactured using digital circuit design rules may include VD2 in contact with MD to improve performance because the resistance of VD2 is at least 50% lower than that of VD.

[0101] On the drain side of the finfet cell 350, MD 362c is electrically coupled to VD 368c, and MD 362d is electrically coupled to VD368d.

[0102] In the FinFET cell 350, MDs 362a and 362b are separated by CMD 364b, and MDs 362c and 362d are also separated by CMD 364b. Furthermore, each of MDs 362c and 362d is further shortened by CMDs 364a and 364c, respectively, which further shortens MDs 362c and 362d. Shortening MDs 362a-362d reduces the capacitance C of the polysilicon from MDs 362a-362d to the gate 354.

[0103] Therefore, using digital circuit design rules to design analog circuits increases GM, where VD2 increases GM by reducing the resistance in MEOL and reducing the capacitance C of the polysilicon from MD to gate 354. This also increases UGF, where UGF = GM / C. Furthermore, using digital circuit design rules to design analog cells provides process location points for ultra-low voltage threshold (ULVT) circuits.

[0104] Figure 12 Table 400 schematically illustrates M0 lines or tracks in analog circuit units 402, 404, 406, 408, and 410 designed using digital circuit design rules and digital fin boundaries according to some embodiments. In some embodiments, each of the analog circuit units 402, 404, 406, 408, and 410 is similar to Figure 6 The finfet unit 100 shown.

[0105] Each of analog circuit cells 402, 404, 406, 408, and 410 includes four fins 412a-412d located within cell boundary 416 and a gate 414. Each of the four fins 412a-412d includes a source region 418 located on one side of the gate 414 and a drain region 420 located on the other side of the gate 414. The fins 412a-412d of analog circuit cells 402, 404, 406, 408, and 410 are not aligned with and are not located on the grid lines 422 of the equal-fin grid. Instead, the fins 412a-412d are located between the grid lines 422. Furthermore, each of analog circuit cells 402, 404, 406, 408, and 410 has the same fin formation or boundary as the logic cell, with two fins 412a and 412b located at the top 426 and two fins 412c and 412d located at the bottom 428. Between the top 426 and the bottom 428 is the middle section 430, which has no fins, allowing for the wiring of metal wires.

[0106] In analog cells using analog circuit design rules and analog fin boundary design, the M0 track is aligned with the fin and substantially aligned with the grid line 422 of the iso-fin grid. This differs from the arrangement of M0 lines or tracks in analog cells using digital circuit design rules and digital fin boundary design (e.g., analog circuit cells 402, 404, 406, 408, and 410). In these analog circuit cells 402, 404, 406, 408, and 410, the number of M0 tracks is optional. For example, in each of analog circuit cells 402, 404, 406, 408, and 410, the number of M0 tracks can range from 1 to 5 or even more.

[0107] Table 400 includes the layout of analog circuit units 402, 404, 406, 408, and 410, each including one M0 track 432, two M0 tracks 434a and 434b, three M0 tracks 436a-436c, four M0 tracks 438a-438d, and five M0 tracks 440a-440e. These M0 track counts do not include the wide M0 tracks 442 and 444 located at the top and bottom of each of the analog circuit units 402, 404, 406, 408, and 410.

[0108] like Figure 12As shown, analog circuit unit 402 includes an M0 track 432 located between fins 412b and 412c and on one of the grid lines 422. Analog unit 404 includes two M0 tracks 434a and 434b, one M0 track 434a located near fins 412a and 412b and on grid line 422, and the other M0 track 434b located near fins 412c and 412d and on grid line 422. Analog unit 406 includes three M0 tracks 436a-436c, one M0 track 436b located between fins 412b and 412c and on or near grid line 422, another M0 track 436a located near fins 412a and 412b and on grid line 422, and another M0 track 436c located near fins 412c and 412d and on grid line 422. Analog unit 408 includes four M0 tracks 438a-438d, one of which is located near each of fins 412a-412d and on or near grid line 422. Analog unit 410 includes five M0 tracks 440a-440e, one of which is located near each of fins 412a-412d, and one M0 track 440e is located between fins 412b and 412c. In other embodiments, analog circuit units 402, 404, 406, 408, and 410 may have more than five M0 lines or tracks.

[0109] Figure 13 Table 500 illustrates threshold voltage (Vt) levels achievable in analog and digital cells using digital circuit design rules and digital fin boundary design, according to some embodiments, relative to Vt levels achievable in analog cells using analog circuit design rules and analog fin boundary design. Vt levels include: Standard Vt (SVT) at 502, with the lowest leakage level; Low Vt (LVTLL) with low leakage at 504; Low Vt (LVT) at 506; Ultra-Low Vt (ULVTLL) with low leakage at 508; Ultra-Low Vt (ULVT) at 510; and Extremely Low Vt (ELVT) at 512. SVT at 502 has the highest Vt, followed by LVTLL at 504, LVT at 506, ULVTLL at 508, ULVT at 510, and ELVT (lowest Vt) at 512, in descending order of Vt.

[0110] As shown in Table 500, the analog cell designed using digital fin boundaries at position 514 and the digital circuit designed using digital fin boundaries at position 516 can be designed and manufactured to have any threshold voltage at positions 502 (SVT), 504 (LVTLL), 506 (LVT), 508 (ULVTLL), 510 (ULVT), and 512 (ELVT). This differs from the analog cell designed using analog fin boundaries at position 518, where positions 508 (ULVTLL) and 512 (ELVT) cannot be constructed using analog circuit design rules and analog fin boundaries.

[0111] Figure 14 This is a schematic illustration of an IC 600 according to some embodiments. The IC 600 includes a digital circuit cell 604 designed using digital circuit design rules and digital fin boundary design, and an analog cell 602 located adjacent to the digital circuit cell 604, designed using digital circuit design rules and digital fin boundary design. With the analog circuit cell 602 and the digital circuit cell 604 using the same digital circuit design rules and the same digital fin boundary design, cells 602 and 604 have the same cell boundary 606 and fin formation of four fins 608. Therefore, the analog cell 602 can be directly adjacent to the digital cell 604 at 610 without providing additional blocking space between the different cells 602 and 604.

[0112] Figure 15 This is a schematic top view illustrating the M0 lines in an IC 700 according to some embodiments and an example below. The IC 700 includes analog cells designed using digital circuit design rules and digital fin boundary design. In the IC 700, at least some metal lines can be made shorter, which increases the maximum permissible EM current through the metal. In embodiments, the IC 700 is similar to... Figure 1 and Figure 2 IC 20.

[0113] IC 700 includes Figure 15 Multiple finfets 702 are positioned from left to right in the middle. Each finfet 702 includes a fin source region 704 (electrically coupled to one or more MDs indicated at S), a fin drain region 706 (electrically coupled to one or more MDs indicated at D), and a gate 708 (located between the respective source and drain regions 704 and 706). In an embodiment, each finfet 702 may have an MD cleaved in a CMD region 709.

[0114] In this embodiment, in each finfet 702, the MD of the source S is connected to M0 710 via one or more VD2 712 and one or more VD 714. Furthermore, in each finfet 702, the MD of the drain D is connected to M0 710 via one or more VD716. Each gate 708 is connected to M0 710 via VG 717.

[0115] like Figure 15 As shown, IC 700 includes a cut M0 region 720, where M0 710 is cut to create a shorter M0 710 line. This cut M0 region 720 is permitted using digital circuit design rules and digital fin boundaries (rather than analog circuit design rules and analog fin boundaries). The shorter the M0 710 line, the higher the maximum EM current. Furthermore, the cut M0 line 710 can be located directly next to VD and / or via VIA0 (e.g., Figure 16 (As shown). In some embodiments, the length of the cut MO lines ranges from 0.5 CPP to 8 CPP, and in some embodiments, the MO spacing ranges from 5 nm to 40 nm.

[0116] Figure 16 This is a schematic top view illustrating an example of the BEOL layer of IC 700 up to M2 740 according to some embodiments. IC 700 includes M2 740 arranged in a horizontal line or track and M1 742 arranged in a vertical line or track.

[0117] like Figure 15 and Figure 16 As shown, M0 710 is positioned on a horizontal line or track on IC 700 such that the vertical line of M1 742 is orthogonal to the horizontal line of M0 710 and to the horizontal line of M2 740. The track of M1 742 is connected to the respective track of M0 710 through via 744 (VIA0), and the track of M1 742 is connected to the track of M2 740 through via 746 (VIA1). Therefore, the BEOL layer is electrically coupled to the source / drain regions 704 and 706 up to M2 740, and in this embodiment, to the gate 708.

[0118] As described herein, finfet cells designed using digital circuit design rules and digital fin boundaries are shorter than those designed using analog circuit design rules and analog fin boundaries, where finfet cells designed using digital fin boundaries can be less than 7 CPP. Therefore, the shorter the cell height, the shorter the length of M1 742 and the higher the maximum current of the EM. Furthermore, in the embodiments, the M1 pitch ranges from 28 nm to 60 nm.

[0119] Figure 17This is a diagram illustrating the temperature distribution 750 of IC 700 according to some embodiments. As shown, the temperature distribution 750 is uniformly distributed across the IC from top to bottom and from side to side. Therefore, EM analysis of the temperature distribution was performed.

[0120] Figure 18 This is a block diagram illustrating a method for manufacturing a semiconductor structure (e.g., an IC) according to some embodiments, the semiconductor structure (e.g., the IC) including analog cells designed using digital circuit design rules and digital fin boundary design.

[0121] At 800, the method includes providing a fin mesh structure with mesh lines based on analog circuit design rules and analog fin boundaries. The method continues at 802 by forming a plurality of finfet cells based on digital circuit design rules and digital fin boundaries on the fin mesh structure (i.e., the fin mesh structure based on analog circuit design rules and analog fin boundaries). Each of the plurality of finfet cells includes a fin located between the mesh lines of the fin mesh structure, rather than located on the mesh lines themselves.

[0122] In some embodiments, the method includes cutting the M0 line in at least one of the plurality of finfet cells to provide a shorter M0 line, which increases the maximum EM current. Furthermore, in some embodiments, the finfet cells designed using digital fin boundaries (rather than analog fin boundaries) have a shorter cell height, resulting in shorter metal lines at least in some cases, which also increases the maximum EM current.

[0123] In some embodiments, the method includes forming a MEOL layer in at least one of a plurality of FINFET cells in at least one analog circuit structure, wherein forming the MEOL layer includes: forming a first source / drain contact VD having a first resistance, and forming a second source / drain contact VD2 having a second resistance less than or equal to 0.5 times the first resistance.

[0124] Furthermore, in some embodiments, the method includes: forming an analog cell structure comprising at least some of a plurality of finfet cells, forming a digital cell structure comprising at least some of a plurality of finfet cells, and adjoining the analog cell structure to the digital cell structure.

[0125] Therefore, the disclosed embodiments provide semiconductor structures, such as ICs, including analog cells designed and manufactured using digital circuit design rules and digital fin boundaries. The integrated circuit includes finfets and is designed with fin formation methods including digital circuit design rules and digital fin boundaries, beneficial MEOL layers, optional M0 rails, various threshold voltages Vt, and features such as direct adjacency between analog cells and digital logic cells.

[0126] The disclosed embodiments include finfet cells where the fins are not located on the grid lines of the fin mesh associated with analog circuit design rules and analog fin boundaries. Instead, the fins are located between the grid lines of the fin mesh. In these embodiments, the finfet cell height is reduced, allowing for a smaller device size. Furthermore, the fin formation in these analog cells leaves space between the fins in the middle of the finfet cell, which can be used for wiring metal. In these embodiments, space utilization inside and around the finfet cell can be improved, and the device size can be reduced.

[0127] The arrangement of NMOS and PMOS finfets in analog circuit devices is flexible. In some embodiments, the arrangement of NMOS and PMOS finfets in analog circuit devices can be the same as that in logic circuit devices. In other embodiments, the arrangement of NMOS and PMOS finfets in analog circuit devices can differ from that in logic circuit devices.

[0128] The beneficial properties of MEOL layers designed using digital circuit design rules and digital fin boundary design include a larger contact area VD2 on MD to improve performance, since the resistance of VD2 is at least 50% lower than that of the smaller contact area VD on MD.

[0129] Furthermore, the arrangement and number of M0 lines in the analog cell designed using digital circuit design rules and digital fin boundary design are optional, and the number varies from 1 to 5 or more M0 lines anywhere. Additionally, the disclosed analog cell designed using digital circuit design rules and digital fin boundary design may include shorter MD lines to achieve a higher maximum EM current, shorter M0 lines to achieve a higher maximum EM current, and shorter M1 lines to achieve a higher maximum EM current.

[0130] The advantages of designing and manufacturing semiconductor structures (such as integrated circuits) that incorporate analog cells designed and manufactured using digital circuit design rules and digital fin boundary design include higher GM, higher UGF, and higher EM in finfet cells. GM is higher due to the lower resistance of the MEOL and BEOL layers. Furthermore, UGF is higher when UGF = GM / C and GM is higher while MEOL capacitance C is smaller. Additionally, shorter metal line lengths result in higher maximum EM current, where digital circuit design rules allow for cut M0, and shorter M1 lines result in shorter cell heights.

[0131] According to some disclosed embodiments, an integrated circuit includes: a plurality of FinFET cells designed using digital circuit design rules to provide smaller FinFET cells with reduced cell height; and an analog circuit cell structure including a first FinFET cell of the plurality of FinFET cells and including at least one diced metal layer. The digital circuit cell structure includes a second FinFET cell of the plurality of FinFET cells, and the analog circuit cell structure is directly adjacent to the digital circuit cell structure. The smaller FinFET cells with reduced cell height provide a first shorter metal track in one direction, and the at least one diced metal layer provides a second shorter metal track in another direction to improve the maximum electromigration current in the integrated circuit.

[0132] According to a further embodiment, a semiconductor structure includes a plurality of finfet cells. A plurality of source / drain conductors are disposed on and electrically coupled to the plurality of finfet cells, the plurality of source / drain conductors including wider and narrower source / drain conductors. A plurality of gate conductors are disposed on and electrically coupled to the plurality of finfet cells, and are interleaved with the plurality of source / drain conductors. A plurality of gate contacts are electrically coupled between the finfet gates and the plurality of gate conductors in the plurality of finfet cells. A plurality of source / drain contacts are electrically coupled between the finfet source / drain regions and the plurality of source / drain conductors in the plurality of finfet cells. The plurality of source / drain contacts include a first source / drain contact and a second source / drain contact, each first source / drain contact having a first width and electrically coupled to at least one of the wider source / drain conductors, and each second source / drain contact having a second width and electrically coupled to at least one of the narrower source / drain conductors, wherein the first width is greater than the second width.

[0133] According to a further embodiment, a method includes: providing a fin mesh structure having uniformly spaced mesh lines and based on an analog fin boundary; providing a plurality of finfet cells based on digital fin boundaries on the fin mesh structure, each of the plurality of finfet cells including a fin intersecting with the mesh lines of the fin mesh structure; and providing a mid-processing (MEOL) layer in at least one of the plurality of finfet cells, wherein providing the MEOL layer includes: providing a first source / drain contact having a first width; and providing a second source / drain contact having a second width, wherein the second width is wider than the first width.

[0134] Example 1 is an integrated circuit comprising: a plurality of finfet cells designed using digital circuit design rules to provide smaller finfet cells with reduced cell height; an analog circuit cell structure including a first finfet cell of the plurality of finfet cells and including at least one cut metal layer; and a digital circuit cell structure including a second finfet cell of the plurality of finfet cells, wherein the analog circuit cell structure is directly adjacent to the digital circuit cell structure, and wherein the smaller finfet cell with reduced cell height includes a first shorter metal track in one direction, and the at least one cut metal layer includes a second shorter metal track in another direction to improve the maximum electromigration current in the integrated circuit.

[0135] Example 2 is the integrated circuit described in Example 1, wherein the plurality of finfet cells are arranged to form multiple rows of NMOS finfets and multiple rows of PMOS finfets according to a first mode for the analog circuit cell structure and a second mode for the digital circuit cell structure, wherein the first mode is the same as the second mode.

[0136] Example 3 is the integrated circuit described in Example 1, wherein the plurality of finfet cells are arranged to form multiple rows of NMOS finfets and multiple rows of PMOS finfets according to a first mode for the analog circuit cell structure and a second mode for the digital circuit cell structure, wherein the first mode is different from the second mode.

[0137] Example 4 is the integrated circuit described in Example 1, wherein, in the analog circuit cell structure, the plurality of finfet cells are interconnected and connected to a metal layer using a mid-process (MEOL) layer, wherein the MEOL layer is designed using the digital circuit design rules.

[0138] Example 5 is the integrated circuit described in Example 4, wherein the MEOL layer includes a plurality of source / drain contacts, wherein the plurality of source / drain contacts include a first source / drain contact having a first resistance and a second source / drain contact having a second resistance, wherein the second resistance is less than or equal to 0.5 times the first resistance of the first source / drain contact.

[0139] Example 6 is the integrated circuit described in Example 1, wherein each of the plurality of FinFET cells is configured to include one to five or more first metal layer tracks.

[0140] Example 7 is the integrated circuit described in Example 1, wherein the analog circuit unit structure includes a threshold voltage based on the digital circuit design rules.

[0141] Example 8 is the integrated circuit described in Example 1, further comprising: a fin mesh structure corresponding to the analog circuit design rules, wherein the fins of the plurality of finfet units are located between the mesh lines of the fin mesh structure.

[0142] Example 9 is the integrated circuit described in Example 1, wherein the second shorter metal track is a first metal layer track, and the first shorter metal track is a second metal layer track.

[0143] Example 10 is the integrated circuit described in Example 1, comprising: a serializer / deserializer (serdes) circuit including the plurality of finfet cells designed using the digital circuit design rules.

[0144] Example 11 is a semiconductor structure comprising: a plurality of finfet cells; a plurality of source / drain conductors disposed on and electrically coupled to the plurality of finfet cells, the plurality of source / drain conductors including wider source / drain conductors and narrower source / drain conductors; a plurality of gate conductors disposed on and electrically coupled to the plurality of finfet cells, and interleaved with the plurality of source / drain conductors; and a plurality of gate contacts electrically coupled to the finfet gates in the plurality of finfet cells and the plurality of gate conductors. The plurality of source / drain contacts are electrically coupled between the FinFET source / drain regions in the plurality of FinFET cells and the plurality of source / drain conductors, wherein the plurality of source / drain contacts include a first source / drain contact and a second source / drain contact, each of the first source / drain contacts having a first width and electrically coupled to at least one of the wider source / drain conductors, and each of the second source / drain contacts having a second width and electrically coupled to at least one of the narrower source / drain conductors, wherein the first width is greater than the second width.

[0145] Example 12 is the semiconductor structure described in Example 11, wherein the first resistance of each of the first source / drain contacts is less than or equal to 0.5 times the second resistance of each of the second source / drain contacts.

[0146] Example 13 is the semiconductor structure described in Example 11, wherein the plurality of finfet cells are arranged to form multiple rows of NMOS finfets and multiple rows of PMOS finfets according to a first mode in an analog circuit cell structure and a second mode in a digital circuit cell structure, wherein the first mode is the same as the second mode.

[0147] Example 14 is the semiconductor structure described in Example 11, wherein the plurality of finfet cells are arranged to form multiple rows of NMOS finfets and multiple rows of PMOS finfets according to a first mode in an analog circuit cell structure and a second mode in a digital circuit cell structure, wherein the first mode is different from the second mode.

[0148] Example 15 is the semiconductor structure described in Example 11, comprising: an analog circuit unit structure including a first finfet unit among the plurality of finfet units; and a digital circuit unit structure including a second finfet unit among the plurality of finfet units, wherein the analog circuit unit structure is directly adjacent to the digital circuit unit structure.

[0149] Example 16 is a method of manufacturing a semiconductor device, comprising: providing a plurality of finfet cells based on digital fin boundaries, wherein each of the plurality of finfet cells includes a fin with a non-uniform fin spacing; and providing a mid-stage process (MEOL) layer in at least one of the plurality of finfet cells, wherein providing the MEOL layer includes: providing a first source / drain contact having a first width; and providing a second source / drain contact having a second width, wherein the second width is wider than the first width.

[0150] Example 17 is the method of Example 16, comprising: cutting a first metal layer line in at least one of the plurality of finfet cells in at least one analog circuit structure to provide a shorter first metal layer line.

[0151] Example 18 is the method of Example 16, comprising: providing a shorter metal wire in at least one of the plurality of finfet cells based on at least one of the plurality of finfet cells having a reduced cell height.

[0152] Example 19 is the method described in Example 16, wherein each of the plurality of finfet units is provided with five or more first metal layer orbitals.

[0153] Example 20 is the method of Example 16, comprising: providing an analog unit including a first finfet unit among the plurality of finfet units; providing a digital unit including a second finfet unit among the plurality of finfet units; and directly adjacent the analog unit to the digital unit.

[0154] This disclosure outlines various embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit, comprising: Multiple finfet cells, which are designed using digital circuit design rules to provide small finfet cells with reduced cell height; An analog circuit unit structure includes a first finfet unit among the plurality of finfet units and includes at least one cut metal layer; The digital circuit unit structure includes a second finfet unit among the plurality of finfet units. The analog circuit unit structure is directly adjacent to the digital circuit unit structure. The small finfet cell with reduced cell height includes a first short metal track in one direction, and the at least one cut metal layer includes a second short metal track in another direction to increase the maximum electromigration current in the integrated circuit. The small finfet cell includes multiple source / drain contacts, including a first source / drain contact and a second source / drain contact. The first source / drain contact has a first width and is electrically coupled to at least one of the wide source / drain conductors. The second source / drain contact has a second width and is electrically coupled to at least one of the narrow source / drain conductors. The first width is greater than the second width.

2. The integrated circuit according to claim 1, wherein, The plurality of finfet cells are arranged to form multiple rows of NMOS finfets and multiple rows of PMOS finfets according to a first mode for the analog circuit cell structure and a second mode for the digital circuit cell structure, wherein the first mode and the second mode are the same.

3. The integrated circuit according to claim 1, wherein, The plurality of finfet cells are arranged to form multiple rows of NMOS finfets and multiple rows of PMOS finfets according to a first mode for the analog circuit cell structure and a second mode for the digital circuit cell structure, wherein the first mode is different from the second mode.

4. The integrated circuit according to claim 1, wherein, In the analog circuit unit structure, the plurality of FINFET units are interconnected and connected to the metal layer using a mid-process layer, wherein the mid-process layer is designed using the digital circuit design rules.

5. The integrated circuit according to claim 4, wherein, The mid-section process layer includes the plurality of source / drain contacts, wherein the first source / drain contact has a first resistance, the second source / drain contact has a second resistance, and the first resistance is less than or equal to 0.5 times the second resistance of the first source / drain contact.

6. The integrated circuit according to claim 1, wherein, Each of the plurality of finfet units is configured to include one to five or more first metal layer orbitals.

7. The integrated circuit according to claim 1, wherein, The analog circuit unit structure includes a threshold voltage based on the digital circuit design rules.

8. The integrated circuit according to claim 1, further comprising: The fin mesh structure corresponds to the analog circuit design rules, wherein the fins of the plurality of finfet units are located between the grid lines of the fin mesh structure.

9. The integrated circuit according to claim 1, wherein, The second short metal orbital is a first metal layer orbital, and the first short metal orbital is a second metal layer orbital.

10. The integrated circuit according to claim 1, comprising: A serializer / deserializer (serdes) circuit, comprising the plurality of finfet units designed using the aforementioned digital circuit design rules.

11. A semiconductor structure, comprising: Multiple finfet units; Multiple source / drain conductors are disposed on and electrically coupled to the multiple finfet cells, and the multiple source / drain conductors include wide source / drain conductors and narrow source / drain conductors; Multiple gate conductors are disposed on and electrically coupled to the multiple finfet cells, and are interleaved with the multiple source / drain conductors; Multiple gate contacts are electrically coupled between the finfet gates and the multiple gate conductors in the multiple finfet cells; as well as Multiple source / drain contacts are electrically coupled between the FinFET source / drain regions in the multiple FinFET cells and the multiple source / drain conductors, wherein the multiple source / drain contacts include first source / drain contacts and second source / drain contacts, each of the first source / drain contacts having a first width and being electrically coupled to at least one of the wide source / drain conductors, and each of the second source / drain contacts having a second width and being electrically coupled to at least one of the narrow source / drain conductors, wherein the first width is greater than the second width.

12. The semiconductor structure according to claim 11, wherein, The first resistance of each of the first source / drain contacts is less than or equal to 0.5 times the second resistance of each of the second source / drain contacts.

13. The semiconductor structure according to claim 11, wherein, The plurality of finfet units are arranged to form multiple rows of NMOS finfets and multiple rows of PMOS finfets according to a first mode in the analog circuit unit structure and a second mode in the digital circuit unit structure, wherein the first mode is the same as the second mode.

14. The semiconductor structure according to claim 11, wherein, The plurality of finfet units are arranged to form multiple rows of NMOS finfets and multiple rows of PMOS finfets according to a first mode in the analog circuit unit structure and a second mode in the digital circuit unit structure, wherein the first mode is different from the second mode.

15. The semiconductor structure according to claim 11, comprising: An analog circuit unit structure, which includes a first finfet unit among the plurality of finfet units; And a digital circuit unit structure, which includes a second finfet unit among the plurality of finfet units, wherein the analog circuit unit structure is directly adjacent to the digital circuit unit structure.

16. A method for manufacturing a semiconductor device, comprising: Provides a plurality of finfet units based on digital fin boundaries, wherein each of the plurality of finfet units includes a fin with a non-uniform fin spacing; and A mid-process layer is provided in at least one of the plurality of FinFET cells, wherein providing the mid-process layer includes: Provide a first source / drain contact having a first width; and A second source / drain contact is provided, wherein the second width is wider than the first width.

17. The method of claim 16, comprising: Cut a first metal layer line in at least one of the plurality of finfet cells in at least one analog circuit structure to provide a short first metal layer line.

18. The method of claim 16, comprising: Based on at least one of the plurality of finfet cells having a reduced cell height, a short metal wire is provided in at least one of the plurality of finfet cells.

19. The method of claim 16, wherein, Each of the plurality of finfet units is provided with five or more first metal layer orbitals.

20. The method of claim 16, comprising: Provide a simulation unit that includes the first FinFET unit among the plurality of FinFET units; Provides a digital unit comprising a second FinFET unit among the plurality of FinFET units; and The analog unit is directly adjacent to the digital unit.

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