Bonding pad including interfacial electromigration barrier layer and method of manufacturing the same

Abstract

The present invention provides a semiconductor die including a first pad-level dielectric layer embedded in a first bonding pad and located above a first substrate. Each of the first bonding pads is located in a corresponding pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes: a first metal liner, the first metal liner containing a first metal liner material and contacting a sidewall of the corresponding pad cavity; a first metal fill material portion, the first metal fill material portion embedded in the first metal liner; and a metal electromigration barrier layer, the metal electromigration barrier layer contacting the first metal fill material portion and adjacent to the first metal liner.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent application serial number 16 / 742,213, filed on January 14, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to a semiconductor structure and a method of manufacturing the same, the semiconductor structure including a semiconductor die having a bonding pad having an interfacial electromigration barrier layer. Background Art

[0004] Three-dimensional vertical NAND strings with one bit per cell are disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to aspects of the present disclosure, there is provided a structure including a first semiconductor die. The first semiconductor die includes: a first pad-level dielectric layer embedded in a first bonding pad and located above a first substrate, wherein each of the first bonding pads is located within a corresponding pad cavity in the first pad-level dielectric layer and includes: a first metal liner including a first metal liner material and contacting a sidewall of the corresponding pad cavity; a first metal fill material portion embedded in the first metal liner; and a metal electromigration barrier layer contacting the first metal fill material portion and adjacent to the first metal liner.

[0006] According to another aspect of the present disclosure, a method for forming a structure is provided. The method includes: forming a first pad-level dielectric layer over a first substrate; forming a pad cavity in the first pad-level dielectric layer; forming a first process bonding pad in each pad cavity in the first pad-level dielectric layer, the first process bonding pad including a first metal liner and a first metal filling material portion; vertically recessing each of the first metal filling material portions; and forming a metal electromigration barrier layer on the vertically recessed surface of each of the first metal filling material portions, wherein a first metal liner including a corresponding first metal liner, a corresponding first metal filling material portion, and a corresponding metal electromigration barrier layer is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a schematic vertical cross-sectional view of a first semiconductor die after forming a first via-level dielectric layer and a via cavity according to an embodiment of the present disclosure.

[0008] Figure 1B is a schematic vertical cross-sectional view of a first semiconductor die after forming a first conductive via structure according to an embodiment of the present disclosure.

[0009] Figure 1C is a schematic vertical cross-sectional view of a first semiconductor die after forming a first pad level dielectric layer and a first opening therethrough according to an embodiment of the present disclosure.

[0010] Figure 1D is a schematic vertical cross-sectional view of a first semiconductor die after forming a first continuous metal liner according to an embodiment of the present disclosure.

[0011] Figure 1E is a schematic vertical cross-sectional view of a first semiconductor die after forming a first continuous layer of metal fill material according to an embodiment of the present disclosure.

[0012] Figure 1F is a schematic vertical cross-sectional view of a first semiconductor die after forming a bonding pad in a first process according to an embodiment of the present disclosure.

[0013] Figure 1G is a schematic vertical cross-sectional view of a first semiconductor die after vertically recessing a first metal fill material portion according to an embodiment of the present disclosure.

[0014] Figure 1H is a schematic vertical cross-sectional view of a first semiconductor die after forming a first continuous metal electromigration barrier layer according to an embodiment of the present disclosure.

[0015] Fig. 1Iis a schematic vertical cross-sectional view of a first semiconductor die after forming a first bonding pad according to an embodiment of the present disclosure.

[0016] Figure 2A is a schematic vertical cross-sectional view of a second semiconductor die after forming a second via-level dielectric layer and a second conductive via structure according to an embodiment of the present disclosure.

[0017] Figure 2B is a schematic vertical cross-sectional view of a second semiconductor die after forming a second pad level dielectric layer and a second opening therethrough according to an embodiment of the present disclosure.

[0018] Figure 2C is a schematic vertical cross-sectional view of a second semiconductor die after forming a second continuous metal liner according to an embodiment of the present disclosure.

[0019] Figure 2D is a schematic vertical cross-sectional view of a second semiconductor die after forming a second continuous layer of metal fill material according to an embodiment of the present disclosure.

[0020] Figure 2E is a schematic vertical cross-sectional view of a second semiconductor die after forming a second bonding pad according to an embodiment of the present disclosure.

[0021] Figure 3 yes Fig. 1I Another schematic vertical cross-sectional view of a first semiconductor die at a processing step of FIG.

[0022] Figure 4 yes Figure 2E Another schematic vertical cross-sectional view of a second semiconductor die at a processing step of .

[0023] Figure 5 is a vertical cross-sectional view of an exemplary structure including a first semiconductor die and a second semiconductor die after the second semiconductor die is aligned to bond with the first semiconductor die according to an embodiment of the present disclosure.

[0024] Fig. 6A is a vertical cross-sectional view of an exemplary structure after bonding a second semiconductor die to a first semiconductor die according to an embodiment of the present disclosure.

[0025] Figure 6B yes Fig. 6A Another view of an exemplary structure of FIG. 1 , with the bonding pads enlarged for clarity. DETAILED DESCRIPTION

[0026] Bond pads comprising copper tend to be recessed in the region near the metal diffusion barrier layer, which can accelerate copper electromigration-induced void formation. Embodiments of the present disclosure are directed to a semiconductor die having a bond pad with a corresponding interfacial electromigration barrier layer and methods of making the same, various aspects of which are described below. The electromigration barrier layer reduces or eliminates copper electromigration-induced void formation.

[0027] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0028] The same reference numerals represent the same elements or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element.

[0029] As used herein, a first element is "electrically connected to" a second element if there is an electrically conductive path comprised of at least one electrically conductive material between the first element and the second element. As used herein, a "prototype" structure or an "in-process" structure

[0030] Refers to a transient structure in which the shape or composition of at least one of its components is subsequently modified.

[0031] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a first continuous structure. For example, a layer may be between the top and bottom surfaces of a first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0032] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolith" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory levels before bonding, but since the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. Various three-dimensional memory devices disclosed herein include monolithic three-dimensional NAND string memory devices and may be manufactured using various embodiments described herein.

[0033] Typically, a semiconductor package may include a memory chip containing one or more semiconductor dies. Thus, each semiconductor package contains one or more dies (e.g., one, two, or four dies). After the substrate is cut into individual dies, multiple dies may be formed on the same substrate. A memory die is the smallest unit that can independently execute a command or report a status. Each memory die contains one or more planes (typically one or two planes). Although there are some limitations, the same concurrent operations can occur on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased by a single erase operation. Each block contains multiple pages, which are the smallest units that can be programmed.

[0034] refer to Figure 1A , shows a first semiconductor die 800 according to an embodiment of the present disclosure. The first semiconductor die 800 includes a first substrate 808 and a first device structure 840 formed above the first substrate 808. The first device structure 840 includes at least one first semiconductor device, such as a field effect transistor, a three-dimensional array of memory elements, or any other semiconductor device known in the art. The first device structure 840 may include at least one dielectric material layer in its upper portion, and may include a plurality of electrically active nodes therein. The electrically active nodes of the first device structure 840 may or may not be arranged in a periodic pattern. In one embodiment, the first device structure 840 may include a control circuit for controlling a memory array disposed in a second semiconductor die, which may be bonded to the first semiconductor die 800. The first device structure 840 may have a flat top surface parallel to the top surface of the first substrate 808.

[0035] A first etch stop dielectric layer 850 may optionally be formed over the top surface of the first device structure 840. The first etch stop dielectric layer 850 includes an etch stop dielectric material having a higher etch resistivity than a dielectric material subsequently deposited over the first etch stop dielectric layer 850. For example, the first etch stop dielectric layer 850 includes silicon nitride or a dielectric metal oxide such as aluminum oxide. The thickness of the first etch stop dielectric layer 850 may be in the range of 5 nm to 30 nm, although lesser and greater thicknesses may also be used.

[0036] A first via-level dielectric layer 872 may be deposited over the top surface of the first etch stop dielectric layer 850. The first via-level dielectric layer 872 includes a dielectric material such as undoped silicate glass (i.e., silicon oxide), doped silicate glass, or organosilicate glass. The thickness of the first via-level dielectric layer 872 may be in the range of 100 nm to 600 nm, although lesser and greater thicknesses may also be employed.

[0037] A first via cavity 81 may be formed through the first via-level dielectric layer 872. For example, a photoresist layer may be applied over the top surface of the first via-level dielectric layer 872 and may be photolithographically patterned to form discrete openings overlying electrically active nodes within the first device structure 840. An anisotropic etching process may be performed to form the first via cavity 81 below the discrete openings in the patterned photoresist layer. The photoresist layer may be removed, for example, by ashing.

[0038] refer to Figure 1B , at least one conductive material may then be deposited in the first via cavity 81. For example, a first continuous via-level metal liner including a metal nitride material such as TiN, TaN, or WN may be deposited by a conformal deposition process such as a chemical vapor deposition process. The thickness of the first continuous via-level metal liner may be in the range of 3 nm to 30 nm, although lesser and greater thicknesses may also be employed. The first continuous via-level metal seed layer may be optionally deposited by a non-conformal deposition process such as a physical vapor deposition process. The first continuous via-level metal seed layer includes at least one metal filler material such as Cu, Mo, Ru, Co, Al, another elemental metal, or an intermetallic alloy. The thickness of the first continuous via-level metal seed layer on a vertical or tapered surface may be in the range of 3 nm to 30 nm, although lesser and greater thicknesses may also be employed. The first continuous via-level metal fill layer may be deposited by a conformal deposition process such as a chemical vapor deposition process or an ultra-conformal deposition process such as electroplating or electroless plating to fill the remaining volume of the first via cavity 81. The first continuous via level metal fill layer may include Cu, CoW, CoWP, Mo, Ru, Co, Al, another elemental metal, or an intermetallic alloy. The material of the first continuous via level metal fill layer may be the same as or different from the material of the first continuous via level metal seed layer.

[0039] Excess portions of at least one conductive material may be removed from above a horizontal plane including the top surface of the first via-level dielectric layer 872 by a planarization process. The planarization process may include a recess etching process and / or a chemical mechanical planarization process. Each remaining portion of the at least one conductive material includes a conductive via structure, which is referred to herein as a first conductive via structure 82. The first conductive via structure 82 may include a via-level metal liner 82A and a via-level metal filling material portion 82B. The via-level metal liner 82A is the remaining patterned portion of the first continuous via-level metal liner. The via-level metal filling material portion 82B is a combination of the remaining patterned portion of the first continuous via-level metal seed layer and the remaining patterned portion of the first continuous via-level metal filling layer. Therefore, each first conductive via structure 82 includes a combination of a via-level metal liner 82A and a via-level metal filling material portion 82B.

[0040] refer to Figure 1C , a first pad-level dielectric layer 874 may be deposited over the first via-level dielectric layer 872. The first pad-level dielectric layer 874 includes a dielectric material such as undoped silicate glass (e.g., silicon oxide) or doped silicate glass. The first pad-level dielectric layer 874 may be deposited by a conformal or non-conformal deposition process. For example, the first pad-level dielectric layer 874 may be formed by a plasma enhanced chemical vapor deposition process. The thickness of the first pad-level dielectric layer 874 may be in the range of 100 nm to 600 nm, although lesser and greater thicknesses may also be employed.

[0041] A photoresist layer (not shown) may be applied over the top surface of the first pad-level dielectric layer 874 and may be photolithographically patterned to form a pad-shaped opening overlying a corresponding one of the first conductive via structures 82. The patterned photoresist layer may be used as an etch mask layer to perform an anisotropic etching process. The pattern in the photoresist layer may be transferred through the first pad-level dielectric layer 874 by the anisotropic etching process to form the first pad cavity 83. The first via-level dielectric layer 872 may be used as an etch stop layer for the anisotropic etching process. The top surface of at least one first conductive via structure 82 may be physically exposed at the bottom of each first pad cavity 83. The maximum lateral dimension of each pad cavity 83 may be in the range of 2 microns to 100 microns, such as 4 microns to 50 microns, but smaller and larger lateral dimensions may also be used. Each first pad cavity 83 may have a horizontal cross-sectional shape that is a polygon (such as a rectangle), a rounded polygon, a circle, an ellipse, or any other curved two-dimensional shape with a closed perimeter.

[0042] The sidewalls of the first pad cavity 83 may include the surface of the material of the first pad-level dielectric layer 874. The sidewalls of the first pad cavity 83 may be vertical, or may have a taper angle of less than 20 degrees relative to the vertical direction. For example, the taper angle may be in the range of 0.1 degrees to 5 degrees. The top surface of the first via-level dielectric layer 872 and the top surface of the first conductive via structure 82 may be physically exposed at the bottom of each first pad cavity 83.

[0043] refer to Figure 1D , a first continuous metal liner 84L including a metal nitride material (such as TiN, TaN or WN) and / or a barrier metal (such as tantalum) may be deposited by a conformal deposition process such as a chemical vapor deposition process.

[0044] The first continuous metal liner 84L may be deposited at the peripheral region of the first liner cavity 83 in the first pad level dielectric layer 874. The thickness of the first continuous metal liner 84L may be in the range of 3 nm to 30 nm, although lesser and greater thicknesses may also be employed.

[0045] refer to Figure 1E , a first continuous metal filling material layer 86L may be formed by depositing at least one metal filling material into the remaining volume of the first liner cavity 83 and over the first continuous metal liner 84L. The first continuous metal filling material layer 86L may include a stack including, from bottom to top, a first continuous metal seed layer and a first continuous metal filling layer. In one embodiment, the first continuous metal filling material layer 86L may include a first metal filling material including copper or a copper alloy.

[0046] For example, the first continuous metal seed layer may optionally be deposited by a non-conformal deposition process such as a physical vapor deposition process. The first continuous metal seed layer includes at least one metal filler material such as Cu, Mo, Ru, Co, Al, another elemental metal, or an intermetallic alloy. The thickness of the first continuous metal seed layer on the vertical or tapered surface may be in the range of 3 nm to 30 nm, although lesser and greater thicknesses may also be used. The first continuous metal seed layer may be formed directly on the first continuous metal liner 84L.

[0047] The first continuous metal fill layer may be deposited on the first continuous metal seed layer by a conformal deposition process (such as a chemical vapor deposition process) or an ultra-conformal deposition process (such as electroplating or electroless plating) to fill the remaining volume of the first liner cavity 83. In one embodiment, the first continuous metal fill layer may be formed by electroplating a copper-containing material on the first continuous metal seed layer. The first continuous metal fill layer may include Cu, CoW, CoWP, Mo, Ru, Co, Al, another elemental metal, or an intermetallic alloy. The material of the first continuous metal fill layer may be the same as or different from the material of the first continuous metal seed layer. In one embodiment, the material of the first continuous metal fill layer may be substantially composed of copper or a copper alloy, wherein the atomic percentage of copper is at least 50%, and / or at least 70%, and / or at least 90%. The composition of the material of the first continuous metal fill layer may be the same as or different from the composition of the material of the via-level metal fill material portion 82B.

[0048] refer to Figure 1F , the excess portion of the first continuous metal filling material layer 86L and the first continuous metal liner 84L can be removed from above the horizontal plane including the top surface (i.e., the horizontal distal surface) of the first pad-level dielectric layer 874 by a planarization process. The planarization process may include a chemical mechanical planarization process. Each remaining portion of the first continuous metal filling material layer 86L constitutes a first metal filling material portion 86. Each remaining portion of the first continuous metal liner 84L constitutes a first metal liner 84. Each combination of the first metal filling material portion 86 and the first metal liner 84 constitutes an in-process bonding pad, which is referred to herein as a first in-process bonding pad 88I. In other words, each first in-process bonding pad 88I may include a first metal liner 84 and a first metal filling material portion 86. In one embodiment, each first metal filling material portion 86 includes a first metal filling material including copper or a copper alloy.

[0049] Typically, a first in-process bonding pad 88I including the first metal liner 84 and the first metal fill material portion 86 may be formed within each pad cavity 83 in the first pad level dielectric layer 874 by removing portions of the first continuous metal fill material layer 86L and the first continuous metal liner 84L from above a horizontal plane including the top surface of the first pad level dielectric layer 874. The remaining continuous material portions of the first continuous metal fill material layer 86L and the first continuous metal liner 84L comprise the first in-process bonding pad 88I.

[0050] The presence of a metal liner proximate to the metal fill material and / or galvanic corrosion during the CMP process may create a peripheral recess 88G (i.e., an edge recess) at the periphery of the remaining portion of the metal fill material 86 adjacent to the first metal liner 84. For example, if a chemical mechanical planarization process is used to planarize copper filling a cavity lined with a first metal liner material (such as TiN or TaN), the remaining portion of the copper has a peripheral recess 88G adjacent to the remaining sidewalls of the first metal liner material. Thus, recesses 88G may be formed at the periphery of each first metal fill material portion 86 that remains after the planarization process. In one embodiment, one or more of the recesses 88G may have a moat configuration extending around the entire periphery of the top surface of the corresponding first metal fill material portion 86. The depth of each recess may be in the range of 2 nm to 50 nm, such as 5 nm to 20 nm, and the width of each recess may be in the range of 1 nm to 50 nm, such as 5 nm to 20 nm, but smaller and larger depths and / or widths may be formed depending on the process characteristics of the chemical mechanical planarization process.

[0051] refer to Figure 1G , the first metal filling material portion 86 may be vertically recessed so that the top surface of the first metal filling material portion 86 is located below the horizontal plane including the top surface of the first pad-level dielectric layer 874. In the case where the first metal filling material portion 86 includes copper or a copper alloy and / or is substantially composed of copper or a copper alloy, the first metal filling material portion 86 may be isotropically etched by a wet etching process using nitric acid, a saturated ferric chloride solution including FeCl3 ions, and / or a mixture of NH4OH and H2O2. A suitable dilution may be used to provide a controlled etching rate. According to one aspect of the present disclosure, the vertical recessed distance of the vertically recessed surface of the first metal filling material portion 86 relative to the horizontal plane including the top surface of the first pad-level dielectric layer 874 may be greater than the thickness of the subsequently deposited first continuous metal electromigration barrier layer. In one embodiment, the dilution of the etchant and the duration of the etching process may be selected so that the vertical recessed distance of the top surface of the first metal filling material portion 86 may be in the range of 5nm to 100nm, such as 10nm to 50nm.

[0052] refer to Figure 1H, the first continuous metal electromigration barrier layer 87L may be deposited on the vertically recessed surface of the first metal filling material portion 86 and on the physically exposed surface of the first metal liner 84 and the first pad-level dielectric layer 874. The first continuous metal electromigration barrier layer 87L includes a metal electromigration barrier material, i.e., an anti-electromigration metal material, which has a greater resistivity than the first metal filling material of the first metal filling material portion 86. Metal electromigration barrier materials that can be used for the first continuous metal electromigration barrier layer 87L include, but are not limited to, TaN, TiN, WN, Ta, Ti, W, Ru, or alloys thereof. In one embodiment, the first continuous metal electromigration barrier layer 87L may include TaN and / or may be substantially composed of TaN. In another embodiment, the first continuous metal electromigration barrier layer 87L may include Ru and / or may be substantially composed of Ru.

[0053] The thickness of the first continuous metal electromigration barrier layer 87L may be in the range of 3 nm to 30 nm, such as 5 nm to 10 nm. As discussed above, the vertically recessed distance of the vertically recessed surface of the first metal filling material portion 86 relative to the horizontal plane including the top surface of the first pad-level dielectric layer 874 is greater than the thickness of the first continuous metal electromigration barrier layer 87L. Therefore, the top surface of each portion of the first continuous metal electromigration barrier layer 87L overlying the first metal filling material portion 86 is vertically recessed below the horizontal plane including the top surface of the first pad-level dielectric layer 874. The first continuous metal electromigration barrier layer 87L conformally covers the physically exposed surface of the first metal filling material portion 86, including the surface of each groove 88G at the peripheral region of the first metal filling material portion 86. The first continuous metal electromigration barrier layer 87L may include a contour portion that protrudes downward into a corresponding one of the grooves 88G at the peripheral region of the first metal filling material portion 86.

[0054] refer to Fig. 1I , a portion of the first continuous metal electromigration barrier layer 87L may be removed from outside the first liner cavity 83 by a planarization process using chemical mechanical planarization (CMP). The topmost portion of the first pad-level dielectric layer 874 may be removed from above a horizontal plane that includes a distal horizontal surface of a horizontally extending portion of the first continuous metal electromigration barrier layer 87L that covers a vertically recessed surface of the first metal filling material portion 86. The horizontally extending portion of the first continuous metal electromigration barrier layer 87L overlying the first metal filling material portion 86 may be used as a stop surface during the planarization process. The remaining portion of the first continuous metal electromigration barrier layer 87L after the planarization process includes the metal electromigration barrier layer 87. Each continuous combination of the first metal liner 84, the first metal filling material portion 86, and the metal electromigration barrier layer 87 constitutes a first bonding pad 88.

[0055] The first semiconductor die 800 includes a first pad-level dielectric layer 874 embedded in first bonding pads 88 located above the first substrate 808. Each of the first bonding pads 88 is located within a corresponding pad cavity 83 in the first pad-level dielectric layer 874. Each of the first bonding pads 88 includes: a first metal liner 84, which includes a first metal liner material and contacts the sidewalls of the corresponding pad cavity 83; a first metal filling material portion 86, which is embedded in the first metal liner 84; and a metal electromigration barrier layer 87, which contacts the first metal filling material portion 86 and is adjacent to the first metal liner 84. In one embodiment, the combination of the metal electromigration barrier layer 87 and the first metal liner 84 encapsulates the first metal filling material portion 86. In other words, the entire first metal filling material portion 86 can be located within a volume defined by the combined surface of the metal electromigration barrier layer 87 and the first metal liner 84, so that the combined surface does not include any holes therethrough. In one embodiment, the distal surface of the first pad level dielectric layer 874 (ie, the surface away from the first substrate 808 ) is located in the same horizontal plane as the distal surface of the metal electromigration barrier layer 87 , which is the planarization horizontal plane of the planarization process.

[0056] In one embodiment, the first metal liner 84 includes an inner sidewall. A distal region of the inner sidewall contacts the metal electromigration barrier layer 87 at a first interface, and a proximal region of the inner sidewall contacts the first metal fill material portion 86 at a second interface located in the same two-dimensional plane P as the first interface. In one embodiment, the second interface is vertically offset from a horizontal plane including a distal horizontal surface of the metal electromigration barrier layer 87 by a vertical spacing that is greater than the thickness of the metal electromigration barrier layer 87.

[0057] In one embodiment, the contact area between the first metal liner 84 and the metal electromigration barrier layer 87 has an upper edge located in a horizontal plane including the distal surface of the first pad-level dielectric layer 874. In one embodiment, the peripheral area of ​​the first metal filling material portion 86 below the groove 88G is vertically recessed from the horizontal plane including the distal surface of the first pad-level dielectric layer 874 by a vertical recess distance that is greater than the thickness of the metal electromigration barrier layer 87. In one embodiment, the vertical recess distance is in the range of 7nm to 50nm, such as 15nm to 30nm, but smaller and larger vertical recess distances may also be used. The entire recessed peripheral portion of each first metal filling material portion 86 may be covered by the downwardly protruding peripheral portion of the metal electromigration barrier layer 87.

[0058] In one embodiment, the first metal fill material portion 86 includes a first metal fill material including copper or a copper alloy, and the metal electromigration barrier layer 87 includes a conductive metal electromigration barrier material used as a copper diffusion barrier. In one embodiment, the metal electromigration barrier material includes at least one material selected from TaN, TiN, WN, Ta, Ti, W, Ru, or alloys thereof. In one embodiment, the metal electromigration barrier layer 87 is laterally spaced apart from the first pad-level dielectric layer 874 by the first metal liner 84.

[0059] refer to Figure 2A , showing a second semiconductor die 900 according to an embodiment of the present disclosure. The second semiconductor die 900 includes a second substrate 908 and a second device structure 940 formed above the second substrate 908. The second device structure 940 includes at least one second semiconductor device, such as a field effect transistor, a three-dimensional array of memory elements, or any other semiconductor device known in the art. The second device structure 940 may include at least one dielectric material layer in its upper portion, and may include a plurality of electrically active nodes therein. The electrically active nodes of the second device structure 940 may or may not be arranged in a periodic pattern. In one embodiment, the second device structure 940 may include a three-dimensional memory device, such as a three-dimensional array of memory elements, wherein the memory elements are stacked vertically. In such cases, the electrically active nodes within the second device structure 940 may include a drain region connected to the top of a corresponding vertical semiconductor channel in a corresponding memory stacking structure. The second device structure 940 may have a flat top surface parallel to the top surface of the second substrate 908.

[0060] A second etch stop dielectric layer 950 may optionally be formed over the top surface of the second device structure 940. The second etch stop dielectric layer 950 includes an etch stop dielectric material having a higher etch resistivity than a dielectric material subsequently deposited over the second etch stop dielectric layer 950. For example, the second etch stop dielectric layer 950 includes silicon nitride or a dielectric metal oxide such as aluminum oxide. The thickness of the second etch stop dielectric layer 950 may be in the range of 5 nm to 30 nm, although lesser and greater thicknesses may also be used.

[0061] A second via-level dielectric layer 972 may be deposited over the top surface of the second etch stop dielectric layer 950. The second via-level dielectric layer 972 includes a dielectric material such as undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the second via-level dielectric layer 972 may be in the range of 200 nm to 600 nm, although lesser and greater thicknesses may also be employed.

[0062] A second via cavity may be formed through the second via-level dielectric layer 972. For example, a photoresist layer may be applied over the top surface of the second via-level dielectric layer 972 and may be photolithographically patterned to form discrete openings overlying electrically active nodes within the second device structure 940. An anisotropic etching process may be performed to form the second via cavity below the discrete openings in the patterned photoresist layer. The photoresist layer may be removed, for example, by ashing.

[0063] At least one conductive material may then be deposited in the second via cavity. For example, a second continuous via-level metal liner including a metal nitride material such as TiN, TaN or WN may be deposited by a conformal deposition process such as a chemical vapor deposition process. The thickness of the second continuous via-level metal liner may be in the range of 3 nm to 30 nm, but lesser and greater thicknesses may also be used. The second continuous via-level metal seed layer may optionally be deposited by a non-conformal deposition process such as a physical vapor deposition process. The second continuous via-level metal seed layer includes at least one metal filler material such as Cu, Mo, Ru, Co, Al, another elemental metal or an intermetallic alloy, and the thickness of the second continuous via-level metal seed layer on a vertical or tapered surface may be in the range of 3 nm to 30 nm, but lesser and greater thicknesses may also be used. The second continuous via-level metal fill layer may be deposited by a conformal deposition process such as a chemical vapor deposition process or an ultra-conformal deposition process such as electroplating or chemical plating to fill the remaining volume of the second via cavity. The second continuous via level metal fill layer may include Cu, CoW, CoWP, Mo, Ru, Co, Al, another elemental metal, or an intermetallic alloy. The material of the second continuous via level metal fill layer may be the same as or different from the material of the second continuous via level metal seed layer.

[0064] Excess portions of at least one conductive material may be removed from above a horizontal plane including the top surface of the second via-level dielectric layer 972 by a planarization process. The planarization process may include a recess etching process and / or a chemical mechanical planarization process. Each remaining portion of the at least one conductive material comprises a conductive via structure, which is referred to herein as a second conductive via structure 92. The second conductive via structure 92 may include a via-level metal liner 92A and a via-level metal filling material portion 92B. The via-level metal liner 92A is the remaining patterned portion of the second continuous via-level metal liner. The via-level metal filling material portion 92B is a combination of the remaining patterned portion of the second continuous via-level metal seed layer and the remaining patterned portion of the second continuous via-level metal filling layer. Therefore, each second conductive via structure 92 includes a combination of a via-level metal liner 92A and a via-level metal filling material portion 92B.

[0065] refer to Figure 2B, a second pad-level dielectric layer 974 may be deposited over the second via-level dielectric layer 972. The second pad-level dielectric layer 974 includes a dielectric material, such as undoped silicate glass or doped silicate glass. The second pad-level dielectric layer 974 may be deposited by a conformal or non-conformal deposition process. For example, the second pad-level dielectric layer 974 may be formed by a plasma enhanced chemical vapor deposition process. The thickness of the second pad-level dielectric layer 974 may be in the range of 200 nm to 600 nm, although lesser and greater thicknesses may also be employed.

[0066] A photoresist layer (not shown) may be applied over the top surface of the second pad-level dielectric layer 974 and may be photolithographically patterned to form a pad-shaped opening overlying a corresponding one of the second conductive via structures 92. The patterned photoresist layer may be used as an etch mask layer to perform an anisotropic etching process. The pattern in the photoresist layer may be transferred through the second pad-level dielectric layer 974 by the anisotropic etching process to form the second pad cavity 93. The second via-level dielectric layer 972 may be used as an etch stop layer for the anisotropic etching process. The top surface of at least one second conductive via structure 92 may be physically exposed at the bottom of each second pad cavity 93. The maximum lateral dimension of each second pad cavity 93 may be in the range of 2 microns to 200 microns, such as 4 microns to 50 microns, although smaller and larger lateral dimensions may also be used.

[0067] Each second pad cavity 93 may have a horizontal cross-sectional shape that is a polygon (such as a rectangle), a rounded polygon, a circle, an ellipse, or any other curved two-dimensional shape with a closed perimeter. In one embodiment, the lateral dimensions of the second pad cavity 93 may be different from the lateral dimensions of the first pad cavity 83, and therefore different from the lateral dimensions of the first bonding pad 88. In one embodiment, the pattern of the second pad cavity 93 may be formed to include all areas in the mirror image pattern of the first bonding pad 88. Alternatively, the pattern of the second pad cavity 93 may be entirely located within the area of ​​the mirror image pattern of the first bonding pad 88.

[0068] The sidewalls of the second pad cavity 93 may include the surface of the material of the second pad-level dielectric layer 974. The sidewalls of the second pad cavity 93 may be vertical, or may have a taper angle of less than 20 degrees relative to the vertical direction. For example, the taper angle may be in the range of 0.1 degrees to 5 degrees. The top surface of the second via-level dielectric layer 972 and the top surface of the second conductive via structure 92 may be physically exposed at the bottom of each second pad cavity 93.

[0069] refer to Figure 2C A second continuous metal liner 94L including a metal nitride material such as TiN, TaN or WN or a barrier metal such as tantalum may be deposited by a conformal deposition process such as a chemical vapor deposition process.

[0070] The second continuous metal liner 94L may be deposited at the peripheral region of the second liner cavity 93 in the second pad level dielectric layer 974. The thickness of the second continuous metal liner 94L may be in the range of 3 nm to 30 nm, although lesser and greater thicknesses may also be employed.

[0071] refer to Figure 2D , a second continuous metal filling material layer 96L may be formed by depositing at least one metal filling material into the remaining volume of the second liner cavity 93 and over the second continuous metal liner 94L. The second continuous metal filling material layer 96L may include a stack including, from bottom to top, an optional second continuous metal seed layer and a second continuous metal filling layer. In one embodiment, the second continuous metal filling material layer 96L may include a second metal filling material including copper or a copper alloy.

[0072] For example, the second continuous metal seed layer may optionally be deposited by a non-conformal deposition process such as a physical vapor deposition process. The second continuous metal seed layer includes at least one metal filler material such as Cu, Mo, Ru, Co, Al, another elemental metal, or an intermetallic alloy. The thickness of the second continuous metal seed layer on the vertical or tapered surface may be in the range of 3 nm to 30 nm, although lesser and greater thicknesses may also be used. The second continuous metal seed layer may be formed directly on the second continuous metal liner 94L.

[0073] The second continuous metal fill layer may be deposited on the second continuous metal seed layer by a conformal deposition process (such as a chemical vapor deposition process) or an ultra-conformal deposition process (such as electroplating or chemical plating) to fill the remaining volume of the second liner cavity 93. In one embodiment, the second continuous metal fill layer may be formed by electroplating a copper-containing material on the second continuous metal seed layer. The second continuous metal fill layer may include Cu, CoW, CoWP, Mo, Ru, Co, Al, another elemental metal, or an intermetallic alloy. The material of the second continuous metal fill layer may be the same as or different from the material of the second continuous metal seed layer. In one embodiment, the material of the second continuous metal fill layer may be substantially composed of copper or a copper alloy, wherein the atomic percentage of copper is at least 50%, and / or at least 70%, and / or at least 90%. The composition of the material of the second continuous metal fill layer may be the same as or different from the composition of the material of the via-level metal fill material portion 92B.

[0074] refer to Figure 2E, excess portions of the second continuous metal filling material layer 96L and the second continuous metal liner 94L may be removed from above a horizontal plane including a top surface (i.e., a horizontal distal surface) of the second pad-level dielectric layer 974 by a planarization process. The planarization process may include a chemical mechanical planarization process. Each remaining portion of the second continuous metal filling material layer 96L constitutes a second metal filling material portion 96. Each remaining portion of the second continuous metal liner 94L constitutes a second metal liner 94. Each continuous combination of the second metal liner 94 and the second metal filling material portion 96 constitutes a second bonding pad 98. Each second bonding pad 98 may include a second metal liner 94 and a second metal filling material portion 96.

[0075] In one embodiment, each second metallic fill material portion 96 includes a second metallic fill material comprising copper or a copper alloy.

[0076] Typically, a second bonding pad 98 including the second metal liner 94 and the second metal filling material portion 96 can be formed within each pad cavity 93 in the second pad-level dielectric layer 974 by removing a portion of the second continuous metal filling material layer 96L and the second continuous metal liner 94L from above a horizontal plane including the top surface of the second pad-level dielectric layer 974. The remaining continuous material portion of the second continuous metal filling material layer 96L and the second continuous metal liner 94L comprises the second bonding pad 98.

[0077] As discussed above, the presence of a metal liner proximate to the metal fill material and / or galvanic corrosion during the CMP process may create peripheral recesses 98G (i.e., edge recesses) at the periphery of the remaining portion of the second metal fill material 96 adjacent to the second metal liner 94. In one embodiment, one or more of the recesses 98G may have a moat configuration extending around the entire periphery of the top surface of the corresponding second metal fill material portion 96. The depth of each recess may be in the range of 2 nm to 50 nm, such as 5 nm to 20 nm, and the width of each recess may be in the range of 2 nm to 50 nm, such as 5 nm to 20 nm, although smaller and larger depths and / or widths may be formed depending on the process characteristics of the chemical mechanical planarization process.

[0078] The second semiconductor die 900 includes a second pad-level dielectric layer 974 embedded in the second bonding pads 98 and located above the second substrate 908. Each of the second bonding pads 98 is located in a corresponding pad cavity 93 in the second pad-level dielectric layer 974. Each of the second bonding pads 98 includes a second metal liner 94 and a second metal filling material portion 96 embedded in the second metal liner 94, the second metal liner including a second metal liner material and contacting a sidewall of the corresponding pad cavity 93. In one embodiment, a distal surface of the second pad-level dielectric layer 974 (i.e., a surface away from the second substrate 908) is located in the same horizontal plane as a distal surface of the second metal filling material portion 96, which is a planarization horizontal plane of a planarization process, and in one embodiment, the second metal filling material portion 96 includes a second metal filling material including copper or a copper alloy.

[0079] refer to Figure 3 ,exist Fig. 1I Another schematic vertical cross-sectional view of the first semiconductor die 800 is shown at the processing step of FIG. . Exemplary components of the first device structure 840 are shown. For example, the first device structure 840 may include logic circuitry for controlling a three-dimensional memory device disposed in the second semiconductor die 900. The logic circuitry may include a field effect transistor 820 in a CMOS configuration and a first metal interconnect structure 870 embedded in the first dielectric material layer 860. The first metal interconnect structure 870 provides interconnections between various nodes of the field effect transistor 820 and between the field effect transistor 820 and the first bonding pad 88.

[0080] refer to Figure 4 ,exist Figure 2EAnother schematic vertical cross-sectional view of the second semiconductor die 900 is shown at the processing step of . Exemplary components of the second device structure 940 are shown. For example, the second device structure 940 may include a three-dimensional memory device, such as a three-dimensional NAND memory device. An optional planar dielectric spacer layer 910 and / or an optional semiconductor material layer 10 may be formed above the second substrate 908. A three-dimensional memory array 920 may be formed above the semiconductor material layer 10. The three-dimensional memory array 920 may include a vertical alternating stack of insulating layers 32 and conductive layers (e.g., word lines / control gate electrodes) 46, and a memory opening extending vertically through the vertical alternating stack (32, 46). A memory opening filling structure 58 may be formed within each memory opening. Each memory opening filling structure 58 may include a corresponding memory stacking structure, which may include a vertical semiconductor channel and a vertical stack of memory elements. The vertical stack of memory elements may include a portion of a continuous charge storage layer at the level of the conductive layer 46, or may include a vertical stack of floating gate structures or discrete charge storage material regions at the level of the conductive layer 46. The vertical alternating stacks (32, 46) may be patterned to form a stepped surface. The anti-step dielectric material portion 65 may be formed over the stepped surface. The contact-level dielectric layer 290 may be formed over the vertical alternating stacks (32, 46), and a contact via structure (not shown) and a bit line 978 may be subsequently formed. The bit line 978 is a subset of the second metal interconnect structure 970 embedded in the second dielectric material layer 960 or in the contact-level dielectric layer 290. The second metal interconnect structure 970 provides electrical connections between various nodes of the three-dimensional memory array 920 and the second bonding pad 98.

[0081] refer to Figure 5 , the second semiconductor die 900 may be aligned to be bonded to the first semiconductor die 800. Specifically, the first semiconductor die 800 and the second semiconductor die 900 may be positioned so that each first bonding pad 88 faces a corresponding second bonding pad 98. In one embodiment, each first bonding pad 88 may have a smaller area than a corresponding second bonding pad 98 facing the first bonding pad 88, and the first semiconductor die 800 may be positioned so that each first bonding pad 88 has a periphery that is completely located within the periphery area of ​​the corresponding second bonding pad 98 facing the first bonding pad 88. In this case, the area of ​​the first bonding pad 88 may be completely within the area of ​​the second bonding pad 98.

[0082] refer to Fig. 6A and Figure 6B, making the second semiconductor die 900 contact the first semiconductor die 800. In one embodiment, the periphery of each first bonding pad 88 in the first semiconductor die 800 may be entirely located within the periphery of the corresponding second bonding pad 98 that the first bonding pad 88 contacts. According to one aspect of an embodiment of the present disclosure, the contact surface between each pair of the first bonding pad 88 and the second bonding pad 98 may include a planar distal surface of the metal electromigration barrier layer 87, a substantially annular horizontal surface of the first metal liner 84 having a uniform width between the inner periphery and the outer periphery, and a substantially annular horizontal surface of the metal electromigration barrier layer 87 (in the presence of a recess 88G in the form of a moat trench).

[0083] The second bonding pad 98 may be bonded to the first bonding pad 88 by performing an annealing process at a high temperature while the second bonding pad 98 contacts the first bonding pad 88 .

[0084] In one embodiment, the material of the metal electromigration barrier layer 87 may be selected so that a metal-to-metal bond may be formed between the material of the metal electromigration barrier layer 87 and the second metal fill material portion 96 during the annealing process. In one embodiment, the metal electromigration barrier layer 87 may include at least one material selected from TaN, TiN, WN, Ta, Ti, W, Ru, or alloys thereof. The high temperature may be in the range of 250 degrees Celsius to 500 degrees Celsius, such as 300 degrees Celsius to 400 degrees Celsius.

[0085] The second semiconductor die 900 is bonded to the first semiconductor die 800 . The second bonding pad 98 is bonded to a corresponding one of the first bonding pads 88 .

[0086] Each of the metal electromigration barrier layers 87 contacts a corresponding one of the second bonding pads 98. The first metal filling material portion 86 is vertically spaced apart from the second bonding pads 98 by the metal electromigration barrier layers 87.

[0087] In one embodiment, each of the second bonding pads 98 includes: a second metal liner 94 including a second metal liner material, and a second metal filling material portion 96 contacting the second metal liner 94 and a corresponding one of the metal electromigration barrier layers 87. In one embodiment, the entire distal surface of the metal electromigration barrier layer 87 and the first metal liner 84 within each of the first bonding pads 88 is in contact with a horizontal surface of one of the second metal filling material portions 96. In one embodiment, the groove 88G of the peripheral recessed area overlying the second metal filling material portion 96 may be entirely located outside the contact area between the second metal filling material portion 96 and a corresponding one of the first bonding pads 88.

[0088] With reference to the accompanying drawings and in accordance with various embodiments of the present disclosure, a structure including a first semiconductor die 800 is provided, wherein the first semiconductor die 800 includes: a first pad-level dielectric layer 874, which is embedded in a first bonding pad 88 located above a first substrate 808, wherein each of the first bonding pads 88 is located in a corresponding pad cavity 83 in the first pad-level dielectric layer 874, and includes: a first metal liner 84, which includes a first metal liner material and contacts the sidewalls of the corresponding pad cavity 83; a first metal filling material portion 86, which is embedded in the first metal liner 84; and a metal electromigration barrier layer 87, which contacts the first metal filling material portion 86 and is adjacent to the first metal liner 84.

[0089] A second semiconductor die 900 including a second bonding pad 98 may be bonded to a corresponding one of the first bonding pads 88. Each of the second bonding pads 98 includes: a second metal liner 94 including a second metal liner material; and a second metal filling material portion 96, which contacts the second metal liner 94 and a corresponding one of the metal electromigration barrier layers 87. In one embodiment, the second metal liner material includes a metal nitride material such as TiN, TaN, or WN, and the second metal filling material portion includes copper or a copper alloy. In one embodiment, the entire distal surface of the metal electromigration barrier layer 87 and the first metal liner 84 within each of the first bonding pads 88 may contact a horizontal surface of one of the second metal filling material portions 96.

[0090] In one embodiment, one of the first semiconductor die 800 and the second semiconductor die 900 may include a memory die. In this case, the memory die may include a three-dimensional memory device including a three-dimensional array of memory elements. The other of the first semiconductor die 800 and the second semiconductor die 900 may include a logic die including a control circuit for controlling the operation of the memory elements within the memory die. For example, the control circuit may include a bit line control circuit, a word line control circuit, a sensing circuit, a power supply circuit, a peripheral circuit, and / or an input / output circuit. The back side of the logic die may be thinned, and a through-substrate via structure and a backside bonding pad may be formed on the logic die to provide an electrical connection to an external device.

[0091] Embodiments of the present disclosure include a metal electromigration barrier layer 87 between a first metal fill material portion 86 within a first bonding pad 88 and a second metal fill material portion 96 within a second bonding pad 98. The metal electromigration barrier layer 87 may include a material that provides a greater electromigration resistance than the material of the first metal fill material portion 86 and the second metal fill material portion 96. For example, the first metal fill material portion 86 and the second metal fill material portion 96 may include copper or a copper alloy and / or may be substantially composed of copper or a copper alloy, and the metal electromigration barrier layer 87 may include a copper diffusion barrier material such as TaN, TiN, WN, Ta, Ti, W, Ru and / or alloys and / or a material stack of two or more thereof. Therefore, the metal electromigration barrier layer 87 may reduce electromigration between the first bonding pad 88 and the second bonding pad 98.

[0092] Without wishing to be bound by a particular theory, it is believed that the electromigration stress current flowing in one direction between the contacting copper bonding pads and the electron wind flowing in the opposite direction will cause copper to diffuse (i.e. migrate) from one pad to another pad in the direction of the electron wind flow. It is believed that copper will diffuse laterally to fill the voids in the peripheral grooves 88G and / or 98G in the periphery of the bonding pad. It is believed that this copper migration will leave a void in one or two pads near the interface between the pads. In other words, the void from the peripheral groove effectively migrates toward the interface between the pads in the opposite direction to the copper migration. The void at the interface can produce an open circuit or a poor electrical connection between the pads, resulting in device failure or poor performance. It is believed that the metal electromigration barrier layer 87 acts as a copper diffusion (i.e., migration) barrier layer, which reduces or prevents copper migration between the copper pads.

[0093] This reduces or eliminates voids at the interface between pads and reduces opens and improves electrical connections between pads.Voids remaining in peripheral recesses 88G and / or 98G do not significantly affect device performance.

[0094] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments employing specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure, comprising a first semiconductor die, wherein the first semiconductor die comprises: a first pad-level dielectric layer embedded in the first bonding pads and located over the first substrate, wherein each of the first bonding pads is located within a corresponding pad cavity in the first pad-level dielectric layer and comprises: a first metal liner comprising a first metal liner material and contacting a sidewall of the corresponding liner cavity; a first metallic filler material portion embedded in the first metallic liner; and A metallic electromigration barrier layer contacts the first metal fill material portion and abuts the first metal liner, wherein a peripheral recess is located over the metallic electromigration barrier layer in a peripheral portion of each of the first bonding pads. 2 . The semiconductor structure of claim 1 , wherein a combination of the first metal liner and the metal electromigration barrier layer encapsulates the first metal fill material portion. 3 . The semiconductor structure of claim 1 , wherein a distal surface of the first pad-level dielectric layer is located in the same horizontal plane as a distal surface of the metal electromigration barrier layer.

4. The semiconductor structure of claim 1, wherein: The first metal liner includes an interior sidewall; The distal region of the inner sidewall contacts the metal electromigration barrier layer at a first interface; and A proximal region of the interior sidewall contacts the first metallic fill material portion at a second interface that is located in the same two-dimensional plane as the first interface. 5 . The semiconductor structure of claim 4 , wherein the second interface is vertically offset from a horizontal plane including a distal horizontal surface of the metal electromigration barrier layer by a vertical spacing greater than a thickness of the metal electromigration barrier layer. 6 . The semiconductor structure of claim 1 , wherein a contact region between the first metal liner and the metal electromigration barrier layer has an upper edge located within a horizontal plane including a distal surface of the first pad-level dielectric layer.

7. The semiconductor structure of claim 6, wherein a peripheral region of the first metal filling material portion is vertically recessed from the horizontal plane including the distal surface of the first pad-level dielectric layer by a vertical recessed distance, the vertical recessed distance being greater than a thickness of the metal electromigration barrier layer.

8. The semiconductor structure of claim 1, wherein: The first metal liner material comprises a metal nitride material; The first metal filler material portion comprises copper or a copper alloy; and The metal electromigration barrier layer includes at least one material selected from TaN, TiN, WN, Ta, Ti, W, Ru or alloys thereof. 9 . The semiconductor structure of claim 1 , the metal electromigration barrier layer being laterally spaced apart from the first pad-level dielectric layer by the first metal liner.

10. The semiconductor structure of claim 1, further comprising a second semiconductor die comprising a second bonding pad bonded to a corresponding one of the first bonding pads.

11. The semiconductor structure of claim 10, wherein each of the second bonding pads comprises: a second metal liner comprising a second metal liner material; and A second metal filling material portion contacts a corresponding one of the second metal liner and the metal electromigration barrier layer.

12. The semiconductor structure of claim 11, wherein: The second metal liner material includes a metal nitride material; The second metal filler material portion includes copper or a copper alloy; and The entire distal surface of the metal electromigration barrier layer and the first metal liner in each of the first bonding pads is in contact with a horizontal surface of one of the second metal filling material portions.

13. The semiconductor structure of claim 10, wherein: One of the first semiconductor die and the second semiconductor die further comprises a memory die, the memory die containing a three-dimensional memory device; and The other of the first semiconductor die and the second semiconductor die further includes a control circuit configured to control operation of the three-dimensional memory device. The semiconductor structure of claim 1 , wherein the peripheral recess is not filled with a solid phase material.

15. The semiconductor structure of claim 1, wherein: the first metallic filler material portion having a top surface including a first horizontally extending surface segment in a first horizontal plane; the metallic electromigration barrier layer having a top surface including a second horizontally extending surface segment in a second horizontal plane below the first horizontal plane; and The peripheral groove extends downwardly from the first horizontal plane above the second horizontal plane.

16. The semiconductor structure of claim 15, wherein a top surface of the metal electromigration barrier layer within each of the first bonding pads further comprises: a first vertically extending surface segment defining an outer boundary of said peripheral recess; and A second vertically extending surface segment adjoins an edge of the first horizontally extending surface segment and defines an inner boundary of the peripheral recess.

17. The semiconductor structure of claim 1, wherein each of the peripheral recesses has a moat configuration, the moat extending laterally continuously around and laterally surrounding a topmost portion of the first metal fill material portion within each of the first bonding pads.

18. The semiconductor structure of claim 10, wherein each of the second bonding pads comprises a bottom surface comprising an additional peripheral recess extending upwardly from a horizontal plane comprising a horizontally extending surface segment of the bottom surface, wherein: The additional peripheral groove is not filled with solid phase material.

19. The semiconductor structure of claim 18, wherein for at least one of the second bonding pads, an inner perimeter of the additional peripheral recess laterally surrounds and is completely outside an outer perimeter of the corresponding peripheral recess of the first bonding pad. 20 . The semiconductor structure of claim 18 , wherein an entirety of a horizontally-extending surface segment of a top surface of each of the first bonding pads contacts a horizontally-extending surface segment of a bottom surface of a corresponding one of the second bonding pads.

21. A method for forming a semiconductor structure, the method comprising: forming a first pad level dielectric layer over the first substrate; forming a pad cavity in the first pad level dielectric layer; forming a first in-process bonding pad within each pad cavity in the first pad-level dielectric layer, the first in-process bonding pad comprising a first metal liner and a first metal fill material portion; vertically recessing each of the first metal fill material portions; as well as A metal electromigration barrier layer is formed on the vertically recessed surface of the first metal filling material portion, wherein a first bonding pad including a corresponding first metal liner, a corresponding first metal filling material portion and a corresponding metal electromigration barrier layer is formed, wherein a peripheral groove is located above the metal electromigration barrier layer in the peripheral portion of each of the first bonding pads.

22. The method for forming a semiconductor structure according to claim 21, further comprising: forming a first continuous metal electromigration barrier layer on the vertically recessed surface of the first metal fill material portion; as well as A portion of the first continuous metal electromigration barrier layer is removed from outside the opening, wherein a remaining portion of the first continuous metal electromigration barrier layer includes the metal electromigration barrier layer.

23. The method of forming a semiconductor structure according to claim 22, further comprising removing a portion of the first pad-level dielectric layer from above a horizontal plane, the horizontal plane comprising a distal horizontal surface of the horizontally extending portion of the first continuous metal electromigration barrier layer, the distal horizontal surface overlying the vertically recessed surface of the first metal fill material portion, in, The vertically recessed surface of the first metal filling material portion is recessed relative to a horizontal plane including a top surface of the first pad level dielectric layer by a distance greater than a thickness of the metal electromigration barrier layer.

24. The method for forming a semiconductor structure according to claim 21, wherein the bonding pad is formed in the first process by: forming a first continuous metal liner at a peripheral region of the liner cavity in the first pad level dielectric layer; forming a first continuous metal fill material layer on the first continuous metal liner; and Portions of the first continuous metal fill material layer and the first continuous metal liner are removed from above a horizontal plane including a top surface of the first pad level dielectric layer, wherein remaining continuous material portions of the first continuous metal fill material layer and the first continuous metal liner include the first in-process bonding pad.

25. The method for forming a semiconductor structure according to claim 21, wherein: The metal electromigration barrier layer is located on the first semiconductor die; The first metal filler material portion includes a first metal filler material, the first metal filler material includes copper or a copper alloy; and The metal electromigration barrier layer includes at least one material selected from TaN, TiN, WN, Ta, Ti, W, Ru or alloys thereof.

26. The method for forming a semiconductor structure according to claim 25, further comprising: providing a second semiconductor die including a second bond pad; as well as The second bonding pad is bonded to a corresponding one of the first bonding pads, wherein each of the metal electromigration barrier layers contacts a corresponding one of the second bonding pads, and wherein the first metal fill material portion is vertically spaced apart from the second bonding pad by the metal electromigration barrier layers.

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