Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, including a target layer for forming a target pattern; forming a core layer on the substrate, the core layer extending along a first direction, and a second direction perpendicular to the first direction; forming a first mask sidewall on a sidewall of the core layer; forming a self-aligned sacrificial sidewall on a sidewall of the first mask sidewall; forming an etch-resistant layer on the substrate exposed by the core layer, the self-aligned sacrificial sidewall, and the first mask sidewall; removing the self-aligned sacrificial sidewall to form a first groove; removing the core layer so that the first mask sidewall surrounds a second groove; and etching the target layer along the first groove and the second groove using the first mask sidewall and the etch-resistant layer as masks to form the target pattern. Embodiments of the present invention are advantageous in improving the dimensional accuracy of the target pattern and the matching degree between the target pattern and the design pattern.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid growth of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] In the development of integrated circuits, as the functional density (i.e. the number of interconnect structures in each chip) gradually increases, the geometric size (i.e. the smallest component size that can be produced by process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] Currently, with the continuous shrinking of technology nodes, improving the matching degree between the patterns formed on the wafer and the design patterns has become a challenge. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which improves the dimensional accuracy of the target pattern and the matching degree between the target pattern and the design pattern.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a target layer for forming a target pattern; forming a core layer on the substrate, the core layer extending along a first direction, and a second direction perpendicular to the first direction; forming a first mask sidewall on a sidewall of the core layer; forming a self-aligned sacrificial sidewall on a sidewall of the first mask sidewall; forming an etch-resistant layer on the substrate exposed by the core layer, the self-aligned sacrificial sidewall, and the first mask sidewall; removing the self-aligned sacrificial sidewall to form a first groove; removing the core layer so that the first mask sidewall forms a second groove; and etching the target layer along the first groove and the second groove using the first mask sidewall and the etch-resistant layer as masks to form a target pattern.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure formation method provided by this embodiment of the invention, after forming the first mask sidewall, a self-aligned sacrificial sidewall is formed on the sidewall of the first mask sidewall, followed by the formation of the etch-resistant layer, and then the removal of the self-aligned sacrificial sidewall to form a first groove, and the removal of the core layer to form a second groove. Compared with the scheme of first forming a sacrificial layer to occupy the first groove, then forming trenches spaced apart from the sacrificial layer by photolithography and etching processes, and then forming sidewalls on the sidewalls of the trenches to form a second groove, in this embodiment of the invention, the self-aligned sacrificial sidewall and the core layer are used to define the shape and size of the first groove and the second groove, respectively, and the self-aligned sacrificial sidewall is formed after the formation of the core layer, and the self-aligned sacrificial sidewall is self-aligned and formed on the sidewall of the core layer. This facilitates precise control over the size and position of the self-aligned sacrificial sidewalls. Subsequently, by removing the self-aligned sacrificial sidewalls and the core layer, the first and second grooves are formed respectively. The process of forming the first and second grooves eliminates the need for photolithography, which helps avoid the problem of overlapping areas between the grooves and the sacrificial layer caused by overlay during the formation of trenches in photolithography and etching processes. This helps to prevent the size of the first groove from being affected by the overlapping area, thus ensuring the dimensional accuracy of the first groove. During the etching of the target layer along the first and second grooves to form the target pattern, the dimensional accuracy of the target pattern and the matching degree between the target pattern and the design pattern are improved. Attached Figure Description

[0009] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in one embodiment of a method for forming a semiconductor structure.

[0010] Figures 7 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0011] Figures 21 to 22 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. Detailed Implementation

[0012] As the background technology shows, with the continuous shrinking of technology nodes, improving the matching degree between the patterns formed on the wafer and the design patterns has become a challenge.

[0013] Taking interconnect trenches as an example, this paper analyzes the challenges of improving the matching degree between the pattern formed on the wafer and the design pattern, using a semiconductor structure formation method as an example. Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1 , Figure 1 (a) is a top view. Figure 1 (b) is Figure 1 (a) is a cross-sectional view along the yy secant line, providing a substrate (not shown), on which an intermetallic dielectric layer 1 is formed.

[0015] Continue to refer to Figure 1 A core layer 2 and a plurality of sacrificial layers 3 are formed on the intermetallic dielectric layer 1, and the plurality of sacrificial layers 3 are arranged at intervals.

[0016] refer to Figure 2 , Figure 2 (a) is a top view. Figure 2 (b) is Figure 2 (a) is a cross-sectional view along the yy secant line. Part of the core layer 2 between adjacent sacrificial layers 3 is removed, and a trench 4 is formed in the core layer 2 that penetrates the core layer 2. The sidewalls of the trench 4 expose the sacrificial layer 3.

[0017] refer to Figure 3 , Figure 3 (a) is a top view. Figure 3 (b) is Figure 3 (a) is a cross-sectional view along the yy secant line. A sidewall 5 is formed on the sidewall of the trench 4, so that the sidewall 5 located on the sidewall of the trench 4 forms a first groove 6.

[0018] refer to Figure 4 , Figure 4 (a) is a top view. Figure 4 (b) is Figure 4 (a) is a cross-sectional view along the yy secant line. After the sidewall 5 is formed, the sacrificial layer 3 is removed, and a plurality of second grooves 7 are formed in the core layer 2, penetrating the core layer 2. The second grooves 7 and the first grooves 6 are isolated by the sidewall 5.

[0019] refer to Figure 5 , Figure 5 (a) is a top view. Figure 5 (b) is Figure 5 (a) is a cross-sectional view along the yy secant line. Using the core layer 2 and sidewall 5 as masks, the intermetallic dielectric layer 1 at the bottom of the first groove 6 and the second groove 7 is etched to form a target pattern in the intermetallic dielectric layer 1. Specifically, the target pattern is an interconnect trench 8.

[0020] refer to Figure 6 , Figure 6 (a) is a top view. Figure 6 (b) is Figure 6 (a) is a cross-sectional view along the yy secant line, in which interconnect lines 9 are formed in interconnect trench 8.

[0021] In the above method, a sacrificial layer 3 is first formed to occupy the space of the first groove 6. Then, trenches 4 are formed at intervals with the sacrificial layer 3 through photolithography and etching processes. Subsequently, sidewalls 5 are formed on the sidewalls of the trenches 4 to form a second groove 7. During the formation of the trenches 4, when there is an overlay in the photolithography process, the trenches 4 and the sacrificial layer 3 have a partial overlap area, which affects the size of the sacrificial layer 3. After the sacrificial layer 3 is removed to form the first groove 6, the size of the first groove 6 is also affected by the overlap area, resulting in a decrease in the dimensional accuracy of the first groove 6. Correspondingly, when etching the metal interlayer dielectric layer 1 at the bottom of the first groove 6 and the second groove 7 to form the target pattern (i.e., the interconnect trench 8), the dimensional accuracy of the target pattern is reduced, and the matching degree between the target pattern and the design pattern is poor, resulting in poor dimensional accuracy of the interconnect line 9 formed in the interconnect trench 8 and poor matching degree between the pattern of the interconnect line 9 and the design pattern.

[0022] To address the aforementioned technical problems, this invention provides a method for forming a semiconductor structure. The self-aligned sacrificial sidewall and the core layer define the shape and size of a first groove and a second groove, respectively. The self-aligned sacrificial sidewall is formed after the core layer is formed, and it is self-aligned on the sidewall of the core layer. This facilitates precise control over the size and position of the self-aligned sacrificial sidewall. Subsequently, by removing the self-aligned sacrificial sidewall and the core layer, the first and second grooves are formed accordingly. The process of forming the first and second grooves eliminates the need for photolithography, which helps avoid the problem of overlapping areas between the groove and the sacrificial layer due to overlay misalignment during photolithography and etching processes. This helps prevent the size of the first groove from being affected by the overlapping area, thus ensuring the dimensional accuracy of the first groove. During the etching of the target layer along the first and second grooves to form the target pattern, the dimensional accuracy of the target pattern and the matching degree between the target pattern and the design pattern are improved.

[0023] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figures 7 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0024] refer to Figure 7 , Figure 7 (a) is a top view. Figure 7 (b) is Figure 7 (a) A cross-sectional view along the yy secant line, providing a substrate 10, including a target layer 100 for forming the target pattern.

[0025] The substrate 10 provides a platform for the process technology. The target layer 100 is a film layer to be patterned to form a target pattern. The target pattern can be a gate structure, an interconnect trench in the back-end process, a fin in a fin field-effect transistor (FinFET), a channel stack in a gate all-around-the-wall (GAA) transistor or a forksheet transistor, a hard mask (HM) layer, etc.

[0026] In this embodiment, the target layer 100 is a dielectric layer, and the target pattern is an interconnect trench. The dielectric layer is subsequently patterned to form multiple interconnect trenches, and then metal interconnects are formed within these interconnect trenches. The dielectric layer is used to achieve electrical isolation between the metal interconnects. Therefore, the dielectric layer is an intermetallic dielectric (IMD) layer. The material of the dielectric layer is a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0027] Semiconductor devices such as transistors and capacitors can be formed in the substrate 10, and functional structures such as resistive structures and conductive structures can also be formed in the substrate 10. In this embodiment, the substrate 10 also includes a substrate 110 located at the bottom of the target layer 100. As an example, the substrate 110 is a silicon substrate.

[0028] In this embodiment, the substrate 10 further includes a hard mask material layer 115 located on the target layer 100. Subsequently, the hard mask material layer 115 is patterned to form a hard mask layer, and then the target layer 100 is patterned using the hard mask layer as a mask. This improves the process stability and pattern transfer accuracy of the patterned target layer 100.

[0029] The hard mask material layer 115 is selected from materials that have etching selectivity with the target layer 100. The material of the hard mask material layer 115 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon carbonitride. As an example, the material of the hard mask material layer 115 is titanium nitride.

[0030] In specific processes, depending on actual process requirements, a stress buffer layer can be provided between the hard mask material layer 115 and the target layer 100. Furthermore, an etching stop layer can be provided between the hard mask material layer 115 and the stress buffer layer, and also on the hard mask material layer 115. The descriptions of the stress buffer layer and the etching stop layer will not be repeated in this embodiment.

[0031] Continue to refer to Figure 7 A core layer 120 is formed on the substrate 10, the core layer 120 being along a first direction (e.g., Figure 7 (a) As shown in the X direction, the direction perpendicular to the first direction is the second direction (as shown in the X direction). Figure 7 (As shown in the Y direction in (b)).

[0032] In this embodiment, both the first direction and the second direction are parallel to the surface of the substrate 10.

[0033] The core layer 120 is used to pre-occupy a spatial position for forming the second groove, and the core layer 120 is also used to provide support for forming the first mask sidewall.

[0034] The core layer 120 will be removed later. Therefore, the core layer 120 is made of a material that is easy to remove, so as to reduce the difficulty of removing the core layer 120 later.

[0035] In this embodiment, the core layer 120 is made of silicon oxide.

[0036] As an example, the steps of forming the core layer 120 include: forming a core material layer (not shown) on the substrate 10; and graphically representing the core material layer to form the core layer 120.

[0037] In other embodiments, the core layer may be formed using other processes, such as self-aligned dual patterning (SADP) or self-aligned quadruple patterning (SAQP).

[0038] It should be noted that, for ease of illustration and explanation, this embodiment only illustrates one core layer 120. However, the number of core layers 120 is not limited to this. In other embodiments, there may be multiple core layers, which are arranged at intervals along the second direction.

[0039] refer to Figure 8 , Figure 8 (a) is a top view. Figure 8 (b) is Figure 8 (a) A cross-sectional view along the yy secant line, showing that a first mask sidewall 130 is formed on the sidewall of the core layer 120.

[0040] The first mask sidewall 130 located on the sidewall of the core layer 120 is used as a mask for the subsequent patterning of the target layer 100. The first mask sidewall 130 located on the sidewall of the core layer 120 is also used to provide support for the subsequent formation of the self-aligned sacrificial sidewall. After the core layer 120 is removed to form the second groove and the self-aligned sacrificial sidewall is removed to form the first sidewall, the first mask sidewall 130 is also used to isolate the adjacent first groove and second groove.

[0041] In this embodiment, the core layer 120 and the first mask sidewall 130 located on the sidewall of the core layer 120 constitute a graphic structure layer 40. The graphic structure layer 40 extends along a first direction and includes a first end 41 and a second end 42 opposite to the first end 41 along the first direction.

[0042] The first mask sidewall 130 is made of a material that has etching selectivity with the core layer 120 and the target layer 100. The material of the first mask sidewall 130 includes one or more of titanium oxide, silicon oxide, silicon nitride, silicon carbide, silicon carbide, aluminum oxide, and amorphous silicon. As an example, the material of the first mask sidewall 130 is titanium oxide.

[0043] In this embodiment, the first mask sidewall 130 is formed using atomic layer deposition (ALD). ALD is advantageous in improving the thickness uniformity and density of the first mask sidewall 130, and also in forming a thinner first mask sidewall 130. This allows for precise control of the thickness of the first mask sidewall 130, making it easier to achieve the minimum design spacing between adjacent first and second grooves after the subsequent formation of the first and second grooves.

[0044] Atomic layer deposition (ALD) technology has good step coverage capabilities. Therefore, in this embodiment, the first mask sidewall 130 is also formed on the top surface of the core layer 120 and the substrate 10.

[0045] In this embodiment, the example is taken as retaining the first mask sidewall 130 located on the top surface of the core layer 120 and the substrate 10 before forming the self-aligned sacrificial sidewall. In the subsequent process of forming the self-aligned sacrificial sidewall, the etching process for forming the self-aligned sacrificial sidewall only needs to have an etching selectivity ratio between the self-aligned sacrificial sidewall and the first mask sidewall 130, thereby improving the controllability of the etching process for forming the self-aligned sacrificial sidewall.

[0046] In other embodiments, depending on actual process requirements, the forming method further includes: removing the first mask sidewall located on the top surface of the core layer and the substrate. Specifically, an anisotropic dry etching process is used to remove the first mask sidewall located on the top surface of the core layer and the substrate.

[0047] In this embodiment, for ease of illustration and explanation, only the first mask sidewall 130 located on the top surface of the core layer 120 is shown in the cross-sectional view.

[0048] refer to Figure 9 , Figure 9 (a) is a top view. Figure 9 (b) is Figure 9 (a) A cross-sectional view along the yy secant line, showing a self-aligned sacrificial sidewall 150 formed on the sidewall of the first mask sidewall 130.

[0049] Subsequent steps include: forming an etch-resistant layer on the substrate 10 exposed by the core layer 120, the first mask sidewall 130, and the self-aligned sacrificial sidewall 150; removing the self-aligned sacrificial sidewall 150 to form a first groove, and removing the core layer 120 to form a second groove. The self-aligned sacrificial sidewall 150 is correspondingly used to pre-occupy a spatial position for forming the second groove.

[0050] Compared to a scheme where a sacrificial layer is first formed to occupy the space for the first groove, then trenches spaced apart from the sacrificial layer are formed by photolithography and etching processes, and finally sidewalls are formed on the sidewalls of the trenches to form a second groove, in this embodiment, the self-aligned sacrificial sidewall 150 and the core layer 120 are used to define the shape and size of the first and second grooves, respectively. Furthermore, the self-aligned sacrificial sidewall 150 is formed after the core layer 120, and its self-aligned formation on the sidewall of the core layer 120 facilitates the control of its size and position. After precise control, the first and second grooves are formed respectively by removing the self-aligned sacrificial sidewall 150 and the core layer 120. The process of forming the first and second grooves eliminates the need for photolithography, which helps to avoid the problem of overlapping areas between the groove and the sacrificial layer due to overlay during the formation of the trenches by photolithography and etching processes. This helps to avoid the size of the first groove being affected by the overlapping area, thus ensuring the dimensional accuracy of the first groove and facilitating precise control of the size of the first groove.

[0051] Therefore, the self-aligned sacrificial sidewall 150 is made of a material that is easy to remove, so as to reduce the difficulty of subsequent removal of the self-aligned sacrificial sidewall 150. In addition, the self-aligned sacrificial sidewall 150 is made of a material that has etching selectivity with the first mask sidewall 130, the substrate 200 and the subsequent etch-resistant layer, so as to prevent the first mask sidewall 130, the substrate 200 and the subsequent etch-resistant layer from being damaged during the subsequent removal of the self-aligned sacrificial sidewall 150.

[0052] The material of the self-aligned sacrificial sidewall 150 includes one or more of amorphous silicon, polycrystalline silicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the self-aligned sacrificial sidewall 150 is amorphous silicon.

[0053] In this embodiment, the self-aligned sacrificial sidewall 150 being self-aligned on the sidewall of the first mask sidewall 130 means that the process of forming the self-aligned sacrificial sidewall 150 does not include the photolithography process step, but uses a process for forming a sidewall (spacer) to form the self-aligned sacrificial sidewall 150.

[0054] In this embodiment, the self-aligned sacrificial sidewall 150 covers the first mask sidewall 130 located on the top surface of the substrate 10, and also exposes the first mask sidewall 130 located on the top surface of the core layer 120.

[0055] Specifically, the step of forming the self-aligned sacrificial sidewall 150 includes: forming a sacrificial sidewall membrane (not shown) on the top surface of the core layer 120, the top surface and sidewall of the first mask sidewall 130, and the top surface of the substrate 10; removing the sacrificial sidewall membrane located on the top surface of the core layer 120, the first mask sidewall 130, and the substrate 10, and retaining the sacrificial sidewall membrane located on the sidewall of the first mask sidewall 150 for use as the self-aligned sacrificial sidewall 150.

[0056] The process for forming the sacrificial sidewall film includes one or both of atomic layer deposition (ALD) and chemical vapor deposition (CVD). In this embodiment, ALD is used to form the sacrificial sidewall film. ALD has good step coverage capability, which is beneficial to improving the coverage of the sacrificial sidewall film on the top surface of the core layer 120, the top surface and sidewalls of the first mask sidewall 130, and the top surface of the substrate 10. This correspondingly improves the thickness uniformity of the sacrificial sidewall film and results in high film quality and high density, thereby improving the film quality of the self-aligned sacrificial sidewall 150.

[0057] In this embodiment, an anisotropic etching process is used to remove the sacrificial sidewall film located on the top surface of the core layer 120, the first mask sidewall 130, and the substrate 10. The anisotropic etching process has the characteristic of anisotropic etching, meaning that the etching rate along the direction perpendicular to the surface of the substrate 10 is greater than the etching rate along the direction parallel to the surface of the substrate 10. Therefore, the sacrificial sidewall film located on the top surface of the core layer 120, the first mask sidewall 130, and the substrate 10 can be removed without a mask. Simultaneously, the sacrificial sidewall film located on the sidewall of the first mask sidewall 130 can be retained to serve as the self-aligned sacrificial sidewall 150, thereby achieving self-alignment of the self-aligned sacrificial sidewall 150 on the sidewall of the first mask sidewall 130.

[0058] Specifically, the anisotropic etching process can be anisotropic dry etching. Anisotropic dry etching has the advantages of high etching efficiency and high controllability.

[0059] In this embodiment, the sidewall of the self-aligned sacrificial sidewall 150 that is along the first direction and does not contact the first mask sidewall 130 is a preset sidewall 51.

[0060] In this embodiment, in the step of forming the self-aligned sacrificial sidewall 150, the self-aligned sacrificial sidewall 150 surrounds the sidewall of the first mask sidewall 130, that is, the self-aligned sacrificial sidewall 150 surrounds the pattern structure layer 40.

[0061] refer to Figures 10 to 11 In this embodiment, the method for forming the semiconductor structure further includes: after forming the self-aligned sacrificial sidewall 150, removing the self-aligned sacrificial sidewall 150 located on the sidewall of any one or both of the first end 41 and the second end 42, so that the self-aligned sacrificial sidewall 150 is broken at the sidewall position of the corresponding end of the patterned structure layer 40.

[0062] Remove the self-aligned sacrificial sidewall 150 located on the sidewall of either one or both of the first end 41 and the second end 42, so that the self-aligned sacrificial sidewall 150 is broken at the sidewall position of the corresponding end of the graphic structure layer 40, thereby breaking the target graphic at the corresponding position based on design requirements.

[0063] In this embodiment, the removal of the self-aligned sacrificial sidewall 150 located on the sidewalls of the first end 41 and the second end 42 is used as an example for illustration. Accordingly, after the self-aligned sacrificial sidewall 150 is subsequently removed to form a first groove and the core layer 120 is removed to form a second groove, the first grooves located on both sides of the second groove are spaced apart.

[0064] As an example, after removing the self-aligned sacrificial sidewall 150 from the sidewalls of the first end 41 and the second end 42, the ends of the self-aligned sacrificial sidewall 150 are recessed relative to the ends on the same side of the graphic structure layer 40 along the first direction. In other embodiments, after removing the self-aligned sacrificial sidewalls from the sidewalls of the first end and the second end, either or both ends of the self-aligned sacrificial sidewalls may also be flush with the ends on the same side of the graphic structure layer along the first direction, only requiring the first and second ends of the graphic structure layer to be exposed.

[0065] In other embodiments, depending on design requirements, the self-aligned sacrificial sidewalls on the sidewalls of either the first end or the second end can be removed. After removing the self-aligned sacrificial sidewalls to form the first groove and removing the core layer to form the second groove, the first groove is connected at one end of the second groove and spaced apart at the other end. This allows the first groove to extend not only along the first direction but also along the second direction. The corresponding pattern of the second groove is a two-dimensional pattern, which improves the design freedom of the target pattern. Furthermore, compared to using a photomask to achieve a two-dimensional pattern, this embodiment utilizes the superposition of process steps to design a two-dimensional pattern, which helps reduce process difficulty and increase the process window.

[0066] In some other embodiments, depending on actual process requirements, the self-aligned sacrificial sidewalls located on the sidewalls of either the first end or the second end may not be removed. This allows the subsequently formed first groove to surround the second groove, with the first groove and the second groove separated by the first mask sidewall. Correspondingly, the first groove surrounding the second groove also enables the two-dimensional design of the first groove, increasing the design freedom of the target pattern. Compared to using a photomask to create a two-dimensional pattern, this approach helps reduce process difficulty and increase the process window.

[0067] As an example, the step of removing the self-aligned sacrificial sidewall 150 from the sidewall located at either one or both of the first end 41 and the second end 42 includes:

[0068] like Figure 10 As shown, Figure 10 (a) is a top view. Figure 10 (b) is Figure 10 (a) A cross-sectional view along the yy secant line, wherein a mask layer 160 is formed on the substrate 10, and on a projection plane parallel to the substrate 10, the mask layer 160 spans the graphic structure layer 40 and the self-aligned sacrificial sidewall 150 along the second direction, and the mask layer 160 exposes the self-aligned sacrificial sidewall 150 on the sidewalls located at either one or both of the first end 41 and the second end 42.

[0069] The mask layer 160 is used as a mask for etching the self-aligned sacrificial sidewall 150.

[0070] In this embodiment, the material of the mask layer 160 includes photoresist.

[0071] In this embodiment, before forming the mask layer 160, the forming method further includes: forming a planarization layer 170 on the first mask sidewall 130 located on the top surface of the substrate 10, covering the top surface and sidewall of the self-alignment sacrificial sidewall 150 and the first mask sidewall 130 located on the top surface of the core layer 120; and forming an anti-reflection layer 180 on the planarization layer 170.

[0072] The planarization layer 140 provides a flat surface for forming the mask layer 160, thereby improving the accuracy of pattern transfer. In this embodiment, the material of the planarization layer 140 is spin-on carbon (SOC).

[0073] The process of forming the mask layer 160 includes exposure and development processes, and the anti-reflective layer 180 is used to reduce the reflection effect during exposure. In this embodiment, the material of the anti-reflective layer 180 is BARC (Bottom Anti-reflective coating).

[0074] In this embodiment, for ease of illustration and explanation, only the planarization layer 170 and the anti-reflection layer 180 are shown in the cross-sectional view.

[0075] like Figure 11 As shown, Figure 11 (a) is a top view. Figure 11 (b) is Figure 11 (a) A cross-sectional view along the yy secant line, with the mask layer 160 as a mask, showing the self-aligned sacrificial sidewall 150 being etched.

[0076] In this embodiment, an anisotropic dry etching process is used to remove the self-aligned sacrificial sidewall 150 located on the sidewalls of any one or both of the first end 41 and the second end 42. The anisotropic dry etching process has the characteristics of anisotropic etching, which is beneficial to improving the control of the etching profile of the self-aligned sacrificial sidewall 150 and also to improving the accuracy of pattern transfer.

[0077] Specifically, using the mask layer 160 as a mask, the anti-reflection layer 180, the planarization layer 170, and the self-aligned sacrificial sidewall 150 are etched sequentially.

[0078] It should be noted that, in this embodiment, after sequentially etching the antireflective layer 180, the planarization layer 170, and the self-aligned sacrificial sidewall 150 using the mask layer 160 as a mask, the formation method further includes: removing the mask layer 160, the antireflective layer 180, and the planarization layer 170 to facilitate subsequent processing steps. Specifically, a sequential ashing process and a wet resist removal process can be used to remove the mask layer 160, the antireflective layer 180, and the planarization layer 170.

[0079] refer to Figures 12 to 13 An anti-etching layer 200 is formed on the substrate 10 exposed by the core layer 120, the self-aligned sacrificial sidewall 150, and the first mask sidewall 130.

[0080] The etch-resistant layer 200 is used as a mask for the subsequent patterning target layer 100.

[0081] In this embodiment, the anti-etching layer 200 covers the first mask sidewall 130 located on the top surface of the substrate 10, and also exposes the first mask sidewall 130 located on the top surface of the core layer 120.

[0082] Specifically, the anti-etching layer 200 covers the top surface of the first mask sidewall 130 located on the top surface of the substrate 10, and covers the sidewall of the self-alignment sacrificial sidewall 150 and the sidewall of the first mask sidewall 130.

[0083] The anti-etching layer 200 is made of a material that has etching selectivity with the core layer 120 and the self-aligned sacrificial sidewall 150, so as to ensure that the anti-etching layer 200 can be used as an etching mask for the patterning target layer 100.

[0084] In this embodiment, the etch-resistant layer 200 is made of the same material as the self-aligned sacrificial sidewall 150, and the etch-resistant layer 200 contains doped ions, which are suitable for increasing the etch selectivity between the etch-resistant layer 200 and the self-aligned sacrificial sidewall 150.

[0085] The etch-resistant layer 200 is made of the same material as the self-aligned sacrificial sidewall 150, which is beneficial to improving process compatibility. Moreover, the etch-resistant layer 200 contains doped ions to increase the etching selectivity between the etch-resistant layer 200 and the self-aligned sacrificial sidewall 150. This reduces the probability of mis-etching the etch-resistant layer 200 during the subsequent removal of the self-aligned sacrificial sidewall 150, thereby ensuring the pattern integrity of the etch-resistant layer 200 and improving the accuracy of subsequent pattern transfer.

[0086] In this embodiment, the doping ions being suitable for increasing the etching selectivity between the etch-resistant layer 200 and the self-aligned sacrificial sidewall 150 means that, during subsequent etching processes, when etching the etch-resistant layer 200, there is a high etching selectivity between the etch-resistant layer 200 and the self-aligned sacrificial sidewall 150, and the etching process of etching the etch-resistant layer 200 has a low probability of causing erroneous etching of the self-aligned sacrificial sidewall 150; when etching the self-aligned sacrificial sidewall 150, there is also a high etching selectivity between the self-aligned sacrificial sidewall 150 and the etch-resistant layer 200, and the etching process of etching the self-aligned sacrificial sidewall 150 has a low probability of causing erroneous etching of the etch-resistant layer 200.

[0087] Specifically, in this embodiment, the material of the etch-resistant layer 200 includes one or more of amorphous silicon, polycrystalline silicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon carbonitride. As an example, the material of the etch-resistant layer 200 is amorphous silicon.

[0088] The dopant ions in the etching-resistant layer 200 include one or more of boron ions, phosphorus ions, and argon ions. As an example, the dopant ions in the etching-resistant layer 200 are boron ions.

[0089] In this embodiment, the step of forming the etch-resistant layer 200 includes:

[0090] like Figure 12 As shown, it illustrates the basis Figure 11 (b) Cross-sectional view showing an etch-resistant material layer 190 forming over the top and sidewalls of the self-aligned sacrificial sidewall 150 and the top surface of the first mask sidewall 130.

[0091] The process for forming the etching-resistant material layer 190 includes one or more of the following: chemical vapor deposition, atomic layer deposition, and spin coating.

[0092] In this embodiment, a doping ion source is also used in the process of forming the anti-etching material layer 190, so as to dop the anti-etching material layer 190 with ions during the formation of the anti-etching material layer 190.

[0093] like Figure 13 As shown, Figure 13 (a) is a top view. Figure 13 (b) is Figure 13 (a) A cross-sectional view along the yy secant line, wherein the anti-etching material layer 190 above the top surface of the self-aligned sacrificial sidewall 150 is removed, and the remaining anti-etching material layer 190 serves as the anti-etching layer 200.

[0094] In this embodiment, a planarization process is used to remove the anti-etching material layer 190 that is above the top surface of the self-aligned sacrificial sidewall 150. Specifically, the planarization process includes one or both of chemical mechanical planarization and dry etching processes.

[0095] refer to Figure 14 , Figure 14 (a) is a top view. Figure 14 (b) is Figure 14 (a) Cross-sectional view along the yy secant line. In this embodiment, the method for forming the semiconductor structure further includes: after forming the etch-resistant layer 200, forming a trench 210 that penetrates the etch-resistant layer 200. The trench 210 extends along a first direction and is spaced apart from the core layer 120 along a second direction. The trench 210 exposes a preset sidewall 51 of the self-aligned sacrificial sidewall 150 located on one or both sides of the core layer 120.

[0096] The sidewalls of the trench 210 serve to provide support for the formation of the second mask sidewalls, thereby forming a first groove around the second mask sidewalls located in the trench 210.

[0097] Compared to the size of the first groove, the size of the trench 210 is larger. In this embodiment, by first forming a larger trench 210, and then forming a second mask sidewall to enclose a smaller first groove, the precision requirements of the photolithography and etching processes for forming the trench 210 are lower, which is conducive to the precise control of the size of the trench 210.

[0098] In this embodiment, the anti-etching layer 200 is made of the same material as the self-aligned sacrificial sidewall 150, and the anti-etching layer 200 contains doped ions, which is suitable for improving the etching selectivity between the anti-etching layer 200 and the self-aligned sacrificial sidewall 150. As a result, during the formation of the trench 210, the probability of the anti-etching layer 200 causing accidental etching of the self-aligned sacrificial sidewall 150 is low. It is easy to ensure that when etching reaches the preset sidewall position of the self-aligned sacrificial sidewall 150, the etching process will no longer etch the self-aligned sacrificial sidewall 150. This is beneficial to ensuring the pattern integrity of the self-aligned sacrificial sidewall 150, preventing any impact on the size of the self-aligned sacrificial sidewall 150, and correspondingly ensuring the pattern integrity and dimensional accuracy of the subsequent first groove.

[0099] In this embodiment, an anisotropic dry etching process is used to etch the anti-etching layer 200 to form the trench 210.

[0100] In this embodiment, the bottom of the trench 210 exposes the first mask sidewall 130 located on the top surface of the substrate 10.

[0101] In this embodiment, one trench 210 is used as an example, and the trench 210 only exposes the preset sidewall 51 of the self-aligned sacrificial sidewall 150 located on one side of the graphic structure layer 40. In other embodiments, the number of trenches may be greater than or equal to two, and the trenches may expose the preset sidewalls of the self-aligned sacrificial sidewalls located on both sides of the graphic structure layer.

[0102] refer to Figure 15 , Figure 15 (a) is a top view. Figure 15 (b) is Figure 15 (a) A cross-sectional view along the yy secant line, wherein a second mask sidewall 220 is formed on the sidewall of the trench 210, such that the second mask sidewall 220 located on the sidewall of the trench 210 forms a third groove 330.

[0103] The second mask sidewall 220 is used to reduce the size of the trench 210, thereby defining a smaller third groove 330 through the larger trench 210 and the second mask sidewall 220 located in the trench 210. At the same time, by adjusting the size of the trench 210 and the second mask sidewall 220, the size of the third groove 330 can also be fine-tuned according to the actual process requirements.

[0104] Furthermore, after the self-alignment sacrificial sidewall 150 is subsequently removed to form the first groove, the second mask sidewall 220 is also used to achieve isolation between the first groove and the third groove. In this embodiment, the thickness of the second mask sidewall 220 can be easily adjusted to ensure that the minimum design spacing between the first groove and the third groove is met.

[0105] The second mask sidewall 220 is also used together with the first mask sidewall 130 and the anti-etching layer 200 as a mask for the patterned target layer 100.

[0106] The second mask sidewall 220 is made of a material that exhibits etching selectivity with the core layer 120, the self-aligned sacrificial sidewall 150, and the etch-resistant layer 200. The material of the second mask sidewall 220 includes one or more of titanium oxide, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide, and amorphous silicon. As an example, the second mask sidewall 220 may be made of the same material as the first mask sidewall 130, specifically titanium oxide, which improves process compatibility.

[0107] In this embodiment, the bottom of the second mask sidewall 220 also covers a portion of the first mask sidewall 130.

[0108] In this embodiment, the step of forming the second mask sidewall 220 includes: forming a sidewall material layer (not shown) on the top surface of the anti-etching layer 200, the self-aligned sacrificial sidewall 150, the first mask sidewall 130 located on the top surface of the core layer 120, and the sidewall and bottom of the trench 210; removing the sidewall material layer located on the top surface of the anti-etching layer 200, the self-aligned sacrificial sidewall 150, the first mask sidewall 130 located on the top surface of the core layer 120, and the bottom of the trench 210, and retaining the sidewall material layer located on the sidewall of the trench 210 as the self-aligned sacrificial sidewall 150.

[0109] refer to Figure 16 , Figure 16 (a) is a top view. Figure 16 (b) is Figure 16 (a) A cross-sectional view along the yy secant line, in which the self-aligned sacrificial sidewall 150 is removed to form a first groove 310.

[0110] The first groove 310 is used to define a portion of the target graphic.

[0111] As described above, the self-aligned sacrificial sidewall 150 and the core layer 120 are used to define the shape and size of the first groove 310 and the second groove, respectively. The self-aligned sacrificial sidewall 150 is formed after the core layer 120 is formed. The self-aligned sacrificial sidewall 150 is self-aligned and formed on the sidewall of the core layer 120, which facilitates precise control over the size and position of the self-aligned sacrificial sidewall 150. Furthermore, by removing the self-aligned sacrificial sidewall 150 and the core layer 120, the first groove 310 and the second groove are formed accordingly. The process omits the photolithography step, which helps to avoid the problem of overlapping areas between the trench and the sacrificial layer due to overlay during the formation of trenches by photolithography and etching processes. This helps to avoid the size of the first groove 310 being affected by the overlapping area, thus ensuring the dimensional accuracy of the first groove 310. In the subsequent etching of the target layer 100 along the first groove 310 and the second groove to form the target pattern, the dimensional accuracy of the target pattern and the matching degree between the target pattern and the design pattern are improved.

[0112] In this embodiment, the self-aligned sacrificial sidewall 150 and the anti-etching layer 200 have a high etching selectivity ratio, so the process of removing the self-aligned sacrificial sidewall 150 has a low risk of damaging the anti-etching layer 200, which is conducive to ensuring the pattern integrity and pattern accuracy of the first groove 310, thereby improving the accuracy of subsequent pattern transfer.

[0113] The process for removing the self-aligned sacrificial sidewall 150 includes one or both of wet etching and dry etching. As an example, a wet etching process is used to remove the self-aligned sacrificial sidewall 150. In this embodiment, the etching solution for the wet etching process includes TMAH solution (tetramethylammonium hydroxide solution), SC1 solution, or SC2 solution. SC1 solution refers to a mixed solution of NH4OH and H2O2, and SC2 solution refers to a mixed solution of HCl and H2O2.

[0114] In this embodiment, the bottom of the first groove 310 exposes the first mask sidewall 130 located on the top surface of the substrate 10.

[0115] refer to Figure 17 , Figure 17 (a) is a top view. Figure 17 (b) is Figure 17 (a) Cross-sectional view along the yy secant line. In this embodiment, the method for forming the semiconductor structure further includes: after removing the self-aligned sacrificial sidewall 150 to form the first groove 310, removing the first mask sidewall 130 located on the top surface of the core layer 120 and the bottom of the first groove 310.

[0116] Remove the first mask sidewall 130 located on the top surface of the core layer 120 and the bottom of the first groove 310 to expose the top surface of the substrate 10 at the top surface of the core layer 120 and the bottom of the first groove 310, so that the core layer 120 can be removed through the exposed top surface of the core layer 120, and the target layer 100 below the first groove 310 can be patterned.

[0117] In this embodiment, during the process of removing the first mask sidewall 130 located on the top surface of the core layer 120 and the bottom of the first groove 310, the first mask sidewall 130 located at the bottom of the third groove 330 is also removed.

[0118] In this embodiment, an anisotropic etching process is used to remove the first mask sidewall 130 located on the top surface of the core layer 120 and at the bottom of the first groove 310 and the third groove 330. The anisotropic etching process has the characteristics of anisotropic etching, which helps to reduce the probability of mis-etching the first mask sidewall 130 located on the sidewall of the core layer 120 along a direction perpendicular to the sidewall of the core layer 120.

[0119] It should be noted that in this embodiment, the second mask sidewall 220 and the first mask sidewall 130 are made of the same material. In the process of removing the first mask sidewall 130 located on the top surface of the core layer 120 and at the bottom of the first groove 310 and the third groove 330, a portion of the height of the second mask sidewall 220 is also consumed.

[0120] refer to Figure 18 , Figure 18 (a) is a top view. Figure 18 (b) is Figure 18 (a) A cross-sectional view along the yy secant line, in which the core layer 120 is removed, so that the first mask sidewall 130 forms the second groove 320.

[0121] The second groove 320, together with the first groove 310 and the third groove 330, defines the shape of the target graphic.

[0122] The second groove 320, the first groove 310, and the third groove 330 all extend along the first direction, and the second groove 320, the first groove 310, and the third groove 330 are arranged at intervals along the second direction. Adjacent second grooves 320 and first grooves 310 are separated by a first mask sidewall 130, and adjacent first grooves 310 and third grooves 330 are separated by a second mask sidewall 220.

[0123] The process for removing the core layer 120 includes one or both of dry etching and wet etching.

[0124] Since the top surface of the core layer 120 still retains the first mask sidewall 130, this embodiment uses the removal of the core layer 120 after the removal of the self-aligned sacrificial sidewall 150 as an example. In other embodiments, when the top surface of the core layer does not retain the first mask sidewall, the order of removing the self-aligned sacrificial sidewall and removing the core layer can be adjusted according to actual process requirements.

[0125] refer to Figure 19 , Figure 19 (a) is a top view. Figure 19 (b) is Figure 19 (a) A cross-sectional view along the yy secant line, showing the target layer 100 etched along the first groove 310 and the second groove 320 using the first mask sidewall 130 and the anti-etching layer 200 as masks to form a target pattern. Specifically, the substrate is etched along the third groove 330, the first groove 310, and the second groove 320 using the first mask sidewall 130, the second mask sidewall 220, and the anti-etching layer 200 as masks to form a target pattern.

[0126] As can be seen from the foregoing description, this embodiment is beneficial to ensuring the dimensional accuracy of the first groove 310. Therefore, during the process of etching the target layer 100 along the first groove 310 and the second groove 320 to form the target pattern, the dimensional accuracy of the target pattern and the matching degree between the target pattern and the design pattern are improved.

[0127] In this embodiment, during the process of graphically mapping the target layer 100, the hard mask material layer 115 is also graphically mapped to form a hard mask layer 230.

[0128] In this embodiment, the target layer 100 is a dielectric layer; the target pattern is an interconnect trench 20.

[0129] Accordingly, refer to Figure 20 , Figure 20 (a) is a top view. Figure 20 (b) is Figure 20 (a) A cross-sectional view along the yy secant line. In this embodiment, the method for forming the semiconductor structure further includes: after forming the interconnect trench 20, forming a metal interconnect 30 in the interconnect trench 20.

[0130] In this embodiment, the interconnect slot 20 has a high degree of matching with the design pattern and high dimensional accuracy. The interconnect slot 20 can achieve smaller critical dimensions, which is beneficial to meet the minimum design spacing between metal interconnects 30 and improve the pattern accuracy of metal interconnects 30. Furthermore, the linewidth of metal interconnects 30 can be precisely controlled, which is beneficial to meet the needs of continuous miniaturization of device size.

[0131] The metal interconnect 30 is used to realize the electrical connection between the semiconductor structure and external circuits or other interconnect structures. In this embodiment, the material of the metal interconnect 30 is copper. In other embodiments, the material of the metal interconnect can also be conductive materials such as cobalt, tungsten, and aluminum.

[0132] In this embodiment, the forming method further includes removing the self-aligned sacrificial sidewall 150 located on the sidewall of any one or both of the first end 41 and the second end 42. As an example, the metal interconnects 30 extend along the first direction and are spaced apart along the second direction.

[0133] In this embodiment, during the step of forming the metal interconnect 30, the anti-etching layer 200, the first mask sidewall 130, and the second mask sidewall 220 are also removed to prepare for subsequent processes.

[0134] Figures 21 to 22 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiment will not be repeated here. The differences between this embodiment and the previous embodiment are as follows:

[0135] refer to Figure 21 The diagram shows a top view, after the self-aligned sacrificial sidewall 350 is formed, the self-aligned sacrificial sidewall is removed from the sidewall of only one of the first and second ends.

[0136] Accordingly, refer to Figure 22 After removing the self-aligned sacrificial sidewall 350 to form the first groove 510 and removing the core layer 420 to form the second groove 520, the first groove 510 is connected to one end of the second groove 520 and spaced apart at the other end of the second groove 520, such that the first groove 510 is not only along the first direction (e.g., Figure 22 It can extend along the X direction (as shown in the middle X direction) and can also extend along the second direction (as shown in the middle X direction). Figure 22 Extending in the Y direction, the second groove 520 has a corresponding two-dimensional graphic, which is beneficial to improving the design freedom of the target graphic. In addition, compared with using the graphic of the photomask to realize the two-dimensional graphic, this embodiment uses the superposition of process steps to realize the design of the two-dimensional graphic, which is beneficial to reduce the process difficulty and increase the process window.

[0137] When the target pattern is an interconnecting slot, metal interconnects will be formed in the interconnecting slot. The metal interconnects are also two-dimensional patterns, which helps to improve the interconnection capability of the metal interconnects.

[0138] The first groove 510 and the second groove 520 are separated by the first mask sidewall 430.

[0139] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0140] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The application relates to a semiconductor structure and a forming method thereof. The application provides a substrate including a target layer for forming a target pattern; a core layer is formed on the substrate, the core layer extends along a first direction, and a direction perpendicular to the first direction is a second direction; a first mask sidewall is formed on a sidewall of the core layer; a self-aligned sacrificial sidewall is formed on a sidewall of the first mask sidewall; an etching-resistant layer is formed on the core layer, the self-aligned sacrificial sidewall and the substrate exposed by the first mask sidewall, wherein the etching-resistant layer is made of the same material as the self-aligned sacrificial sidewall, and the etching-resistant layer contains doped ions which are suitable for increasing the etching selectivity between the etching-resistant layer and the self-aligned sacrificial sidewall; the self-aligned sacrificial sidewall is removed to form a first groove; the core layer is removed to form a second groove surrounded by the first mask sidewall; the target layer is etched along the first groove and the second groove to form the target pattern by taking the first mask sidewall and the etching-resistant layer as masks.

2. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the self-aligned sacrificial sidewall, the self-aligned sacrificial sidewall surrounds the sidewall of the first mask sidewall.

3. The method of forming a semiconductor structure of claim 2, wherein, In the step of forming the first mask sidewall, the core layer and the first mask sidewall on the sidewall of the core layer form a pattern structure layer which extends along the first direction and includes a first end and a second end opposite to the first end along the first direction. The forming method of the semiconductor structure further includes: removing the self-aligned sacrificial sidewall on the sidewall of any one or both of the first end and the second end before forming the etching-resistant layer after forming the self-aligned sacrificial sidewall, so that the self-aligned sacrificial sidewall is disconnected at the sidewall position of the corresponding end of the pattern structure layer.

4. The method of forming a semiconductor structure of claim 3, wherein, The step of removing the self-aligned sacrificial sidewall on the sidewall of any one or both of the first end and the second end includes: forming a mask layer on the substrate, and the mask layer spans the pattern structure layer and the self-aligned sacrificial sidewall along the second direction on a projection plane parallel to the substrate, and the mask layer exposes the self-aligned sacrificial sidewall on the sidewall of any one or both of the first end and the second end. The self-aligned sacrificial sidewall is etched by taking the mask layer as a mask.

5. The method of forming a semiconductor structure of claim 3, wherein, The self-aligned sacrificial sidewall on the sidewall of any one or both of the first end and the second end is removed by using an anisotropic dry etching process.

6. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the self-aligned sacrificial sidewall includes: forming a sacrificial sidewall film on the top surface of the core layer, the top surface and the sidewall of the first mask sidewall and the top surface of the substrate. The sacrificial sidewall film on the top surfaces of the core layer, the first mask sidewall and the substrate is removed, and the sacrificial sidewall film on the sidewall of the first mask sidewall is reserved as the self-aligned sacrificial sidewall.

7. The method of forming a semiconductor structure of claim 6, wherein, The process of forming the sacrificial sidewall film includes one or both of an atomic layer deposition process and a chemical vapor deposition process.

8. The method of forming a semiconductor structure of claim 6, wherein, An anisotropic dry etching process is used to remove the sacrificial sidewall film on the top surface of the core layer, the first mask sidewall and the substrate.

9. The method of forming a semiconductor structure of claim 1, wherein, The material of the etch-resistant layer and the self-aligned sacrificial sidewall includes one or more of amorphous silicon, polysilicon, silicon oxide, amorphous carbon, silicon nitride, amorphous germanium, silicon oxynitride, carbon nitride, silicon carbide, silicon carbon nitride and silicon carbon oxynitride.

10. The method of forming a semiconductor structure of claim 1 or 9, wherein, The doping ions in the etch-resistant layer include one or more of boron ions, phosphorus ions and argon ions.

11. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the self-aligned sacrificial sidewall, the preset sidewall of the self-aligned sacrificial sidewall is along the first direction and is not in contact with the sidewall of the first mask sidewall. The method further includes, after forming the etch-resistant layer and before removing the core layer, forming a trench through the etch-resistant layer, the trench extending along the first direction and being spaced apart from the core layer along the second direction, the trench exposing the preset sidewall of the self-aligned sacrificial sidewall on one side or both sides of the core layer; and forming a second mask sidewall on the sidewall of the trench, the second mask sidewall on the sidewall of the trench forming a third recess. The first mask sidewall, the second mask sidewall and the etch-resistant layer are used as masks to etch the substrate along the third recess, the first recess and the second recess to form a target pattern.

12. The method of forming a semiconductor structure of claim 11, wherein, The material of the second mask sidewall is the same as that of the first mask sidewall.

13. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the first mask sidewall, the first mask sidewall is also formed on the top surface of the core layer and the substrate. The self-aligned sacrificial sidewall and the etch-resistant layer cover the first mask sidewall on the top surface of the substrate and also expose the first mask sidewall on the top surface of the core layer. After removing the self-aligned sacrificial sidewall, the core layer is removed. The method further includes, after removing the self-aligned sacrificial sidewall and forming the first recess, and before removing the core layer, removing the first mask sidewall on the top surface of the core layer and the bottom of the first recess.

14. The method of forming a semiconductor structure of claim 13, wherein, An anisotropic etching process is used to remove the first mask sidewall on the top surface of the core layer and the bottom of the first recess.

15. The method of forming a semiconductor structure of claim 1, wherein, The target layer is a dielectric layer, and the target pattern is an interconnection trench. The method further includes, after forming the interconnection trench, forming a metal interconnection line in the interconnection trench.

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