Interactive data verification method, device, equipment and medium for programmable device

Abstract

The present invention discloses a method, device, equipment and medium for verifying interactive data of a programmable device, and belongs to the field of integrated circuit technology. It includes: obtaining interactive data to be verified; obtaining a first public key digest and a second public key digest of the interactive data through a first digest algorithm; obtaining a first data stream digest and a second data stream digest of the interactive data through an RSA encryption algorithm, and obtaining a third data stream digest of the interactive data through a second digest algorithm; judging whether the first public key digest and the second public key digest are consistent, and obtaining a public key judgment result; judging whether the first data stream digest, the second data stream digest and the third data stream digest are consistent, and obtaining a data stream judgment result; determining whether the interactive data has been tampered with or part of the data has been lost according to the public key judgment result and the data judgment result. The verification speed of the interactive data of the present invention is fast and the time spent is short, thereby shortening the development cycle of the entire programmable device.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to an interactive data verification method, device, equipment and medium for a programmable device. Background Art

[0002] At present, during the development process of programmable devices (such as FPGA chips), it is necessary to verify (i.e., check and authenticate) the interaction data between the above-mentioned programmable devices and software tools (such as IspLever software) so that the developers of the programmable devices can accurately and timely know whether the above-mentioned interaction data has been tampered with or some data has been lost, thereby ensuring that the above-mentioned programmable devices are always in a safe development environment.

[0003] In the prior art, developers of programmable devices (such as FPGA chips) often use DPI (Deep Packet Inspection) detection technology to verify the interactive data between programmable devices and software tools.

[0004] The inventors found that since the above-mentioned prior art solution, in order to obtain summary information (such as data flow summary) when verifying the interactive data, the above-mentioned DPI detection technology must use the DPI interface, and when using the DPI interface, the GCC compiler (GNU Compiler Collection) must be used to compile the called C language model (mainly used to implement the encryption algorithms needed in the verification process, such as the RSA encryption algorithm).

[0005] The inventors believe that: since it takes a certain amount of time for the DPI interface to call the C language model through the GCC compiler, the above-mentioned prior art solution has a slow verification speed and takes a long time when verifying the interactive data, which prolongs the development cycle of the entire programmable device, so it is necessary to make improvements. Summary of the invention

[0006] The embodiments of the present invention provide a method, device, equipment and medium for verifying interactive data of a programmable device, so as to solve the problem that the verification speed of interactive data is slow and time-consuming, thereby prolonging the development cycle of the entire programmable device.

[0007] The technical solution of the present invention is to provide an interactive data verification method for a programmable device, comprising: obtaining interactive data to be verified, the interactive data comprising a public key to be verified, a private key to be verified, a modulus to be verified and a data stream to be verified; obtaining a first public key summary of the interactive data through a first summary algorithm implemented based on the Verilog language, obtaining a second public key summary of the interactive data through a first summary algorithm implemented based on the SystemVerilog language, the first public key summary and the second public key summary having the same bit width; obtaining a first data stream summary of the interactive data through an RSA encryption algorithm implemented based on the SystemVerilog language, A second data stream digest of the interactive data is obtained by an RSA encryption algorithm implemented based on the Verilog language, and a third data stream digest of the interactive data is obtained by a second digest algorithm implemented based on the Verilog language, wherein the bit widths of the first data stream digest, the second data stream digest and the third data stream digest are the same; whether the first public key digest and the second public key digest are consistent is determined to obtain a public key determination result; whether the first data stream digest, the second data stream digest and the third data stream digest are consistent is determined to obtain a data stream determination result; and whether the interactive data is tampered with or part of the data is lost according to the public key determination result and the data determination result.

[0008] Optionally, the obtaining the first public key digest of the interaction data through a first digest algorithm implemented based on the Verilog language, and the obtaining the second public key digest of the interaction data through a first digest algorithm implemented based on the SystemVerilog language, include: driving the public key to be verified into the first digest algorithm implemented based on the Verilog language to obtain the first public key digest; driving the public key to be verified into the first digest algorithm implemented based on the SystemVerilog language to obtain the second public key digest.

[0009] Optionally, the step of obtaining a first data stream digest of the interaction data through an RSA encryption algorithm implemented based on the Verilog language and obtaining a second data stream digest of the interaction data through an RSA encryption algorithm implemented based on the Verilog language includes: driving the data stream to be verified into a second digest algorithm implemented based on the SystemVerilog language to obtain a prefix data digest; driving the prefix data digest, the private key to be verified and the modulus to be verified into an RSA encryption algorithm implemented based on the SystemVerilog language to obtain authentication data with a signature; and driving the authentication data into an RSA encryption algorithm implemented based on the Verilog language and an RSA encryption algorithm implemented based on the SystemVerilog language, respectively, to obtain the first data stream digest and the second data stream digest.

[0010] Optionally, the obtaining of the third data flow summary of the interaction data by using the second summary algorithm implemented based on the Verilog language includes: driving the data flow to be verified into the second summary algorithm implemented based on the Verilog language to obtain the third data flow summary.

[0011] Optionally, determining whether the interaction data has been tampered with or part of the data has been lost based on the public key judgment result and the data judgment result includes: judging whether both the public key judgment result and the data judgment result are yes, and obtaining a data verification result; if the data verification result is yes, the interaction data of the programmable device has not been tampered with and no data has been lost during the interaction process; if the data verification result is no, the interaction data of the programmable device has been tampered with or part of the data has been lost during the interaction process.

[0012] Optionally, the first digest algorithm and / or the second digest algorithm is one of a SHA-2 algorithm, a SHA-3 algorithm and a MessageDigest algorithm, and a bit width of the first data stream digest is not less than 1024 bits.

[0013] Optionally, the first digest algorithm is one of SHA3-224 algorithm, SHA3-256 algorithm, SHA3-384 algorithm, SHA3-512 algorithm, SHAKE128 algorithm and SHAKE256 algorithm, the second digest algorithm is SHAKE128 algorithm or SHAKE256 algorithm, and the bit width of the first data stream digest is 4096 bits.

[0014] Another technical solution of the present invention is to provide an interactive data verification device for a programmable device, comprising: an interactive data acquisition module, used to obtain interactive data to be verified, wherein the interactive data includes a public key to be verified, a private key to be verified, a modulus to be verified, and a data stream to be verified; a public key summary generation module, used to obtain a first public key summary of the interactive data through a first summary algorithm implemented based on the Verilog language, and to obtain a second public key summary of the interactive data through a first summary algorithm implemented based on the SystemVerilog language, wherein the bit widths of the first public key summary and the second public key summary are the same; a data stream summary generation module, used to obtain the first public key summary of the interactive data through an RSA encryption algorithm implemented based on the SystemVerilog language. A first data stream summary, a second data stream summary of the interactive data is obtained by an RSA encryption algorithm implemented based on the Verilog language, and a third data stream summary of the interactive data is obtained by a second summary algorithm implemented based on the Verilog language, wherein the first data stream summary, the second data stream summary and the third data stream summary have the same bit width; a summary judgment module, used to judge whether the first public key summary and the second public key summary are consistent, and obtain a public key judgment result; judge whether the first data stream summary, the second data stream summary and the third data stream summary are consistent, and obtain a data stream judgment result; a data judgment module, used to determine whether the interactive data has been tampered with or part of the data is lost according to the public key judgment result and the data judgment result.

[0015] Another technical solution of the present invention is: to provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the interactive data verification method of the above-mentioned programmable device when executing the computer program.

[0016] Another technical solution of the present invention is to provide a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the interactive data verification method of the above-mentioned programmable device are implemented.

[0017] The interactive data verification method, device, equipment and medium of the programmable device of the present invention can accurately and timely know whether the interactive data to be verified has been tampered with or part of the data has been lost through the public key judgment result and the data judgment result, thereby ensuring that the above-mentioned programmable device is always in a safe development environment; at the same time, since the present invention implements the corresponding digest algorithm (including the first digest algorithm, the second digest algorithm and the RSA encryption algorithm) through the Verilog language and the SystemVerilog language respectively, and then allows the above-mentioned digest algorithm to directly obtain the summary information (public key digest and data flow digest) of the interactive data to be verified, in this way, when verifying the interactive data to be verified, the present invention does not need to use the GCC compiler to call the programming language (such as C language), so the verification speed of the interactive data of the present invention is faster and the time spent is shorter (about 1 second can be saved on average for every 1G of data), thereby shortening the development cycle of the entire programmable device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0019] Figure 1 It is a flow chart of the interactive data verification method of a programmable device in the first embodiment of the present invention;

[0020] Figure 2 It is a structural diagram of an interactive data verification device of a programmable device according to a second embodiment of the present invention;

[0021] Figure 3 is a schematic structural diagram of an electronic device according to a third embodiment of the present invention;

[0022] Figure 4 is a schematic structural diagram of a storage medium according to a fourth embodiment of the present invention; DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] The terms "first", "second" and "third" in the present invention are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second" and "third" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0025] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] At present, in order to ensure that programmable devices are always in a safe development environment, people need to verify (i.e. check and authenticate) the interaction data between programmable devices and software tools (such as IspLever software) so that the developers of programmable devices can accurately and timely know whether the above interaction data has been tampered with or some data has been lost.

[0027] The prior art usually obtains the data stream digest of the interaction data to be verified respectively through the RSA encryption algorithm and the SHAKE256 algorithm implemented (programmed) by C language, and judges whether the interaction data to be verified has been tampered with or part of the data is lost by comparing the above two data stream digests. In this way, when the above prior art scheme verifies the interaction data, the accuracy of its verification result is poor, and it is necessary to improve it.

[0028] At the same time, in order to verify the above-mentioned interactive data through DPI detection technology, the above-mentioned prior art solution usually uses the GCC compiler to call the C language. In this way, the interactive data verification speed of the above-mentioned prior art solution is slow, which makes the verification speed of the interactive data slow and takes a long time, thereby making the development cycle of the entire programmable device longer. Therefore, it is necessary to make improvements.

[0029] In view of the above technical problems, the present invention implements corresponding digest algorithms (such as SHA3-384 algorithm and RSA encryption algorithm) through Verilog language and SystemVerilog language respectively, and then allows the above digest algorithms to directly obtain summary information (public key digest and data flow digest) of the interaction data to be verified. In this way, when the present invention verifies the interaction data to be verified, the verification speed of the interaction data is faster, and about 1 second can be saved on average for every 1G of data.

[0030] It should be noted that the first digest algorithm and the second digest algorithm in the present invention can be collectively referred to as digest algorithms. The C language, Verilog language, System Verilog language, RSA encryption algorithm and digest algorithm recorded in the present invention are all prior arts, which are described as follows:

[0031] C is a procedural computer programming language, which is different from object-oriented programming languages ​​such as C++, C#, and Java. The design goal of C is to provide a programming language that can be compiled in a simple way, process low-level memory, generate only a small amount of machine code, and can run without any operating environment support. C is generally only 10%-20% less efficient than the target program generated by assembly language code, so C can be used to write system software.

[0032] Verilog language (also known as Verilog HDL) is a hardware description language used to model digital systems at multiple levels of abstraction, from algorithm level, gate level to switch level. The complexity of the digital system objects being modeled can range from simple gates to complete electronic digital systems. Digital systems can be described hierarchically and timing modeling can be explicitly performed in the same description.

[0033] SystemVerilog, referred to as SV language, is a relatively new language. It is built on the basis of Verilog language. It is an extension and enhancement of IEEE 1364Verilog-2001 standard. It is compatible with Verilog2001. It combines hardware description language (HDL) with modern high-level verification language (HVL), and has recently become the next generation of hardware design and verification language.

[0034] The RSA encryption algorithm is an asymmetric encryption algorithm that can effectively ensure the security of encrypted data. It is currently the most widely used public key encryption algorithm based on the difficulty of large integer decomposition problems. Since the RSA algorithm was proposed in 1978, researchers at home and abroad have conducted in-depth research on its security and fast software and hardware implementation, and have made many breakthroughs. In a public key cryptographic system, the public key and private key must satisfy the one-way trapdoor function characteristic, that is, only the forward transformation from the private key to the public key can be calculated, but the private key cannot be obtained from the public key.

[0035] The digest algorithm of the present invention can also be called a message digest generation algorithm, including the SHA algorithm (Secure Hash Algorithm algorithm) and the Message Digest algorithm, wherein:

[0036] The SHA algorithm is also known as the Secure Hash Algorithm, which was designed by the National Security Agency of the United States and published as the Federal Information Processing Standard (FIPS) by the National Institute of Standards and Technology (NIST). The SHA algorithm includes the SHA-1 algorithm, the SHA-2 algorithm, and the SHA-3 algorithm. Among them, the SHA-1 algorithm has been cracked, but the SHA-2 algorithm and the SHA-3 algorithm have not been cracked so far.

[0037] In August 2015, the U.S. National Institute of Standards and Technology formally proposed six SHA3 algorithms based on the highly flexible Keccak algorithm in FIPS PUB 202, including SHA3-224, SHA3-256, SHA3-384, SHA3-512, SHAKE128 and the above-mentioned SHAKE256 algorithm. The above-mentioned SHA3 algorithms can be used to generate data stream digests.

[0038] The MessageDigest algorithm is a diffusion algorithm that aims to achieve a complete avalanche effect by making elements interact with each other through diffusion processing. The avalanche effect refers to the accumulation of small changes in the original input and the resulting huge changes in the output. With a complete avalanche effect, any small change in the input will cause a complete change in the output (100% diffusion rate).

[0039] Figure 1 FIG. 1 is a flow chart of the interactive data verification method of a programmable device according to the first embodiment of the present invention. It should be noted that if there is substantially the same result, the method of the present invention is not limited to the method of FIG. Figure 1 The process sequence shown is limited. Figure 1 As shown, the interactive data verification method of the programmable device includes the steps of:

[0040] S1. Acquire interaction data to be verified, where the interaction data includes a public key to be verified, a private key to be verified, a modulus to be verified, and a data stream to be verified;

[0041] In this embodiment, the interaction data to be verified refers to information data obtained after the interaction data between the programmable device and the software tool is driven into a preset encryption algorithm (such as the RSA encryption algorithm).

[0042] In actual operation, the present invention drives the interactive data between the programmable device and the software tool into the RSA encryption algorithm implemented based on the SystemVerilog language, thereby obtaining the interactive data to be verified, that is, obtaining the public key to be verified, the private key to be verified, the modulus to be verified and the data stream to be verified.

[0043] S2. Obtain a first public key digest of the interaction data by using a first digest algorithm implemented based on the Verilog language, and obtain a second public key digest of the interaction data by using a first digest algorithm implemented based on the SystemVerilog language, wherein the first public key digest and the second public key digest have the same bit width;

[0044] In this embodiment, an encryption algorithm implemented based on the Verilog language or the SystemVerilog language (such as the SHA3-384 algorithm) refers to the encryption algorithm compiled through the Verilog language or the SystemVerilog language. For example, the RSA encryption algorithm implemented based on the SystemVerilog language refers to the RSA encryption algorithm compiled through the SystemVerilog language. This part of the content is basically the same as the RSA encryption algorithm compiled through the C language in the prior art, the only difference is that the C language is replaced by the SystemVerilog language.

[0045] In this step, the steps of obtaining the first public key digest and the second public key digest include:

[0046] S21, driving the public key to be verified into a first digest algorithm implemented based on the Verilog language to obtain a first public key digest;

[0047] S22. Drive the public key to be verified into a first digest algorithm implemented based on the SystemVerilog language to obtain a second public key digest.

[0048] In actual operation, the first digest algorithm implemented based on the Verilog language and the first digest algorithm implemented based on the SystemVerilog language are encryption algorithms obtained according to the same algorithm protocol. For example, the first digest algorithm implemented in the Verilog language and the first digest algorithm implemented in the SystemVerilog language are both SHA3-384 algorithms.

[0049] In actual working hours, after a specific encryption algorithm is selected for the first digest algorithm in the above step S2, the bit width of the public key digest is also determined when obtaining the public key digest. For example, for the SHA3-384 algorithm, when obtaining the public key digest, regardless of whether the SHA3-384 algorithm is implemented in the Verilog language or the SystemVerilog language, its bit width is 384 bits.

[0050] S3, obtaining a first data stream digest of the interactive data by using an RSA encryption algorithm implemented based on the SystemVerilog language, obtaining a second data stream digest of the interactive data by using an RSA encryption algorithm implemented based on the Verilog language, and obtaining a third data stream digest of the interactive data by using a second digest algorithm implemented based on the Verilog language, wherein the first data stream digest, the second data stream digest, and the third data stream digest have the same bit width;

[0051] In this embodiment, obtaining the public key digest and the data stream digest by a selected encryption algorithm (such as the RSA encryption algorithm) is a prior art in the art and will not be described in detail here.

[0052] In this step, the steps of obtaining the first data stream summary, the second data stream summary and the third data stream summary include:

[0053] S31, driving the data stream to be verified into a second digest algorithm implemented based on the SystemVerilog language to obtain a front-end data digest;

[0054] S32, driving the pre-data summary, the private key to be verified and the modulus to be verified into the RSA encryption algorithm implemented based on the SystemVerilog language to obtain authentication data with signature;

[0055] S33. Drive the authentication data into an RSA encryption algorithm implemented based on the Verilog language and an RSA encryption algorithm implemented based on the SystemVerilog language respectively to obtain the first data stream digest and the second data stream digest.

[0056] S34, driving the data flow to be verified into a second digest algorithm implemented based on the Verilog language to obtain a third data flow digest.

[0057] In this embodiment, the second digest algorithm implemented based on the Verilog language and the second digest algorithm implemented based on the SystemVerilog language are encryption algorithms obtained according to the same algorithm protocol. For example, the second digest algorithm implemented based on the Verilog language and the second digest algorithm implemented based on the SystemVerilog language are both SHAKE256 algorithms.

[0058] In actual working hours, after a specific encryption algorithm is selected for the second digest algorithm in the above step S3, when obtaining the data stream digest, the bit width of the obtained data stream digest can be selected as needed. At the same time, in order to prevent the interactive data to be verified from being cracked, thereby improving the accuracy of the verification result of the present invention, the bit width of the first data stream digest should be no less than 1024 bits (bit), preferably, the bit width of the first data stream digest is 4096 bits, so that the verification result of the present invention is more accurate.

[0059] S4. Determine whether the first public key digest and the second public key digest are consistent, and obtain a public key determination result; determine whether the first data flow digest, the second data flow digest and the third data flow digest are consistent, and obtain a data flow determination result;

[0060] In this step, the above public key judgment result is mainly used to authenticate the public key to be verified, and the above data flow judgment result is mainly used to authenticate all parameters of the interactive data to be verified, that is, the data flow judgment result needs to verify the public key to be verified, the private key to be verified, the modulus to be verified and the data flow to be verified. The specific authentication steps can refer to the above steps S2 to S4.

[0061] Preferably, the step of obtaining the data flow judgment result in this embodiment may include: S41, first judging whether the second data flow summary and the third data flow summary are consistent, and obtaining the first data flow result; S42, then judging whether the first data flow summary and the second data flow summary are consistent, and obtaining the second data flow result; S43, if both the first data flow result and the second data flow result are yes, the data flow judgment result is yes; S44, if at least one of the first data flow result and the second data flow result is no, the data flow judgment result is no.

[0062] S5. Determine whether the interactive data has been tampered with or part of the data is lost according to the public key judgment result and the data judgment result.

[0063] In this step, the step of determining whether the interactive data has been tampered with or part of the data has been lost based on the judgment result includes: S51, determining whether the public key judgment result and the data judgment result are both yes, and obtaining a data verification result; S52, if the data verification result is yes, the interactive data of the programmable device has not been tampered with and no data has been lost during the interactive data process; S53, if the data verification result is no, the interactive data of the programmable device has been tampered with or part of the data has been lost during the interactive data process.

[0064] In this embodiment, when it is determined that the interactive data has been tampered with or part of the data is lost, it means that the verification has failed, and the programmable device is not in a safe environment, and the developer of the programmable device needs to make adjustments in time.

[0065] In this embodiment, the first digest algorithm and / or the second digest algorithm of the present invention may be one of the SHA-2 algorithm, the SHA-3 algorithm and the MessageDigest algorithm:

[0066] For example, the first digest algorithm may be one of the SHA2-384 algorithm, the SHA3-224 algorithm, the SHA3-256 algorithm, the SHA3-384 algorithm, the SHA3-512 algorithm, the SHAKE128 algorithm, the SHAKE256 algorithm, and the MessageDigest-5 algorithm;

[0067] The second digest algorithm can be SHAKE128 algorithm or SHAKE256. When the second digest algorithm is one of SHA3-224 algorithm, SHA3-256 algorithm, SHA3-384 algorithm and SHA3-512 algorithm, the above-mentioned second digest algorithm preferably adopts Stream mode to obtain the third data stream digest.

[0068] In order to better illustrate the technical solution of the present invention, this embodiment takes the SHA3-384 algorithm and the SHAKE256 algorithm as examples to further illustrate the technical solution of the present invention:

[0069] When the SHA3-384 algorithm is used as the first digest algorithm to obtain the first public key digest, the SHA3-384 algorithm is implemented by the Verilog language; when the SHA3-384 algorithm is used as the first digest algorithm to obtain the second public key digest, the SHA3-384 algorithm is implemented by the SystemVerilog language. When the SHA3-384 algorithm is used as the second digest algorithm to obtain the third data stream digest, the SHA3-384 algorithm is implemented by the Verilog language, and at this time, the SHA3-384 algorithm preferably runs in Stream mode.

[0070] When the SHAKE256 algorithm is used as the first digest algorithm to obtain the first public key digest, the SHAKE256 algorithm is implemented by the Verilog language; when the SHAKE256 algorithm is used as the first digest algorithm to obtain the second public key digest, the SHAKE256 algorithm is implemented by the SystemVerilog language. When the SHAKE256 algorithm is used as the second digest algorithm to obtain the third data stream digest, the SHA3-384 algorithm is implemented by the Verilog language, and at this time, the SHAKE256 algorithm does not need to run the Stream mode.

[0071] In the present invention, the encryption algorithm implemented by the Verilog language is mainly used in the chip design process, and the encryption algorithm implemented by the SystemVerilog language is mainly used in the chip verification process. For example, the SHA3-384 algorithm implemented by the Verilog language is mainly used in the chip design process, and the SHA3-384 algorithm is completed by the chip design engineer; the SHA3-384 algorithm implemented by the SystemVerilog language is mainly used in the chip verification process, and the SHA3-384 algorithm is completed by the chip verification engineer.

[0072] In actual work, for the summary information (including the first public key digest, the second public key digest, the first data stream digest, the second data stream digest and the third data stream digest), if the authentication is successful, the same summary information (such as the public key digest) obtained by the same summary algorithm (this algorithm is respectively based on the SystemVerilog language and the Verilog language implementation, such as the SHA3-384 algorithm) is the same; if the authentication fails, the same summary information (such as the public key digest) obtained by the same summary algorithm (this algorithm is respectively based on the SystemVerilog language and the Verilog language implementation, such as the SHA3-384 algorithm) is different.

[0073] The following uses the public key digest obtained by the SHA3-384 algorithm implemented in different languages ​​when verifying a certain piece of data as an example to illustrate the technical solution of the present application (other algorithms can use this SHA3-384 algorithm as an example):

[0074] 1) When the authentication succeeds, the public key digest obtained by the SHA3-384 algorithm implemented by the Verilog language and the public key digest obtained by the SHA3-384 algorithm implemented by the SystemVerilog language are the same, as follows:

[0075] UM_INF0 / home / IC / aas / auto_aut_system 3_0 / dv / env / . / autd_refermodel.sv(45)@54-000:uwm_test_top.env.d mdl[aut d refermodel]expect rsa dd=6801ac8295fa5cc1673b36ce7eea19ef4a81d154e1c2c0f35a8be37bad93fd28096f4e2be729eac9b07f1089d39386e

[0076] 672indut_sha3_wrapper, sha3_d_actual=680lac8295fa5cc1673b36ce7eea19ef4a81d154e1c2c0f35aBbe37bad93fd28096f4e2d6.

[0077] 1) When the authentication fails, the public key digest obtained by the SHA3-384 algorithm implemented by the Verilog language is still the data displayed when the authentication succeeds, but the public key digest obtained by the SHA3-384 algorithm implemented by the SystemVerilog language is:

[0078] UVM_INFO / home / IC / aas / auto_aut_system_3_0 / dv / env / . / aut_d_refermodel.sv(45)@540000:uvm_test_top.env.d_mdl[aut_d_refermodel]expect rsa_d_d=6801ac8295fa5cc1673b36ce7eea19ef4a81d154e1c2c0f35a0be37bad93fd28096f4e2d6e729eac9b07f1089d39386ein dut_sha3_wrapper,sha3_d_actual=c98c3a859774d9269ec1db01e0a194d35d0b16e3c95e6c670b9f2521ae9c031eeeb2c71a3f97cc003d8ffcd43595179f.

[0079] In actual work, this application uses a digest algorithm implemented based on the SystemVerilog language (such as the SHA3-384 algorithm) to verify whether the interactive data has been tampered with or some data has been lost. This is because this application needs to verify the functional correctness of the digest algorithm implemented based on the Verilog language (such as the SHA3-384 algorithm); in addition, if the authentication fails, for the data stream digest, the first data stream digest, the second data stream digest and the third data stream digest will be different.

[0080] Figure 2 FIG. 2 is a schematic diagram of the structure of an interactive data verification device of a programmable device according to the second embodiment of the present invention. Figure 2 As shown, the interactive data verification device of the programmable device includes:

[0081] The interactive data acquisition module 21 is used to obtain the interactive data to be verified, wherein the interactive data includes the public key to be verified, the private key to be verified, the modulus to be verified and the data stream to be verified;

[0082] A public key digest generating module 22, configured to obtain a first public key digest of the interaction data by using a first digest algorithm implemented in the Verilog language, and obtain a second public key digest of the interaction data by using a first digest algorithm implemented in the SystemVerilog language, wherein the first public key digest and the second public key digest have the same bit width;

[0083] A data flow summary generation module 23, configured to obtain a first data flow summary of the interaction data by using an RSA encryption algorithm implemented based on the SystemVerilog language, obtain a second data flow summary of the interaction data by using an RSA encryption algorithm implemented based on the Verilog language, and obtain a third data flow summary of the interaction data by using a second summary algorithm implemented based on the Verilog language, wherein the first data flow summary, the second data flow summary, and the third data flow summary have the same bit width;

[0084] The digest judgment module 24 is used to judge whether the first public key digest and the second public key digest are consistent, and obtain a public key judgment result; judge whether the first data flow digest, the second data flow digest and the third data flow digest are consistent, and obtain a data flow judgment result;

[0085] The data judgment module 25 is used to determine whether the interactive data has been tampered with or part of the data has been lost according to the public key judgment result and the data judgment result.

[0086] For the specific definition of the interactive data verification device of the programmable device, please refer to the definition of the interactive data verification method of the programmable device above, which will not be repeated here. Each module in the interactive data verification device of the above-mentioned programmable device can be implemented in whole or in part based on software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0087] Figure 3 Schematic diagram of the structure of the electronic device according to the third embodiment of the present invention. Figure 3 As shown, the electronic device 30 includes a processor 31 and a memory 32 coupled to the processor 31 .

[0088] The memory 32 stores program instructions for implementing the interactive data verification method for a programmable device according to any of the above embodiments.

[0089] The processor 31 is used to execute program instructions stored in the memory 32 to process the pollution monitoring data.

[0090] The processor 31 may also be referred to as a CPU (Central Processing Unit). The processor 31 may be an integrated circuit chip having signal processing capabilities. The processor 31 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0091] See also Figure 4 , Figure 4 Schematic diagram of the structure of the storage medium of the fourth embodiment of the present invention. The storage medium 40 of the fourth embodiment of the present invention stores program instructions 41 that can implement all the above methods, wherein the program instructions 41 can be stored in the above storage medium in the form of a software product, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or terminal devices such as a computer, a server, a mobile phone, and a tablet.

[0092] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented based on other methods. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection based on some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0093] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional units. The above is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present invention.

[0094] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware based on a computer program. The computer program can be stored in a non-volatile and / or volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0095] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the present invention only takes the division of the above-mentioned functional units and modules as examples. In actual applications, the above-mentioned functions can be distributed to different functional units and modules as needed, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

Claims

1. A method for interactive data verification of a programmable device, characterized in that: include: Acquire interaction data to be verified, wherein the interaction data includes a public key to be verified, a private key to be verified, a modulus to be verified, and a data stream to be verified; Obtain a first public key digest of the interaction data by using a first digest algorithm implemented based on the Verilog language, and obtain a second public key digest of the interaction data by using a first digest algorithm implemented based on the SystemVerilog language, wherein the first public key digest and the second public key digest have the same bit width; Obtaining a first data stream digest of the interactive data by using an RSA encryption algorithm implemented based on the SystemVerilog language, obtaining a second data stream digest of the interactive data by using an RSA encryption algorithm implemented based on the Verilog language, and obtaining a third data stream digest of the interactive data by using a second digest algorithm implemented based on the Verilog language, wherein the first data stream digest, the second data stream digest, and the third data stream digest have the same bit width; Determine whether the first public key digest and the second public key digest are consistent, and obtain a public key determination result; determine whether the first data flow digest, the second data flow digest and the third data flow digest are consistent, and obtain a data flow determination result; Determine whether the interactive data has been tampered with or part of the data is lost according to the public key judgment result and the data judgment result.

2. The method according to claim 1, characterized in that The method of obtaining a first public key digest of the interaction data by using a first digest algorithm implemented based on the Verilog language, and obtaining a second public key digest of the interaction data by using a first digest algorithm implemented based on the SystemVerilog language, includes: Driving the public key to be verified into a first digest algorithm implemented based on the Verilog language to obtain a first public key digest; The public key to be verified is driven into a first digest algorithm implemented based on the SystemVerilog language to obtain a second public key digest.

3. The method according to claim 1, characterized in that The step of obtaining a first data stream summary of the interactive data by using an RSA encryption algorithm implemented based on the Verilog language, and obtaining a second data stream summary of the interactive data by using an RSA encryption algorithm implemented based on the Verilog language, comprises: Driving the data stream to be verified into a second digest algorithm implemented based on the SystemVerilog language to obtain a front-end data digest; Driving the preceding data summary, the private key to be verified, and the modulus to be verified into an RSA encryption algorithm implemented based on the SystemVerilog language to obtain authentication data with a signature; The authentication data is driven into an RSA encryption algorithm implemented based on the Verilog language and an RSA encryption algorithm implemented based on the SystemVerilog language respectively to obtain the first data stream digest and the second data stream digest.

4. The method according to claim 1, 2 or 3, characterized in that: The step of obtaining a third data stream summary of the interaction data by using a second summary algorithm implemented based on the Verilog language includes: The data stream to be verified is driven into a second digest algorithm implemented based on the Verilog language to obtain a third data stream digest.

5. The method according to claim 4, characterized in that The determining, according to the public key judgment result and the data judgment result, whether the interactive data has been tampered with or part of the data has been lost includes: Determine whether the public key judgment result and the data judgment result are both yes, and obtain a data verification result; If the data verification result is yes, the interactive data of the programmable device has not been tampered with and no data has been lost during the interactive data process; If the data verification result is no, then the interactive data of the programmable device has been tampered with during the interactive data process or part of the data has been lost.

6. The method according to claim 1, characterized in that The first digest algorithm and / or the second digest algorithm is one of a SHA-2 algorithm, a SHA-3 algorithm and a MessageDigest algorithm, and a bit width of the first data stream digest is not less than 1024 bits.

7. The method according to claim 6, characterized in that The first digest algorithm is one of the SHA3-224 algorithm, the SHA3-256 algorithm, the SHA3-384 algorithm, the SHA3-512 algorithm, the SHAKE128 algorithm and the SHAKE256 algorithm, the second digest algorithm is the SHAKE128 algorithm or the SHAKE256 algorithm, and the bit width of the first data stream digest is 4096 bits.

8. An interactive data verification device for a programmable device, characterized in that: include: An interactive data acquisition module, used to obtain interactive data to be verified, wherein the interactive data includes a public key to be verified, a private key to be verified, a modulus to be verified, and a data stream to be verified; A public key digest generation module, used for obtaining a first public key digest of the interaction data by using a first digest algorithm implemented based on the Verilog language, and obtaining a second public key digest of the interaction data by using a first digest algorithm implemented based on the SystemVerilog language, wherein the first public key digest and the second public key digest have the same bit width; a data flow summary generation module, used for obtaining a first data flow summary of the interaction data by using an RSA encryption algorithm implemented based on the SystemVerilog language, obtaining a second data flow summary of the interaction data by using an RSA encryption algorithm implemented based on the Verilog language, and obtaining a third data flow summary of the interaction data by using a second summary algorithm implemented based on the Verilog language, wherein the first data flow summary, the second data flow summary, and the third data flow summary have the same bit width; a digest judgment module, configured to judge whether the first public key digest and the second public key digest are consistent, and obtain a public key judgment result; and judge whether the first data flow digest, the second data flow digest and the third data flow digest are consistent, and obtain a data flow judgment result; The data judgment module is used to determine whether the interactive data has been tampered with or part of the data is lost according to the public key judgment result and the data judgment result.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the interactive data verification method of the programmable device as claimed in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the interactive data verification method of a programmable device as claimed in any one of claims 1 to 7 are implemented.

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