Display device and method for manufacturing the same

Abstract

The display device may include: a substrate including a pixel region; and a pixel disposed in each of the pixel regions. Each pixel may include: a transistor and a driving voltage line disposed on the substrate; a first electrode and a second electrode spaced apart from each other; a bank pattern disposed on each of the first electrode and the second electrode; an intermediate layer disposed on the bank pattern; a light emitting element disposed between two adjacent intermediate layers; a first contact electrode disposed on one of the two adjacent intermediate layers and connected to one of the two ends of each of the light emitting elements; and a second contact electrode disposed on the other of the two adjacent intermediate layers and connected to the other of the two ends of each of the light emitting elements.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] As interest in information display increases and demand for using portable information media increases, demand and commercialization of display devices come into focus. Summary of the invention

[0003] Technical issues

[0004] An object of the present disclosure is to provide a display device in which a manufacturing process is simplified while the degree of alignment of light emitting elements is improved.

[0005] In addition, an object of the present disclosure is to provide a display device capable of improving the degree of alignment of light emitting elements by minimizing defects occurring during alignment of the light emitting elements.

[0006] In addition, an object of the present disclosure is to provide a method for manufacturing the above-mentioned display device.

[0007] Technical Solution

[0008] According to an embodiment of the present disclosure, a display device may include: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas, the non-display area surrounding the display area; and a pixel disposed in each of the plurality of pixel areas.

[0009] In an embodiment of the present disclosure, a pixel may include: a driving voltage line and at least one transistor, which are arranged on a substrate; a first electrode and a second electrode, which extend in one direction on the at least one transistor and the driving voltage line and are spaced apart from each other; a dam pattern, which is respectively arranged on the first electrode and the second electrode; an intermediate layer, which is arranged on the dam pattern; a plurality of light-emitting elements, which are arranged between two intermediate layers adjacent to each other in another direction intersecting the one direction; a first contact electrode, which is arranged on one of the two adjacent intermediate layers and connected to one of the two ends of each of the plurality of light-emitting elements; and a second contact electrode, which is arranged on the remaining intermediate layer of the two adjacent intermediate layers and connected to the remaining of the two ends of each of the plurality of light-emitting elements.

[0010] In an embodiment of the present disclosure, the intermediate layer may include an insulating material.

[0011] In an embodiment of the present disclosure, the intermediate layer may be a multilayer in which at least three double layers are sequentially stacked, the double layers being formed by stacking a first inorganic insulating layer and a second inorganic insulating layer. Here, the refractive indices of the first inorganic insulating layer and the second inorganic insulating layer may be different from each other.

[0012] In an embodiment of the present disclosure, one of the first contact electrode and the second contact electrode may be electrically connected to the transistor, and the remaining contact electrode may be electrically connected to the driving voltage line.

[0013] In the embodiment of the present disclosure, the first electrode and the second electrode may be disposed in the same layer, or may be disposed in different layers.

[0014] In an embodiment of the present disclosure, each of the first electrode and the second electrode may extend in one direction and may be provided in common with respect to adjacent pixels positioned in the same pixel column as the pixel.

[0015] In an embodiment of the present disclosure, the intermediate layer may include a conductive material.

[0016] In an embodiment of the present disclosure, one intermediate layer may be provided in a pixel, and the remaining intermediate layers may be provided in common to the pixel and adjacent pixels.

[0017] In an embodiment of the present disclosure, the pixel may further include an insulating layer disposed between the first and second electrodes and the bank pattern.

[0018] In an embodiment of the present disclosure, one intermediate layer and one of the first electrode and the second electrode, an insulating layer disposed between the intermediate layer and the one electrode, and a bank pattern corresponding to the one electrode may form a capacitor. In addition, the remaining intermediate layer and the remaining electrode of the first electrode and the second electrode, an insulating layer disposed between the remaining intermediate layer and the remaining electrode, and a bank pattern corresponding to the remaining electrode may form a capacitor.

[0019] In an embodiment of the present disclosure, the pixel may further include a first sub-electrode and a second sub-electrode disposed on the insulating layer, extending in one direction and spaced apart from each other. Here, the first sub-electrode may overlap the first electrode, and the second sub-electrode may overlap the second electrode.

[0020] In an embodiment of the present disclosure, the first electrode and the first sub-electrode and the insulating layer disposed between the first electrode and the first sub-electrode may form a capacitor. The second electrode and the second sub-electrode and the insulating layer disposed between the second electrode and the second sub-electrode may form a capacitor.

[0021] In an embodiment of the present disclosure, one intermediate layer may cover the first sub-electrode and may be electrically connected to the first sub-electrode, and the remaining intermediate layer may cover the second sub-electrode and may be electrically connected to the second sub-electrode.

[0022] In the embodiment of the present disclosure, the intermediate layer may overlap each of the first electrode and the second electrode when viewed in a plan view.

[0023] The display device according to the above-described embodiment may be manufactured by including a pixel provided in each pixel region.

[0024] In an embodiment of the present disclosure, setting a pixel may include: forming a driving voltage line and at least one transistor on a substrate; forming an interlayer insulating layer on the transistor and the driving voltage line; forming a first electrode and a second electrode extending in one direction and spaced apart from each other on the interlayer insulating layer; forming a dam pattern on the first electrode and the second electrode; forming an intermediate layer on the dam pattern; inputting a plurality of light-emitting elements, and then aligning the plurality of light-emitting elements between two intermediate layers adjacent to each other in another direction intersecting the one direction by applying an alignment signal corresponding to each of the first electrode and the second electrode; forming an insulating layer on the upper surface of each of the plurality of light-emitting elements; and forming a first contact electrode and a second contact electrode on the insulating layer.

[0025] Beneficial Effects

[0026] According to the embodiments of the present disclosure, the degree of alignment of the light emitting elements can be improved by separating a configuration for aligning the light emitting elements and a configuration for driving the light emitting elements so as to accurately align the light emitting elements in a desired area.

[0027] In addition, according to the embodiments of the present disclosure, a display device with a simplified manufacturing process can be provided by aligning a light emitting element in each pixel using a conductive line provided in a pixel circuit portion, thereby omitting a separate process of lines for alignment of the light emitting elements.

[0028] In addition, according to an embodiment of the present disclosure, a method of manufacturing the above-mentioned display device can be provided.

[0029] The effects according to the embodiments of the present disclosure are not limited to the contents exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1a is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0031] Figure 1b yes Figure 1a A cross-sectional view of a light-emitting element.

[0032] Figure 2a is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure.

[0033] Figure 2b yes Figure 2a A cross-sectional view of a light-emitting element.

[0034] Figure 3ais a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure.

[0035] Figure 3b yes Figure 3a A cross-sectional view of a light-emitting element.

[0036] Figure 4a is a perspective view schematically showing a light emitting element according to still another embodiment of the present disclosure.

[0037] Figure 4b yes Figure 4a A cross-sectional view of a light-emitting element.

[0038] Figure 5 is a diagram showing a display device according to an embodiment of the present disclosure, specifically, using Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b A schematic plan view of a display device using any one of the light-emitting elements shown in FIG. 1 as a light source.

[0039] Figures 6a to 6e is a diagram showing various embodiments including Figure 5 A circuit diagram showing the electrical connection relationship between components in one pixel.

[0040] Figure 7 It is schematically shown Figure 5 A plan view of one of the pixels shown in .

[0041] Figure 8 It is along Figure 7 A cross-sectional view taken along line I-I'.

[0042] Fig. 9 yes Figure 8 An enlarged cross-sectional view of portion EA1.

[0043] Fig.10 It is along Figure 7 A cross-sectional view taken along line II to II'.

[0044] Fig.11 According to another embodiment, Fig.10 The embodiment of the first bank pattern shown in Figure 7 A cross-sectional view corresponding to line II to II'.

[0045] Fig.12 According to another embodiment, Fig.11 The embodiment of the display element portion shown in Figure 7 A cross-sectional view corresponding to line II to II'.

[0046] Figures 13a to 13h The manufacturing sequence is shown in Figure 8 A cross-sectional view of the method for one pixel is shown in FIG.

[0047] Fig.14 and Fig.15 The display device according to the embodiment of the present disclosure is schematically shown. Figure 7 A cross-sectional view corresponding to line II to II'.

[0048] Fig.16 It is only schematically shown Figure 5 A plan view of some signal lines each of which transmits a predetermined signal in pixels in a display device shown in FIG. 1 and pads connected to the some signal lines.

[0049] Fig.17 yes Fig.16 An enlarged plan view of portion EA2.

[0050] Figures 18a to 18c It is along Fig.17 A cross-sectional view taken along line III-III'.

[0051] Fig.19 It is along Fig.17 A cross-sectional view taken along line IV to IV'.

[0052] Fig. 20 According to another embodiment, Fig.19 The embodiment of the first bank pattern shown in Fig.17 A cross-sectional view corresponding to line IV to IV'.

[0053] Fig.21 According to another embodiment, Fig. 20 The embodiment of the display element portion shown in Fig.17 A cross-sectional view corresponding to line IV to IV'.

[0054] Figure 22a to Figure 22h The manufacturing sequence is shown in Fig.18a A cross-sectional view of the method for one pixel is shown in FIG.

[0055] Fig.23 The display device according to the embodiment of the present disclosure is schematically shown. Fig.16 The corresponding plan view of section EA2.

[0056] Fig.24 is with Fig.23 A cross-sectional view corresponding to the line V to V'.

[0057] Fig.25 is with Fig.23 A cross-sectional view corresponding to line VI~VI'. DETAILED DESCRIPTION

[0058] Since the present disclosure can be modified in various ways and have various forms, specific embodiments will be shown in the drawings and will be described in detail in the specification. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed, and the present disclosure includes all modifications, equivalents and replacements within the technical scope of the present disclosure.

[0059] When describing each of the accompanying drawings, similar reference numerals are used for similar components. In the accompanying drawings, for the purpose of clarity of the present disclosure, the size of the structure is enlarged from the actual size. Terms such as "first" and "second" can be used to describe various components, but the components should not be limited by the terms. Terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present disclosure, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0060] It should be understood that, in the present application, the terms "including" or "having" are used to illustrate the existence of the features, quantities, steps, operations, components, parts or combinations thereof described in the specification, but do not exclude the possibility of pre-existence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof. In addition, when a part of a layer, film, region or plate, etc. is referred to as "on" another part, it not only includes the case where the part is "directly on" the other part, but also includes the case where there is another part between the part and the other part. In addition, in the present specification, when a part of a layer, film, region or plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region or plate, etc. is formed "under" another part, this not only includes the case where the part is "directly under" the other part, but also includes the case where there is another part between the part and the other part.

[0061] Hereinafter, preferred embodiments of the present disclosure and other matters required for those skilled in the art to easily understand the contents of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0062] Figure 1a is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure, Figure 1b yes Figure 1aA cross-sectional view of a light emitting element, Figure 2a is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure, Figure 2b yes Figure 2a A cross-sectional view of a light emitting element, Figure 3a is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure, Figure 3b yes Figure 3a A cross-sectional view of a light emitting element, Figure 4a is a perspective view schematically showing a light emitting element according to another embodiment of the present disclosure, Figure 4b yes Figure 4a A cross-sectional view of a light-emitting element.

[0063] For convenience, in the description of the light emitting element manufactured by the etching method, Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b Next, a description is given of a light emitting element produced by the growth method. Figure 4a and Figure 4b In the embodiments of the present disclosure, the type and / or shape of the light emitting element is not limited to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b The embodiment shown in .

[0064] First, refer to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b , the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be implemented as a light emitting stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0065] According to an embodiment of the present disclosure, the light emitting element LD extends in one direction. When the extending direction of the light emitting element LD is referred to as a longitudinal direction, the light emitting element LD may have one side end and another side end along the extending direction. Any one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at one side end of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the other side end of the light emitting element LD.

[0066] The light emitting element LD may be provided in various shapes. For example, the light emitting element LD may have a rod-shaped shape, a strip-shaped shape, a column-shaped shape, etc. that is long in the longitudinal direction (i.e., the aspect ratio is greater than 1). According to an embodiment, the light emitting element LD may have a rod-shaped shape, a strip-shaped shape, a column-shaped shape, etc. that is short in the longitudinal direction (i.e., the aspect ratio is less than 1). According to another embodiment, the light emitting element LD may have a rod-shaped shape, a strip-shaped shape, a column-shaped shape, etc. that has the same length L and width. In an embodiment of the present disclosure, the length L of the light emitting element LD in the longitudinal direction may be greater than the diameter D (or the width of the cross section) of the light emitting element LD. The light emitting element LD may include, for example, a light emitting diode that is manufactured to be very small to have a diameter D and / or a length L of about nanometer to micrometer level. In an embodiment of the present disclosure, the size of the light emitting element LD may be changed to meet the required conditions (or design conditions) of the lighting device or the self-luminous display device.

[0067] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and may include an n-type semiconductor layer doped with a first conductive dopant such as Si, Ge, or Sn. However, the material constituting the first semiconductor layer 11 is not limited thereto, and various other materials may constitute the first semiconductor layer 11.

[0068] The active layer 12 may be disposed on the first semiconductor layer 11, and may be formed in a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 may be changed differently depending on the type of the light emitting element LD. The active layer 12 may emit light having a wavelength of 400nm to 900nm, and may have a double heterostructure. In an embodiment of the present disclosure, a cap layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cap layer may be formed of an AlGaN layer or an InAlGaN layer. According to an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may constitute the active layer 12.

[0069] When an electric field of a predetermined voltage or higher is applied to both ends of the light emitting element LD, the light emitting element LD emits light while electron-hole pairs are combined in the active layer 12. By controlling the light emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source for various light emitting devices including pixels of a display device.

[0070] The second semiconductor layer 13 may be disposed on the active layer 12, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant such as Mg. However, the material constituting the second semiconductor layer 13 is not limited thereto, and various other materials may constitute the second semiconductor layer 13.

[0071] In the embodiment of the present disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) from each other in the longitudinal direction of the light emitting element LD. For example, along the longitudinal direction of the light emitting element LD, the first semiconductor layer 11 may have a width relatively wider than that of the second semiconductor layer 13 (or a thickness thicker than that of the second semiconductor layer 13). Figures 1a to 3b As shown in , the active layer 12 of the light emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than the lower surface of the first semiconductor layer 11 .

[0072] According to an embodiment of the present disclosure, in addition to the above-mentioned first semiconductor layer 11, active layer 12 and second semiconductor layer 13, the light emitting element LD may further include an additional electrode 15 disposed on the second semiconductor layer 13. In addition, according to an embodiment, as Figure 3a and Figure 3b As shown in , the light emitting element LD may further include another additional electrode 16 disposed at one end of the first semiconductor layer 11 .

[0073] The additional electrodes 15 and 16 may be ohmic contact electrodes, but are not limited thereto, and according to an embodiment, the additional electrodes 15 and 16 may be Schottky contact electrodes. The additional electrodes 15 and 16 may include metals or metal oxides, for example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), oxides or alloys thereof, or ITO, etc., may be used alone or in combination, but the present disclosure is not limited thereto.

[0074] The material included in each of the additional electrodes 15 and 16 may be the same or different from each other. The additional electrodes 15 and 16 may be substantially transparent or translucent. Therefore, the light generated by the light emitting element LD may pass through the additional electrodes 15 and 16 and may be emitted to the outside of the light emitting element LD. According to an embodiment, in the case where the light generated by the light emitting element LD does not pass through the additional electrodes 15 and 16 and is emitted to the outside of the light emitting element LD through the region other than both ends of the light emitting element LD, the additional electrodes 15 and 16 may include an opaque metal.

[0075] In the embodiment of the present disclosure, the light emitting element LD may further include an insulating layer 14. However, according to the embodiment, the insulating layer 14 may be omitted or provided to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0076] The insulating layer 14 can prevent an electrical short circuit that may occur when the active layer 12 contacts a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, by forming the insulating layer 14, the life and efficiency of the light-emitting element LD can be improved by minimizing surface defects of the light-emitting element LD. In addition, in the case where a plurality of light-emitting elements LD are closely arranged, the insulating layer 14 can prevent an undesirable short circuit that may occur between the light-emitting elements LD. In the case where the active layer 12 can prevent a short circuit with an external conductive material, the presence or absence of the insulating layer 14 is not limited.

[0077] like Figure 1a and Figure 1b As shown in FIG. 1 , the insulating layer 14 may be provided in a form that completely surrounds the outer peripheral surface of the light emitting stack including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and the additional electrode 15. For ease of description, Figure 1a A portion of the insulating layer 14 is removed, and the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the additional electrode 15 included in the actual light emitting element LD may be surrounded by the insulating layer 14 .

[0078] In the above-described embodiment, the insulating layer 14 completely surrounds the outer peripheral surface of each of the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the additional electrode 15 , but the present disclosure is not limited thereto.

[0079] According to an embodiment, Figure 2a and Figure 2b As shown in , the insulating layer 14 may surround the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and may not completely surround the outer peripheral surface of the additional electrode 15 provided on the second semiconductor layer 13, or may surround only a portion of the outer peripheral surface of the additional electrode 15 and may not surround the remaining portion of the outer peripheral surface of the additional electrode 15. However, the insulating layer 14 may expose at least both ends of the light emitting element LD, for example, the insulating layer 14 may expose one end of the first semiconductor layer 11 and the additional electrode 15 provided at one end of the second semiconductor layer 13. In addition, according to the embodiment, as Figure 3a and Figure 3b As shown in FIG. 1 , in the case where the additional electrodes 15 and 16 are provided at both ends of the light emitting element LD, the insulating layer 14 may expose at least one region of each of the additional electrodes 15 and 16. As another example, in another embodiment, the insulating layer 14 may not be provided.

[0080] According to an embodiment of the present disclosure, the insulating layer 14 may include a transparent insulating material. For example, the insulating layer 14 may include a transparent insulating material made of SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 One or more insulating materials selected from the group consisting of, but not limited thereto, various materials having insulating properties may be used. The insulating layer 14 may be provided in the form of a single layer, or may be provided in the form of multiple layers including at least a double layer.

[0081] In the case where the insulating layer 14 is provided for the light emitting element LD, a short circuit between the active layer 12 and the first electrode and / or the second electrode (not shown) can be prevented. In addition, by forming the insulating layer 14, the life and efficiency of the light emitting element LD can be improved by minimizing surface defects of the light emitting element LD. In addition, in the case where a plurality of light emitting elements LD are closely arranged, the insulating layer 14 can prevent an undesirable short circuit that may occur between the light emitting elements LD.

[0082] The above-mentioned light emitting element LD can be used as a light source of various display devices. The light emitting element LD can be manufactured by a surface treatment process. For example, in the case where a plurality of light emitting elements LD are mixed in a fluid solution (or solvent) and supplied to each emission area (for example, the emission area of ​​each pixel or the emission area of ​​each sub-pixel), each of the light emitting elements LD can be subjected to surface treatment so that the light emitting elements LD can be uniformly sprayed without being unevenly aggregated in the solution.

[0083] The light-emitting device including the above-mentioned light-emitting element LD can be used in various types of devices (including display devices) that require a light source. For example, in the case where a plurality of light-emitting elements LD are arranged in the emission region of each pixel of the display panel, the light-emitting element LD can be used as a light source for each of the pixels. However, the application field of the light-emitting element LD is not limited to the above-mentioned example. For example, the light-emitting element LD can be used in other types of devices (such as lighting devices) that require a light source.

[0084] Next, refer to Figure 4a and Figure 4b The light emitting element LD manufactured by the growth method is described.

[0085] When describing the light-emitting element LD manufactured by the growth method, the present disclosure is described based on the points different from the above-mentioned embodiments, and the parts not specifically described in the light-emitting element LD manufactured by the growth method follow the above-mentioned embodiments, and the same figure marks are given to components similar and / or identical to those of the above-mentioned embodiments.

[0086] Reference Figure 4a and Figure 4b , the light emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. According to an embodiment, the light emitting element LD may include a light emitting pattern 10 of a core-shell structure, the light emitting pattern 10 of the core-shell structure including the first semiconductor layer 11 positioned at the center, the active layer 12 surrounding at least one side of the first semiconductor layer 11, the second semiconductor layer 13 surrounding at least one side of the active layer 12, and the additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0087] The light emitting element LD may be arranged in a polygonal trumpet shape extending in one direction. For example, the light emitting element LD may be arranged in a hexagonal trumpet shape. In the case where the extending direction of the light emitting element LD is referred to as the longitudinal direction, the light emitting element LD may have one end (or lower end) and the other end (or upper end) along the longitudinal direction. A portion of one of the first semiconductor layer 11 and the second semiconductor layer 13 may be exposed at one end (or lower end) of the light emitting element LD, and a portion of the other semiconductor layer of the first semiconductor layer 11 and the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light emitting element LD. For example, a portion of the first semiconductor layer 11 may be exposed at one end (or lower end) of the light emitting element LD, and a portion of the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light emitting element LD. In this case, in the case where the light emitting element LD is used as a light source of a display device, the exposed portion of the first semiconductor layer 11 may be in contact with one of the driving electrodes driving the light emitting element LD, and the exposed portion of the second semiconductor layer 13 may be in contact with the other driving electrode.

[0088] According to an embodiment, in the case where the light emitting element LD includes the additional electrode 15, a portion of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light emitting element LD. In this case, when the light emitting element LD is used as a light source of a display device, the exposed portion of the additional electrode 15 may be in contact with another driving electrode and may be electrically connected to one electrode.

[0089] In an embodiment of the present disclosure, the first semiconductor layer 11 may be positioned at the core (i.e., the center of the light emitting element LD). The light emitting element LD may be provided in a shape corresponding to the shape of the first semiconductor layer 11. For example, in the case where the first semiconductor layer 11 has a hexagonal trumpet shape, the light emitting element LD or the light emission pattern 10 may also have a hexagonal trumpet shape.

[0090] The active layer 12 may be disposed and / or formed in a shape surrounding the outer peripheral surface of the first semiconductor layer 11 in the longitudinal direction of the light emitting element LD. Specifically, the active layer 12 may be disposed and / or formed in a shape surrounding the remaining area of ​​the first semiconductor layer 11 except for one end disposed at the lower side of both ends in the longitudinal direction of the light emitting element LD.

[0091] The second semiconductor layer 13 may be disposed and / or formed in a shape surrounding the active layer 12 in the longitudinal direction of the light emitting element LD, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

[0092] In an embodiment of the present disclosure, the light emitting element LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 may be an ohmic contact electrode or a Schottky contact electrode electrically connected to the second semiconductor layer 13, but is not limited thereto.

[0093] As described above, the light emitting element LD may be configured in a hexagonal trumpet shape having a shape in which both ends protrude, and may be implemented as a core-shell structured light emitting pattern 10 including a first semiconductor layer 11 disposed at the center thereof, an active layer 12 surrounding the first semiconductor layer 11, a second semiconductor layer 13 surrounding the active layer 12, and an additional electrode 15 surrounding the second semiconductor layer 13. The first semiconductor layer 11 may be disposed at one end (or lower end) of the light emitting element LD having the hexagonal trumpet shape, and the additional electrode 15 may be disposed at the other end (or upper end) of the light emitting element LD.

[0094] In addition, according to the embodiment, the light emitting element LD may further include an insulating layer 14 disposed on the outer peripheral surface of the core-shell structured light emission pattern 10. The insulating layer 14 may include a transparent insulating material.

[0095] Figure 5 is a diagram showing a display device according to an embodiment of the present disclosure, specifically, using Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b A schematic plan view of a display device using any one of the light-emitting elements shown in FIG. 1 as a light source.

[0096] exist Figure 5In the figure, for convenience, the structure of the display device is briefly shown based on the display area of ​​the display image. However, according to an embodiment, at least one driving circuit part (for example, a scan driver and a data driver, etc.) and / or a plurality of signal lines not shown may be further provided in the display device.

[0097] Reference Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a , Figure 4b and Figure 5 According to an embodiment of the present disclosure, a display device may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and including at least one light emitting element LD, a driver (not shown) disposed on the substrate SUB and driving the pixels PXL, and a line portion (not shown) connecting the pixels PXL and the driver to each other.

[0098] The display device can be classified into a passive matrix type display device and an active matrix type display device according to a method of driving the light emitting element LD. For example, in the case where the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor that controls the amount of current supplied to the light emitting element LD and a switching transistor that transmits a data signal to the driving transistor, etc.

[0099] Recently, active matrix display devices that select and light up each pixel PXL based on resolution, contrast, and operating speed have become mainstream, but the present disclosure is not limited to this, and a passive matrix display device that performs lighting on each pixel PXL may also use components for driving the light-emitting element LD (for example, a first electrode and a second electrode, etc.).

[0100] The substrate SUB may include a display area DA and a non-display area NDA.

[0101] According to an embodiment, the display area DA may be disposed in the central area of ​​the display device, and the non-display area NDA may be disposed in the edge area of ​​the display device to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and the positions of the display area DA and the non-display area NDA may be changed.

[0102] The display area DA may be an area where pixels PXL displaying an image are disposed. The non-display area NDA may be an area where a driver for driving the pixels PXL and a portion of a line portion connecting the pixels PXL and the driver to each other are disposed.

[0103] The display area DA may have various shapes. For example, the display area DA may be set as a polygon of a closed shape including sides formed by straight lines. In addition, the display area DA may be set in a circular shape and / or an elliptical shape including sides formed by curved lines. In addition, the display area DA may be set in various shapes such as a semicircle and a semiellipse including sides formed by straight lines and curved lines.

[0104] The non-display area NDA may be disposed at at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround a periphery (or edge) of the display area DA.

[0105] The substrate SUB may include a transparent insulating material and may transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

[0106] One area of ​​the substrate SUB may be set as a display area DA where the pixel PXL is set, and the remaining area of ​​the substrate SUB may be set as a non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel area where each pixel PXL is set, and a non-display area NDA set around the display area DA.

[0107] Each of the pixels PXL may be disposed in the display area DA on the substrate SUB. In an embodiment of the present disclosure, the pixels PXL may be arranged in the display area DA in a stripe or pentile array structure, but the present disclosure is not limited thereto.

[0108] Each of the pixels PXL may include at least one light emitting element LD driven by a corresponding scan signal and a data signal. The light emitting element LD may have a size as small as nanometer to micrometer and may be connected in parallel with adjacent light emitting elements, but the present disclosure is not limited thereto. The light emitting element LD may constitute a light source of each pixel PXL.

[0109] Each of the pixels PXL may include at least one light source driven by a predetermined signal (e.g., a scan signal and a data signal) and / or a predetermined power (e.g., a first driving power and a second driving power). For example, each pixel PXL may include at least one ultra-small light emitting element LD having Figures 1a to 4b The small size of about nanometer order to micrometer order shown in each of the embodiments of FIG. However, the type of the light emitting element LD that can be used as the light source of each pixel PXL is not limited thereto.

[0110] In the embodiment of the present disclosure, the color, type, and / or number of the pixels PXL are not particularly limited, and for example, the color of light emitted from each pixel PXL may be changed differently.

[0111] The driver may provide a predetermined signal and a predetermined power to each pixel PXL through the line portion, thereby controlling the driving of the pixel PXL. Figure 5 In the figure, for the convenience of description, the line part is omitted.

[0112] The driver may include a scan driver that provides a scan signal to the pixel PXL through a scan line, an emission driver that provides an emission control signal to the pixel PXL through an emission control line, a data driver that provides a data signal to the pixel PXL through a data line, and a timing controller. The timing controller may control the scan driver, the emission driver, and the data driver.

[0113] Figures 6a to 6e is a diagram showing various embodiments including Figure 5 A circuit diagram showing the electrical connection relationship between components in one pixel shown in FIG.

[0114] For example, according to various embodiments, Figures 6a to 6e The electrical connection relationship between components included in the pixel PXL that can be applied to an active type display device is shown. However, the types of components included in the pixel PXL to which the embodiments of the present disclosure can be applied are not limited thereto.

[0115] exist Figures 6a to 6e In, not only Figure 5 The components in each of the pixels shown in FIG. 1 and the area where the components are arranged are referred to as a pixel PXL. According to an embodiment, Figures 6a to 6e Each pixel PXL shown in FIG. 1 may be included in Figure 5 In any one of the pixels PXL in the display device of the present invention, the pixel PXL may have substantially the same or similar structure.

[0116] Reference Figures 1a to 4b , Figure 5 as well as Figures 6a to 6e One pixel PXL (hereinafter referred to as "pixel") may include an emission unit EMU that generates light of brightness corresponding to a data signal. In addition, the pixel PXL may further selectively include a pixel circuit 144 for driving the emission unit EMU.

[0117] According to an embodiment, the emission unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 to which a first driving power VDD is applied and a second power line PL2 to which a second driving power VSS is applied. For example, the emission unit EMU may include a first electrode EL1 (or "first alignment electrode") connected to the first driving power VDD via the pixel circuit 144 and the first power line PL1, a second electrode EL2 (or "second alignment electrode") connected to the second driving power VSS via the second power line PL2, and a plurality of light emitting elements LD connected in parallel in the same direction. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0118] In an embodiment of the present disclosure, each of the light-emitting elements LD included in the emission unit EMU may include a first end connected to a first drive power VDD through a first electrode EL1 and a second end connected to a second drive power VSS through a second electrode EL2. The first drive power VDD and the second drive power VSS may have different potentials. For example, the first drive power VDD may be set to a high potential power, and the second drive power VSS may be set to a low potential power. At this time, during the light emission period of the pixel PXL, the potential difference between the first drive power VDD and the second drive power VSS may be set to a threshold voltage of the light-emitting element LD or a higher voltage.

[0119] As described above, each light emitting element LD connected in parallel in the same direction (eg, forward direction) between the first electrode EL1 and the second electrode EL2 to which voltages of different potentials are supplied can constitute each effective light source. Such effective light sources can be gathered to form an emission unit EMU of the pixel PXL.

[0120] The light emitting element LD of the emission unit EMU can emit light having a brightness corresponding to the driving current supplied by the corresponding pixel circuit 144. For example, the pixel circuit 144 can supply a driving current corresponding to the grayscale value of the corresponding frame data to the emission unit EMU during each frame period. The driving current supplied to the emission unit EMU can be shunted and flow to the light emitting elements LD connected in the same direction. Therefore, each of the light emitting elements LD can emit light having a brightness corresponding to the current flowing through the light emitting element LD, and thus the emission unit EMU can emit light having a brightness corresponding to the driving current.

[0121] at the same time, Figures 6a to 6cAn embodiment in which the light emitting element LD is connected in the same direction between the first driving power VDD and the second driving power VSS is shown, but the present disclosure is not limited thereto. According to an embodiment, the emission unit EMU may further include at least one ineffective light source in addition to the light emitting element LD constituting each effective light source. For example, Figure 6d and Figure 6e As shown in , at least one reverse light emitting element LDr may be further connected between the first electrode EL1 and the second electrode EL2 of the emission unit EMU. The reverse light emitting element LDr may be connected in parallel between the first electrode EL1 and the second electrode EL2 together with the light emitting element LD constituting the effective light source, and may be connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to that of the light emitting element LD. Even if a predetermined driving voltage (e.g., a driving voltage in the forward direction) is applied between the first electrode EL1 and the second electrode EL2, the reverse light emitting element LDr remains in an inactive state, so that current substantially does not flow through the reverse light emitting element LDr.

[0122] The pixel circuit 144 may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, in the case where the pixel PXL is disposed in the i-th (i is a positive integer)-th row and the j-th (j is a positive integer)-th column of the display area DA, the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. Figure 6a and Figure 6b As shown in FIG. 1 , the pixel circuit 144 may include a first transistor T1, a second transistor T2 and a storage capacitor Cst. However, the structure of the pixel circuit 144 is not limited to Figure 6a and Figure 6b The embodiment shown in .

[0123] First, refer to Figure 6a , the pixel circuit 144 may include first and second transistors T1 and T2 and a storage capacitor Cst.

[0124] A first terminal of the second transistor T2 (switching transistor) may be connected to the data line Dj, and a second terminal may be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 may be different terminals, for example, when the first terminal is a source electrode, the second terminal may be a drain electrode. In addition, a gate electrode of the second transistor T2 may be connected to the scan line Si.

[0125] The second transistor T2 can be turned on when a scan signal of a voltage (e.g., a low voltage) from the scan line Si is supplied to turn on the second transistor T2, so that the data line Dj and the first node N1 are electrically connected to each other. At this time, a data signal of a corresponding frame is supplied to the data line Dj, and thus the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 is charged in the storage capacitor Cst.

[0126] A first terminal of the first transistor T1 (driving transistor) may be connected to a first driving power VDD, and a second terminal may be electrically connected to a first electrode EL1 of each of the light emitting elements LD. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 controls the amount of driving current supplied to the light emitting element LD in response to a voltage of the first node N1.

[0127] One electrode of the storage capacitor Cst may be connected to the first driving power VDD, and the other electrode may be connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1 and maintains the charged voltage until a data signal of the next frame is supplied.

[0128] Figure 6a and Figure 6b Each of them shows a pixel circuit 144, which includes a second transistor T2 for transmitting a data signal to the pixel PXL, a storage capacitor Cst for storing the data signal, and a first transistor T1 for supplying a driving current corresponding to the data signal to the light emitting element LD.

[0129] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 may be modified and implemented differently. For example, the pixel circuit 144 may include a transistor element for compensating for the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the light emission time of the light emitting element LD, and may include other circuit elements such as a boost capacitor for boosting the voltage of the first node N1.

[0130] In addition, Figure 6a In the embodiment, the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit 144 are P-type transistors, but the present disclosure is not limited thereto. That is, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be changed to an N-type transistor.

[0131] Next, refer to Figures 1a to 4b , Figure 5 as well as Figure 6bAccording to an embodiment of the present invention, the first transistor T1 and the second transistor T2 can be implemented as N-type transistors. In addition to the change in the connection position of some components due to the change in transistor type, Figure 6b The configuration or operation of the pixel circuit 144 shown in FIG. Figure 6a The configuration or operation of the pixel circuit 144 is similar. Therefore, a description thereof will be provided briefly.

[0132] In the embodiments of the present disclosure, Figure 6b The pixel circuit 144 shown in FIG. 1 may include a first transistor T1 and a second transistor T2 formed of N-type transistors and a storage capacitor Cst. In the case where the first transistor T1 and the second transistor T2 are formed of N-type transistors, in order to stabilize the storage capacitor Cst charged with a voltage corresponding to the data signal supplied to the first node N1, the emission unit EMU may be connected between the first driving power VDD and the pixel circuit 144. However, the present disclosure is not limited thereto, and according to an embodiment, Figure 6b The emission unit EMU shown in FIG. 1 may be connected between the pixel circuit 144 and the second driving power VSS. In the embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figure 6a and Figure 6b For example, the pixel circuit 144 can be constructed as follows Figure 6c and Figure 6d Pixel circuit 144 in the embodiment shown in .

[0133] like Figure 6c and Figure 6d As shown in , the pixel circuit 144 can be connected to the scan line Si and the data line Dj of the pixel PXL. For example, when the pixel PXL is arranged in the i-th row and the j-th column of the display area DA, the pixel circuit 144 of the corresponding pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0134] In addition, according to an embodiment, the pixel circuit 144 may also be connected to at least another scan line. For example, the pixel PXL disposed in the i-th row of the display area DA may also be connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In addition, according to an embodiment, the pixel circuit 144 may also be connected to a third power in addition to the first drive power VDD and the second drive power VSS. For example, the pixel circuit 144 may also be connected to a power line to which the initialization power Vint is applied.

[0135] The pixel circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0136] One electrode (e.g., source electrode) of the first transistor T1 (driving transistor) may be connected to the first driving power VDD via the fifth transistor T5, and the other electrode (e.g., drain electrode) may be connected to one side end of the light emitting element LD via the sixth transistor T6. In addition, the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 controls the driving current flowing between the first driving power VDD and the second driving power VSS via the light emitting element LD in response to the voltage of the first node N1.

[0137] The second transistor T2 (switching transistor) may be connected between the j-th data line Dj connected to the pixel PXL and the source electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 may be connected to the i-th scan line Si connected to the pixel PXL. The second transistor T2 may be turned on when a scan signal of a gate-on voltage (e.g., a low voltage) is supplied to the i-th scan line Si, so that the j-th data line Dj is electrically connected to the source electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj is transmitted to the first transistor T1.

[0138] The third transistor T3 may be connected between the drain electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 may be connected to the i-th scan line Si. The third transistor T3 may be turned on when a scan signal of a gate-on voltage is supplied to the i-th scan line Si, so that the drain electrode of the first transistor T1 and the first node N1 are electrically connected to each other.

[0139] The fourth transistor T4 may be connected between the first node N1 and the power line to which the initialization power Vint is applied. In addition, the gate electrode of the fourth transistor T4 may be connected to a previous scan line, for example, the i-1th scan line Si-1. The fourth transistor T4 may be turned on when a scan signal of a gate-on voltage is supplied to the i-1th scan line Si-1 to transmit the voltage of the initialization power Vint to the first node N1. Here, the initialization power Vint may have a voltage equal to or less than the lowest voltage of the data signal.

[0140] The fifth transistor T5 may be connected between the first driving power VDD and the first transistor T1. In addition, the gate electrode of the fifth transistor T5 may be connected to a corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal of a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0141] The sixth transistor T6 may be connected between the first transistor T1 and one end of the light emitting element LD. In addition, the gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. The sixth transistor T6 may be turned off when the emission control signal of the gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0142] The seventh transistor T7 may be connected between one end of the light emitting element LD (or the second node N2) and the power line to which the initialization power Vint is applied. In addition, the gate electrode of the seventh transistor T7 may be connected to any one of the next scan lines, for example, the i+1th scan line Si+1. The seventh transistor T7 may be turned on when a scan signal of a gate-on voltage is supplied to the i+1th scan line Si+1, so that the voltage of the initialization power Vint is supplied to one end of the light emitting element LD.

[0143] The storage capacitor Cst may be connected between the first driving power VDD and the first node N1. The storage capacitor Cst may store the data signal supplied to the first node N1 and a voltage corresponding to the threshold voltage of the first transistor T1 during each frame period.

[0144] exist Figure 6c and Figure 6d In the embodiment, the transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit 144 are P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0145] In the embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figures 6a to 6d For example, the pixel circuit 144 can be constructed as follows Figure 6e Pixel circuit 144 in the embodiment shown in .

[0146] like Figure 6e As shown in , the pixel circuit 144 can also be connected to the control line CLi and the sensing line SENj. For example, the pixel circuit 144 of the pixel PXL disposed in the i-th row and j-th column of the display area DA can be connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA. Figure 6a and Figure 6b In addition to the first transistor T1 and the second transistor T2 shown in FIG. 1 , the pixel circuit 144 may further include a third transistor T3 .

[0147] The third transistor T3 is connected between the first transistor T1 and the sensing line SENj. For example, one electrode of the third transistor T3 may be connected to one terminal (e.g., source electrode) of the first transistor T1 connected to the first electrode EL1, and the other electrode of the third transistor T3 may be connected to the sensing line SENj. Meanwhile, in the case where the sensing line SENj is omitted, the other electrode of the third transistor T3 may be connected to the data line Dj.

[0148] According to an embodiment, the gate electrode of the third transistor T3 is connected to the control line CLi. Meanwhile, in the case where the control line CLi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si. The third transistor T3 may be turned on by a control signal of a gate-on voltage (e.g., a high level) supplied to the control line CLi during a predetermined sensing period to electrically connect the sensing line SENj and the first transistor T1 to each other.

[0149] According to an embodiment, the sensing period may be a period for extracting characteristic information (e.g., threshold voltage of the first transistor T1, etc.) of each of the pixels PXL provided in the display area DA. During the above-mentioned sensing period, the first transistor T1 may be turned on by supplying a predetermined reference voltage that may turn on the first transistor T1 to the first node N1 via the data line Dj and the second transistor T2, or by connecting each pixel PXL to a current source, etc. In addition, the first transistor T1 may be connected to the sensing line SENj by supplying a control signal of a gate-on voltage to the third transistor T3 to turn on the third transistor T3. Therefore, characteristic information including the threshold voltage of the first transistor T1, etc., of each pixel PXL may be extracted through the sensing line SENj. The extracted characteristic information may be used to convert image data, thereby compensating for characteristic deviations between the pixels PXL.

[0150] at the same time, Figure 6e An embodiment is disclosed in which all of the first to third transistors T1 to T3 are N-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to third transistors T1 to T3 may be changed to a P-type transistor. In addition, Figure 6e An embodiment in which the emission unit EMU is connected between the pixel circuit 144 and the second driving power VSS is disclosed, but the emission unit EMU may also be connected between the first driving power VDD and the pixel circuit 144. OLED It may be formed between the source electrode of the first transistor T1 and the second power line PL2 .

[0151] in addition, Figures 6a to 6eAn embodiment in which all of the light emitting elements LD constituting each emission unit EMU are connected in parallel is shown, but the present disclosure is not limited thereto. According to an embodiment, the emission unit EMU may be constructed to include at least one series stage including a plurality of light emitting elements LD connected in parallel to each other. That is, the emission unit EMU may be constructed in a series / parallel hybrid structure.

[0152] The structure of the pixel PXL applicable to the present disclosure is not limited to Figures 6a to 6e , and the corresponding pixels may have various structures. In addition, in another embodiment of the present disclosure, each pixel PXL may be constructed inside a passive light-emitting display device or the like. In this case, the pixel circuit 144 may be omitted, and each of the two ends of the light-emitting element LD included in the emission unit EMU may be directly connected to the scan lines Si-1, Si and Si+1, the data line Dj, the first power line PL1 to which the first drive power VDD is applied, the second power line PL2 to which the second drive power VSS is applied, and / or a predetermined control line, etc.

[0153] Figure 7 It is schematically shown Figure 5 A plan view of one of the pixels shown in , Figure 8 It is along Figure 7 A cross-sectional view taken along line I to I', Fig. 9 yes Figure 8 An enlarged cross-sectional view of part EA1, Fig.10 It is along Figure 7 A cross-sectional view taken along line II to II', Fig.11 According to another embodiment, Fig.10 The embodiment of the first bank pattern shown in Figure 7 The cross-sectional view corresponding to the line II to II', Fig.12 According to another embodiment, Fig.11 The embodiment of the display element portion shown in Figure 7 A cross-sectional view corresponding to line II to II'.

[0154] Figure 7 The pixels shown in can be Figures 6a to 6e Any one of the pixels shown in each of the .

[0155] exist Figure 7 In the figure, for convenience, the transistor connected to the light emitting element and the signal line connected to the transistor are omitted.

[0156] Figures 7 to 12 The structure of one pixel PXL is simplified and illustrated, such as illustrating each electrode as a single electrode layer and illustrating each insulating layer as a single insulating layer, but the disclosure is not limited thereto.

[0157] In addition, in the disclosed embodiments, “formed and / or disposed in the same layer” may mean formed in the same process, and “formed and / or disposed in different layers” may mean formed in different processes.

[0158] In addition, in the embodiments of the present disclosure, “connection” between two components may mean inclusively using both electrical connection and physical connection.

[0159] Reference Figures 1a to 5 as well as Figures 7 to 12 , the display device according to the embodiment may include a substrate SUB, a line portion, and a plurality of pixels PXL.

[0160] The substrate SUB may include a transparent insulating material and may transmit light. The substrate SUB may be a rigid substrate or a flexible substrate.

[0161] For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate. The flexible substrate may be one of a film substrate and a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0162] During the manufacturing process of the display device, the material applied to the substrate SUB may preferably have resistance (or heat resistance) to high process temperature.

[0163] The substrate SUB may include a display area DA including at least one pixel area PXA in which the pixel PXL is disposed, and a non-display area NDA disposed around the display area DA.

[0164] The pixel area PXA in which each pixel PXL is disposed (or arranged) may include an emission area in which light is emitted and a peripheral area surrounding the periphery of the emission area. In the disclosed embodiment, the peripheral area may include a non-emission area in which light is not emitted.

[0165] The line portion may include a plurality of signal lines that transmit signals (or voltages) to each pixel PXL. The signal line may include, for example, a scan line (eg, reference line 100) that transmits a scan signal to each pixel PXL. Figure 6a ”Si”), a data line (for example, referring to Figure 6a ” Dj ”) and an emission control line (eg, reference line 200 ) for transmitting an emission control signal to each pixel PXL. Figure 6cHowever, the present disclosure is not limited thereto, and according to an embodiment, the line portion may further include signal lines for transmitting other signals in addition to the above-mentioned signal lines.

[0166] Each pixel PXL may be disposed on a substrate SUB and may include a pixel circuit portion PCL and a display element portion DPL. The pixel circuit portion PCL includes a pixel circuit (refer to Figures 6a to 6e 144), the display element part DPL includes a plurality of light emitting elements LD. The light emitting element LD may be positioned in an emission region disposed in a pixel region PXA of each pixel PXL.

[0167] For convenience, the pixel circuit portion PCL is described first, and then the display element portion DPL is described.

[0168] The pixel circuit portion PCL may include a buffer layer BFL, a pixel circuit 144 and a protection layer PSV.

[0169] The buffer layer BFL may prevent impurities from diffusing into the transistor T included in the pixel circuit. The buffer layer BFL may include an inorganic insulating layer including an inorganic material. For example, the buffer layer BFL may include an inorganic material such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON) and aluminum oxide (AlO x ) of inorganic materials. The buffer layer BFL may be provided as a single layer, or may be provided as a multilayer of at least two layers. The buffer layer BFL is provided as a multilayer, and each layer may be formed of the same material or may be formed of different materials. The buffer layer BFL may be omitted according to the material of the substrate SUB, process conditions, etc.

[0170] The pixel circuit 144 may include at least one transistor T and a storage capacitor Cst. Here, the transistor T may include a driving transistor Tdr that controls the driving current of the light emitting element LD and a switching transistor Tsw connected to the driving transistor Tdr. However, the present disclosure is not limited thereto, and in addition to the driving transistor Tdr and the switching transistor Tsw, the pixel circuit 144 may also include a circuit element that performs another function. In the following embodiments, in any case where one of the driving transistor Tdr and the switching transistor Tsw is mentioned or in the case where the driving transistor Tdr and the switching transistor Tsw are mentioned together, the one of the driving transistor Tdr and the switching transistor Tsw or the driving transistor Tdr and the switching transistor Tsw may be referred to as a transistor T or a plurality of transistors T.

[0171] Each of the driving transistor Tdr and the switching transistor Tsw may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be any one of a source electrode and a drain electrode, and the second terminal DE may be another electrode. For example, in the case where the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

[0172] The transistor semiconductor pattern SCL may be disposed and / or formed on the buffer layer BFL. The transistor semiconductor pattern SCL may include a first contact region contacting the first terminal SE and a second contact region contacting the second terminal DE. The region between the first contact region and the second contact region may be a channel region. The transistor semiconductor pattern SCL may be a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, or an oxide semiconductor, etc. The channel region may be a semiconductor pattern not doped with impurities, and may be an intrinsic semiconductor. The first contact region and the second contact region may be a semiconductor pattern doped with impurities.

[0173] The gate electrode GE may be disposed and / or formed on the transistor semiconductor pattern SCL with the gate insulating layer GI interposed therebetween.

[0174] The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON) and aluminum oxide (AlO x ) at least one of inorganic materials. However, the material of the gate insulating layer GI is not limited to the above-mentioned embodiment. According to an embodiment, the gate insulating layer GI may be formed of an organic insulating layer including an organic material. The gate insulating layer GI may be set as a single layer, but may also be set as a multilayer of at least a double layer.

[0175] The respective first and second terminals SE and DE may make contact with the first and second contact regions of the transistor semiconductor pattern SCL through contact holes passing through the first interlayer insulating layer ILD1 and the gate insulating layer GI.

[0176] In the above-described embodiment, the first terminal SE and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw are described as being electrically connected to separate electrodes of the transistor semiconductor pattern SCL, but the present disclosure is not limited thereto. According to an embodiment, the first terminal SE of each of the driving transistor Tdr and the switching transistor Tsw may be one of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL, and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw may be the remaining region of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. In this case, the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw may be electrically connected to the light emitting element LD of the corresponding pixel PXL through a bridge electrode or a contact electrode, etc.

[0177] In an embodiment of the present disclosure, the transistor T included in the pixel circuit 144 may be composed of an LTPS thin film transistor, but the present disclosure is not limited thereto, and may be composed of an oxide semiconductor thin film transistor according to an embodiment. In addition, the case where the transistor T is a thin film transistor having a top gate structure is described as an example, but the present disclosure is not limited thereto. According to an embodiment, the transistor T may be a thin film transistor having a bottom gate structure.

[0178] The driving voltage line DVL may be disposed and / or formed on the first interlayer insulating layer ILD1, but the present disclosure is not limited thereto, and according to an embodiment, the driving voltage line DVL may be disposed on any one of the insulating layers included in the pixel circuit portion PCL. Figures 6a to 6e The driving voltage line DVL may be applied to the driving voltage line DVL. In an embodiment of the present disclosure, the driving voltage line DVL may be Figures 6a to 6e In each of the second power lines PL2, the second driving power VSS is applied thereto.

[0179] A second interlayer insulating layer ILD2 may be disposed and / or formed on the transistor T and the driving voltage line DVL.

[0180] The second interlayer insulating layer ILD2 may cover the transistor T and the driving voltage line DVL. The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. According to an embodiment, the second interlayer insulating layer ILD2 may include the same material as the first interlayer insulating layer ILD1, but the present disclosure is not limited thereto. The second interlayer insulating layer ILD2 may be provided as a single layer, or may be provided as a multilayer of at least two layers. The second interlayer insulating layer ILD2 may include a first contact hole CH1 exposing a portion of the driving transistor Tdr and a second contact hole CH2 exposing a portion of the driving voltage line DVL.

[0181] The first to fourth electrodes EL1 to EL4 may be disposed and / or formed on the second interlayer insulating layer ILD2. The first to fourth electrodes EL1 to EL4 may be spaced apart from each other on the second interlayer insulating layer ILD2.

[0182] Each of the first to fourth electrodes EL1 to EL4 may extend along the second direction DR2 and may be commonly provided for each pixel PXL and an adjacent pixel PXL positioned in the same pixel column as each pixel PXL.

[0183] The first electrode EL1 and the second electrode EL2 may be spaced apart from each other and have a predetermined distance therebetween, the second electrode EL2 and the third electrode EL3 may be spaced apart from each other and have a predetermined distance therebetween, and the third electrode EL3 and the fourth electrode EL4 may be spaced apart from each other and have a predetermined distance therebetween. In the pixel area PXA of each pixel PXL, the distance between the first electrode EL1 and the second electrode EL2, the distance between the second electrode EL2 and the third electrode EL3, and the distance between the third electrode EL3 and the fourth electrode EL4 may be the same. However, the present disclosure is not limited thereto, and according to an embodiment, the distance between the first electrode EL1 and the second electrode EL2, the distance between the second electrode EL2 and the third electrode EL3, and the distance between the third electrode EL3 and the fourth electrode EL4 may be different from each other. In an embodiment of the present disclosure, the distance d1 between two adjacent electrodes among the first electrode EL1 to the fourth electrode EL4 may be less than the length L of each of the light emitting elements LD. For example, the distance d1 between the adjacent first electrode EL1 and the second electrode EL2 among the first electrode EL1 to the fourth electrode EL4 may be about 3.5 μm or less, but the present disclosure is not limited thereto.

[0184] In an embodiment of the present disclosure, each of the first electrode EL1 to the fourth electrode EL4 can be used as an alignment electrode (or alignment line) for aligning the light emitting element LD in the emission region of each of the pixels PXL. According to an embodiment, the first electrode EL1 to the fourth electrode EL4 can be disposed on the second interlayer insulating layer ILD2, and can block the electric field induced by the transistor T included in the pixel circuit portion PCL and the signal line connected to the transistor T to prevent the electric field from affecting the alignment and / or driving of the light emitting element LD included in the display element portion DPL. That is, the first electrode EL1 to the fourth electrode EL4 can be used as an electric field shielding line. In addition, according to another embodiment, each of the first electrode EL1 to the fourth electrode EL4 can form a coupling between the structures to which a predetermined signal (or voltage) is applied among the structures included in the display element portion DPL, so as to align the light emitting element LD in the desired region.

[0185] The first to fourth electrodes EL1 to EL4 may be disposed on the second interlayer insulating layer ILD2 and may include the same material. For example, the first to fourth electrodes EL1 to EL4 may form a single layer selected from the group consisting of molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof or mixtures thereof, or may be formed with a double layer or multiple layers of molybdenum (Mo), aluminum (Al), or silver (Ag) as a low resistance material for reducing line resistance.

[0186] In the above-described embodiment, the first to fourth electrodes EL1 to EL4 are disposed at the same layer, but the present disclosure is not limited thereto. According to an embodiment, some of the first to fourth electrodes EL1 to EL4 and the remaining electrodes may be disposed at different layers.

[0187] A protection layer PSV may be disposed and / or formed on the first to fourth electrodes EL1 to EL4 .

[0188] The protective layer PSV may be provided in the form of an organic insulating layer, an inorganic insulating layer, or an organic insulating layer provided on an inorganic insulating layer. Here, the inorganic insulating layer may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON) and aluminum oxide (AlO x ). The organic insulating layer may include an organic insulating material capable of transmitting light. The organic insulating layer may include at least one of acrylic resin (polyacrylate resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin and benzocyclobutene resin.

[0189] In an embodiment of the present disclosure, the protection layer PSV may include a first contact hole CH1 corresponding to the first contact hole CH1 of the second interlayer insulating layer ILD2 and a second contact hole CH2 corresponding to the second contact hole CH2 of the second interlayer insulating layer ILD2. Therefore, each of a portion of the second terminal DE of the driving transistor Tdr and a portion of the driving voltage line DVL may be exposed to the outside.

[0190] The display element portion DPL may be disposed on the protection layer PSV.

[0191] The display element part DPL may include first and second bank patterns BNK1 and BNK2 , an intermediate layer CTL, a light emitting element LD, and a contact electrode CNE.

[0192] The first bank pattern BNK1 may be a supporting member supporting the intermediate layer CTL to change a surface profile of the intermediate layer CTL so that light emitted from the light emitting element LD further travels in an image display direction of the display device.

[0193] The first bank pattern BNK1 may be disposed in the emission region of each pixel PXL and / or formed between the protective layer PSV and the intermediate layer CTL. The first bank pattern BNK1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. According to an embodiment, the first bank pattern BNK1 may include a single-layer organic insulating layer and / or a single-layer inorganic insulating layer, but the present disclosure is not limited thereto. According to an embodiment, the first bank pattern BNK1 may be disposed in the form of a multilayer in which at least one organic insulating layer and at least one inorganic insulating layer are stacked. However, the material of the first bank pattern BNK1 is not limited to the above-described embodiment, and according to an embodiment, the first bank pattern BNK1 may include a conductive material.

[0194] The first bank pattern BNK1 may have a cross-section in a trapezoidal shape that becomes narrower from one surface of the protective layer PSV toward an upper portion, but the present disclosure is not limited thereto. Fig.11 As shown in , the first bank pattern BNK1 may include a curved surface having a cross-section of a semi-elliptical shape or a semi-circular shape (or a hemispherical shape), etc., in which the width becomes narrower from one surface of the protective layer PSV toward the upper portion. When viewed in cross-section, the shape of the first bank pattern BNK1 is not limited to the above-described embodiment, and may be variously changed within a range capable of improving the efficiency of light emitted from each of the light emitting elements LD. Adjacent first bank patterns BNK1 may be disposed on the same plane on the protective layer PSV, and may have the same height (or thickness).

[0195] When viewed in a plan view, the first bank pattern BNK1 may have a bar shape extending in one direction, for example, the second direction DR2 (vertical direction), but the present disclosure is not limited thereto and the first bank pattern BNK1 may be changed into various shapes.

[0196] The second bank pattern BNK2 may be disposed in a peripheral region of the pixel area PXA in which each pixel PXL is disposed.

[0197] The second bank pattern BNK2 may surround at least one side of the peripheral area included in the pixel area PXA of each pixel PXL. The second bank pattern BNK2 may be a structure that defines (or divides) the emission area of ​​each pixel PXL and the pixel PXL adjacent thereto among the pixels PXL, and may be, for example, a pixel defining layer. The second bank pattern BNK2 may be configured to include a reflective material and / or at least one light blocking material to prevent a light leakage defect in which light (or light) leaks between each pixel PXL and the pixel PXL adjacent thereto. According to an embodiment, a reflective material layer may be formed on the second bank pattern BNK2 to further improve the efficiency of light emitted from each pixel PXL. According to an embodiment, the second bank pattern BNK2 may be formed at a layer different from that of the first bank pattern BNK1, or may be formed at the same layer as the first bank pattern BNK1.

[0198] The intermediate layer CTL may be disposed in the pixel area PXA of each pixel PXL and may extend in one direction. For example, the intermediate layer CTL may extend in a direction parallel to the extension direction of each of the first electrode EL1 to the fourth electrode EL4 (ie, the second direction DR2). The intermediate layer CTL may be disposed and / or formed on the first bank pattern BNK1 to overlap each of the first electrode EL1 to the fourth electrode EL4 when viewed in a plan view.

[0199] In an embodiment of the present disclosure, the distance between the intermediate layer CTL overlapping the first electrode EL1 (hereinafter referred to as the "first intermediate layer") and the intermediate layer CTL overlapping the second electrode EL2 (hereinafter referred to as the "second intermediate layer"), the distance between the second intermediate layer and the intermediate layer CTL overlapping the third electrode EL3 (hereinafter referred to as the "third intermediate layer"), and the distance between the third intermediate layer CTL and the intermediate layer CTL overlapping the fourth electrode EL4 (hereinafter referred to as the "fourth intermediate layer") may be the same. However, the present disclosure is not limited thereto, and according to an embodiment, the distance between the first intermediate layer CTL and the second intermediate layer CTL, the distance between the second intermediate layer CTL and the third intermediate layer CTL, and the distance between the third intermediate layer CTL and the fourth intermediate layer CTL may be different. In an embodiment of the present disclosure, the distance d2 between two adjacent intermediate layers CTL may be less than the length L of each of the light emitting elements LD, and may be greater than the distance d1 between two adjacent electrodes.

[0200] The intermediate layer CTL may be disposed and / or formed on the first bank pattern BNK1 to have a surface profile corresponding to the shape of the first bank pattern BNK1. For example, the intermediate layer CTL may include a protrusion portion corresponding to the first bank pattern BNK1 and a flat portion corresponding to the protection layer PSV.

[0201] In an embodiment of the present disclosure, the intermediate layer CTL may be provided in the form of a multilayer including a double layer. As an example, the intermediate layer CTL may be composed of a multilayer including a first intermediate layer CTL1 to a tenth intermediate layer CTL10 sequentially stacked from one surface of the first bank pattern BNK1, but the present disclosure is not limited thereto. According to an embodiment, the intermediate layer CTL may be composed of a multilayer including six or more inorganic insulating layers sequentially stacked from one surface of the first bank pattern BNK1.

[0202] In an embodiment of the present disclosure, the odd-numbered intermediate layers CTL1, CTL3, CTL5, CTL7, and CTL9 and the even-numbered intermediate layers CTL2, CTL4, CTL6, CTL8, and CTL10 may have different refractive indices n (refractive index and / or refractive index). For example, the refractive index of the odd-numbered intermediate layers CTL1, CTL3, CTL5, CTL7, and CTL9 may be smaller than the refractive index of the even-numbered intermediate layers CTL2, CTL4, CTL6, CTL8, and CTL10.

[0203] The thickness of each of the first to tenth intermediate layers CTL1 to CTL10 may be determined within a range in which the wavelength of light reflected from each intermediate layer and the refractive index of the material satisfy λ / 4n. Each of the first to tenth intermediate layers CTL1 to CTL10 may have the same thickness or different thicknesses. The thickness of each of the first to tenth intermediate layers CTL1 to CTL10 may be determined within a range (or limit) that does not affect the entire thickness of the display device.

[0204] In the following embodiments, for convenience of description, the refractive index of the odd-numbered intermediate layers CTL1, CTL3, CTL5, CTL7 and CTL9 is referred to as a first refractive index, and the refractive index of the even-numbered intermediate layers CTL2, CTL4, CTL6, CTL8 and CTL10 is referred to as a second refractive index.

[0205] In the embodiment of the present disclosure, the odd-numbered intermediate layers CTL1, CTL3, CTL5, CTL7, and CTL9 may include silicon oxide (SiO x ) of an inorganic insulating layer, the even-numbered intermediate layers CTL2, CTL4, CTL6, CTL8, and CTL10 may be an inorganic insulating layer including silicon nitride (SiN x). The refractive index difference between the odd-numbered intermediate layers CTL1, CTL3, CTL5, CTL7, and CTL9 and the even-numbered intermediate layers CTL2, CTL4, CTL6, CTL8, and CTL10 may be less than approximately 1 / 2, but the present disclosure is not limited thereto. For example, each of the even-numbered intermediate layers CTL2, CTL4, CTL6, CTL8, and CTL10 may have a refractive index of 1.887954, and each of the odd-numbered intermediate layers CTL1, CTL3, CTL5, CTL7, and CTL9 may have a refractive index of 1.472646.

[0206] The intermediate layer CTL according to an embodiment of the present disclosure may be composed of a multilayer having a structure in which at least three double layers are sequentially stacked, in which a silicon oxide (SiO x ) and having a second refractive index and comprising silicon nitride (SiN x ) are paired with at least one intermediate layer. However, the present disclosure is not limited thereto, and according to an embodiment, the odd-numbered intermediate layers CTL1, CTL3, CTL5, CTL7, and CTL9 may be made of silicon nitride (SiN x ), the even-numbered intermediate layers CTL2, CTL4, CTL6, CTL8, and CTL10 may be made of silicon oxide (SiO x )form.

[0207] As described above, in the case where the intermediate layer CTL is composed of a plurality of layers, the intermediate layer CTL can change the traveling direction of light emitted from each of the light emitting elements LD using interference caused by a refraction difference between the odd-numbered intermediate layers CTL1, CTL3, CTL5, CTL7, and CTL9 and the even-numbered intermediate layers CTL2, CTL4, CTL6, CTL8, and CTL10. For example, the intermediate layer CTL can reflect light emitted from each of the light emitting elements LD in an image display direction of the display device.

[0208] In the embodiment of the present disclosure, since the intermediate layer CTL has a surface profile corresponding to the shape of the first bank pattern BNK1 disposed thereunder, light emitted from each of the light emitting elements LD may be reflected by the intermediate layer CTL and may further travel in the image display direction of the display device. Ultimately, the efficiency of light emitted from each of the light emitting elements LD may be further improved.

[0209] The first bank pattern BNK1 and the intermediate layer CTL may function as a reflective member for improving light output efficiency of the light emitting element LD by allowing light emitted from the light emitting element LD to travel in an image display direction of the display device.

[0210] The intermediate layer CTL may be formed to be disposed only in the pixel area PXA of each pixel PXL. For example, the intermediate layer CTL disposed in one pixel PXL may not be connected to and separated from the intermediate layer CTL disposed in each of adjacent pixels PXL disposed in the same pixel column as the one pixel PXL.

[0211] Meanwhile, in the above-described embodiments, the intermediate layer CTL includes an insulating material (or substance), but the present disclosure is not limited thereto. According to an embodiment, the intermediate layer CTL may include a conductive material (or substance).

[0212] In addition, in the above-mentioned embodiments, the intermediate layer CTL is described as a multilayer having a structure in which at least three double insulating layers are sequentially stacked, in which the silicon oxide (SiO x ) and at least one intermediate layer formed of silicon nitride (SiN x ), but the present disclosure is not limited thereto. According to an embodiment, the intermediate layer CTL may be composed of a plurality of layers including a plurality of layers composed of aluminum oxide (Al2O3) on the uppermost layer of a plurality of layers having a structure in which at least three double insulating layers are sequentially stacked. 2 O 3 ) is formed, in the double insulating layer, a middle layer is formed by silicon oxide (SiO x ) and at least one intermediate layer formed of silicon nitride (SiN x ) form at least one intermediate layer in pairs.

[0213] In an embodiment of the present disclosure, after the intermediate layer CTL is disposed in the pixel area PXA of each pixel PXL, a predetermined alignment signal (or alignment voltage) may be applied to each of the first to fourth electrodes EL1 to EL4. In the case where a predetermined alignment signal is applied to each of the first to fourth electrodes EL1 to EL4, each of the first to fourth electrodes EL1 to EL4 may be used as an alignment electrode (or alignment line) for alignment of the light emitting element LD.

[0214] The first electrode EL1 can receive a first alignment signal (or a first alignment voltage) to serve as a first alignment electrode (or a first alignment line), the second electrode EL2 can receive a second alignment signal (or a second alignment voltage) to serve as a second alignment electrode (or a second alignment line), the third electrode EL3 can receive a third alignment signal (or a third alignment voltage) to serve as a third alignment electrode (or a third alignment line), and the fourth electrode EL4 can receive a fourth alignment signal (or a fourth alignment voltage) to serve as a fourth alignment electrode (or a fourth alignment line).

[0215] The first to fourth alignment signals may be signals having voltage differences and / or phase differences of levels that can align the light emitting element LD between the first intermediate layer CTL, the second intermediate layer CTL, the third intermediate layer CTL, and the fourth intermediate layer CTL. According to an embodiment, the first alignment signal and the third alignment signal among the first to fourth alignment signals may have the same voltage level, and the second alignment signal and the fourth alignment signal may have the same voltage level. At least some of the above-mentioned first to fourth alignment signals may be AC ​​signals, but the present disclosure is not limited thereto.

[0216] When the corresponding alignment signal is applied to each of the first electrode EL1 to the fourth electrode EL4, an electric field may be formed between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4, respectively. The light emitting element LD may be aligned and / or disposed in the pixel area PXA of each pixel PXL by the electric field formed between the two adjacent electrodes. For example, the light emitting element LD may be aligned and / or disposed between two adjacent intermediate layers CTL along the longitudinal direction of each of the light emitting elements LD.

[0217] In an embodiment of the present disclosure, when aligning the light emitting element LD in the pixel area PXA of each pixel PX, by controlling the alignment signal (or alignment voltage) applied to each of the first electrode EL1 to the fourth electrode EL4, the light emitting element LD supplied to the pixel area PXA can be controlled to be aligned to be relatively biased.

[0218] Each of the light-emitting elements LD can be an ultra-small light-emitting element (e.g., having a size as small as nanometer to micrometer) using an inorganic crystal structure material. For example, each of the light-emitting elements LD can be an ultra-small light-emitting element manufactured by an etching method or an ultra-small light-emitting element manufactured by a growth method. However, the type, size, shape, etc. of the light-emitting element LD can be changed differently. At least two to tens of light-emitting elements LD can be aligned and / or arranged in the emission area of ​​each pixel PXL, but the number of light-emitting elements LD is not limited thereto. According to an embodiment, the number of light-emitting elements LD aligned and / or arranged in the emission area of ​​each pixel PXL can be changed differently.

[0219] Each of the light emitting elements LD may be disposed between two intermediate layers CTL adjacent in a first direction DR1 parallel to the longitudinal direction thereof. The light emitting element LD may include a first light emitting element LD1 disposed between the first intermediate layer CTL and the second intermediate layer CTL, a second light emitting element LD2 disposed between the second intermediate layer CTL and the third intermediate layer CTL, and a third light emitting element LD3 disposed between the third intermediate layer CTL and the fourth intermediate layer CTL. In the following embodiments, when one of the first to third light emitting elements LD1 to LD3 is arbitrarily mentioned, or when the first to third light emitting elements LD1 to LD3 are collectively mentioned, the one of the first to third light emitting elements LD1 to LD3 or the first to third light emitting elements LD1 to LD3 are referred to as the light emitting element LD.

[0220] In an embodiment of the present disclosure, each of the light emitting elements LD may emit any one of color light and / or white light. The light emitting element LD may be provided in a form of being sprayed into a solution and may be injected into the pixel area PXA of each pixel PXL.

[0221] In the disclosed embodiment, the light emitting element LD may be injected into the pixel region PXA of each pixel PXL by an inkjet printing method, a slit coating method, or various other methods. For example, the light emitting element LD may be mixed with a volatile solvent and supplied to the pixel region PXA of each pixel PXL by an inkjet printing method or a slit coating method. At this time, when an alignment signal (or alignment voltage) corresponding to each of the first electrode EL1 to the fourth electrode EL4 positioned in the pixel region PXA of each pixel PXL is applied, an electric field may be formed between two adjacent electrodes of the first electrode EL1 to the fourth electrode EL4.

[0222] After the light emitting element LD is aligned, the solvent may be evaporated or removed by other methods, and thus the light emitting element LD may be finally aligned and / or disposed in the emission region included in the pixel area PXA of each pixel PXL.

[0223] An insulating layer INS may be disposed and / or formed on each of the light emitting elements LD. The insulating layer INS may be disposed and / or formed on each of the light emitting elements LD to cover a portion of the upper surface of each of the light emitting elements LD and to expose both ends of each of the light emitting elements LD to the outside. The insulating layer INS may be formed as a separate insulating pattern, but the present disclosure is not limited thereto.

[0224] The insulating layer INS may be composed of a single layer or a plurality of layers, and may include an inorganic insulating layer including at least one inorganic material or an organic insulating layer including at least one organic material. The insulating layer INS may also fix each of the light emitting elements LD. In the disclosed embodiment, the insulating layer INS may include an inorganic insulating layer that is beneficial for protecting the active layer 12 of each of the light emitting elements LD from external oxygen and moisture, etc. However, the disclosure is not limited thereto. The insulating layer INS may include an organic insulating layer including an organic material according to the design conditions of the display device to which the light emitting element LD is applied, etc.

[0225] In the disclosed embodiment, after the alignment of the light emitting element LD is completed in the emission area of ​​the pixel area PXA of each pixel PXL, the light emitting element LD can be prevented from being separated from the alignment position by forming an insulating layer INS on the light emitting element LD. In the case where there is a gap (or space) between the protective layer PSV and the light emitting element LD before the insulating layer INS is formed, the gap can be filled with the insulating layer INS in the process of forming the insulating layer INS. Therefore, the light emitting element LD can be composed of an organic insulating layer that is conducive to filling the gap between the protective layer PSV and the light emitting element LD.

[0226] In the disclosed embodiment, an insulating layer INS may be formed on the light emitting elements LD to prevent the active layer 12 of each of the light emitting elements LD from contacting an external conductive material. The insulating layer INS may cover only a portion of the surface of each of the light emitting elements LD so that both ends of each of the light emitting elements LD are exposed to the outside.

[0227] The contact electrode CNE may be disposed on the insulating layer INS.

[0228] The contact electrode CNE may be formed of various transparent conductive materials. For example, the contact electrode CNE may include at least one of various transparent conductive materials (including ITO, IZO, and ITZO), and may be implemented to be substantially transparent or translucent to satisfy a predetermined light transmittance. However, the material of the contact electrode CNE is not limited to the above-mentioned embodiment, and according to the embodiment, the contact electrode CNE may be formed of various opaque conductive materials.

[0229] The contact electrode CNE may include a first contact electrode CNE1 disposed on the first intermediate layer CTL, a second contact electrode CNE2 disposed on the second intermediate layer CTL, a third contact electrode CNE3 disposed on the third intermediate layer CTL, and a fourth contact electrode CNE4 disposed on the fourth intermediate layer CTL.

[0230] The first contact electrode CNE1 may be directly disposed on the first intermediate layer CTL, and may be disposed on one end EP1 of both ends EP1 and EP2 of each of the first light emitting elements LD1. The first contact electrode CNE1 may be electrically connected to a partial configuration of the pixel circuit portion PCL. For example, the first contact electrode CNE1 may be electrically connected to the second terminal DE of the driving transistor Tdr through a first contact hole CH1 that sequentially passes through the protective layer PSV and the second interlayer insulating layer ILD2. In an embodiment of the present disclosure, when the first contact electrode CNE1 is connected to the driving transistor Tdr, a predetermined signal (or voltage) applied to the driving transistor Tdr may be transmitted to the first contact electrode CNE1. The signal transmitted to the first contact electrode CNE1 may be applied to one end EP1 of both ends EP1 and EP2 of each of the first light emitting elements LD1.

[0231] The second contact electrode CNE2 may be directly disposed on the second intermediate layer CTL, and may be disposed on the remaining end EP2 of both ends EP1 and EP2 of each of the first light emitting elements LD1. In addition, the second contact electrode CNE2 may be connected to one of both ends of each of the second light emitting elements LD2. When viewed in a plan view, the second contact electrode CNE2 may overlap the remaining end EP2 of both ends EP1 and EP2 of each of the first light emitting elements LD1 and the one of both ends of each of the second light emitting elements LD2.

[0232] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed to be spaced apart from each other. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed to be spaced apart from each other on the insulating layer INS with a predetermined distance therebetween.

[0233] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed in the same layer, but the present disclosure is not limited thereto. According to an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed in different layers. Fig.12 As shown in , the first contact electrode CNE1 may be disposed on the insulating layer INS and may be covered by the auxiliary insulating layer AUINS. In addition, the second contact electrode CNE2 may be disposed on the auxiliary insulating layer AUINS and may be covered by the encapsulation layer ENC. At this time, the auxiliary insulating layer AUINS may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0234] The third contact electrode CNE3 may be directly disposed on the third intermediate layer CTL, and may be disposed on the remaining end of both ends of each of the second light emitting elements LD2. In addition, the third contact electrode CNE3 may be connected to one end of both ends of each of the third light emitting elements LD3. When viewed in a plan view, the third contact electrode CNE3 may overlap the remaining end of both ends of each of the second light emitting elements LD2 and the one end of both ends of each of the third light emitting elements LD3.

[0235] The second contact electrode CNE2 and the third contact electrode CNE3 may be disposed to be spaced apart from each other. For example, the second contact electrode CNE2 and the third contact electrode CNE3 may be disposed to be spaced apart from each other on the insulating layer INS with a predetermined distance therebetween.

[0236] The fourth contact electrode CNE4 may be directly disposed on the fourth intermediate layer CTL and may be connected to the remaining end of both ends of each of the third light emitting elements LD3. In addition, the fourth contact electrode CNE4 may be electrically connected to a partial configuration of the pixel circuit portion PCL. For example, the fourth contact electrode CNE4 may be electrically connected to the driving voltage line DVL by sequentially passing through the protection layer PSV and the second interlayer insulating layer ILD2 through the second contact hole CH2. When the fourth contact electrode CNE4 is directly connected to the driving voltage line DVL, the second driving power VSS applied to the driving voltage line DVL may be transmitted to the fourth contact electrode CNE4. The second driving power VSS transmitted to the fourth contact electrode CNE4 may be applied to the remaining end of each of the third light emitting elements LD3.

[0237] In an embodiment of the present disclosure, after the light emitting element LD is aligned in the emission region included in the pixel area PXA of each pixel PXL, the first to fourth contact electrodes CNE1 to CNE4 may serve as driving electrodes for driving the light emitting element LD.

[0238] In driving current from the first power line (refer to Figures 6a to 6e In the case where a driving current flows to the driving voltage line DVL through the driving transistor Tdr of the pixel circuit part PCL included in each pixel PXL, the driving current may flow into the emission unit EMU of each pixel PXL through the first contact hole CH1. For example, the driving current is supplied to the first contact electrode CNE1 through the first contact hole CH1, and the driving current flows to the second contact electrode CNE2 via the first light emitting element LD1. Therefore, the first light emitting element LD1 may emit light having a brightness corresponding to the current distributed to each of the first light emitting elements LD1.

[0239] The driving current flowing through the second contact electrode CNE2 flows to the third contact electrode CNE3 via the second light emitting element LD2. Therefore, the second light emitting element LD2 can emit light having brightness corresponding to the current distributed to each of the second light emitting elements LD2.

[0240] The driving current flowing through the third contact electrode CNE3 flows to the fourth contact electrode CNE4 via the third light emitting element LD3. Therefore, the third light emitting element LD3 may emit light having brightness corresponding to the current distributed to each of the third light emitting elements LD3.

[0241] In the above method, the driving current of each pixel PXL may flow while sequentially passing through the first, second, and third light emitting elements LD1, LD2, and LD3. Therefore, each pixel PXL may emit light having brightness corresponding to the data signal supplied during each frame period.

[0242] The encapsulation layer ENC may be disposed and / or formed on the first to fourth contact electrodes CNE1 to CNE4. The encapsulation layer ENC may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the encapsulation layer ENC may have a structure in which at least one inorganic insulating layer and at least one organic insulating layer are alternately stacked. The encapsulation layer ENC may completely cover the display element portion DPL to prevent water or moisture, etc. from flowing from the outside into the display element portion DPL including the light emitting element LD.

[0243] According to the above-mentioned embodiment, the alignment signal (or alignment voltage) for aligning the light-emitting element LD can be transmitted to each of the first electrode EL1 to the fourth electrode EL4, so that the light-emitting element LD can be aligned in the pixel area PXA of each pixel PXL. In the embodiment of the present disclosure, since the first electrode EL1 to the fourth electrode EL4 are arranged on the second interlayer insulating layer ILD2, the first electrode EL1 to the fourth electrode EL4 can have a surface profile corresponding to the second interlayer insulating layer ILD2. Since the second interlayer insulating layer ILD2 has a flat surface, the first electrode EL1 to the fourth electrode EL4 can also have a flat surface. In this case, as described above, when the alignment signal (or alignment voltage) corresponding to each of the first electrode EL1 to the fourth electrode EL4 is applied, an electric field with a constant intensity can be formed only between two adjacent electrodes. Therefore, the light-emitting element LD can be densely aligned between two adjacent electrodes, so the alignment degree of the light-emitting element LD can be improved.

[0244] Typically, the light emitting element LD is aligned in the pixel area PXA of each pixel PXL by forming a reflective electrode (not shown) formed of a conductive material on the first bank pattern BNK1 and applying an alignment signal to the reflective electrode. In this case, the reflective electrode may have a surface profile corresponding to the shape of the first bank pattern BNK1, so the reflective electrode may have an inclined portion and a flat portion, the inclined portion has a predetermined inclination, and the flat portion does not have a predetermined inclination. At this time, in the case where the alignment signal is applied to the reflective electrode, the electric field strength may be relatively increased at the inclined portion of the reflective electrode, so the light emitting element LD may be aligned in an undesirable area by the corresponding electric field. That is, the misalignment of the light emitting element LD may increase.

[0245] The reflective electrode may be formed by an optical process using a mask, and control of a critical dimension (CD) between the reflective electrode including the inclined portion and the reflective electrode adjacent to the reflective electrode may be difficult due to reflow of a photoresist layer used in the optical process, and thus a short defect may occur.

[0246] Therefore, in the present disclosure, by aligning the light emitting element LD using the first electrode EL1 to the fourth electrode EL4 disposed on the second interlayer insulating layer ILD2, misalignment of the light emitting element LD can be prevented, and the alignment degree of the light emitting element LD can be improved by densely aligning the light emitting element LD in a desired area in the pixel area PXA of each pixel PXL. In addition, in the present disclosure, by forming the first electrode EL1 to the fourth electrode EL4 on the second interlayer insulating layer ILD2 having a flat surface, CD control between two adjacent electrodes can be easy, thereby preventing a short circuit defect.

[0247] In addition, according to the above-described embodiment, by aligning the light emitting element LD in each pixel PXL using the first electrode EL1 to the fourth electrode EL4, a process of removing a portion of the alignment electrode (or alignment line) after aligning the light emitting element LD to drive each of the pixels PXL individually (or singly) can be omitted. Ultimately, the manufacturing process of the display device according to the above-described embodiment can be simplified.

[0248] Figures 13a to 13h The manufacturing sequence is shown in Figure 8 A cross-sectional view of the method for one pixel is shown in FIG.

[0249] Reference Figures 1a to 5 as well as Figures 7 to 13a A transistor T, a driving voltage line DVL, and at least one insulating layer are formed on a substrate SUB. Here, the at least one insulating layer may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, and a second interlayer insulating layer ILD2 sequentially formed on the substrate SUB.

[0250] Subsequently, first to fourth electrodes EL1 to EL4 spaced apart from each other are formed on the second interlayer insulating layer ILD2 .

[0251] The first to fourth electrodes EL1 to EL4 may be commonly provided for the pixels PXL positioned in the same pixel column in the display area DA. That is, the pixels PXL positioned in the same pixel column may be commonly connected to the first to fourth electrodes EL1 to EL4.

[0252] Next, after forming a protection layer PSV on the first to fourth electrodes EL1 to EL4, a first contact hole CH1 exposing a portion of the driving transistor Tdr and a second contact hole CH2 exposing a portion of the driving voltage line DVL are formed by simultaneously patterning the protection layer PSV and a second interlayer insulating layer ILD2 disposed thereunder.

[0253] Reference Figures 1a to 5 as well as Figures 7 to 13b , a first bank pattern BNK1 is formed on the protective layer PSV. On the protective layer PSV, the first bank pattern BNK1 may be spaced apart from the adjacent first bank pattern BNK1 by a predetermined distance. When viewed in a plan view, the first bank pattern BNK1 may have a strip shape extending in one direction (e.g., the second direction DR2), but the present disclosure is not limited thereto. The first bank pattern BNK1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material.

[0254] Reference Figures 1a to 5 as well as Figures 7 to 13c , an intermediate layer CTL is formed on the protective layer PSV on which the first bank pattern BNK1 is formed. The intermediate layer CTL may be formed of at least 10 inorganic insulating layers stacked sequentially and may have high reflectivity. The intermediate layer CTL may be formed on the corresponding first bank pattern BNK1 in the emission region in the pixel region PXA of each of the pixels PXL, and the intermediate layers CTL may be spaced apart from each other.

[0255] Reference Figures 1a to 5 as well as Figures 7 to 13d The second bank pattern BNK2 is formed in the peripheral area included in the pixel area PXA of each pixel PXL. The second bank pattern BNK2 may be a pixel defining layer that defines (or divides) the emission area of ​​each pixel PXL and pixels PXL adjacent to the pixel PXL.

[0256] Reference Figures 1a to 5 as well as Figures 7 to 13eBy applying an alignment signal (or an alignment voltage) corresponding to each of the first to fourth electrodes EL1 to EL4, an electric field is formed between two adjacent electrodes.

[0257] Next, in a state where an electric field is formed between two adjacent electrodes, a mixed solution including a light-emitting element LD is injected into the pixel area PXA of each of the pixels PXL using an inkjet printing method or the like. For example, an inkjet nozzle may be provided on the protective layer PSV, and a solvent in which a plurality of light-emitting elements LD are mixed may be injected into the pixel area PXA of each of the pixels PXL through the inkjet nozzle. Here, the solvent may be any one or more of acetone, water, alcohol, and toluene, but the present disclosure is not limited thereto. For example, the solvent may be in the form of ink or paste. The method of injecting the light-emitting element LD into the pixel area PXA of each of the pixels PXL is not limited to the above-described embodiment, and the method of injecting the light-emitting element LD may be changed differently.

[0258] After the light emitting element LD is injected into the pixel area PXA of each of the pixels PXL, the solvent may be removed.

[0259] In the case where the light emitting element LD is injected into the pixel area PXA of each of the pixels PXL, due to the electric fields formed between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4, respectively, the self-alignment of the light emitting element LD can be caused. Therefore, the first light emitting element LD1 can be aligned between the first electrode EL1 and the second electrode EL2, the second light emitting element LD2 can be aligned between the second electrode EL2 and the third electrode EL3, and the third light emitting element LD3 can be aligned between the third electrode EL3 and the fourth electrode EL4. Each of the first light emitting element LD1 to the third light emitting element LD3 can be aligned on the protective layer PSV between two adjacent intermediate layers CTL in the pixel area PXA of each of the pixels PXL. For example, each of the first light emitting elements LD1 can be aligned on the protective layer PSV between the intermediate layer CTL on the first electrode EL1 and the intermediate layer CTL on the second electrode EL2. Each of the second light emitting elements LD2 can be aligned on the protective layer PSV between the intermediate layer CTL on the second electrode EL2 and the intermediate layer CTL on the third electrode EL3. Each of the third light emitting elements LD3 may be aligned on the protective layer PSV between the intermediate layer CTL on the third electrode EL3 and the intermediate layer CTL on the fourth electrode EL4 .

[0260] Reference Figures 1a to 5 as well as Figures 7 to 13fAn insulating layer INS is formed on each of the first to third light emitting elements LD1 to LD3. The insulating layer INS may cover at least a portion of an upper surface of each of the first to third light emitting elements LD1 to LD3 so that both ends of each of the light emitting elements LD are exposed to the outside.

[0261] Reference Figures 1a to 5 as well as Figures 7 to 13g , first to fourth contact electrodes CNE1 to CNE4 are formed on the insulating layer INS.

[0262] The first contact electrode CNE1 may overlap the intermediate layer CTL on the first electrode EL1 and one of both ends EP1 and EP2 of each of the first light emitting element LD1. The first contact electrode CNE1 may be electrically connected to the driving transistor Tdr through a first contact hole CH1 sequentially passing through the protection layer PSV and the second interlayer insulating layer ILD2.

[0263] The second contact electrode CNE2 may overlap the intermediate layer CTL on the second electrode EL2 , the remaining end EP2 of both ends EP1 and EP2 of each of the first light emitting elements LD1 , and one of both ends of each of the second light emitting elements LD2 .

[0264] The third contact electrode CNE3 may overlap the intermediate layer CTL on the third electrode EL3 , the remaining end of each of the two ends of the second light emitting elements LD2 , and one end of each of the two ends of the third light emitting elements LD3 .

[0265] The fourth contact electrode CNE4 may overlap the remaining end of each of the intermediate layer CTL and the third light emitting element LD3 on the fourth electrode EL4 and may be electrically connected to the driving voltage line DVL through a second contact hole CH2 sequentially passing through the protection layer PSV and the second interlayer insulating layer ILD2.

[0266] Reference Figures 1a to 5 as well as Figure 7 to Figure 13h , an encapsulation layer ENC covering the first to fourth contact electrodes CNE1 to CNE4 is formed. The encapsulation layer ENC may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked.

[0267] Fig.14 and Fig.15 The display device according to the embodiment of the present disclosure is schematically shown. Figure 7 A cross-sectional view corresponding to line II to II'.

[0268] exist Fig.14 and Fig.15In the embodiment, only one first light emitting element LD1 aligned between the first electrode EL1 and the second electrode EL2 is shown, but one first light emitting element LD1 may replace Figure 7 Each of the plurality of light emitting elements LD shown in .

[0269] exist Fig.14 and Fig.15 In order to avoid repeated description, the points different from those of the above-mentioned embodiment are mainly described. The parts not specifically described in the present disclosure are consistent with the above-mentioned embodiment, and the same reference numerals represent the same components, and similar reference numerals represent similar components.

[0270] Reference Figures 1a to 5 , Figure 7 , Fig.14 as well as Fig.15 In the pixel area PXA in which one pixel PXL is disposed (or arranged), at least one insulating layer disposed on the substrate SUB, at least one transistor T, a driving voltage line DVL, and a display element portion DPL including a light emitting element LD may be disposed. Here, the at least one insulating layer may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1 and a second interlayer insulating layer ILD2, and a protective layer PSV sequentially disposed and / or formed on the substrate SUB.

[0271] The display element part DPL may include an intermediate layer CTL, a light emitting element LD, an insulating layer INS, a contact electrode CNE, and an encapsulation layer ENC.

[0272] In an embodiment of the present disclosure, the display element portion DPL may be disposed on the protective layer PSV having a flat surface and may include a first electrode EL1 and a second electrode EL2 spaced apart from each other. The first electrode EL1 and the second electrode EL2 may be disposed at the same layer and may include the same material.

[0273] A distance d1 between the first electrode EL1 and the second electrode EL2 may be smaller than a length L of each of the light emitting elements LD. A predetermined alignment signal (or alignment voltage) may be applied to each of the first electrode EL1 and the second electrode EL2.

[0274] The first bank pattern BNK1 may be disposed and / or formed on the first electrode EL1 and the second electrode EL2. Thus, each of the first electrode EL1 and the second electrode EL2 may overlap the corresponding first bank pattern BNK1.

[0275] The intermediate layer CTL may be disposed and / or formed on the first bank pattern BNK1. For example, the intermediate layer CTL (hereinafter referred to as the "first intermediate layer") may be disposed and / or formed on the first electrode EL1 and / or formed on the first bank pattern BNK1, and the intermediate layer CTL (hereinafter referred to as the "second intermediate layer") may be disposed and / or formed on the second electrode EL2 and / or formed on the first bank pattern BNK1.

[0276] In an embodiment of the present disclosure, the first intermediate layer CTL and the second intermediate layer CTL may be spaced apart from each other by a predetermined distance. The distance d2 between the first intermediate layer CTL and the second intermediate layer CTL may be greater than the distance d1 between the first electrode EL1 and the second electrode EL2, and may be greater than the length L of each of the light emitting elements LD. However, the present disclosure is not limited thereto. The intermediate layer CTL may directly contact the remaining portion of each of the first electrode EL1 and the second electrode EL2 except for a portion. For example, Fig.14 As shown in FIG. 1 , the intermediate layer CTL may directly contact a remaining region of each of the first electrode EL1 and the second electrode EL2 except for one region covered by the first bank pattern BNK1 .

[0277] In the embodiment of the present disclosure, both ends of each of the first electrode EL1 and the second electrode EL2 may not be covered by the intermediate layer CTL and may be exposed to the outside. In this case, when an alignment signal (or alignment voltage) corresponding to each of the first electrode EL1 and the second electrode EL2 is applied, an electric field having a relatively strong intensity may be formed in the portion of each of the first electrode EL1 and the second electrode EL2 exposed to the outside. Therefore, the light emitting element LD may be more densely aligned in the portion of each of the first electrode EL1 and the second electrode EL2 exposed to the outside, and thus the alignment degree of the light emitting element LD may be improved.

[0278] In the above-described embodiment, the first electrode EL1 and the second electrode EL2 are disposed on the same layer (eg, on the protective layer PSV), but the present disclosure is not limited thereto. Fig.15As shown in , the first electrode EL1 and the second electrode EL2 may be arranged on different layers. For example, the first electrode EL1 may be arranged on the second interlayer insulating layer ILD2, and the second electrode EL2 may be arranged on the protective layer PSV. Although the first electrode EL1 and the second electrode EL2 are positioned (or arranged) on different layers, each of the first electrode EL1 and the second electrode EL2 may have a profile corresponding to the second interlayer insulating layer ILD2 and the protective layer PSV having a flat surface. In this case, when an alignment signal (or alignment voltage) corresponding to each of the first electrode EL1 and the second electrode EL2 is applied, an electric field having a constant intensity may be formed between the first electrode EL1 and the second electrode EL2. Therefore, the light-emitting element LD may be densely aligned between the first electrode EL1 and the second electrode EL2, and thus the alignment degree of the light-emitting element LD in each pixel PXL may be improved.

[0279] Fig.16 It is only schematically shown Figure 5 A plan view of some signal lines that transmit predetermined signals and pads (or "pads") connected to the some signal lines in each pixel of the display device shown in FIG. For ease of explanation, Fig.16 Only the signal lines for aligning the light emitting elements LD in each of the pixels PXL are shown.

[0280] Reference Figures 1a to 5 as well as Fig.16 The display device may include a substrate SUB including a display area DA and a non-display area NDA. Figure 5 The configuration of the described substrate SUB corresponds to the same configuration, and thus a detailed description is omitted.

[0281] In the display area DA, first to fourth connection lines CL1 to CL4 and first to fourth electrodes EL1 to EL4 for applying an alignment signal (or an alignment voltage) to each pixel PXL may be disposed.

[0282] Each of the first to fourth electrodes EL1 to EL4 may have a strip shape extending in one direction (e.g., the second direction DR2) in the display area DA. However, the present disclosure is not limited thereto, and according to an embodiment, each of the first to fourth electrodes EL1 to EL4 may have a shape extending in various directions within a range (or limit) of maintaining a state of being electrically insulated from adjacent electrodes.

[0283] The first to fourth connection lines CL1 to CL4 may have a bar shape extending in the first direction DR1 crossing the second direction DR2 in the display area DA, but the extending directions of the first to fourth connection lines CL1 to CL4 are not limited to the above embodiments.

[0284] In an embodiment of the present disclosure, one of the first to fourth electrodes EL1 to EL4 and one of the first to fourth connection lines CL1 to CL4 may be integrally provided. For example, the first electrode EL1 may be integrally provided with the first connection line CL1, the second electrode EL2 may be integrally provided with the second connection line CL2, the third electrode EL3 may be integrally provided with the third connection line CL3, and the fourth electrode EL4 may be integrally provided with the fourth connection line CL4.

[0285] The first electrode EL1 and the first connection line CL1 extending in different directions and integrally provided may have a grid shape in the display area DA. The second electrode EL2 and the second connection line CL2 extending in different directions and integrally provided may have a grid shape in the display area DA. In addition, the third electrode EL3 and the third connection line CL3 extending in different directions and integrally provided may have a grid shape in the display area DA. In addition, the fourth electrode EL4 and the fourth connection line CL4 extending in different directions and integrally provided may have a grid shape in the display area DA.

[0286] The pad portion PD connected to the first to fourth electrodes EL1 to EL4 and the first to fourth connection lines CL1 to CL4 may be disposed in the non-display area NDA. The pad portion PD may include first to fourth pad portions PD1 to PD4.

[0287] The first pad portion PD1 may be electrically connected to the first connection line CL1 and the first electrode EL1 to apply a predetermined signal (or voltage) (e.g., a first alignment signal (or a first alignment voltage)) to the first connection line CL1 and the first electrode EL1. The second pad portion PD2 may be electrically connected to the second connection line CL2 and the second electrode EL2 to apply a predetermined signal (or voltage) (e.g., a second alignment signal (or a second alignment voltage)) to the second connection line CL2 and the second electrode EL2. The third pad portion PD3 may be electrically connected to the third connection line CL3 and the third electrode EL3 to apply a predetermined signal (or voltage) (e.g., a third alignment signal (or a third alignment voltage)) to the third connection line CL3 and the third electrode EL3. The fourth pad portion PD4 may be electrically connected to the fourth connection line CL4 and the fourth electrode EL4 to apply a predetermined signal (or voltage) (e.g., a fourth alignment signal (or a fourth alignment voltage)) to the fourth connection line CL4 and the fourth electrode EL4.

[0288] The above-mentioned first to fourth alignment signals (or alignment voltages) may have different voltage levels, but the present disclosure is not limited thereto, and some of the first to fourth alignment signals may have the same voltage level, and the remaining alignment signals (or alignment voltages) may have different voltage levels. In addition, among the first to fourth alignment signals, the first alignment signal and the third alignment signal may have the same voltage level, and the second alignment signal and the fourth alignment signal may have the same voltage level.

[0289] When a corresponding alignment signal is applied from each of the first to fourth pad portions PD1 to PD4 to corresponding electrodes of the first to fourth electrodes EL1 to EL4, an electric field may be formed between the first to fourth electrodes EL1 to EL4, so that the light emitting element LD may be aligned in the pixel area PXA of each of the pixels PXL.

[0290] After alignment of the light emitting element LD, the first to fourth pad portions PD1 to PD4 may apply corresponding driving power to each of the first to fourth electrodes EL1 to EL4 to drive the light emitting element LD aligned in the pixel area PXA. For example, the first pad portion PD1 may apply a first driving power set to a high potential level to the first electrode EL1 (refer to Figures 6a to 6e The second pad portion PD2 may apply the second driving power set to a low potential level to the second electrode EL2 (refer to Figures 6a to 6e The third pad portion PD3 may apply the first driving power VDD to the third electrode EL3, and the fourth pad portion PD4 may apply the second driving power VSS to the fourth electrode EL4.

[0291] Fig.17 yes Fig.16 An enlarged plan view of part EA2, Figures 18a to 18c It is along Fig.17 A cross-sectional view taken along line III to III', Fig.19 It is along Fig.17 A cross-sectional view taken along line IV to IV', Fig. 20 According to another embodiment, Fig.19 The embodiment of the first bank pattern shown in Fig.17 The cross-sectional view corresponding to the line IV to IV', Fig.21 According to another embodiment, Fig. 20 The embodiment of the display element portion shown in Fig.17 A cross-sectional view corresponding to line IV to IV'.

[0292] exist Figures 17 to 21In order to avoid repeated description, the points different from those of the above-mentioned embodiment are mainly described. The parts not specifically described in the present disclosure are consistent with the above-mentioned embodiment, and the same reference numerals represent the same components, and similar reference numerals represent similar components.

[0293] Reference Figures 1a to 6e as well as Figures 17 to 21 , the display device according to the embodiment may include a substrate SUB, a line portion, and a plurality of pixels PXL.

[0294] Each pixel PXL may be disposed on a substrate SUB, and may include a pixel circuit portion PCL including a pixel circuit 144 and a display element portion DPL including a light emitting element LD.

[0295] The pixel circuit portion PCL may include a buffer layer BFL, a pixel circuit 144 and a protection layer PSV.

[0296] The buffer layer BFL, the pixel circuit 144 and the protection layer PSV can be respectively Figures 7 to 12 The described buffer layer BFL, pixel circuit 144, and protection layer PSV have the same configuration.

[0297] The pixel circuit portion PCL may include first to fourth electrodes EL1 to EL4 disposed and / or formed between the second interlayer insulating layer ILD2 and the protective layer PSV and spaced apart from each other. A distance d1 between two adjacent electrodes among the first to fourth electrodes EL1 to EL4 may be less than a length L of each of the light emitting elements LD. The first to fourth electrodes EL1 to EL4 may have a length L that is equal to the reference length L. Figures 7 to 12 The configurations of the first electrode EL1 to the fourth electrode EL4 described above are the same configuration.

[0298] Each of the first to fourth electrodes EL1 to EL4 may be used as an alignment electrode (or alignment line) for aligning the light emitting element LD in the pixel area PXA of each of the pixels PXL. According to an embodiment, the first to fourth electrodes EL1 to EL4 may be disposed on the second interlayer insulating layer ILD2 to block an electric field induced by the transistor T included in the pixel circuit portion PCL and a signal line connected to the transistor T to prevent the electric field from affecting the alignment and / or driving of the light emitting element LD included in the display element portion DPL. In addition, according to another embodiment, a vertical capacitive coupling (e.g., a parasitic capacitor C (see FIG. 1 ) may be formed between the intermediate layer CTL in the structure included in the display element portion DPL and the first to fourth electrodes EL1 to EL4. Fig.19 )) so that the light emitting element LD is aligned in a desired area.

[0299] The display element part DPL may include first and second bank patterns BNK1 and BNK2 , an intermediate layer CTL, a light emitting element LD, and a contact electrode CNE.

[0300] The intermediate layer CTL may be disposed in the pixel area PXA of each pixel PXL and may extend along an extension direction of each of the first to fourth electrodes EL1 to EL4. The intermediate layer CTL may be disposed and / or formed on the first bank pattern BNK1 to overlap each of the first to fourth electrodes EL1 to EL4 when viewed in a plan view.

[0301] In an embodiment of the present disclosure, the intermediate layer CTL may be formed of a material (or substance) having a constant reflectivity to allow the light emitted from each of the light emitting elements LD to travel in the image display direction of the display device. For example, the intermediate layer CTL may be formed of a conductive material (or substance) having a constant reflectivity. The conductive material (or substance) may include an opaque metal that is conducive to reflecting the light emitted from the light emitting element LD in the image display direction of the display device. For example, the opaque metal may include a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or an alloy thereof. According to an embodiment, the intermediate layer CTL may include a transparent conductive material (or substance). The transparent conductive material may include a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO)) and a conductive polymer (such as PEDOT), etc. In the case where the intermediate layer CTL includes a transparent conductive material (or substance), a separate conductive layer formed of an opaque metal for reflecting the light emitted from the light emitting element LD in the image display direction of the display device may be additionally included. However, the material of the intermediate layer CTL is not limited to the above materials.

[0302] In addition, each of the intermediate layers CTL may be provided and / or formed as a single layer, but the present disclosure is not limited thereto. According to an embodiment, the intermediate layer CTL may be provided and / or formed as a multilayer in which at least two materials of metal, alloy, conductive oxide, and conductive polymer are stacked. The intermediate layer CTL may be formed as a multilayer of at least two layers to minimize distortion due to signal delay when a predetermined signal (or voltage) is transmitted to both ends of each of the light emitting elements LD. For example, the intermediate layer CTL may be formed as a multilayer stacked sequentially in the order of ITO / Ag / ITO.

[0303] The intermediate layer CTL (hereinafter referred to as the "first intermediate layer") overlapped with the first electrode EL1 may be provided to correspond to the first electrode EL1, the intermediate layer CTL (hereinafter referred to as the "second intermediate layer") overlapped with the second electrode EL2 may be provided to correspond to the second electrode EL2, the intermediate layer CTL (hereinafter referred to as the "third intermediate layer") overlapped with the third electrode EL3 may be provided to correspond to the third electrode EL3, and the intermediate layer CTL (hereinafter referred to as the "fourth intermediate layer") overlapped with the fourth electrode EL4 may be provided to correspond to the fourth electrode EL4. When viewed in a plan view, the first intermediate layer CTL, the first bank pattern BNK1, and the first electrode EL1 may overlap with each other. When viewed in a plan view, the second intermediate layer CTL, the first bank pattern BNK1, and the second electrode EL2 may overlap with each other. When viewed in a plan view, the third intermediate layer CTL, the first bank pattern BNK1, and the third electrode EL3 may overlap with each other. When viewed in a plan view, the fourth intermediate layer CTL, the first bank pattern BNK1, and the fourth electrode EL4 may overlap with each other.

[0304] In an embodiment of the present disclosure, after the intermediate layer CTL is disposed in the pixel area PXA of each pixel PXL, a predetermined alignment signal (or alignment voltage) may be applied to each of the first to fourth electrodes EL1 to EL4. In the case where a predetermined alignment signal is applied to each of the first to fourth electrodes EL1 to EL4, each of the first to fourth electrodes EL1 to EL4 may serve as an alignment electrode (or alignment line).

[0305] In an embodiment of the present disclosure, the first intermediate layer CTL may include a first protrusion portion PRT1. The first protrusion portion PRT1 may be integrally provided with the first intermediate layer CTL and may branch from the first intermediate layer CTL in the first direction DR1. The first protrusion portion PRT1 may be a region of the first intermediate layer CTL. The fourth intermediate layer CTL may include a second protrusion portion PRT2. The second protrusion portion PRT2 may be integrally provided with the fourth intermediate layer CTL and may branch from the fourth intermediate layer CTL in the first direction DR1. The second protrusion portion PRT2 may be a region of the fourth intermediate layer CTL.

[0306] The first protrusion portion PRT1 may be connected to a partial structure of the pixel circuit portion PCL (e.g., a driving transistor Tdr) by passing through the first contact hole CH1 of the protection layer PSV and the second interlayer insulating layer ILD2. Therefore, a predetermined signal (or voltage) applied to the driving transistor Tdr may be transmitted to the first intermediate layer CTL. The second protrusion portion PRT2 may be connected to a partial structure of the pixel circuit portion PCL (e.g., a driving voltage line DVL) by passing through the second contact hole CH2 of the protection layer PSV and the second interlayer insulating layer ILD2. Therefore, a predetermined signal (or voltage) applied to the driving voltage line DVL may be transmitted to the fourth intermediate layer CTL.

[0307] In the above-described embodiment, the fourth intermediate layer CTL is connected to the driving voltage line DVL through the second contact hole CH2 penetrating the protection layer PSV and the second interlayer insulating layer ILD2, and a predetermined signal (or voltage) applied to the driving voltage line DVL is transmitted to the fourth intermediate layer CTL, but the present disclosure is not limited thereto. Fig.18c As shown in , the fourth intermediate layer CTL can be connected to the fourth electrode EL4 through the second contact hole CH2 that passes only through the protective layer PSV. In this case, a predetermined signal (or voltage) (for example, the second driving power VSS) can be applied to the fourth electrode EL4. In the case where the fourth intermediate layer CTL is directly connected to the fourth electrode EL4, the predetermined signal (or voltage) applied to the fourth electrode EL4 can be directly transmitted to the fourth intermediate layer CTL. In the case where the fourth intermediate layer CTL is connected to the fourth electrode EL4 through the second contact hole CH2, a predetermined signal (or voltage) different from the second driving power VSS can be applied to the driving voltage line DVL.

[0308] The light emitting element LD may include a first light emitting element LD1 disposed between the first and second intermediate layers CTL, a second light emitting element LD2 disposed between the second and third intermediate layers CTL, and a third light emitting element LD3 disposed between the third and fourth intermediate layers CTL.

[0309] The light emitting element LD may be disposed in the pixel area PXA of each pixel PXL and / or formed on the first insulating layer INS1 .

[0310] The first insulating layer INS1 may be formed in the pixel area PXA of each pixel PXL and / or disposed under each of the light emitting elements LD aligned and / or disposed between the two intermediate layers CTL. The first insulating layer INS1 may fill the space between each of the light emitting elements LD and the protective layer PSV to stably support the light emitting element LD, and may prevent the light emitting element LD from being separated from the protective layer PSV.

[0311] In addition, the first insulating layer INS1 may expose one region of the intermediate layer CTL and cover the remaining region except the one region. For example, the first insulating layer INS1 may expose each of one region of the first intermediate layer CTL, one region of the second intermediate layer CTL, one region of the third intermediate layer CTL, and one region of the fourth intermediate layer CTL, and may cover each of the remaining region of the first intermediate layer CTL, the remaining region of the second intermediate layer CTL, the remaining region of the third intermediate layer CTL, and the remaining region of the fourth intermediate layer CTL.

[0312] The first insulating layer INS1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In an embodiment of the present disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer that is conducive to protecting the light emitting element LD from the pixel circuit portion PCL of each pixel PXL, but the present disclosure is not limited thereto. According to an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer that is conducive to flattening the support surface of the light emitting element LD.

[0313] The second insulating layer INS2 may be disposed and / or formed on each of the light emitting elements LD. The second insulating layer INS2 may be disposed and / or formed on each of the light emitting elements LD to cover a portion of the upper surface of each of the light emitting elements LD and to expose both ends of each of the light emitting elements LD to the outside. The second insulating layer INS2 may be formed as a separate insulating pattern in the pixel area PXA of each pixel PXL, but the present disclosure is not limited thereto. The second insulating layer INS2 may have the same thickness as the reference numeral 2. Figures 7 to 12 The construction of the insulating layer INS described above is identical to the construction described above.

[0314] The contact electrode CNE may be disposed and / or formed on the second insulating layer INS2. The contact electrode CNE may include a first contact electrode CNE1 disposed on the first intermediate layer CTL, a second contact electrode CNE2 disposed on the second intermediate layer CTL, a third contact electrode CNE3 disposed on the third intermediate layer CTL, and a fourth contact electrode CNE4 disposed on the fourth intermediate layer CTL.

[0315] The first contact electrode CNE1 may be directly disposed on the exposed region of the first intermediate layer CTL to be connected to the first intermediate layer CTL. In addition, the first contact electrode CNE1 may be disposed on one of both ends of each of the first light emitting elements LD1 to be connected to the one end. Therefore, a predetermined signal (or voltage) applied to the first intermediate layer CTL may be transmitted to one of both ends of each of the first light emitting elements LD1 through the first contact electrode CNE1. When viewed in a plan view, the first contact electrode CNE1 may overlap with one of both ends of each of the first intermediate layer CTL and the first light emitting element LD1.

[0316] In the above-described embodiment, the first contact electrode CNE1 is indirectly connected to the driving transistor Tdr of the pixel circuit portion PCL through the first intermediate layer CTL, but the present disclosure is not limited thereto. Fig.18b As shown in FIG. 1 , the first contact electrode CNE1 may be directly connected to the driving transistor Tdr through the first contact hole CH1 sequentially passing through the protection layer PSV and the second interlayer insulating layer ILD2. In this case, a predetermined signal (or voltage) applied to the driving transistor Tdr may be transmitted to one of the two ends of each of the first light emitting elements LD1 through the first contact electrode CNE1.

[0317] The second contact electrode CNE2 may be directly disposed on the exposed region of the second intermediate layer CTL to be connected to the second intermediate layer CTL. In addition, the second contact electrode CNE2 may be disposed on the remaining end of both ends of each of the first light emitting elements LD1 to be connected to the remaining end. In addition, the second contact electrode CNE2 may be disposed on one end of both ends of each of the second light emitting elements LD2 to be connected to the one end. When viewed in a plan view, the second contact electrode CNE2 may overlap the remaining end of both ends of each of the first light emitting elements LD1 and one end of both ends of each of the second light emitting elements LD2.

[0318] The first and second contact electrodes CNE1 and CNE2 may be disposed to be spaced apart from each other on the second insulating layer INS2 with a predetermined distance therebetween.

[0319] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed in the same layer, but the present disclosure is not limited thereto. According to an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed in different layers. Fig.21 As shown in , the first contact electrode CNE1 may be disposed on the second insulating layer INS2 and may be covered by the auxiliary insulating layer AUINS. In addition, the second contact electrode CNE2 may be disposed on the auxiliary insulating layer AUINS and may be covered by the encapsulation layer ENC. The auxiliary insulating layer AUINS may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0320] The third contact electrode CNE3 may be directly disposed on the exposed region of the third intermediate layer CTL to be connected to the third intermediate layer CTL. In addition, the third contact electrode CNE3 may be disposed on the remaining end of both ends of each of the second light emitting elements LD2 to be connected to the remaining end. In addition, the third contact electrode CNE3 may be disposed on one end of both ends of each of the third light emitting elements LD3 to be connected to the one end. When viewed in a plan view, the third contact electrode CNE3 may overlap with the remaining end of both ends of each of the second light emitting elements LD2 and one end of both ends of each of the third light emitting elements LD3.

[0321] The fourth contact electrode CNE4 may be directly disposed on the exposed region of the fourth intermediate layer CTL and may be connected to the fourth intermediate layer CTL. In addition, the fourth contact electrode CNE4 may be disposed on the remaining end of both ends of each of the third light emitting elements LD3 to be connected to the remaining end. Therefore, the second driving power VSS applied to the fourth intermediate layer CTL may be transmitted to the remaining end of both ends of each of the third light emitting elements LD3 through the fourth contact electrode CNE4. When viewed in a plan view, the fourth contact electrode CNE4 may overlap the remaining end of both ends of each of the fourth intermediate layer CTL and the third light emitting element LD3.

[0322] In the above-described embodiment, the fourth contact electrode CNE4 is indirectly connected to the driving voltage line DVL of the pixel circuit part PCL through the fourth intermediate layer CTL, but the present disclosure is not limited thereto. Fig.18b As shown in FIG. 1 , the fourth contact electrode CNE4 may be directly connected to the driving voltage line through the second contact hole CH2 sequentially passing through the protection layer PSV and the second interlayer insulating layer ILD2. In this case, a predetermined signal (or voltage) applied to the driving voltage line DVL may be transmitted to the remaining end of both ends of each of the third light emitting elements LD3 through the fourth contact electrode CNE4.

[0323] In an embodiment of the present disclosure, after the light emitting element LD is aligned in the pixel area PXA of each pixel PXL, the first to fourth contact electrodes CNE1 to CNE4 and the intermediate layer CTL corresponding thereto may serve as driving electrodes for driving the light emitting element LD.

[0324] In the case where a driving current flows from the first power line PL1 to the driving voltage line DVL through the driving transistor Tdr of the pixel circuit part PCL included in each pixel PXL, the driving current may flow into the emission unit EMU of each pixel PXL through the first contact hole CH1. For example, the driving current is supplied to the first contact electrode CNE1 through the first contact hole CH1 and the first intermediate layer CTL, and the driving current flows to the second contact electrode CNE2 via the first light emitting element LD1. Therefore, the first light emitting element LD1 may emit light having a brightness corresponding to the current distributed to each of the first light emitting elements LD1.

[0325] The driving current flowing through the second contact electrode CNE2 flows to the third contact electrode CNE3 via the second light emitting element LD2. Therefore, the second light emitting element LD2 can emit light having brightness corresponding to the current distributed to each of the second light emitting elements LD2.

[0326] The driving current flowing through the third contact electrode CNE3 flows to the fourth contact electrode CNE4 via the third light emitting element LD3. Therefore, the third light emitting element LD3 may emit light having brightness corresponding to the current distributed to each of the third light emitting elements LD3.

[0327] In the above method, the driving current of each pixel PXL may flow while sequentially passing through the first, second, and third light emitting elements LD1, LD2, and LD3. Therefore, each pixel PXL may emit light having brightness corresponding to the data signal supplied during each frame period.

[0328] The encapsulation layer ENC may be disposed and / or formed on the first to fourth contact electrodes CNE1 to CNE4. The encapsulation layer ENC may have the same Figures 7 to 12 The configuration of the encapsulation layer ENC is the same as described.

[0329] Meanwhile, in the existing display device in which a configuration included in the display element portion DPL serves as an alignment electrode (or alignment line) for aligning the light emitting element LD and a driving electrode for driving the light emitting element LD, after aligning the light emitting element LD, a process of removing a portion of the alignment electrode (or alignment line) may be performed to drive each of the pixels PXL separately (or singly). At this time, in the pixel region PXA of each pixel PXL, the second bank pattern BNK2 surrounding the region in which the light emitting element LD is disposed (or positioned in the peripheral region of the pixel region PXA) may include a groove portion exposing the region C in which a portion of the alignment electrode (or alignment line) is removed. In this case, the light emitting element LD may be aligned in the first region A of the pixel region PXA of each pixel PXL.

[0330] According to an embodiment of the present disclosure, since the intermediate layer CTL as the driving electrode for driving the light emitting element LD is formed only in the pixel region PXA of each pixel PXL, the second bank pattern BNK2 may not include the above-mentioned groove. In this case, the area occupied by the second bank pattern BNK2 in the pixel region PXA of each pixel PXL can be reduced, and the light emitting element LD can be aligned in the second region B of the pixel region PXA. Therefore, in an embodiment of the present disclosure, the alignment area of ​​the light emitting element LD in the pixel region PXA of each pixel PXL can be further ensured compared to the existing display device.

[0331] According to the above-described embodiment, the light emitting element LD is aligned in each pixel PXL using the first electrode EL1 to the fourth electrode EL4, and a process of removing a portion of an alignment electrode (or alignment line) in order to drive each of the pixels PXL individually (or singly) after aligning the light emitting element LD can be omitted. Ultimately, the manufacturing process of the display device according to the above-described embodiment can be simplified.

[0332] In addition, according to the above-described embodiment, an alignment signal (or alignment voltage) for alignment of the light emitting element LD may be transmitted to each of the first electrode EL1 to the fourth electrode EL4, so that the light emitting element LD may be aligned in the pixel area PXA. When a corresponding alignment signal (or alignment voltage) is applied to each of the first electrode EL1 to the fourth electrode EL4, an electric field may be formed between two adjacent electrodes among the first electrode EL1 to the fourth electrode EL4. At this time, a capacitive coupling (e.g., vertical capacitive coupling (parasitic capacitor C)) may be formed between each of the first electrode EL1 to the fourth electrode EL4 and the intermediate layer CTL disposed thereon to correspond thereto. For example, vertical capacitive coupling may be formed between the first electrode EL1 and the first intermediate layer CTL, vertical capacitive coupling may be formed between the second electrode EL2 and the second intermediate layer CTL, vertical capacitive coupling may be formed between the third electrode EL3 and the third intermediate layer CTL, and vertical capacitive coupling may be formed between the fourth electrode EL4 and the fourth intermediate layer CTL.

[0333] The capacitance can be increased by forming a vertical capacitive coupling between each of the first electrode EL1 to the fourth electrode EL4 and the intermediate layer CTL disposed thereon to correspond thereto, and the capacitance can affect the electric field formed between two adjacent electrodes. For example, the electric field can be concentrated between two adjacent electrodes by forming a vertical capacitive coupling between each of the first electrode EL1 to the fourth electrode EL4 and the intermediate layer CTL disposed thereon to correspond thereto. Therefore, the light emitting element LD can be densely aligned between two adjacent electrodes, so the alignment degree of the light emitting element LD in each pixel PXL can be improved.

[0334] Figure 22a to Figure 22h is shown in order to manufacture Fig.18a A cross-sectional view of the method for one pixel is shown in FIG.

[0335] Reference Figures 1a to 5 as well as Figure 16 to Figure 22a , a transistor T, a driving voltage line DVL and at least one insulating layer are formed on a substrate SUB.

[0336] First to fourth electrodes EL1 to EL4 spaced apart from each other are formed on the second interlayer insulating layer ILD2 among at least one insulating layer.

[0337] After forming a protective layer PSV on the first to fourth electrodes EL1 to EL4 , a first contact hole CH1 exposing a portion of the driving transistor Tdr and a second contact hole CH2 exposing a portion of the driving voltage line DVL are formed.

[0338] Reference Figures 1a to 5 and Figure 16 to Figure 22b , a first bank pattern BNK1 is formed on the protection layer PSV.

[0339] Reference Figures 1a to 5 as well as Figure 16 to Figure 22c , an intermediate layer CTL including a conductive material (or substance) having a high reflectivity is formed on the protection layer PSV having the first bank pattern BNK1 formed thereon.

[0340] An intermediate layer CTL may be formed on the first bank pattern BNK1 on the first to fourth electrodes EL1 to EL4 , respectively.

[0341] The intermediate layer CTL formed on the first bank pattern BNK1 on the first electrode EL1 may be connected to the driving transistor Tdr through the first contact hole CH1. The intermediate layer CTL formed on the first bank pattern BNK1 on the fourth electrode EL4 may be connected to the driving voltage line DVL through the second contact hole CH2.

[0342] The intermediate layer CTL on the first to fourth electrodes EL1 to EL4 may be formed to be disposed only in the pixel area PXA of each of the pixels PXL. For example, the intermediate layer CTL on the first electrode EL1, the intermediate layer CTL on the second electrode EL2, and the intermediate layer CTL on the third electrode EL3 disposed in one pixel PXL may not be connected to and may be separated from the intermediate layer CTL on the first electrode EL1, the intermediate layer CTL on the second electrode EL2, and the intermediate layer CTL on the third electrode EL3 disposed for each of the adjacent pixels PXL disposed in the same column as the one pixel PXL.

[0343] The intermediate layer CTL on the fourth electrode EL4 connected to the driving voltage line DVL may be commonly provided for the pixels PXL positioned in the same pixel column. For example, the intermediate layer CTL on the fourth electrode EL4 provided in one pixel PXL may be commonly provided for the adjacent pixels PXL provided in the same pixel column as the one pixel PXL. That is, the pixels PXL provided in the same pixel column may be connected to the intermediate layer CTL on the fourth electrode EL4. However, the present disclosure is not limited thereto, and according to an embodiment, the intermediate layer CTL on the fourth electrode EL4 may be formed to be provided only in the pixel area PXA of each pixel PXL.

[0344] Reference Figures 1a to 5 as well as Figures 16 to 22d An insulating material layer INSM is formed on the protective layer PSV on which the intermediate layer CTL is formed. The insulating material layer INSM may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material.

[0345] Subsequently, a second bank pattern BNK2 is formed in a pixel region of each pixel PXL. The second bank pattern BNK2 may be formed on the insulating material layer INSM.

[0346] Reference Figures 1a to 5 as well as Figure 16 to Figure 22e In a state in which an electric field is formed between two adjacent electrodes by applying an alignment signal (or alignment voltage) corresponding to each of the first to fourth electrodes EL1 to EL4, a mixed solution (or solvent) including a light emitting element LD is injected into the pixel area PXA of each of the pixels PXL using an inkjet printing method, etc. After the light emitting element LD is injected, the solvent may be removed.

[0347] The light emitting element LD may be aligned between two adjacent electrodes. The light emitting element LD may be aligned on the insulating material layer INSM between two adjacent intermediate layers CTL in the pixel area PXA of each of the pixels PXL. For example, each of the first light emitting elements LD1 among the light emitting elements LD may be aligned on the insulating material layer INSM between the intermediate layer CTL on the first electrode EL1 and the intermediate layer CTL on the second electrode EL2. Each of the second light emitting elements LD2 among the light emitting elements LD may be aligned on the insulating material layer INSM between the intermediate layer CTL on the second electrode EL2 and the intermediate layer CTL on the third electrode EL3. Each of the third light emitting elements LD3 among the light emitting elements LD may be aligned on the insulating material layer INSM between the intermediate layer CTL on the third electrode EL3 and the intermediate layer CTL on the fourth electrode EL4.

[0348] Reference Figures 1a to 5 as well as Figure 16 to Figure 22f After aligning the light emitting element LD in the pixel area PXA of each pixel PXL, a second insulating layer INS2 is formed on each of the light emitting elements LD. The second insulating layer INS2 may cover at least a portion of the upper surface of each of the light emitting elements LD so that both ends of each of the light emitting elements LD except the active layer 12 are exposed to the outside.

[0349] The first insulating layer INS1 may be formed by etching the insulating material layer INSM to expose a portion of the intermediate layer CTL through a process of forming the second insulating layer INS2 or an etching process performed before and after the process.

[0350] Reference Figures 1a to 5 as well as Figure 16 to Figure 22g , first to fourth contact electrodes CNE1 to CNE4 are formed on the second insulating layer INS2 .

[0351] Reference Figures 1a to 5 as well as Figure 16 to Figure 22h , an encapsulation layer ENC covering the first to fourth contact electrodes CNE1 to CNE4 is formed.

[0352] Fig.23 The display device according to the embodiment of the present disclosure is schematically shown. Fig.16 The plane diagram corresponding to part EA2 is, Fig.24 is with Fig.23 The cross-sectional view corresponding to the line V~V', Fig.25 is with Fig.23 A cross-sectional view corresponding to line VI~VI'.

[0353] exist Figure 23 to Figure 25 In order to avoid repeated description, the points different from those of the above-mentioned embodiment are mainly described. The parts not specifically described in the present disclosure are consistent with the above-mentioned embodiment, and the same reference numerals represent the same components, and similar reference numerals represent similar components.

[0354] Reference Figures 1a to 5 , Fig.16 as well as Figure 23 to Figure 25 , each pixel PXL may include a pixel circuit portion PCL disposed on the substrate SUB and a display element portion DPL disposed on the pixel circuit portion PCL.

[0355] Since the pixel circuit part PCL is the same as the reference Figure 17 to Figure 22h The configuration of the pixel circuit portion PCL described above corresponds to the same configuration, and thus a detailed description thereof is omitted.

[0356] The display element portion DPL may include first to fourth sub-electrodes SEL1 to SEL4 , a first bank pattern BNK1 , an intermediate layer CTL, a light emitting element LD, first and second insulating layers INS1 and INS2 , a contact electrode CNE, and an encapsulation layer ENC.

[0357] Each of the first to fourth sub-electrodes SEL1 to SEL4 may be disposed and / or formed between the protection layer PSV and the first bank pattern BNK1 .

[0358] The first sub-electrode SEL1 can be set and / or formed on the protective layer PSV to correspond to the first electrode EL1, the second sub-electrode SEL2 can be set and / or formed on the protective layer PSV to correspond to the second electrode EL2, the third sub-electrode SEL3 can be set and / or formed on the protective layer PSV to correspond to the third electrode EL3, and the fourth sub-electrode SEL4 can be set and / or formed on the protective layer PSV to correspond to the fourth electrode EL4.

[0359] When viewed in a plan view, the first electrode EL1 and the first sub-electrode SEL1 may overlap each other, the second electrode EL2 and the second sub-electrode SEL2 may overlap each other, the third electrode EL3 and the third sub-electrode SEL3 may overlap each other, and the fourth electrode EL4 and the fourth sub-electrode SEL4 may overlap each other.

[0360] The first bank patterns BNK1 may be disposed and / or formed on the first to fourth sub-electrodes SEL1 to SEL4 , respectively.

[0361] An intermediate layer CTL may be disposed and / or formed on the first bank pattern BNK1 .

[0362] An intermediate layer CTL (hereinafter referred to as a "first intermediate layer") disposed on the first bank pattern BNK1 on the first sub-electrode SEL1 may cover the first sub-electrode SEL1 and the first bank pattern BNK1. The first intermediate layer CTL may contact two side portions of the first sub-electrode SEL1 that are not covered by the first bank pattern BNK1 and are exposed to the outside. Therefore, the first intermediate layer CTL may be connected to the first sub-electrode SEL1.

[0363] An intermediate layer CTL (hereinafter referred to as a "second intermediate layer") disposed on the first bank pattern BNK1 on the second sub-electrode SEL2 may cover the second sub-electrode SEL2 and the first bank pattern BNK1. The second intermediate layer CTL may contact two side portions of the second sub-electrode SEL2 that are not covered by the first bank pattern BNK1 and are exposed to the outside. Therefore, the second intermediate layer CTL may be connected to the second sub-electrode SEL2.

[0364] An intermediate layer CTL (hereinafter referred to as a "third intermediate layer") disposed on the first bank pattern BNK1 on the third sub-electrode SEL3 may cover the third sub-electrode SEL3 and the first bank pattern BNK1. The third intermediate layer CTL may contact two side portions of the third sub-electrode SEL3 that are not covered by the first bank pattern BNK1 and exposed to the outside. Therefore, the third intermediate layer CTL may be connected to the third sub-electrode SEL3.

[0365] An intermediate layer CTL (hereinafter referred to as a "fourth intermediate layer") disposed on the first bank pattern BNK1 on the fourth sub-electrode SEL4 may cover the fourth sub-electrode SEL4 and the first bank pattern BNK1. The fourth intermediate layer CTL may contact two side portions of the fourth sub-electrode SEL4 that are not covered by the first bank pattern BNK1 and exposed to the outside. Therefore, the fourth intermediate layer CTL may be connected to the fourth sub-electrode SEL4.

[0366] In the embodiment of the present disclosure, since each of the first to fourth sub-electrodes SEL1 to SEL4 is disposed on the corresponding electrode and the protection layer PSV is disposed between each of the first to fourth sub-electrodes SEL1 to SEL4 and the corresponding electrode, a vertical capacitive coupling (for example, a parasitic capacitor C (see FIG. 1 )) can be formed between each of the first to fourth sub-electrodes SEL1 to SEL4 and the corresponding electrode. Fig.25 )). For example, since the first sub-electrode SEL1 is disposed on the first electrode EL1 and the protective layer PSV is placed therebetween, vertical capacitive coupling may be formed between the first sub-electrode SEL1 and the first electrode EL1. Since the second sub-electrode SEL2 is disposed on the second electrode EL2 and the protective layer PSV is placed therebetween, vertical capacitive coupling may be formed between the second sub-electrode SEL2 and the second electrode EL2. Since the third sub-electrode SEL3 is disposed on the third electrode EL3 and the protective layer PSV is placed therebetween, vertical capacitive coupling may be formed between the third sub-electrode SEL3 and the third electrode EL3. Since the fourth sub-electrode SEL4 is disposed on the fourth electrode EL4 and the protective layer PSV is placed therebetween, vertical capacitive coupling may be formed between the fourth sub-electrode SEL4 and the fourth electrode EL4.

[0367] As described above, the capacitance can be increased due to the vertical capacitive coupling formed between a sub-electrode and an electrode corresponding thereto. In addition, since a sub-electrode and an electrode corresponding thereto are spaced apart and only the protective layer PSV is between them, the capacitance generated between the sub-electrode and the electrode can be further increased. In this case, when an alignment signal (or alignment voltage) corresponding to each of the first electrode EL1 to the fourth electrode EL4 is applied, a stronger electric field can be formed between two adjacent electrodes among the first electrode EL1 to the fourth electrode EL4. Therefore, the light-emitting element LD can be densely aligned between the first electrode EL1 to the fourth electrode EL4, so the alignment of the light-emitting element LD in each pixel PXL can be improved.

[0368] Although the above content has been described with reference to the preferred embodiments of the present disclosure, those skilled in the art or those having ordinary knowledge in the corresponding technical field will understand that the present disclosure may be variously changed and modified without departing from the technical scope of the present disclosure described in the claims.

[0369] Therefore, the technical scope of the present disclosure should not be limited to the contents described in the specific embodiments of the specification, but should be defined by the claims.

Claims

1. A display device, comprising: A substrate, comprising a display area and a non-display area, wherein the display area comprises a plurality of pixel areas, and the non-display area surrounds the display area; as well as a pixel disposed in each of the plurality of pixel regions, The pixel includes: a driving voltage line and at least one transistor, which are arranged on the substrate; a first electrode and a second electrode, which extend in one direction on the at least one transistor and the driving voltage line and are spaced apart from each other; a dam pattern, which is respectively arranged on the first electrode and the second electrode; an intermediate layer, which is arranged on the dam pattern; a plurality of light-emitting elements, which are arranged between two intermediate layers adjacent to each other in another direction intersecting the one direction; a first contact electrode, which is arranged on one of the two adjacent intermediate layers and connected to one of the two ends of each of the plurality of light-emitting elements; and a second contact electrode, which is arranged on the remaining intermediate layer of the two adjacent intermediate layers and connected to the remaining of the two ends of each of the plurality of light-emitting elements.

2. The display device according to claim 1, wherein: The intermediate layer includes an insulating material.

3. The display device according to claim 2, wherein: The intermediate layer is a multilayer in which at least three double layers are sequentially stacked, the double layers being formed by stacking a first inorganic insulating layer and a second inorganic insulating layer.

4. The display device according to claim 3, wherein: The first inorganic insulating layer and the second inorganic insulating layer have different refractive indices from each other.

5. The display device according to claim 1, wherein: One of the first contact electrode and the second contact electrode is electrically connected to the at least one transistor, and the remaining contact electrode is electrically connected to the driving voltage line.

6. The display device according to claim 5, wherein: The first electrode and the second electrode are arranged on the same layer.

7. The display device according to claim 5, wherein: The first electrode and the second electrode are provided in different layers.

8. The display device according to claim 1, wherein: Each of the first electrode and the second electrode extends in the one direction and is provided in common with respect to adjacent pixels positioned in the same pixel column as the pixel.

9. The display device according to claim 1, wherein: The intermediate layer includes a conductive material.

10. The display device according to claim 9, wherein: The one intermediate layer is provided in the pixel, and the remaining intermediate layers are provided in common with respect to the pixel and adjacent pixels.

11. The display device according to claim 9, wherein: The pixel further includes an insulating layer disposed between the first and second electrodes and the bank pattern.

12. The display device according to claim 11, wherein: The one intermediate layer and one of the first electrode and the second electrode, the insulating layer interposed between the one intermediate layer and the one electrode, and the bank pattern corresponding to the one electrode form a capacitor, and The remaining intermediate layer and the remaining electrode of the first electrode and the second electrode, and the insulating layer interposed between the remaining intermediate layer and the remaining electrode and a bank pattern corresponding to the remaining electrode form a capacitor.

13. The display device according to claim 11, wherein: The pixel further includes a first sub-electrode and a second sub-electrode disposed on the insulating layer, extending along the one direction and spaced apart from each other, and The first sub-electrode overlaps the first electrode, and the second sub-electrode overlaps the second electrode.

14. The display device according to claim 13, wherein: The first electrode and the first sub-electrode and the insulating layer interposed between the first electrode and the first sub-electrode form a capacitor, and The second electrode and the second sub-electrode and the insulating layer interposed between the second electrode and the second sub-electrode form a capacitor.

15. The display device according to claim 14, wherein: The one intermediate layer covers the first sub-electrode and is electrically connected to the first sub-electrode, and The remaining intermediate layer covers the second sub-electrode and is electrically connected to the second sub-electrode.

16. The display device according to claim 1, wherein: When viewed in a plan view, the intermediate layer overlaps each of the first electrode and the second electrode.

17. A method for manufacturing a display device, the method comprising: Setting the pixels to be set in each pixel region; Setting the pixel comprises: forming a driving voltage line and at least one transistor on a substrate; forming an interlayer insulating layer on the at least one transistor and the driving voltage line; forming a first electrode and a second electrode extending in one direction and spaced apart from each other on the interlayer insulating layer; forming a bank pattern on the first electrode and the second electrode; forming an intermediate layer on the bank pattern; inputting a plurality of light emitting elements, and then aligning the plurality of light emitting elements between two intermediate layers adjacent to each other direction intersecting the one direction by applying an alignment signal corresponding to each of the first electrode and the second electrode; forming an insulating layer on an upper surface of each of the plurality of light emitting elements; and A first contact electrode and a second contact electrode are formed on the insulating layer.

18. The method according to claim 17, wherein: The intermediate layer includes a conductive material.

19. The method according to claim 17, wherein: The intermediate layer includes an insulating material.

20. The method according to claim 19, wherein: The intermediate layer includes a multilayer in which at least three double layers are sequentially stacked, the double layers being formed by stacking a first inorganic insulating layer and a second inorganic insulating layer, and The first inorganic insulating layer and the second inorganic insulating layer have different refractive indices from each other.

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