Phase change material layer structure and preparation method thereof and phase change memory

Abstract

The present disclosure discloses a phase-change material layer structure, a method for preparing the same, and a phase-change memory. The phase-change material layer structure is applied to a phase-change memory and includes: a first material layer made of GeTe; a second material layer made of at least Ga and Sb; and alternating stacks of the first and second material layers.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of memory, and relate to, but are not limited to, a phase change material layer structure, a preparation method thereof, and a phase change memory. Background Art

[0002] Phase change memory (PCM) is a new type of memory that uses the significant difference in resistance between the crystalline and amorphous phase change materials to store information. In the amorphous state, the material has a higher resistance due to its disordered molecular structure; in the crystalline state, the material has a lower resistance due to its ordered molecular structure. The resistance difference between the two states typically reaches two orders of magnitude.

[0003] The phase change material can be rapidly transformed between two resistance states (high resistance and low resistance) through Joule heating induced by current.

[0004] PCM is attracting increasing attention from researchers and companies due to its advantages, including strong stability, low power consumption, high storage density, and compatibility with traditional CMOS processes. With these significant advantages, PCM is considered one of the most promising next-generation non-volatile memories.

[0005] Phase change materials are the core of PCMs, and their performance determines the key technical performance of PCMs. Researching high-performance phase change materials has become an urgent issue that needs to be addressed. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a phase change material layer structure, a preparation method thereof, and a phase change memory.

[0007] In a first aspect, an embodiment of the present disclosure provides a phase-change material layer structure, which is applied to a phase-change memory; the phase-change material layer structure includes:

[0008] A first material layer, wherein the material of the first material layer is GeTe;

[0009] a second material layer, wherein the material of the second material layer includes at least Ga and Sb;

[0010] The first material layers and the second material layers are stacked alternately.

[0011] In some embodiments, the GeTe satisfies the general formula Ge m Te n , where m and n are any integers.

[0012] In some embodiments, the material of the second material layer includes:

[0013] GaSbGe or GaSb.

[0014] In some embodiments, the GaSbGe contains a doping element or the GaSb contains a doping element; wherein the doping element includes at least one of the following: N element, C element, Si element or O element.

[0015] In some embodiments, the number of the first material layer is greater than or equal to 1; the difference between the number of the second material layer and the number of the first material layer is 0 or 1.

[0016] In some embodiments, the phase change material layer structure is a superlattice-like structure.

[0017] In some embodiments, the general formula of the superlattice-like structure is [the first material layer (a) / Second material layer (b) ] x , wherein a is the single layer thickness of the first material layer; b is the single layer thickness of the second material layer; and X is the number of alternating cycles of a single layer of the first material layer and a single layer of the second material layer.

[0018] In a second aspect, an embodiment of the present disclosure provides a method for preparing a phase change material layer structure, the method comprising:

[0019] Alternately forming a stack of first material layers and second material layers;

[0020] The material of the first material layer is GeTe; the material of the second material layer includes at least Ga and Sb elements.

[0021] In some embodiments, the second material layer includes at least GaSbGe, GaSb, doped GaSbGe or doped GaSb; wherein the doping element includes at least one of the following: N element, C element, Si element or O element.

[0022] In a third aspect, an embodiment of the present disclosure provides a phase change memory, the phase change memory comprising: phase change memory cells arranged in an array; wherein the phase change memory cells comprise:

[0023] A lower electrode, a bidirectional threshold switch, an intermediate electrode, a phase change material layer structure as described in any of the above embodiments, and an upper electrode are stacked in sequence.

[0024] In the embodiments of the present disclosure, the materials within the GaSb family and the materials within the GaSbGe family are not used alone as phase change materials, but are compounded with GeTe to form a composite phase change material. Compared with using the materials within the GaSb family and the materials within the GaSbGe family alone, the composite phase change material structure is less susceptible to temperature changes and has high thermal stability. It also has good data retention. The phase change memory formed using the composite phase change material can have a longer service life and better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a perspective diagram of a 3D XPoint memory device;

[0026] Figure 2A The resistance of GaSbGe family materials and the resistivity-temperature curve of GST-225 family materials;

[0027] Figure 2B The resistance of GaSbGe family materials in reset state and set state changes with the number of erase and write cycles;

[0028] Figure 2C A graph showing the ten-year and hundred-year data retention capabilities of materials within the GaSbGe family;

[0029] Figure 3 A schematic diagram of a phase change material layer structure provided in an embodiment of the present disclosure;

[0030] Figure 4A A schematic diagram of a phase change material layer structure provided in an embodiment of the present disclosure;

[0031] Figure 4B A schematic diagram of another phase change material layer structure provided in an embodiment of the present disclosure;

[0032] Figure 4C A schematic diagram of another phase change material layer structure provided in an embodiment of the present disclosure;

[0033] Figure 5 A schematic diagram of a phase change material layer structure of a superlattice-like structure provided by an embodiment of the present disclosure;

[0034] Figure 6 A schematic diagram of a memory cell array in a phase change memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in a variety of different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. The terms used herein in the specification of this disclosure are intended only to describe specific embodiments and are not intended to limit this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] The basic storage principle of phase change memory is to apply voltage or current pulse signals of different widths and heights to the device unit to cause the physical phase of the phase change material to change, that is, a reversible phase change occurs between the crystalline state (low resistance state) and the amorphous state (high resistance state), thereby realizing the writing ("1") and erasing ("0") operations of information. The mutual conversion process includes two processes: the amorphization transition from the crystalline state to the amorphous state and the crystallization transition from the amorphous state to the crystalline state. The former is called the amorphization process (RESET) and the latter is called the crystallization process (SET). The information is then read out by measuring and comparing the resistance difference between the two physical phases. This non-destructive reading process can ensure that the information stored in the device unit is accurately read out.

[0038] Phase change memory includes two-dimensional phase change memory and three-dimensional phase change memory. The three-dimensional phase change memory includes three-dimensional cross-point (3D X Point) memory, which stores data based on the resistance change of bulk material properties (for example, in a high resistance state or a low resistance state). This scheme is combined with a stackable cross-point data access array to enable bit addressing. For example, Figure 1 A perspective view of the structure of an exemplary 3D XPoint memory 100 is shown. According to some embodiments, 3D XPoint memory 100 has a transistor-free crosspoint architecture, in which memory cells are located at the intersections of vertical conductors. The vertical conductors include word lines (WLs) and bit lines (BLs) that intersect perpendicularly. The WLs and BLs typically consist of 20nm / 20nm line / space (L / S) lines formed after a patterning process. Memory cells are formed at the intersections of the perpendicular WLs and BLs. 3D XPoint memory 100 includes multiple parallel lower bit lines 111 in the same plane and multiple parallel upper bit lines 121 in the same plane above the lower bit lines 111.

[0039] The 3D X Point memory 100 further includes a plurality of lower word lines 112 and upper word lines 122 that are parallel to each other and located in the same plane between the lower bit lines 111 and the upper bit lines 121 in the vertical direction. Figure 1 As shown, each lower bit line 111 and each upper bit line 121 extends laterally along the bit line direction in a top plan view (parallel to the wafer plane), and each lower word line 112 and each upper word line 122 extends laterally along the word line direction in a top plan view, and each lower word line 112 and each upper word line 122 is perpendicular to each lower bit line 111 and each upper bit line 121.

[0040] like Figure 1 As shown, 3D X Point memory 100 includes a plurality of lower memory cells 110 and a plurality of upper memory cells 120. Each lower memory cell 110 is located at the intersection of a lower bit line 111 and a corresponding lower word line 112, and each upper memory cell 120 is located at the intersection of an upper bit line 121 and a corresponding upper word line 122. Each memory cell 110 / 120 includes at least a vertically stacked PCM element and a selector. Each memory cell 110 / 120 stores a single bit of data and can be written to or read from by varying the voltage applied to the corresponding selector (which eliminates the need for transistors). Each memory cell can be individually accessed by applying current through top and bottom conductors contacting each memory cell (e.g., the corresponding lower word line 112 or upper word line 122 and the lower bit line 111 or upper bit line 121). The memory cells in 3D X Point memory 100 are arranged in a memory array. This design of stacking two groups of WL, BL and storage units improves the bit density.

[0041] The performance parameters of phase change materials include the crystallization transition temperature (Tx), data retention performance (Data Retention), and the ratio of RESET resistance to SET resistance (the ratio of the resistance in the amorphous state to the resistance in the crystalline state). Generally, a higher crystallization transition temperature is beneficial for improving thermal stability and reducing power consumption. Data retention is used to evaluate the probability of generating erroneous data and losing the required stored data due to undesired conversion of the phase change material in the active area of ​​the memory cell in an array under operation at elevated temperature. A higher ratio of RESET resistance to SET resistance is beneficial for distinguishing the amorphous and crystalline states of the phase change material, which is conducive to increasing the PCM read-write-erase (RWM) window.

[0042] In some embodiments, a composite material (GST) containing germanium (Ge), antimony (Sb), and tellurium (Te), such as Ge2Sb2Te5, is used as a phase change material in phase change memory. However, this material has problems such as a low crystallization transition temperature and poor data retention.

[0043] In some embodiments, a composite material (GaSb) containing gallium (Ga) and antimony (Sb) is used as a phase-change material in phase-change memory. While this material exhibits high Tx and good data retention, its ratio of RESET resistance to SET resistance is much lower than that of GST, which is detrimental to the PCM read, write, and erase window. This is primarily due to phase segregation in the GaSb or GaSbGe system, which forms large Sb clusters and hinders the formation of a high RESET resistance state.

[0044] Below through Figures 2A to 2C Conduct a detailed analysis of the above performance indicators.

[0045] Figure 2A The pre-deposited film of GST-225 (curve 121), Ga 46 Sb 54 The relationship between the resistivity and temperature of GST-225 (curve 122), Ga1Sb1Ge1 (curve 123), and doped (e.g., silicon oxide) GaSbGe composition (curve 124). As shown in curve 121, the resistivity of GST-225 begins to drop significantly at a temperature of about 150°C. This indicates that the crystal transition temperature of GST-225 is about 150°C. As shown in curve 122, Ga 46 Sb 54 The resistivity of Ga begins to drop sharply at a temperature of about 250°C, indicating that 46 Sb 54 The crystallization transition temperature of Ga1Sb1Ge1 is approximately 250°C. As shown in curve 123, the resistivity of Ga1Sb1Ge1 begins to drop significantly at approximately 360°C, indicating that the crystallization transition temperature of Ga1Sb1Ge1 is approximately 360°C. Therefore, the crystallization transition temperature of Ga1Sb1Ge1 is approximately 210°C higher than that of GST-225, achieving the expected performance characteristics and improving data retention at high temperatures.

[0046] As shown by curve 124 , the resistivity of the doped (eg, silicon oxide) GaSbGe composition begins to drop significantly at a temperature of 441° C., indicating that the crystallization transition temperature of the doped (eg, silicon oxide) GaSbGe composition is approximately 360° C.

[0047] Figure 2B Used to represent the fatigue characteristic curve of materials in the GaSbGe family. The materials in the GaSbGe family are Gax Sb y Ge z (where x, y and z add up to 100% in the combination), materials within the GaSbGe family also include doping elements. In this case, the concentrations of Ga, Sb and Ge can be normalized so that Ga, Sb and Ge add to 100% in the combination, even when additional elements are added. The concentrations of the additional elements are not normalized, and given their atomic concentrations, it is assumed that Ga, Sb and Ge add to 100%, so the sum of the normalized concentration percentages is greater than 100%. Therefore, in the case of added elements, the actual atomic percentage (added to 100%) can be determined by scaling the values ​​of Ga, Sb and Ge by a factor of ((100-sum of added elements) / 100).

[0048] Curve 131 represents the amorphous reset state, and curve 132 represents the crystalline set state. Figure 2B It can be seen that the fatigue-free repeated erasure and programming times of the materials in the GaSbGe family are as high as 10 8 times, in 10 8 During this cycle, the high-resistance and low-resistance states of materials in the GaSbGe family have relatively stable resistance values, ensuring the reliability required for device applications using materials in the GaSbGe family.

[0049] Figure 2C This graph shows the calculated 10-year data retention performance of materials within the GaSbGe family. The activation energy of materials within the GaSbGe family is calculated to be 3.3 eV. At a data failure rate of 0.01%, the 10-year data retention is 220°C. At a data failure rate of 1%, the 100-year data retention is 205°C.

[0050] For example, Ge2Sb2Te5 is used as a phase change material. However, this material has problems such as low crystallization transition temperature and poor data retention performance.

[0051] The present disclosure provides a phase change material layer structure, such as Figure 3 As shown, the phase change material layer structure is applied to a phase change memory; the phase change material layer structure includes:

[0052] A first material layer 201, wherein the material of the first material layer 201 is GeTe;

[0053] A second material layer 202, wherein the material of the second material layer 202 includes at least Ga and Sb;

[0054] The first material layers 201 and the second material layers 202 are stacked alternately.

[0055] The material of the second material layer 202 includes at least Ga and Sb, that is, any material in the GaSb family. The material of the second material layer 202 may also include other elements, such as Ge, so the second material layer may also include materials in the GaSbGe family.

[0056] In some embodiments, the positions of the first material layer 201 and the second material layer 202 may be interchanged.

[0057] As can be seen from the above examples, materials in the GaSb family and the GaSbGe family have high crystallization transition temperatures and good data retention. However, these materials are prone to phase segregation, which can form large Sb clusters and hinder the formation of a high RESET resistance state.

[0058] By arranging the first material layer 201 on the upper layer and / or lower layer of the second material layer 202, the phase segregation problem existing in this type of material can be solved. At the same time, the new phase change material layer structure composed of the second material layer 202 and the first material layer 201 maintains the advantages of higher crystallization transition temperature and good data retention of materials in the GaSb family and materials in the GaSbGe family.

[0059] The first material layer 201 includes GeTe. When materials within the GaSb family and materials within the GaSbGe family are not used alone as phase change materials, but are compounded with GeTe to form a composite phase change material, the composite phase change material structure is not susceptible to temperature changes and has high thermal stability. It also has good data retention, a high ratio of RESET resistance to SET resistance, a low RESET current (the high RESET resistance also determines that it has a low RESET current, resulting in lower power consumption) and a high endurance cycle (number of erase and write cycles).

[0060] In some embodiments, the GeTe satisfies the general formula Ge m Te n , where m and n are any integers.

[0061] The first layer of materials includes materials of the GeTe family. The GeTe family of materials refers to phase change materials including Ge and Te elements, which satisfy the general formula Ge m Te n (For example, GeTe and GeTe4.) Other elements may be added to GeTe family materials, such as at least one of S, N, O, Cu, Si, Au, Al, W, Ga, etc., to optimize the performance of GeTe family materials for phase change materials.

[0062] In some embodiments, the material of the second material layer includes:

[0063] GaSbGe or GaSb.

[0064] The GaSbGe family of materials refers to phase change materials including Ga, Sb and Ge elements, wherein the sum of the composition ratios of Ga, Sb and Ge is 1. For example, Ga 0.22 Sb 0.29 Ge 0.49 、Ga 0.3 Sb 0.36 Ge 0.34 and Ga 0.21 Sb 0.28 Ge 0.51 The GaSb family of materials refers to phase change materials including Ga and Sb elements, wherein the sum of the composition ratios of Ga and Sb is 1. For example, Ga 0.4 Sb 0.6 、Ga 0.3 Sb 0.7 and Ga 0.46 Sb 0.54 .

[0065] It should be noted that the subscripts in the above material formula represent the proportion of elements in the material. In other embodiments, the atomic weight of each element in the material can also be used to represent its respective components. This is not limited here and is only for illustration.

[0066] In the embodiment of the present disclosure, by compounding at least one layer of GeTe family material alternately stacked on the GaSbGe family material or the GaSb family material to form the phase change material layer structure of the present disclosure, the phase segregation problem existing when the GaSb family or the GaSbGe family is used as a phase change material can be effectively reduced, thereby increasing the resistance value in the RESET state.

[0067] In some embodiments, the GaSbGe contains a doping element or the GaSb contains a doping element; wherein the doping element includes at least one of the following: N element, C element, Si element or O element.

[0068] Materials of the GaSbGe family and materials of the GaSb family may be doped with other elements to optimize the performance of the materials of the GaSbGe family or the GaSb family.

[0069] In some embodiments, the number of the first material layer is greater than or equal to 1; the difference between the number of the second material layer and the number of the first material layer is 0 or 1.

[0070] When the phase change material layer structure includes only one first material layer 201 , the second material layer may be located above and / or below the first material layer, that is, the first material layer at least needs to be in contact with the second material layer.

[0071] When the number of first material layers in the phase change material layer structure is two or more, the top layer of the phase change material layer structure may be the first material layer or the second material layer, and the bottom layer of the phase change material layer structure may be the first material layer or the second material layer.

[0072] Since the first material layers and the second material layers are stacked alternately, the difference between the number of the second material layers and the number of the first material layers is 0 or 1.

[0073] Figure 4A 、 Figure 4B as well as Figure 4C is a partial schematic diagram of the phase change material layer structure, such as Figure 4A As shown, the top layer is the first material layer 201, and the bottom layer is the second material layer 202, which has an alternating period (each first material layer 201 and second material layer 202 can form an alternating period); Figure 4B As shown, the top layer is the first material layer 201, the bottom layer is the second material layer 202, and there are two alternating periods; Figure 4C As shown, the top layer is the second material layer 202, and the bottom layer is the second material layer 202, that is, another second material layer 202 is stacked on two alternating periods. The phase change material layer structure can also include more alternating periods, which will not be described in detail here.

[0074] It is understood that the positions of the first material layer 201 and the second material layer 202 can be interchanged. Figure 4A For example, the top layer is the second material layer 202 , and the bottom layer is the first material layer 201 .

[0075] The thickness of each phase change material layer may be the same as or different from the thickness of other layers.

[0076] In some embodiments, the phase change material layer structure is a superlattice-like structure.

[0077] When the thickness of each of the first material layer and the second material layer is at the nanometer level, the structure of the phase-change material layer is a superlattice-like structure.

[0078] like Figure 5As shown, a super lattice-like structure (SLL) is formed by alternating first and second material layers 201 and 202. In some embodiments, the first material layer 201 can be the bottom layer. It is understood that the positions of the first and second material layers 201 and 202 can be interchangeable, so in some embodiments, the second material layer 202 can be the bottom layer.

[0079] In one embodiment, if Figure 5 The top layer of the superlattice-like structure shown can be stacked with another layer of material that is consistent with the bottom layer of material.

[0080] Figure 5 Each layer of the phase change material layer structure shown in FIG is at the nanoscale.

[0081] In some embodiments, the general formula of the superlattice-like structure is [the first material layer (a) / Second material layer (b) ] x , wherein a is the single layer thickness of the first material layer; b is the single layer thickness of the second material layer; and X is the number of alternating cycles of a single layer of the first material layer and a single layer of the second material layer.

[0082] In some embodiments, the structure of the phase change material layer is a superlattice structure, and the thickness of each single layer of the first material layer is set to a nanometer (for example, 5nm), and the thickness of each single layer of the second material layer is set to b nanometers (for example, 6nm). A first material layer and a second material layer can be used as a composite layer. The thickness of a composite layer is (a+b) nanometers (for example, 5nm+6nm=11nm). X is the number of alternating periods of a single layer of the first material layer and a single layer of the second material layer, for example, X can be 4. Then the expression of this type of superlattice structure can be [GeTe (5) / GaSb (6) ] (4) or [GeTe (5) / GaSbGe (6) ] (4) , and its thickness is 44nm.

[0083] The single layer thickness a of the first material layer, the single layer thickness b of the second material layer, and the number of alternating cycles X can all be controlled and set by semiconductor equipment. The above embodiment is only an example, but is not limited thereto.

[0084] The present disclosure provides a method for preparing a phase change material layer structure, the method comprising:

[0085] Alternately forming a stack of first material layers and second material layers;

[0086] The material of the first material layer is GeTe; the material of the second material layer includes at least Ga and Sb elements.

[0087] The phase change material layer structure can be prepared by a deposition process or a growth process.

[0088] Deposition processes include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

[0089] In some embodiments, the first material layer or the second material layer may be formed by an epitaxial growth process, and then the second material layer or the first material layer may be formed by a deposition process or a growth process, and this step may be repeated until the desired phase change material layer structure is manufactured.

[0090] In some embodiments, a phase change material layer structure having a superlattice-like structure may be formed by a deposition process, such as sputtering or atomic layer deposition.

[0091] In some embodiments, the phase change material layer structure described in the above embodiments can be manufactured by a sputtering system.

[0092] The sputtering system includes a chamber and a substrate, wherein the substrate is installed in the chamber. The first sputtering target material includes a GaSb family material and a GaSbGe family material, and the second sputtering target material includes a GeTe family material.

[0093] The substrate is coupled to a power supply controller, which is used to apply a bias voltage during the sputtering process. The applied bias voltage can be direct current, pulsed direct current, radio frequency, or a combination thereof, and can be turned on and off by the power process controller to coordinate the sputtering process.

[0094] The chamber also includes a vacuum pump or other device for evacuating the chamber and removing exhaust gas. In addition, the chamber is also equipped with a gas source. In one embodiment of the present disclosure, the gas source can be a source of inert gas, and the inert gas can be argon. The system also includes the ability to dynamically control the flow rate of the gas generated by the gas source. The flow rate of different gases can affect the different layers formed during the sputtering process, such as the film thickness. The power supply controller is used to control the composition of the deposited layer so that the composition is required to alternately form a stacked first material layer and a second material layer; wherein the material of the first material layer is GeTe; the material of the second material layer includes at least Ga and Sb elements.

[0095] In some embodiments, the second material layer includes at least GaSbGe, GaSb, doped GaSbGe or doped GaSb; wherein the doping element includes at least one of the following: N element, C element, Si element or O element.

[0096] Materials of the GaSbGe family and materials of the GaSb family may be doped with other elements, including at least one of the following: N, C, Si, or O, to optimize the performance of the GaSbGe family or GaSb family materials.

[0097] In some embodiments, the gas source may include a gas for reaction, such as oxygen or nitrogen for addition to the GaSbGe family or the GaSb family.

[0098] In some embodiments, GaSbGe-Si or GaSb-Si can be used as a sputtering target to form a GaSbGe family or GaSb family material doped with SiOx by reacting with oxygen. Similarly, the sputtering target can be formed by introducing reactive nitrogen into the chamber to form a GaSbGe family or GaSb family material doped with SiN. x GaSbGe family materials or GaSb family materials.

[0099] In some embodiments, GaSbGe-Si or GaSb-Si may be used as a sputtering target to form a GaSbGe family material or a GaSb family material doped with Si.

[0100] In some embodiments, GaSbGe-Si or GaSb-Si can be used as a sputtering target with a reactive gas containing oxygen or nitrogen to form a GaSbGe family material or a GaSb family material doped with silicon oxide or nitrogen oxide.

[0101] The present disclosure also provides a phase change memory, such as Figure 6 As shown, the phase change memory includes: phase change memory units 500 arranged in an array; wherein, the phase change memory unit 500 includes:

[0102] A lower electrode 508 , an Ovonic Threshold Switch (OTS) 507 , an intermediate electrode 506 , a phase change material layer structure 504 as described in any of the above embodiments, and an upper electrode 502 are stacked in sequence.

[0103] The phase-change material layer structure 504 described in the embodiment of the present disclosure may be used in various phase-change memories including two-dimensional phase-change memories and three-dimensional phase-change memories.

[0104] Figure 6 This is an example of a phase-change memory cell array, comprising multiple phase-change memory cells 500. Each phase-change memory cell has a first conductive line 501 above it and a second conductive line 509 below it. Each phase-change memory cell 500 includes an upper electrode 502, a phase-change material layer structure 504, and first and second conductive layers 503 and 505 located above and below the phase-change material layer structure 504, an intermediate electrode 506, a bidirectional threshold switch 507, and a lower electrode 508. The left and right sidewalls of the phase-change material layer structure 504 also include a liner layer 510, a first dielectric layer 511, and a spacer layer 512.

[0105] The material of the first conductive line 501 and the material of the second conductive line 509 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

[0106] The first conductive line 501 can function as a bit line or a word line; the second conductive line 509 can also function as a word line or a bit line. For example, when the first conductive line 501 functions as a bit line, the second conductive line 509 can function as a word line. The phase-change memory cell is used to store data based on a phase change caused by a voltage difference between the first conductive line and the second conductive line.

[0107] The materials of the upper electrode 502 , the middle electrode 506 , and the lower electrode 508 include carbon-containing materials, including but not limited to amorphous carbon (ac), carbon nanotubes, graphene, and the like.

[0108] The first conductive layer 503 and the second conductive layer 505 can be used to improve the contact sensitivity between the phase change material layer structure 504 and the upper electrode 502 and the middle electrode 506. In some embodiments, the first conductive layer 503 and the second conductive layer 505 may not be used.

[0109] The material of the bidirectional threshold switch 507 may include a chalcogenide material, such as Ge-Se, Si-Te, C-Te, B-Te, Ge-Te, Al-Te, Ge-Sb-Te, Ge-Sb, Bi-Te, As-Te, Sn-Te, Ge-Te-Pb or Ge-Se-Te, etc.

[0110] The material of the phase change material layer structure 504 can adopt the phase change material layer structure described in the embodiment of the present disclosure, including: a first material layer, the material of the first material layer is GeTe; a second material layer, the material of the second material layer includes at least Ga elements and Sb elements; the first material layer and the second material layer are alternately stacked.

[0111] A first gap fill layer (Gap Fill) 514 is further provided between each phase change memory cell 500, and the sidewalls of the phase change memory cell array further include a second gap fill layer 513 and a second dielectric layer 515. Examples of gap fill materials used in the gap fill layer include, but are not limited to, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium tellurite (CdTe), zinc sulfide (ZnS), lead sulfide (PbS), lead selenide (PbSe), cobalt-based compounds, and any combination thereof.

[0112] The materials of the first gap-filling layer 514 and the second gap-filling layer 513 may be the same or different.

[0113] The material of the second dielectric layer 515 can be oxide. The material of the first dielectric layer 511 can be the same as or different from that of the second dielectric layer 515.

[0114] In some embodiments, the positions of the phase-change material layer structure 504 and the bidirectional threshold switch 507 may be interchanged.

[0115] The phase change memory cell array and the peripheral circuit can constitute a phase change memory.

[0116] The phase change memory composed of the phase change material structure of the embodiment of the present invention also has the advantages of the phase change material structure of the present invention, that is, it is not easily affected by temperature changes and has high thermal stability. It also has good data retention, a high ratio of RESET resistance to SET resistance, low RESET current (high RESET resistance also determines that it has low RESET current, so that its power consumption is small) and high endurance cycle (number of erase and write cycles).

[0117] It should be understood that “some embodiments”, “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0118] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0119] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A phase change material layer structure, characterized in that: The phase change material layer structure is applied to a phase change memory; The phase change material layer structure comprises: A first material layer, wherein the material of the first material layer is GeTe; a second material layer, wherein the material of the second material layer includes: GaSbGe or GaSb; the first material layer is used to suppress phase segregation of the second material layer; The first material layers and the second material layers are alternately stacked to form a superlattice-like structure, and the difference between the number of layers of the second material layers and the number of layers of the first material layers is 0 or 1.

2. The phase change material layer structure according to claim 1, wherein: The GeTe satisfies the general formula Ge m Te n , where m and n are any integers.

3. The phase change material layer structure according to claim 1, wherein: The GaSbGe contains a doping element or the GaSb contains a doping element; wherein the doping element includes at least one of the following: N element, C element, Si element or O element.

4. The phase change material layer structure according to claim 1, wherein: The general formula of the superlattice-like structure is [the first material layer (a) / Second material layer (b) ] x , wherein a is the single layer thickness of the first material layer; b is the single layer thickness of the second material layer; and X is the number of alternating cycles of a single layer of the first material layer and a single layer of the second material layer.

5. A method for preparing a phase change material layer structure, characterized in that: The method comprises: Alternately stacking first material layers and second material layers to form a superlattice-like structure, wherein the difference between the number of layers of the second material layers and the number of layers of the first material layers is 0 or 1; The material of the first material layer is GeTe; the material of the second material layer includes GaSbGe or GaSb, wherein the first material layer is used to suppress phase segregation of the second material layer.

6. The method according to claim 5, wherein The second material layer includes doped GaSbGe or doped GaSb; wherein the doping element includes at least one of the following: N element, C element, Si element or O element.

7. A phase change memory, characterized in that: The phase change memory comprises: phase change memory cells arranged in an array; wherein the phase change memory cells comprise: A lower electrode, a bidirectional threshold switch (OTS), an intermediate electrode, a phase change material layer structure according to any one of claims 1 to 4, and an upper electrode are stacked in sequence.

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