A dual-power switching circuit and a power supply architecture

Abstract

The present application discloses a dual-power switching circuit and a power supply architecture. Its first-stage switching module is configured to generate a first output voltage for supplying power to the first-stage control module based on a first power supply voltage and a second power supply voltage; the first-stage control module is configured to operate under the power supply of the first output voltage to respectively generate a first judgment signal and a second judgment signal; the second-stage switching module includes a first switch component and a second switch component, and is configured to, according to the first judgment signal and the second judgment signal, turn on the first switch component so that the target output voltage output by the output end of the second-stage switching module is the first power supply voltage, or turn on the second switch component so that the target output voltage output by the output end of the second-stage switching module is the second power supply voltage. In this technical solution, it can effectively complete the switching of dual-power voltage inputs without causing voltage drop loss after the power supply voltage input, and can be applicable to application scenarios where the initially input power supply voltage is very low.

Description

Technical Field

[0001] This application relates to the technical field of power supplies, and particularly to a dual-power switching circuit and a power supply architecture. Background Art

[0002] Whether it is a dual-power supply system for a touch and display driver integration (TDDI) chip applied to a touch screen solution or a dual-power supply system for a mains / battery applied to an MCU (such as a laptop, which is powered by an adapter when plugged in and by a battery when used for portable work). In these dual-power supply systems, there is a scenario where one power supply may lose power (or does not exist), and it is necessary to ensure that the system can work properly, or at least, the system can enter a certain predetermined state without errors. For this purpose, the mainstream solution adopted by the prior art is to use two diodes at the board level. Due to the forward conduction characteristic of the diode and no reverse backflow, this solution can ensure that there is no leakage or backflow phenomenon when any one of the power supplies does not exist (floating or pulled to GND). However, since this solution uses two diodes and the voltage drop of a diode is usually 0.5V - 0.7V, the final input power supply voltage loses a diode voltage drop compared to the initial input of the two power supply voltages, resulting in its inapplicability to application scenarios with a very low initial input power supply voltage. Summary of the Invention

[0003] An embodiment of this application provides a dual-power switching circuit to solve the technical problem that the prior art's implementation of dual-power switching using two diodes at the board level is inapplicable to application scenarios with a very low initial input power supply voltage.

[0004] In a first aspect, this application provides a dual-power switching circuit, including a first-stage switching module, a first-stage control module, and a second-stage switching module, where,

[0005] The first-stage switching module is configured to generate a first output voltage for supplying power to the first-stage control module based on a first power supply voltage and a second power supply voltage;

[0006] The first-stage control module is configured to operate under the power supply of the first output voltage to respectively generate a first judgment signal for judging whether the first power supply voltage has lost power and a second judgment signal for judging whether the second power supply voltage has lost power;

[0007] The second - stage switching module includes a first switch component and a second switch component, and is configured to turn on the first switch component according to the first judgment signal and the second judgment signal, so that the target output voltage output by the output end of the second - stage switching module is the first power supply voltage, or turn on the second switch component, so that the target output voltage output by the output end of the second - stage switching module is the second power supply voltage.

[0008] Optionally, in some embodiments, the first - stage switching module includes a first switch transistor, a second switch transistor, a third switch transistor, and a fourth switch transistor. The drain of the first switch transistor, the drain of the second switch transistor, and the gate of the third switch transistor are all connected to the first power supply voltage. The gate of the second switch transistor, the drain of the third switch transistor, and the drain of the fourth switch transistor are all connected to the second power supply voltage. The gate of the first switch transistor, the source of the first switch transistor, the source of the second switch transistor, the source of the third switch transistor, the source of the fourth switch transistor, and the gate of the fourth switch transistor are all electrically connected to the output end of the first - stage switching module to output the first output voltage at the output end of the first - stage switching module.

[0009] Optionally, in some embodiments, the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are all Native PMOS transistors;

[0010] Or, the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are all PMOS transistors. The first - stage switching module further includes a first resistor and a second resistor connected in series between the first power supply voltage and the second power supply voltage. The connection point between the first resistor and the second resistor is electrically connected to the output end of the first - stage switching module.

[0011] Optionally, in some embodiments, the first - stage control module includes a reference voltage generation module, a first comparator, and a second comparator. The reference voltage generation module is configured to generate a reference output voltage with a first preset voltage value based on the first output voltage. The power supply terminals of the first comparator and the second comparator are both connected to the first output voltage. The first input terminals of the first comparator and the second comparator are both connected to the reference output voltage. The second input terminal of the first comparator is connected to the first power supply voltage to output the first judgment signal through the output terminal of the first comparator. The second input terminal of the second comparator is connected to the second power supply voltage to output the second judgment signal through the output terminal of the second comparator.

[0012] Optionally, in some embodiments, a third resistor is further connected in series between the second input terminal of the first comparator and the first power supply voltage. The connection between the third resistor and the second input terminal of the first comparator is also electrically connected to one end of a fourth resistor, and the other end of the fourth resistor is grounded. The third resistor and the fourth resistor form a resistor voltage division network to attenuate the first power supply voltage and then send it to the second input terminal of the first comparator; a fifth resistor is further connected in series between the second input terminal of the second comparator and the second power supply voltage. The connection between the fifth resistor and the second input terminal of the second comparator is also electrically connected to one end of a sixth resistor, and the other end of the sixth resistor is grounded. The fifth resistor and the sixth resistor form a resistor voltage division network to attenuate the second power supply voltage and then send it to the second input terminal of the second comparator.

[0013] Optionally, in some embodiments, the second-stage switching module further includes a control logic component configured to perform a first preset logical operation on the first determination signal and the second determination signal to output a first logical signal for controlling the conduction or cut-off of the first switching component, and perform a second preset logical operation on the first determination signal and the second determination signal to output a second logical signal for controlling the conduction or cut-off of the second switching component.

[0014] Optionally, in some embodiments, both the first switching component and the second switching component include a first PMOS transistor. The drain of the first PMOS transistor is connected to the first power supply voltage or the second power supply voltage. The gate of the first PMOS transistor is connected to the first logical signal or the second logical signal. The source and substrate of the first PMOS transistor are electrically connected to the output terminal of the second-stage switching module to output the first power supply voltage or the second power supply voltage through the output terminal of the second-stage switching module.

[0015] Alternatively, both the first switching component and the second switching component include a second PMOS transistor, a third PMOS transistor, and an NMOS transistor. The source and substrate of the second PMOS transistor are both connected to the first power supply voltage or the second power supply voltage. The gates of the second PMOS transistor, the third PMOS transistor, and the NMOS transistor are all connected to the first logical signal or the second logical signal. The drain of the second PMOS transistor is electrically connected to the drains of the third PMOS transistor and the NMOS transistor respectively. The source of the NMOS transistor is grounded. The source and substrate of the third PMOS transistor are both electrically connected to the output terminal of the second-stage switching module to output the first power supply voltage or the second power supply voltage through the output terminal of the second-stage switching module.

[0016] Optionally, in some embodiments, it further includes a second-level control module and a third-level switching and voltage regulation module, where

[0017] The second-level switching module is reconfigured to turn on the first switch component according to the first judgment signal and the second judgment signal, so that the second output voltage output by the output end of the second-level switching module is the first power supply voltage, or turn on the second switch component, so that the second output voltage output by the output end of the second-level switching module is the second power supply voltage;

[0018] The second-level control module is configured to operate under the power supply of the second output voltage to generate a first control signal according to the first judgment signal and a second control signal according to the second judgment signal;

[0019] The third-level switching and voltage regulation module includes a first LDO voltage regulation output module and a second LDO voltage regulation output module, and is configured to enable the first LDO voltage regulation output module according to the first control signal, so that the target output voltage output by the output end of the third-level switching and voltage regulation module is the first regulated voltage generated based on the first power supply voltage, or enable the second LDO voltage regulation output module according to the second control signal, so that the target output voltage output by the output end of the third-level switching and voltage regulation module is the second regulated voltage generated based on the second power supply voltage.

[0020] Optionally, in some embodiments, both the first LDO voltage regulation output module and the second LDO voltage regulation output module include a fourth PMOS transistor and an operational amplifier. The substrate of the fourth PMOS transistor and the power supply terminal of the operational amplifier are both connected to the second output voltage. The non-inverting input terminal of the operational amplifier is connected to a reference output voltage of a second preset voltage value. The output terminal of the operational amplifier is electrically connected to the gate of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the first power supply voltage or the second power supply voltage. The inverting input terminal of the operational amplifier and the source of the fourth PMOS transistor are both electrically connected to the output end of the third-level switching and voltage regulation module, so as to output the first regulated voltage or the second regulated voltage through the output end of the third-level switching and voltage regulation module.

[0021] In a second aspect, the present application provides a power supply architecture, including a first power supply, a second power supply, and the above-mentioned dual-power switching circuit. The first power supply outputs the first power supply voltage, and the second power supply outputs the second power supply voltage.

[0022] In this application, the dual - power - supply switching circuit adopts a two - stage power - supply switching circuit solution, with the capabilities increasing level by level, similar to a step - by - step "bootstrap". Specifically, the first - stage switching module generates a first output voltage. This output voltage is extremely weak, with a load - carrying capacity of only a few micro - amperes. However, it can ensure the normal operation of the circuit powered by it (i.e., the first - stage control module, which has extremely low power consumption). Two judgment signals (i.e., the first judgment signal and the second judgment signal) formed by the first - stage control module powered by the first output voltage are used to turn on the first switching component of the second - stage switching module, so that the target output voltage output at the output end of the second - stage switching module is the first power supply voltage, or to turn on the second switching component of the second - stage switching module, so that the target output voltage output at the output end of the second - stage switching module is the second power supply voltage, thereby realizing the dual - power - supply switching. It can be seen that the entire switching process does not require the use of external diodes. Only by controlling the first switching component or the second switching component to turn on through corresponding signals can the corresponding power supply voltage be switched and output as the target output voltage, without the problem of diode voltage drop. Therefore, this technical solution can effectively complete the switching of the dual - power - supply input voltage without causing voltage drop loss of the power - supply input voltage, and can be applicable to application scenarios with extremely low initial input power supply voltages at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following will clearly show the technical solutions and their beneficial effects of this application through a detailed description of the specific embodiments of this application in conjunction with the drawings.

[0024] Figure 1 is the connection block diagram of the traditional dual - power - supply switching circuit.

[0025] Figure 2 is a connection block diagram of the dual - power - supply switching circuit provided by an embodiment of this application.

[0026] Figure 3 is Figure 2 the circuit schematic diagram of the dual - power - supply switching circuit shown.

[0027] Figure 4 is Figure 2 a circuit schematic diagram of the first - stage switching module of the dual - power - supply switching circuit shown.

[0028] Figure 5 is Figure 2 another circuit schematic diagram of the first - stage switching module of the dual - power - supply switching circuit shown.

[0029] Figure 6 is Figure 3 a circuit schematic diagram of the first switching component or the second switching component of the dual - power - supply switching circuit shown.

[0030] Figure 7 is Figure 3Another circuit schematic diagram of the first switch component or the second switch component of the dual-power switching circuit shown.

[0031] Figure 8 is Figure 2 Another connection block diagram of the dual-power switching circuit shown.

[0032] Figure 9 is Figure 8 Connection block diagram of the second-stage control module and the third-stage switching and voltage regulation module of the dual-power switching circuit shown.

[0033] Figure 10 is Figure 9 Circuit schematic diagram of the second-stage control module and the third-stage switching and voltage regulation module of the dual-power switching circuit shown.

[0034] Figure 11 It is a connection block diagram of a power supply architecture provided by an embodiment of the present application.

[0035] Figure 12 It is another connection block diagram of a power supply architecture provided by an embodiment of the present application. Specific implementation manners

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. Without conflict, the following various embodiments and their technical features can be combined with each other.

[0037] Whether it is a dual-power supply system applied to a touch and display integrated chip (Touch and Display Driver Integration, abbreviated as "TDDI" chip) for a touch screen solution, or a mains / battery dual-power supply system applied to an MCU (for example, a laptop computer, powered by an adapter when plugged in and powered by a battery when used for portable work). In these dual-power supply systems, there is a scenario where one power supply may lose power (or does not exist), and it is necessary to ensure that the system can work normally, or at least, the system can enter a certain predetermined state without errors. For this reason, the mainstream solutions adopted by the prior art are as Figure 1As shown in the figure, it is solved by using two diodes at the board level. Due to the forward conduction characteristic of the diode, there will be no reverse backflow. Therefore, this solution can ensure that there is no leakage or backflow when any one of the power supplies does not exist (floating or pulled to GND). However, since this solution uses two diodes, and the voltage drop of the diode is usually 0.5V - 0.7V, the final input power supply voltage (VIN) is lost by a diode voltage drop compared to the initial input of the two power supply voltages (VCC or VBAT), resulting in its inapplicability to application scenarios where the initial input power supply voltage (VCC or VBAT) is very low.

[0038] Based on this, it is necessary to provide a new dual - power - supply switching circuit solution to solve the technical problem that the existing technology of implementing dual - power - supply switching by using two diodes at the board level is inapplicable to application scenarios where the initial input power is very low.

[0039] In one embodiment, as Figure 2 and Figure 3 shown in the figure, this embodiment provides a dual - power - supply switching circuit 100. The dual - power - supply switching circuit 100 includes a first - stage switching module 110, a first - stage control module 120, and a second - stage switching module 130. Among them, the first - stage switching module 110 can be specifically configured to generate a first output voltage VDDI_AO1 for supplying power to the first - stage control module 120 based on a first power supply voltage VDDIA and a second power supply voltage VDDIB. The first - stage control module 120 can be specifically configured to operate under the power supply of the first output voltage VDDI_AO1 to respectively generate a first judgment signal VDDIA_OK for judging whether the first power supply voltage VDDIA has a power failure and a second judgment signal VDDIB_OK for judging whether the second power supply voltage VDDIB has a power failure. The second - stage switching module 130 can specifically include a first switch component 131 and a second switch component 132, and is configured to conduct the first switch component 131 according to the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK, so that the target output voltage VDD output from the output end of the second - stage switching module 130 is the first power supply voltage VDDIA, or conduct the second switch component 132, so that the target output voltage VDD output from the output end of the second - stage switching module 130 is the second power supply voltage VDDIB.

[0040] It should be noted that the first power supply voltage VDDIA and the second power supply voltage VDDIB are specifically the power supply voltages output by two power supplies in a dual - power - supply system. Based on the working states of the two power supplies, the first power supply voltage VDDIA and the second power supply voltage VDDIB can exist simultaneously, or only one of the power supply voltages (the first power supply voltage VDDIA or the second power supply voltage VDDIB) can exist, that is, the other power supply voltage (the second power supply voltage VDDIB or the first power supply voltage VDDIA) has a power - off phenomenon. In addition, the first power supply voltage VDDIA and the second power supply voltage VDDIB can be either equal output voltages or unequal output voltages. However, since both the first power supply voltage VDDIA and the second power supply voltage VDDIB are power supply voltages for the same load in a dual - power - supply system, generally, the first power supply voltage VDDIA and the second power supply voltage VDDIB are equal output voltages.

[0041] In this way, in the embodiment of the present application, the dual - power - supply switching circuit 100 adopts a two - stage power - supply switching circuit solution, with each stage having enhanced capabilities, similar to a step - by - step "bootstrap". Specifically, the first - stage switching module 110 generates a first output voltage VDDI_AO1. This output voltage is very, very weak, with a load - carrying capacity of only a few μA, but it can ensure the normal operation of the circuit powered by it (that is, the first - stage control module 120, with extremely low power consumption). Two judgment signals (i.e., the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK) formed by the first - stage control module 120 powered by the first output voltage VDDI_AO1 are used to turn on the first switch component 131 of the second - stage switching module 130, so that the target output voltage VDD output by the output end of the second - stage switching module 130 is the first power supply voltage VDDIA, or to turn on the second switch component 132 of the second - stage switching module 130, so that the target output voltage VDD output by the output end of the second - stage switching module 130 is the second power supply voltage VDDIB, thereby realizing dual - power - supply switching. It can be seen that the entire switching process does not require the use of external diodes. Only by controlling the first switch component 131 or the second switch component 132 to conduct through corresponding signals, the corresponding power supply voltage can be switched and output as the target output voltage VDD, without the problem of diode voltage drop. Therefore, this technical solution can effectively complete the switching of dual - power - supply input voltages without causing voltage drop loss of the power - supply input voltage, and can be applicable to application scenarios with very low initial input power supplies.

[0042] In some examples, such as Figure 4As shown, in order for the first-stage switching module 110 to generate a first output voltage VDDI_AO1 for supplying power to the first-stage control module 120 based on the first power supply voltage VDDIA and the second power supply voltage VDDIB. The first-stage switching module 110 may specifically include a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, and a fourth switching transistor M4. The drain of the first switching transistor M1, the drain of the second switching transistor M2, and the gate of the third switching transistor M3 are all connected to the first power supply voltage VDDIA. The gate of the second switching transistor M2, the gate of the third switching transistor M3, and the drain of the fourth switching transistor M4 are all connected to the second power supply voltage VDDIB. The gate of the first switching transistor M1, the source of the first switching transistor M1, the source of the second switching transistor M2, the source of the third switching transistor M3, the source of the fourth switching transistor M4, and the gate of the fourth switching transistor M4 are all electrically connected to the output terminal of the first-stage switching module 110 to output the first output voltage VDDI_AO1 at the output terminal of the first-stage switching module 110. At this time, the first switching transistor M1 and the fourth switching transistor M4 form a diode connection, while the second switching transistor M2 and the third switching transistor M3 form a cross-coupled connection. When VDDIA ≠ VDDIB, VDDI_AO1 = max{VDDIA, VDDIB}. When VDDIA = VDDIB, this is the shortcoming of this circuit: the output VDDI_AO1 loses a threshold voltage Vth of a switching transistor compared to the input VDDIA or VDDIB. Taking the above first switching transistor M1, second switching transistor M2, third switching transistor M3, and fourth switching transistor M4 as ordinary PMOS transistors as an example, if VDDIA = VDDIB = 1.8V and the threshold voltage Vth of each PMOS transistor = 0.8V, then VDDI_AO1 = 1.0V, and this voltage is very low. That is, the first output voltage VDDI_AO1 is very, very weak and has a load-carrying capacity of only a few μA, and is only used to ensure the normal operation of the circuit powered by it (that is, the first-stage control module 120, with extremely low power consumption).

[0043] To avoid the problem that when VDDIA = VDDIB, the output VDDI_AO1 loses a threshold voltage Vth of a switching transistor compared to the input VDDIA or VDDIB. In some examples, the above first switching transistor M1, second switching transistor M2, third switching transistor M3, and fourth switching transistor M4 may specifically all be Native PMOS transistors. The characteristic of Native PMOS transistors is that the threshold voltage is close to 0V (it may be 200mV under the worst corner), so the loss of Vth is very small and acceptable. This is a very ingenious solution, but it depends on whether the process library supports Native PMOS transistors (generally, the lcd driver process provides Native PMOS transistors, while the standard cmos logic process does not have Native PMOS transistors).

[0044] To avoid the problem that when VDDIA = VDDIB, the output VDDI_AO1 loses the threshold voltage Vth of a switching transistor compared to the input VDDIA or VDDIB, as Figure 5 shown, in some examples, the above-mentioned first switching transistor M1, second switching transistor M2, third switching transistor M3, and fourth switching transistor M4 are all MOS transistors. Specifically, the MOS transistor can be an ordinary PMOS transistor. At this time, the first-stage switching module 110 further includes a first resistor R1 and a second resistor R2 connected in series between the first power supply voltage VDDIA and the second power supply voltage VDDIB. The connection point between the first resistor R1 and the second resistor R2 is electrically connected to the output end of the first-stage switching module 110. In this way, to solve the problem of excessive output threshold loss when VDDIA = VDDIB, this example adds two resistors R1 and R2 to form an additional parallel branch for supplying power to VDDI_AO1. That is, when VDDIA = VDDIB, at this time, the above-mentioned first switching transistor M1, second switching transistor M2, third switching transistor M3, and fourth switching transistor M4 do not work, and VDDI_AO1 is powered by the resistors R1 and R2. Assuming that the load current of VDDI_AO1 is 1uA and R2 = R3 = 200K, then VDDI_AO1 = VDDIA - 0.1V, and this loss is completely acceptable and does not affect the normal operation of the circuit connected to VDDI_AO1 below.

[0045] In some examples, as Figure 2 and Figure 3 shown, the above-mentioned first-stage control module 120 may specifically include a reference voltage generation module 121, a first comparator LPCMP1, and a second comparator LPCMP2. Among them, the reference voltage generation module 121 is configured to generate a reference output voltage VREF with a first preset voltage value based on the first output voltage VDDI_AO1. The power supply terminals of the first comparator LPCMP1 and the second comparator LPCMP2 are both connected to the first output voltage VDDI_AO1. The first input terminals of the first comparator LPCMP1 and the second comparator LPCMP2 are both connected to the reference output voltage VREF. The second input terminal of the first comparator LPCMP1 is connected to the first power supply voltage VDDIA to output a first judgment signal VDDIA_OK through the output terminal of the first comparator LPCMP1. The second input terminal of the second comparator LPCMP2 is connected to the second power supply voltage VDDIB to output a second judgment signal VDDIB_OK through the output terminal of the second comparator LPCMP2. In this example, as Figure 2As shown, the first input terminal of the above comparator (the first comparator LPCMP1 or the second comparator LPCMP2) may specifically be the inverting input terminal of the comparator, and the second input terminal of the above comparator (the first comparator LPCMP1 or the second comparator LPCMP2) may specifically be the non-inverting input terminal of the comparator.

[0046] Since the first output voltage VDDI_AO1 is very, very weak and has a load driving capacity of only a few μA, the reference voltage generation module 121 may specifically be a low-power bandgap reference circuit (LPBGR), and the first comparator LPCMP1 and the second comparator LPCMP2 may specifically be low-power comparators (LPCMP). These circuits constitute the first-stage control module 120. Typical power consumption: about 0.7 μA for LPBGR and about 0.1 μA for LPCMP. Therefore, the total power consumption of these circuits is <1 μA. When the first-stage control module 120 operates, the first comparator LPCMP1 and the second comparator LPCMP2 are used to detect whether the first power supply voltage VDDIA and the second power supply voltage VDDIB are greater than the reference output voltage VREF respectively to determine whether the corresponding power supply voltage has a power failure, and the corresponding first judgment signal VDDIA_OK and second judgment signal VDDIB_OK are obtained.

[0047] In order to adjust the detection thresholds for the first power supply voltage VDDIA and the second power supply voltage VDDIB, a resistor voltage-dividing network can be added to the input terminals of the comparator to attenuate the first power supply voltage VDDIA and the second power supply voltage VDDIB by voltage division respectively. Specifically, a third resistor R3 is also connected in series between the second input terminal of the first comparator LPCMP1 and the first power supply voltage VDDIA. The connection point between the third resistor R3 and the second input terminal of the first comparator LPCMP1 is also electrically connected to one end of a fourth resistor R4, and the other end of the fourth resistor R4 is grounded. The third resistor R3 and the fourth resistor R4 form a resistor voltage-dividing network to attenuate the first power supply voltage VDDIA and then send it to the second input terminal of the first comparator LPCMP1. A fifth resistor R5 is also connected in series between the second input terminal of the second comparator LPCMP2 and the second power supply voltage VDDIB. The connection point between the fifth resistor R5 and the second input terminal of the second comparator LPCMP2 is also electrically connected to one end of a sixth resistor R6, and the other end of the sixth resistor R6 is grounded. The fifth resistor R5 and the sixth resistor R6 form a resistor voltage-dividing network to attenuate the second power supply voltage VDDIB and then send it to the second input terminal of the second comparator LPCMP2. At this time, the first comparator LPCMP1 is used to detect whether the first power supply voltage VDDIA has a power failure. The specific method is to compare the first power supply voltage VDDIA after voltage division by the resistor string R3 / R4 with the reference output voltage VREF to generate a first judgment signal VDDIA_OK. Similarly, the second comparator LPCMP2 is used to detect whether the second power supply voltage VDDIB has a power failure. The specific method is to compare the second power supply voltage VDDIB after voltage division by the resistor string R5 / R6 with the reference output voltage VREF to generate a second judgment signal VDDIB_OK. After simple analysis, the logical expression is:

[0048] VDDIA_OK = (VDDIA >= (1 + R1 / R2) · VREF)? 1:0;

[0049] VDDIB_OK = (VDDIB >= (1 + R1 / R2) · VREF)? 1:0;

[0050] It can be seen that (1 + R1 / R2) · VREF sets the comparison threshold for power supply detection as the judgment basis for detecting whether the corresponding input power supply voltage (the first power supply voltage VDDIA or the second power supply voltage VDDIB) has a power failure.

[0051] Since the first judgment signal VDDIA_OK can be used to judge whether the first power supply voltage VDDIA has a power failure, and the second judgment signal VDDIB_OK can be used to judge whether the second power supply voltage VDDIB has a power failure, therefore, it can be as Figure 2As shown, the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK are respectively led out to be able to give an indication signal to indicate whether the current input power supply voltage (the first power supply voltage VDDIA or the second power supply voltage VDDIB) is OK, or which power supply voltage (the first power supply voltage VDDIA or the second power supply voltage VDDIB) has a power-down event. Especially for the scenario of power floating, it is very difficult for the prior art to reliably detect and handle, and this technical solution can effectively solve this problem.

[0052] To make the second-stage switching module 130 specifically configurable to conduct the first switch component 131 according to the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK, so that the target output voltage VDD output by the output end of the second-stage switching module 130 is the first power supply voltage VDDIA, or conduct the second switch component 132, so that the target output voltage VDD output by the output end of the second-stage switching module 130 is the second power supply voltage VDDIB. In some examples, such as Figure 2 and Figure 3 As shown, the second-stage switching module 130 further includes a control logic component 133, configured to perform a first preset logical operation on the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK to output a first logical signal netA for controlling the conduction or closing of the first switch component 131, and perform a second preset logical operation on the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK to output a second logical signal netB for controlling the conduction or closing of the second switch component 132. In this way, the input of the control logic component 133 is the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK, and the output is the first logical signal netA and the second logical signal netB, which are used to control the conduction or cut-off of two switch components (i.e., the first switch component 131 and the second switch component 132) respectively. Taking the switch component being specifically selected as a PMOS transistor as an example, since the first logical signal netA and the second logical signal netB being 0 indicates that the corresponding switch component is conducting, and the first logical signal netA and the second logical signal netB being 1 indicates that the corresponding switch component is disconnected, at this time, their truth table relationship can be:

[0053]

[0054]

[0055] What this truth table reflects is that there is a priority difference between the two power supply voltages. Generally, the power supply voltage with a larger voltage value is preferably selected. Taking the voltage value of the first power supply voltage VDDIA being greater than the voltage value of the second power supply voltage VDDIB as an example, we set the first power supply voltage VDDIA to be prioritized through the logic component 133 here: that is to say, when both power supply voltages are powered on, only the first power supply voltage VDDIA is selected to be on. Note that both power supply voltages should not be turned on, because this will form a direct short - circuit path from the first power supply voltage VDDIA to the second power supply voltage VDDIB, which is not allowed. Through simple analysis, to implement the above - mentioned truth table, the logical expression for performing a first preset logical operation on the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK to output the first logical signal netA that controls the conduction or cutoff of the first switch component 131 is: The logical expression for performing a second preset logical operation on the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK to output the second logical signal netB that controls the conduction or cutoff of the second switch component 132 is: Therefore, the control logic component 133 can be specifically implemented based on the above - mentioned logical expressions through a corresponding combination of gate circuits (including any combination of AND - gate circuits, OR - gate circuits, and NOT - gate circuits).

[0056] In some examples, such as Figure 6 shown, the first switch component 131 and the second switch component 132 may specifically both include a first PMOS transistor M5. The drain of the first PMOS transistor M5 is connected to the power supply voltage VDDIx (the first power supply voltage VDDIA or the second power supply voltage VDDIB), the gate of the first PMOS transistor M5 is connected to the logical signal netX (the first logical signal netA or the second logical signal netB), and the source and substrate of the first PMOS transistor M5 are electrically connected to the output terminal of the second - stage switching module 130 to output the first power supply voltage VDDIA or the second power supply voltage VDDIB through the output terminal of the second - stage switching module 130. In this way, when the logical signal netx (the first logical signal netA or the second logical signal netB) is 0, the corresponding first PMOS transistor M5 is turned on, so that the target output voltage VDD output by the output terminal of the second - stage switching module 130 is the power supply voltage VDDIx (the first power supply voltage VDDIA or the second power supply voltage VDDIB).

[0057] In some examples, such as Figure 7 shown, Figure 7In which VDDIx represents the power supply voltage, netx represents the logic signal, where x = A or B. The first switch component 131 and the second switch component 132 may specifically include a second PMOS transistor M6, a third PMOS transistor M7 and an NMOS transistor M8. The source and substrate of the second PMOS transistor M6 are both connected to the power supply voltage VDDIx (the first power supply voltage VDDIA or the second power supply voltage VDDIB), the gate of the second PMOS transistor M6, the gate of the third PMOS transistor M7 and the gate of the NMOS transistor M8 are all connected to the logic signal netx (the first logic signal netA or the second logic signal netB), the drain of the second PMOS transistor M6 is electrically connected to the drain of the third PMOS transistor M7 and the drain of the NMOS transistor M8 respectively, the source of the NMOS transistor M8 is grounded, and the source and substrate of the third PMOS transistor M7 are both electrically connected to the output end of the second-stage switching module 130, so as to output the power supply voltage VDDIx (the first power supply voltage VDDIA or the second power supply voltage VDDIB) as the target output voltage VDD through the output end of the second-stage switching module 130. In this way, the second PMOS tube M6 and the third PMOS tube M7 form a so-called "back-to-back" connection scheme. When the logic signal netx (the first logic signal netA or the second logic signal netB) is 0, the corresponding second PMOS tube M6 and the third PMOS tube M7 are turned on, and the NMOS tube M8 is not turned on. At this time, it is a normal working state, so that the target output voltage VDD output by the output end of the second-stage switching module 130 is the power supply voltage VDDIx (the first power supply voltage VDDIA or the second power supply voltage VDDIB). When the logic signal netx (the first logic signal netA or the second logic signal netB) is 1, the corresponding second PMOS tube M6 and the third PMOS tube M7 are turned off, and the NMOS tube M8 is turned on, and the middle node of the connection between the second PMOS tube M6 and the third PMOS tube M7 is pulled to the ground. At this time, the NMOS tube M8 only needs a very small size NMOS tube. At the same time, through such a structural setting, when the voltage of the first power supply voltage VDDIA is different from that of the second power supply voltage VDDIB, the substrate backflow leakage of the switch tube can be avoided.

[0058] In the embodiment of the present application, a two-stage power switching circuit is specifically adopted, with each stage having stronger capabilities than the previous one, similar to step-by-step "bootstrapping". At this time, although the output voltage output by the second-stage switching module 130 is stronger than the first output voltage VDDI_AO1 output by the first-stage switching module 110, it is only applicable to powering the entire chip and is applicable to application scenarios where the power consumption of the entire chip is not large (for example, <1mA). For some application scenarios with higher power consumption, it needs to be further improved to a three-stage power switching circuit solution. Therefore, in some examples, such as Figure 8 , Figure 9 as well as Figure 10As shown, the dual - power - supply switching circuit 100 specifically further includes a second - stage control module 140 and a third - stage switching and voltage - regulating module 150. Among them, the second - stage switching module 130 is reconfigured to conduct the first switch component 131 according to the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK, so that the second output voltage VDDI_AO2 output from the output end of the second - stage switching module 130 is the first power - supply voltage VDDIA, or conduct the second switch component 132, so that the second output voltage VDDI_AO2 output from the output end of the second - stage switching module 130 is the second power - supply voltage VDDIB. The second - stage control module 140 can be specifically configured to operate under the power supply of the second output voltage VDDI_AO2 to generate a first control signal (not shown) according to the first judgment signal VDDIA_OK, and generate a second control signal (not shown) according to the second judgment signal VDDIB_OK. The third - stage switching and voltage - regulating module 150 can specifically include a first LDO voltage - regulating output module LDOA and a second LDO voltage - regulating output module LDOB, configured to enable the first LDO voltage - regulating output module LDOA according to the first control signal, so that the target output voltage VDD output from the output end of the third - stage switching and voltage - regulating module 150 is the first regulated voltage generated based on the first power - supply voltage VDDIA, or enable the second LDO voltage - regulating output module LDOB according to the second control signal, so that the target output voltage VDD output from the output end of the third - stage switching and voltage - regulating module 150 is the second regulated voltage generated based on the second power - supply voltage VDDIB.

[0059] In this way, the target output voltage VDD is generated by the parallel output of two LDO voltage - regulating output modules. These two LDO voltage - regulating output modules can specifically be exactly the same low - dropout linear regulators (Low Dropout Regulator, abbreviated as LDO). Among them, the main input power supply of LDOA is the first power - supply voltage VDDIA, and the auxiliary input power supply is the second output voltage VDDI_AO2. It can be like Figure 9 shown, directly input the first judgment signal VDDIA_OK to enable or disable the LDOA, or can be like Figure 10 shown, input the first control signal generated by the control logic module of the second - stage control module 140 through the judgment signal VDDIx_OK (specifically the first judgment signal VDDIA_OK) to enable or disable the LDOA. When the first LDO voltage - regulating output module LDOA is enabled, the first LDO voltage - regulating output module LDOA can generate the first regulated voltage based on the first power - supply signal power voltage VDDIA for the corresponding output at the output end of the third - stage switching and voltage - regulating module 150. Similarly, the main input power supply of LDOB is the second power - supply voltage VDDIB, and the auxiliary input power supply is the second output voltage VDDI_AO2. It can be like Figure 9As shown, the second judgment signal VDDIB_OK is directly input to enable or disable the LDOB. It can also be as Figure 10 As shown, the input judgment signal VDDIx_OK (specifically the second judgment signal VDDIB_OK) is used to generate a second control signal through the control logic module of the second-stage control module 140 to enable or disable the LDOB. When the second LDO voltage regulation output module LDOB is enabled, the second LDO voltage regulation output module LDOB can generate a second regulated voltage based on the second power supply signal VDDIB for corresponding output at the output end of the third-stage switching and voltage regulation module 150. When a certain LDO (LDOA or LDOB) is turned off, its output is in a high-impedance state and does not affect the normal operation of the other LDO (LDOB or LDOA).

[0060] In some examples, as Figure 10 As shown, the first LDO voltage regulation output module LDOA and the second LDO voltage regulation output module LDOB both include a fourth PMOS transistor M9 and an operational amplifier U1. The substrate of the fourth PMOS transistor M9 and the power supply terminal of the operational amplifier U1 are both connected to the second output voltage VDDI_AO2. The non-inverting input terminal of the operational amplifier U1 is connected to the reference voltage VREF2 of the second preset voltage value. The output terminal of the operational amplifier U1 is electrically connected to the gate of the fourth PMOS transistor M9. The drain of the fourth PMOS transistor M9 is connected to the first power supply voltage VDDIA or the second power supply voltage VDDIB. The inverting input terminal of the operational amplifier U1 and the source of the fourth PMOS transistor M9 are both electrically connected to the output end of the third-stage switching and voltage regulation module 150 to output the first regulated voltage or the second regulated voltage through the output end of the third-stage switching and voltage regulation module 150. In this way, the substrate end of the fourth PMOS transistor M9, the power supply terminal of the operational amplifier U1, and the power supply of the control logic module are all the second output voltage VDDI_AO2. This ensures that even if the power supply voltage VDDIx (the first power supply voltage VDDIA or the second power supply voltage VDDIB) loses power, the substrate of the LDO (LDOA or LDOB) will not have reverse leakage, and the control logic module can work normally. Therefore, it is ensured that the LDO (LDOA or LDOB) can be normally turned off. The power consumption of the operational amplifier U1 is usually not large, about 10 - 20 μA, which is completely within the load-carrying capacity range of the second output voltage VDDI_AO2.

[0061] In addition, based on the above embodiments, (1 + R1 / R2)·VREF sets the comparison threshold for power supply detection. At the same time, the first judgment signal VDDIA_OK also acts on the first LDO voltage stabilization output module LDOA of the third-stage switching and voltage stabilization module 150, and the second judgment signal VDDIB_OK also acts on the second LDO voltage stabilization output module LDOB of the third-stage switching and voltage stabilization module 150. At this time, in order to solve the situation where the power supply floats after the first power supply voltage VDDIA or the second power supply voltage VDDIB loses power, the selection of the threshold value of (1 + R1 / R2)·VREF is very important: it needs to be greater than or equal to the target output voltage VDD output at the output end of the third-stage switching and voltage stabilization module 150. Because when a power failure occurs, assuming that the first power supply voltage VDDIA loses power, the first LDO voltage stabilization output module LDOA of the third-stage switching and voltage stabilization module 150 will drag the first power supply voltage VDDIA through the power transistor substrate backflow, preventing the first power supply voltage VDDIA from further decreasing, so that the first power supply voltage VDDIA will eventually stabilize at a voltage slightly lower than the target output voltage VDD. If the detection threshold (1 + R1 / R2)·VREF < VDD, then the comparator (the first comparator LPCMP1 and the second comparator LPCMP2) may not detect the power failure event of the power supply voltage (the first power supply voltage VDDIA and the second power supply voltage VDDIB) due to the too low threshold value. Take a design example: assume VDD = 1.32V, then (1 + R1 / R2)·VREF = 1.4V can be selected. Assume VREF = 1.0V, then R1 / R2 = 0.4, and R1 = 80K and R2 = 200K can be selected.

[0062] In one embodiment, the embodiment of the present application provides a power supply architecture (not shown), including a first power supply, a second power supply, and the above-mentioned dual-power switching circuit 100. The first power supply outputs a first power supply voltage VDDIA, and the second power supply outputs a second power supply voltage VDDIB.

[0063] Taking this power supply architecture as the SOC power supply architecture as an example, in some examples, such as Figure 11 shown, the one proposed uses Figure 8The SoC power supply architecture of the dual power supply switching circuit shown. The Power Switch inputs two power supply voltages (the first power supply voltage VDDIA and the second power supply voltage VDDIB), and the Power Switch outputs two "always on" output voltages (the first output voltage VDDI_AO1 and the second output voltage VDDI_AO2). Among them, the ability of the first output voltage VDDI_AO1 is very weak (the load-carrying capacity is several μA), and the ability of the second output voltage VDDI_AO2 is medium (the load-carrying capacity is several hundred μA). The PowerSwitch also outputs two power supply indication flag signals (the first judgment signal VDDIA_OK and the second judgment signal VDDIB_OK), which are sent to LDOA and LDOB and other required circuits. LDOA and LDOB are used in parallel to output the target output voltage VDD, forming a power supply switching and voltage stabilizing circuit with strong load-carrying capacity. Preferably, LDOA and LDOB are exactly the same LDO. When both the first power supply voltage VDDIA and the second power supply voltage VDDIB are powered on, both LDOA and LDOB work, and they share the load current together. When VDDIx (the first power supply voltage VDDIA or the second power supply voltage VDDIB) is powered off (floating or pulled to GND), the Power Switch detects that VDDIx (the first power supply voltage VDDIA or the second power supply voltage VDDIB) is powered off, and then outputs VDDIx_OK (the first judgment signal VDDIA_OK or the second judgment signal VDDIB_OK) = 0, thereby turning off LDOx (LDOA or LDOB). At this time, the other LDOx (LDOB or LDOA) provides the target output voltage VDD and the corresponding load current.

[0064] Generally, we will make the core part of the clock / reset / power supply system work under the second output voltage VDDI_AO2, which includes circuits such as OSC, POR (VDDI_POR), BGR / IBIAS, etc. If any VDDIx (the first power supply voltage VDDIA or the second power supply voltage VDDIB) loses power, the second output voltage VDDI_AO2 is still powered on, and these circuits will not be affected. This is a necessary condition for the entire system to still be able to maintain normal operation.

[0065] The main part of the SoC system, including the CPU, memory system, and peripheral system, is connected under the target output voltage VDD. The corresponding POR circuit (VDD_POR) should also be included under the target output voltage VDD. As long as one of VDDIx (the first power supply voltage VDDIA or the second power supply voltage VDDIB) is powered on, the target output voltage VDD is always powered on, ensuring that the SoC system can work normally.

[0066] There may be some I / O PADs used to define or change the function of the Power Switch. This part of the I / O PADs needs to work under the first output voltage VDDI_AO1. For example, the BYP PAD is used for the bypass function of the Power Switch: when BYP = 0, the Power Switch works normally; when BYP = 1, the Power Switch is blocked, and the first power supply voltage VDDIA can directly pass through the first output voltage VDDI_AO1 and the second output voltage VDDI_AO2. Using I / O PADs to define and change the function of the chip is an important design for testability means.

[0067] There may be some I / O PADs (except for the Power Switch) used to define or change the function of the chip. For example, the reset pin RSTN, the IM pin (used to select the communication interface mode) for driving the display chip, the enable pin of the LDO, the enable pin of the OSC external injection mode, etc. This part of the I / O must be powered to ensure the normal operation of the system. Therefore, it needs to work under the second output voltage VDDI_AO2.

[0068] In some examples, such as Figure 12 shown, a proposed Figure 2 SoC power supply architecture using the dual - power - switching circuit shown. There is only one LDO, and its working power supply is VDDI_AO2. From this block diagram, the working power supply of the entire chip is VDDI_AO2. The circuits below it include BGR, OSC, POR, LDO, IO, etc. Below the LDO, there are CPU, System, POR, etc. In short, the final current all comes from VDDI_AO2. For the SoC system adopting this power supply scheme, the power consumption should not be too large.

[0069] Although the present application has been shown and described relative to one or more implementations, those skilled in the art will envision equivalent variations and modifications based on the reading and understanding of this specification and the drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, regarding the various functions performed by the above - mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the described component (i.e., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of this specification shown herein.

[0070] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of the present application, such as the mutual combination of technical features between various embodiments, or directly or indirectly applied in other related technical fields, is similarly included in the patent protection scope of the present application.

[0071] In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0072] In the present application, the word "exemplary" is used to mean "serving as an example, illustration, or explanation". Any embodiment described as "exemplary" in the present application is not necessarily construed as more preferred or more advantageous than other embodiments. The above description is given in order to enable any person skilled in the art to implement and use the present application. In the above description, various details are set forth for purposes of explanation. It should be understood that those of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail so as not to obscure the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope that conforms to the principles and features disclosed in the present application.

Claims

1. A dual-power switching circuit, characterized in that, It includes a first-stage switching module, a first-stage control module, and a second-stage switching module. Among them, the first-stage switching module is configured to generate a first output voltage for supplying power to the first-stage control module based on a first power supply voltage and a second power supply voltage; the first-stage control module is configured to operate under the power supply of the first output voltage to respectively generate a first judgment signal for judging whether the first power supply voltage has a power failure and a second judgment signal for judging whether the second power supply voltage has a power failure; the second-stage switching module includes a first switch component and a second switch component, and is configured to conduct the first switch component according to the first judgment signal and the second judgment signal, so that the target output voltage output by the output end of the second-stage switching module is the first power supply voltage, or conduct the second switch component, so that the target output voltage output by the output end of the second-stage switching module is the second power supply voltage; the first-stage switching module includes a first switch transistor, a second switch transistor, a third switch transistor, and a fourth switch transistor. The drain of the first switch transistor, the drain of the second switch transistor, and the gate of the third switch transistor are all connected to the first power supply voltage. The gate of the second switch transistor, the drain of the third switch transistor, and the drain of the fourth switch transistor are all connected to the second power supply voltage. The gate of the first switch transistor, the source of the first switch transistor, the source of the second switch transistor, the source of the third switch transistor, the source of the fourth switch transistor, and the gate of the fourth switch transistor are all electrically connected to the output end of the first-stage switching module to output the first output voltage at the output end of the first-stage switching module.

2. The dual-power switching circuit according to claim 1, wherein The first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are all Native PMOS transistors; or, the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are all PMOS transistors. The first-stage switching module further includes a first resistor and a second resistor connected in series between the first power supply voltage and the second power supply voltage. The connection point between the first resistor and the second resistor is electrically connected to the output end of the first-stage switching module.

3. The double power supply switching circuit according to claim 1, wherein The first-stage control module includes a reference voltage generation module, a first comparator, and a second comparator. The reference voltage generation module is configured to generate a reference output voltage with a first preset voltage value based on the first output voltage. The power supply terminals of the first comparator and the second comparator are both connected to the first output voltage. The first input terminals of the first comparator and the second comparator are both connected to the reference output voltage. The second input terminal of the first comparator is connected to the first power supply voltage to output the first judgment signal through the output terminal of the first comparator. The second input terminal of the second comparator is connected to the second power supply voltage to output the second judgment signal through the output terminal of the second comparator.

4. The dual-power switching circuit according to claim 3, wherein A third resistor is also connected in series between the second input terminal of the first comparator and the first power supply voltage. The connection point between the third resistor and the second input terminal of the first comparator is also electrically connected to one end of a fourth resistor, and the other end of the fourth resistor is grounded. The third resistor and the fourth resistor form a resistor voltage dividing network to attenuate the first power supply voltage and then send it to the second input terminal of the first comparator; a fifth resistor is also connected in series between the second input terminal of the second comparator and the second power supply voltage. The connection point between the fifth resistor and the second input terminal of the second comparator is also electrically connected to one end of a sixth resistor, and the other end of the sixth resistor is grounded. The fifth resistor and the sixth resistor form a resistor voltage dividing network to attenuate the second power supply voltage and then send it to the second input terminal of the second comparator.

5. The dual-power switching circuit according to claim 1, characterized in that, The second-stage switching module further includes: A control logic component configured to perform a first preset logic operation on the first judgment signal and the second judgment signal to output a first logic signal for controlling the conduction or cutoff of the first switching component, and perform a second preset logic operation on the first judgment signal and the second judgment signal to output a second logic signal for controlling the conduction or cutoff of the second switching component.

6. The dual power supply switching circuit according to claim 5, wherein Both the first switching component and the second switching component include a first PMOS transistor. The drain of the first PMOS transistor is connected to the first power supply voltage or the second power supply voltage. The gate of the first PMOS transistor is connected to the first logic signal or the second logic signal. The source and substrate of the first PMOS transistor are electrically connected to the output terminal of the second-stage switching module to output the first power supply voltage or the second power supply voltage through the output terminal of the second-stage switching module. Alternatively, both the first switching component and the second switching component include a second PMOS transistor, a third PMOS transistor, and an NMOS transistor. The source and substrate of the second PMOS transistor are both connected to the first power supply voltage or the second power supply voltage. The gates of the second PMOS transistor, the third PMOS transistor, and the NMOS transistor are all connected to the first logic signal or the second logic signal. The drain of the second PMOS transistor is electrically connected to the drains of the third PMOS transistor and the NMOS transistor respectively. The source of the NMOS transistor is grounded. The source and substrate of the third PMOS transistor are both electrically connected to the output terminal of the second-stage switching module to output the first power supply voltage or the second power supply voltage through the output terminal of the second-stage switching module.

7. The dual-power switching circuit according to any one of claims 1-6, characterized in that, It further includes a second-stage control module and a third-stage switching and voltage stabilizing module, where The second-stage switching module is reconfigured to, according to the first judgment signal and the second judgment signal, turn on the first switching component so that the second output voltage output by the output terminal of the second-stage switching module is the first power supply voltage, or turn on the second switching component so that the second output voltage output by the output terminal of the second-stage switching module is the second power supply voltage. The second - stage control module is configured to operate under the power supply of the second output voltage, generate a first control signal according to the first judgment signal, and generate a second control signal according to the second judgment signal; The third - stage switching and voltage - stabilizing module includes a first LDO voltage - stabilizing output module and a second LDO voltage - stabilizing output module, and is configured to enable the first LDO voltage - stabilizing output module according to the first control signal, so that the target output voltage output by the output end of the third - stage switching and voltage - stabilizing module is a first regulated voltage generated based on the first power supply voltage, or enable the second LDO voltage - stabilizing output module according to the second control signal, so that the target output voltage output by the output end of the third - stage switching and voltage - stabilizing module is a second regulated voltage generated based on the second power supply voltage.

8. The dual-power switching circuit according to claim 7, characterized in that, Both the first LDO voltage - stabilizing output module and the second LDO voltage - stabilizing output module include a fourth PMOS transistor and an operational amplifier. The substrate of the fourth PMOS transistor and the power supply terminal of the operational amplifier are both connected to the second output voltage. The non - inverting input terminal of the operational amplifier is connected to a reference voltage of a second preset voltage value. The output terminal of the operational amplifier is electrically connected to the gate of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the first power supply voltage or the second power supply voltage. The inverting input terminal of the operational amplifier and the source of the fourth PMOS transistor are both electrically connected to the output end of the third - stage switching and voltage - stabilizing module, so as to output the first regulated voltage or the second regulated voltage through the output end of the third - stage switching and voltage - stabilizing module.

9. A power supply architecture, characterized in that, It includes a first power supply, a second power supply, and the dual - power - supply switching circuit according to any one of claims 1 - 8. The first power supply outputs the first power supply voltage, and the second power supply outputs the second power supply voltage.

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