Semiconductor memory device and error detection and correction method

Abstract

The present invention provides a semiconductor storage device and an error detection and correction method, achieving coexistence of error detection and correction capabilities and write or read performance. The error detection and correction method of the flash memory of the present invention includes: a setting step of setting selection information for selecting a first error detection and correction function for performing 1-bit error detection and correction or a second error detection and correction function for performing multi-bit error detection and correction; and an execution step of executing the first error detection and correction function or the second error detection and correction function based on the set selection information during a read operation or a write operation.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and an error detection and correction method for a NAND (Not AND) type flash memory, and particularly to a switching of an error detection and correction function. Background Art

[0002] In a NAND type flash memory, bit errors are caused by repeatedly programming or erasing data. As a countermeasure against such bit errors, an error detection and correction circuit (hereinafter referred to as an ECC (Error Correcting Code) circuit) is mounted on the flash memory (for example, Patent Documents: Japanese Patent No. 6744950, Japanese Patent No. 6744951).

[0003] In Figure 1 shows a schematic structure of a conventional NAND type flash memory equipped with an on-chip ECC function. The flash memory 10 includes: a memory cell array 20, a page buffer / sensing circuit 30, an ECC circuit 40, and an input / output circuit 50. The ECC circuit 40 includes: a transmission circuit 42, an ECC core 44, an error register 46, and a write circuit 48.

[0004] In a read operation, data read from a selected page of the memory cell array 20 is held in the page buffer / sensing circuit 30, and the data held in the page buffer / sensing circuit 30 is transmitted to the ECC core 44 via the transmission circuit 42. The ECC core 44 performs an ECC operation on the transmitted data, and holds the error information obtained by the operation in the error register 46. The write circuit 48 writes the corrected data back to the page buffer / sensing circuit 30 based on the error information held in the error register 46. Thus, after the ECC processing of one page is completed, the data held in the page buffer / sensing circuit 30 is read out to the data bus 60 in accordance with the column address, and the read data is provided to the input / output circuit 50. The input / output circuit 50 outputs the read data to the outside from an input / output terminal (not shown).

[0005] In a write operation, data to be programmed input from the outside is held in the page buffer / sensing circuit 30, the ECC core 44 generates a code (parity bit) of the data transmitted from the page buffer / sensing circuit 30, and the write circuit 48 writes the generated code to a position corresponding to the spare area of the page buffer / sensing circuit 30. After the ECC processing, the data held in the page buffer / sensing circuit 30 is programmed into the memory cell array 20.

[0006] If the data size of one page becomes larger, it will have a great impact on the read or write time of the page, or the operation frequency during continuous multi-page reading synchronized with an external clock signal based on the Serial Peripheral Interface (SPI). In addition, although high speed is achieved through pipelining, it also leads to an increase in chip size, making it difficult to achieve the coexistence of error detection and correction capabilities and reading performance.

[0007] Focusing on such existing problems, an object of the present invention is to provide a semiconductor memory device and an error detection and correction method that achieve the coexistence of error detection and correction capabilities and write or read performance. Summary of the Invention

[0008] The error detection and correction method of the semiconductor memory device of the present invention includes: a setting step of setting selection information for selecting a first error detection and correction function for performing error detection and correction of m bits or a second error detection and correction function for performing error detection and correction of n bits (m and n are natural numbers, m < n); and an execution step of executing the first error detection and correction function or the second error detection and correction function based on the selection information during a read operation or a write operation.

[0009] The semiconductor memory device of the present invention includes: a memory cell array; an error detection and correction circuit including a first error detection and correction function for performing error detection and correction of m bits and a second error detection and correction function for performing error detection and correction of n bits (m and n are natural numbers, m < n); a setting register for setting selection information for selecting the first error detection and correction function or the second error detection and correction function; and a controller for executing the first error detection and correction function or the second error detection and correction function based on the selection information during a read operation or a write operation.

[0010] According to the present invention, since the first error detection and correction function or the second error detection and correction function can be selected, for example, the coexistence with the performance of read or write operations can be achieved by switching the error detection and correction capabilities according to the product life cycle or the like. Brief Description of the Drawings

[0011] Figure 1 It is a diagram showing a schematic structure of a NAND flash memory equipped with an existing on-chip ECC function.

[0012] Figure 2 It is a block diagram showing the structure of a NAND flash memory according to an embodiment of the present invention.

[0013] Figure 3 It is a diagram showing the internal structure of an ECC circuit according to an embodiment of the present invention.

[0014] Figure 4 This is a diagram showing an example of a setting register according to the first embodiment of the present invention.

[0015] Figure 5 This is a diagram for explaining the operation of the ECC circuit according to the first embodiment of the present invention.

[0016] Figure 6 This is a flowchart for explaining the switching operation of the error detection and correction capability of the ECC circuit according to the first embodiment of the present invention.

[0017] Figure 7 This is a diagram showing an example of a setting register according to the third embodiment of the present invention.

[0018] Figure 8 This is a flowchart for explaining the switching operation of the error detection and correction capability of the ECC circuit according to the third embodiment of the present invention.

[0019] Figure 9 of (A), Figure 9 of (B) is a block diagram showing the structure of the decoder of the ECC circuit according to the embodiment of the present invention.

[0020] Description of symbols

[0021] 10, 100: Flash memory

[0022] 20, 110: Memory cell array

[0023] 30, 170: Page buffer / sensing circuit

[0024] 40, 130: ECC circuit

[0025] 42, 136: Transmission circuit

[0026] 44: ECC core

[0027] 46: Error register

[0028] 48, 138: Write circuit

[0029] 50, 120: Input / output circuit

[0030] 60: Data bus

[0031] 132: First ECC section

[0032] 134: Second ECC section

[0033] 135: ECC processing section

[0034] 140: Address register

[0035] 150: Controller

[0036] 160: Word line selection circuit

[0037] 180: Column selection circuit

[0038] 190: Setting register

[0039] 200: Regular area

[0040] 210: Spare area

[0041] 300: BCH decoder

[0042] 310: Syndrome calculation unit

[0043] 320: Euclidean division calculation unit

[0044] 330: Error position search unit

[0045] 340: Error bit correction unit

[0046] Ax: Row address information

[0047] Ay: Column address information

[0048] BLK(0), BLK(1), …, BLK(m - 1): Memory blocks

[0049] CLK: Clock signal

[0050] CLK_ECC: Internal clock signal

[0051] DATA_IN: Data

[0052] EN_1: First enable signal

[0053] EN_2: Second enable signal

[0054] ENABLE_IN: Enable signal

[0055] EUC_E: End signal (pulse signal)

[0056] EUC_S: Start signal (pulse signal)

[0057] S100, S110, S120, S130, S200, S210, S220, S230: Steps

[0058] t1, t2, t3, t4: Processing periods

[0059] VALID_IN: Valid signal Detailed implementation manners

[0060] Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The semiconductor memory device of the present invention is, for example, a NAND type flash memory, or a microprocessor, a microcontroller, logic, an application specific integrated circuit (ASIC), a processor for processing images or sounds, or a processor for processing wireless signals in which such a flash memory is embedded.

[0061] Figure 2 FIG. is a diagram showing the internal structure of a NAND type flash memory according to an embodiment of the present invention. The flash memory 100 includes: a memory cell array 110 in which a plurality of memory cells are arranged in a matrix; an input / output circuit 120 connected to an external input / output terminal and outputting read data to the outside or importing data input from the outside; an ECC circuit 130 generating an error correction code for data to be programmed or performing error detection and correction of data read based on the error correction code; an address register 140 receiving address data via the input / output circuit 120; a controller 150 controlling each part based on a command (instruction) received via the input / output circuit 120 or a control signal applied to a control terminal; a word line selection circuit 160 selecting a block or a word line based on a decoding result of row address information Ax from the address register 140; a page buffer / sensing circuit 170 holding data read from a selected page of the memory cell array 110 or holding data to be programmed to the selected page; a column selection circuit 180 selecting a column based on a decoding result of column address information Ay from the address register 140; and a setting register 190 setting selection information regarding a plurality of error detection and correction functions. Although not shown here, the flash memory 100 includes an internal voltage generation circuit that generates voltages (programming voltage Vpgm, pass voltage Vpass, read voltage Vread, erase voltage Vers) required for data reading, programming (writing), and erasing. In addition, the NAND type flash memory 100 may be equipped with an SPI for achieving compatibility with the operation of a NOR type flash memory.

[0062] The memory cell array 110 has, for example, m memory blocks BLK(0), BLK(1), …, BLK(m−1) arranged in the column direction. A plurality of NAND strings are formed in one memory block. One NAND string includes a plurality of memory cells connected in series, a bit line side selection transistor, and a source line side selection transistor. The drain of the bit line side selection transistor is connected to a corresponding global bit line, and the source of the source line side selection transistor is connected to a common source line. The gates of the memory cells are connected to corresponding word lines, and the gates of the bit line side selection transistor and the source line side selection transistor are connected to a selection gate line SGD and a selection gate line SGS, respectively. The word line selection circuit 160 drives the bit line side selection transistor and the source line side selection transistor via the selection gate line SGD and the selection gate line SGS based on the row address information Ax to select a block or a word line.

[0063] The NAND strings can be formed two-dimensionally on the substrate surface or three-dimensionally on the substrate surface. In addition, the memory cells can be of a single level cell (SLC) type that stores 1 bit (binary data) or a type that stores multiple bits.

[0064] In a read operation, a certain positive voltage is applied to the bit line, a certain voltage (e.g., 0V) is applied to the selected word line, a pass voltage Vpass (e.g., 4.5V) is applied to the non-selected word lines, and a positive voltage (e.g., 4.5V) is applied to the selection gate line SGD and the selection gate line SGS to turn on the bit line side selection transistor and the source line side selection transistor and make the common source line SL 0V. In a programming operation, a high programming voltage Vpgm (e.g., 15V to 20V) is applied to the selected word line, an intermediate potential (e.g., 10V) is applied to the non-selected word lines, the bit line side selection transistor is turned on, the source line side selection transistor is turned off, and a potential corresponding to data “0” or “1” is supplied to the bit line. In an erase operation, 0V is applied to the selected word line in the block, and a high voltage (e.g., 20V) is applied to the P well.

[0065] In one embodiment, the ECC circuit 130 is as Figure 3includes a first ECC unit 132 having a 1-bit error detection and correction function and a second ECC unit 134 having an 8-bit error detection and correction function as shown. The first ECC unit 132 encodes / decodes data using a Hamming code, and the second ECC unit 134 encodes / decodes data using a BCH code. A first enable signal EN_1 and a second enable signal EN_2 are respectively supplied to the first ECC unit 132 and the second ECC unit 134 from a controller 150. The first ECC unit 132 is enabled when the first enable signal EN_1 is in a first logic state and disabled when the first enable signal EN_1 is in a second logic state. The second ECC unit 134 is enabled when the second enable signal EN_2 is in a first logic state and disabled when the second enable signal EN_2 is in a second logic state. The first ECC unit 132 and the second ECC unit 134 perform ECC processing synchronously with the supplied internal clock signal CLK_ECC.

[0066] The setting register 190 sets selection information for selecting the operation of the first ECC unit 132 or the second ECC unit 134 and holds the same. The selection information includes, for example, a 1-bit flag as shown Figure 4 where the flag "0" designates the selection of the first ECC unit 132 and the flag "1" designates the selection of the second ECC unit 134. In one form, the selection information is loaded from a fuse read-only memory (ROM) (fuse memory cell) during the power-on sequence of the flash memory 100. In the default state or at the factory, the flag "0" is saved as the selection information in the fuse ROM. During the initial or first half of the life cycle, the aging deterioration of the memory cells is relatively small, so the frequency of predicted errors is small. Therefore, the first ECC unit 132 is selected as the initial setting. Thus, during the first half of the life cycle, the ECC processing time is short, and accordingly, the read or write time is suppressed from becoming longer due to the ECC processing.

[0067] The setting register 190 can be accessed externally, and the user can rewrite the selection information set in the setting register 190 using a prescribed instruction. When a write instruction and write data for the setting register are received from a host computer via the input / output circuit 120, the controller 150 writes the write data to the setting register 190. Thereby, the selection information is rewritten. When the life cycle reaches the second half and aging deterioration of the memory cells occurs, the predicted error occurrence frequency increases accordingly. To cope with this, by selecting the second ECC unit 134, a switch is made from a single-bit error detection and correction function to a multi-bit error detection and correction function. Thus, during the second half of the life cycle, the read or write time becomes longer due to the ECC processing, but conversely, the error detection and correction ability increases, and a decrease in reliability is suppressed.

[0068] The controller 150 includes a microcontroller or a state machine, and controls the overall operations such as switching of read, program, erase, and error detection and correction functions of the flash memory 100 based on instructions or control signals received from the outside.

[0069] Next, the operation of the ECC circuit 130 will be described. During the program operation, the data input from the input / output circuit 120 is held in the page buffer / sensing circuit 170, and then the held data is transferred to the ECC circuit 130. The ECC circuit 130 performs an ECC operation on the transferred data, generates an error correction code (e.g., parity bits), and writes the generated error correction code back to the spare area of the page buffer / sensing circuit 170. Thereafter, the input data and the error correction code are programmed to the selected page of the memory cell array 110.

[0070] During the read operation, the data read from the selected page of the memory cell array 110 is transferred to the page buffer / sensing circuit 170 and held therein. Then, the held data is transferred to the ECC circuit 130, and the ECC circuit 130 detects whether there is an error based on the error correction code. In the case where an error is detected, the error of the data is corrected. The correction of the error is performed, for example, by rewriting the data held in the page buffer / sensing circuit 170. Thereafter, the data held in the page buffer / sensing circuit 170 is output to the outside via the input / output circuit 120.

[0071] In Figure 5 an example of the data structure of the page buffer / sensing circuit 170 is shown. The page buffer / sensing circuit 170 includes, for example: a normal area 200, which is divided into 8 sectors from sector 0 to sector 7; and a spare area 210, which is divided into 4 sectors of spare 0, spare 1, spare 2, and spare 3. The normal area is used for storing data. One sector of the normal area 200 contains, for example, 256 bytes, and the 8 sectors of the normal area 200 hold approximately 2K bytes of data in total.

[0072] One sector of the spare area 210 contains, for example, 16 bytes, and the 4 sectors (spare 0 to spare 3) hold 64 bytes of data in total. The error correction codes of sectors 0 and 1 of the normal area 200 are stored in spare 0, the error correction codes of sectors 2 and 3 of the normal area 200 are stored in spare 1, the error correction codes of sectors 4 and 5 of the normal area 200 are stored in spare 2, and the error correction codes of sectors 6 and 7 of the normal area 200 are stored in spare 3.

[0073] The ECC circuit 130 includes: a transmission circuit 136 that receives data transmitted in units of sectors and transmits the data to the ECC processing unit 135; an ECC processing unit 135 that includes a first ECC unit 132 having a 1-bit error detection and correction function and a second ECC circuit 134 having an 8-bit error detection and correction function; and a write circuit 138 that writes an error correction code to the spare area 210 or writes the corrected data to the normal area 200.

[0074] Based on the selection information (flag) set in the setting register 190, the controller 150 outputs an enable signal EN_1 and an enable signal EN_2 to the ECC circuit 130, and selectively operates the first ECC unit 132 or the second ECC unit 134. The first ECC unit 132 performs single-bit error detection and correction using a Hamming code, and the second ECC unit 134 performs 8-bit error detection and correction using a BCH code. The time required for the first ECC unit 132 is shorter than the time required for the second ECC unit 134. Therefore, when the first ECC unit 132 is selected, the time required for reading or writing can be shortened compared to when the second ECC unit 134 is selected. On the contrary, when the second ECC unit 134 is selected, more error bits can be detected and corrected compared to when the first ECC unit 132 is selected.

[0075] Figure 6 This is a flowchart illustrating the switching operation of the error detection and correction capability of the ECC circuit according to the first embodiment of the present invention. The initial value of the selection information of the first ECC unit 132 or the second ECC unit 134 of the ECC circuit 130 is stored in a fuse ROM (for example, an area inaccessible to the user) different from the user usage area of the memory cell array 110. The initial value of the selection information sets the selection of the first ECC unit 132 as the information when the product leaves the factory. When the power-up sequence is executed, the selection information stored in the fuse ROM is loaded into the setting register 190 (S100).

[0076] The controller 150 refers to the selection information in the setting register 190, enables the first ECC unit 132 via the enable signal EN_1, and disables the second ECC unit 134 via the enable signal EN_2. As a result, during the read or write operation, the selected first ECC unit 132 operates and the second ECC unit 134 does not operate (S110).

[0077] Thereafter, the user rewrites the selection information of the setting register 190 according to the usage status of the flash memory to select the second ECC unit 134 (S120). After the selection information is rewritten, the controller 150 disables the first ECC unit 132 via the enable signal EN_1 and enables the second ECC unit 134 via the enable signal EN_2. Thus, during the read or write operation, the selected second ECC unit 134 operates, and the first ECC unit 132 does not operate (S130).

[0078] As described above, according to this embodiment, since the first ECC unit 132 or the second ECC unit 134 is operated according to the selection information of the setting register, the error detection and correction capability can be selectively switched according to the product life cycle, and the processing time of error detection and correction can be optimally managed to suppress the decrease in the page read time or the operation frequency of continuous reading. That is, during the period when the aging deterioration of the memory cells is small, the time required for ECC processing can be shortened to achieve high-speed reading or writing. On the other hand, during the period when the aging deterioration of the memory cells increases, the error correction capability can be enhanced to improve the reliability.

[0079] Furthermore, the setting register 190 loads the initial value from the fuse ROM, but this is just an example, and this embodiment is not necessarily limited to this form. For example, the setting register 190 can use a part of the memory space in the area that can be used by the user of the memory cell array 110, and the default value (erased state) of this memory space can also indicate the selection of the first ECC unit 132. In this case, the controller 150 reads the default value of the memory space, enables the first ECC unit 132, and disables the second ECC unit 134. When the second ECC unit 134 is selected, the user programs the default value of the memory space and rewrites the selection information.

[0080] Next, a second embodiment of the present invention will be described. In the first embodiment, when switching the operation from the first ECC unit 132 to the second ECC unit 134, the second ECC unit 134 cannot decode the data encoded by the first ECC unit 132. That is, the error correction code generated by the first ECC unit 132 stored in the memory cell array 110 cannot be interpreted by the second ECC unit 134. Therefore, when switching to the second ECC unit 134, the error correction code generated by the first ECC unit 132 must be converted into the error correction code generated by the second ECC unit 134.

[0081] Therefore, the second embodiment utilizes the copy back function of the flash memory to read the page processed by the first ECC unit 132 from the memory cell array to the page buffer / sensing circuit 170, and uses the first ECC unit 132 to decode the read data (i.e., perform error detection and correction), and then uses the second ECC unit 134 to encode the decoded data again to generate an error correction code, and programs the data including the generated error correction code to the original page of the memory cell array.

[0082] This kind of data conversion is implemented for all data regarding the first ECC unit 132 stored in the memory cell array 110. The controller 150 automatically implements the data conversion using the copy back function in the background without interfering with the operation of the flash memory 100, or automatically implements the data conversion using the copy back function during the period when no operations such as reading or writing are performed. Additionally, in a certain form, it can be set to save a flag indicating data conversion or non-conversion in the spare area, and the controller 150 refers to the flag to perform data conversion and rewrites the flag after conversion.

[0083] Thus, according to this embodiment, since the data conversion is automatically performed using the copy back function, the switching of the error correction function from the first ECC unit 132 to the second ECC unit 134 can be smoothly implemented.

[0084] Next, a third embodiment of the present invention will be described. In this embodiment, the error detection and correction capability is switched according to the address space. Figure 7 FIG. shows a setting example of the setting register 190 of this embodiment. The relationship between the address space and the corresponding flag is preset in the setting register 190. The address space defines the range of the row address of the memory cell array 110. For example, the flag "0" is assigned to the address space 1, the flag "1" is assigned to the address space 2, and the flag "0" is assigned to the address space 3. The flag "0" indicates the selection of the first ECC unit 132, and the flag "1" indicates the selection of the second ECC unit 134. Therefore, when reading or writing to the address space 1, the first ECC unit 132 is selected, and when reading or writing to the address space 2, the second ECC unit 134 is selected.

[0085] Figure 8 FIG. shows the flow of the switching operation of the error detection and correction capability of the ECC circuit based on the third embodiment. When performing a read or write operation, an instruction or address for reading or writing is input from the outside via the input / output circuit 120 (S200).

[0086] The controller 150 refers to the setting register 190, identifies the flag of the address space corresponding to the row address of the input address (S210), selects the first ECC unit 132 or the second ECC unit 134 according to the identified flag, and thus enables the first ECC unit 132 or the second ECC unit 134 via the enable signal EN_1 and the enable signal EN_2. In this way, during the read operation or the write operation, error detection and correction are performed by the first ECC unit 132 or the second ECC unit 134 selected according to the address (S230).

[0087] In this way, according to this embodiment, the error detection and correction capability can be changed according to the address space. For example, it can be set that in the case where the host-side computer manages the number of data rewrite times or erase times of the memory cell array in units of blocks, the address space is set in units of blocks, and when the number of data rewrite times or erase times reaches a certain level or more, the flag of the address space is rewritten from "0" to "1". Thus, the error detection and correction capability can be changed according to the aging deterioration of the memory cells in the address space.

[0088] Next, a specific example of the second ECC unit 134 will be described. The second ECC unit 134 includes an encoder that encodes data using a BCH code and a decoder that decodes the BCH-encoded data. Figure 9 FIG. (A) is a block diagram showing the internal structure of a BCH decoder. The BCH decoder 300 includes: a syndrome calculation unit 310 that evaluates the syndrome of data, a Euclidean division calculation unit 320 that calculates an error location polynomial (ELP), an error location search unit 330 that calculates the roots of the error location polynomial and searches for the error location, and an error bit correction unit 340 that writes the corrected data back to the page buffer / sensing circuit 170 based on the searched error location.

[0089] In the BCH decoder 300, input terminals for receiving a reset signal RST, a clock signal CLK for ECC operation, an enable signal ENABLE_IN, a valid signal VALID_IN, and data DATA_IN are provided. The syndrome calculation unit 310 outputs a start signal EUC_S indicating its evaluation result and the start of Euclidean division calculation to the Euclidean division calculation unit 320. The Euclidean division calculation unit 320 outputs the calculation result of the error location polynomial and an end signal EUC_E indicating the end of the calculation to the error location search unit 330.

[0090] Figure 9Part (B) is a timing diagram showing the processing examples of the respective parts of the BCH decoder. t1 represents the processing period of the syndrome calculation unit 310, t2 represents the processing period of the Euclidean reciprocal division calculation unit 320, t3 represents the processing period of the error position search unit 330, and t4 represents the processing period of the error bit correction unit 340.

[0091] The BCH decoder 300 processes in synchronization with the input clock signal CLK and can be operated by changing the enable signal ENABLE_IN to the H level. During the H level period of the valid signal VALID_IN, the data held in the page buffer / sensing circuit is imported from DATA_IN to the syndrome calculation unit 310. When the calculation of the syndrome is completed, the syndrome calculation unit 310 outputs a pulse signal EUC_S indicating the start of the Euclidean reciprocal division. In response to this, the Euclidean reciprocal division calculation unit 320 calculates the error position polynomial. When the calculation of the error position polynomial is completed, the Euclidean reciprocal division calculation unit 320 outputs a pulse signal EUC_E indicating its end. In response to this, the error position search unit 330 searches for the error position. The error bit correction unit 340 rewrites the data of the page buffer / sensing circuit 170 via the output terminal DATA_OUT.

[0092] For example, in the case of performing 8-bit error detection and correction every 528 bytes using the BCH code, the syndrome calculation requires 149 clock cycles, the Euclidean reciprocal division calculation requires 82 clock cycles, the error position search requires 143 clock cycles, the error correction requires 48 clock cycles, and overall it requires 422 clock cycles. When the frequency of the clock signal CLK is 50 MHz, the period time of one clock is 20 ns, and the decoding process of the BCH code consumes 8.44 μs. If the size of one page of the page buffer / sensing circuit 170 is 2K bytes, it takes about 34 μs (1688 cycles = 422 * 4).

[0093] On the other hand, in the case of performing 1-bit error detection and correction using the Hamming code, in order to simplify the structure of the syndrome calculation and error correction, the number of clock cycles required for 2K-byte error detection and correction is about 330. If the period time of one clock is 20 ns, the processing is completed in about 6.7 μs. Compared simply with the 8-bit BCH code, the processing time is about 1 / 6. In the case of a 4K-byte page length and an array read time of 20 ns, in the 8-bit BCH code, tRD2 = (20 μs + 34 μs * 2) = 88 μs. In contrast, in the 1-bit Hamming code, tRD2 = (20 μs + (6.7 μs * 2) = 34 μs, and the difference between the two is very large. Therefore, in the case of using the BCH code, it affects the page read time (tRD2) or the upper limit of the clock frequency for continuous read operations.

[0094] In the embodiment, the 1-bit error detection and correction function (the first ECC unit 132) and the 8-bit error detection and correction function (the second ECC unit 134) are installed doubly. However, the circuit scale is dominated by the 8-bit error detection and correction circuit, and the error bit correction unit 340 can be reused. Therefore, the ECC circuit 130 can be implemented by only adding a syndrome calculation unit of the 1-bit error detection and correction circuit to the 8-bit error correction function. Therefore, it does not have much impact on the chip size.

[0095] In the embodiment, error detection and correction using Hamming code and error detection and correction using BCH code are illustrated. However, this is just an example, and the present invention can also be applied to error detection and correction using other codes.

[0096] Furthermore, in the embodiment, 8-bit error detection and correction is performed in the BCH code of the second ECC unit 134. However, this is just an example, and the BCH code of the second ECC unit 134 can also perform 2-bit, 4-bit, or 16-bit error detection and correction. Furthermore, in the embodiment, 1-bit error detection and correction is performed in the first ECC unit 132. However, this is just an example. If there is a relationship of the error detection and correction function based on the first ECC unit 132 < the error detection and correction function based on the second ECC unit 134, the first ECC unit 132 can also perform error detection and correction of 2 bits or more.

[0097] The preferred embodiments of the present invention have been described in detail. However, the present invention is not limited to specific embodiments and can be variously deformed and changed within the scope of the gist of the present invention described in the claims.

Claims

1. An error detection and correction method, which is an error detection and correction method for a semiconductor memory device, comprising: A setting step of setting selection information for selecting a first error detection and correction function for performing error detection and correction of m bits or a second error detection and correction function for performing error detection and correction of n bits, where m and n are natural numbers and m is less than n; An execution step of, during a read operation or a write operation, performing the first error detection and correction function or the second error detection and correction function based on the selection information; And A conversion step of, when switching the operation from the first error detection and correction function to the second error detection and correction function, converting first data related to the first error detection and correction function written to a memory cell array into second data related to the second error detection and correction function, wherein the conversion step is performed using a write-back function.

2. The error detection and correction method according to claim 1, wherein the selection information in the setting step can be changed from the outside by an instruction.

3. The error detection and correction method according to claim 1, wherein the selection information defines a first address space of the memory cell array for selecting the first error detection and correction function and a second address space of the memory cell array for selecting the second error detection and correction function, and the execution step performs the first error detection and correction function or the second error detection and correction function based on the first address space or the second address space corresponding to the address of the read operation or the write operation.

4. The error detection and correction method according to claim 1, wherein the conversion step reads the first data from the memory cell array into a page buffer / sensing circuit, operates the second error detection and correction function to convert the read first data into the second data, and writes the converted second data to the original position of the memory cell array.

5. The error detection and correction method according to claim 1, wherein the first error detection and correction function performs 1-bit error detection and correction using a Hamming code, and the second error detection and correction function performs 2-bit, 4-bit, or 8-bit error detection and correction using a Bose-Chaudhuri-Hocquenghem code.

6. The error detection and correction method according to claim 1, wherein the memory cell array is a NAND-type memory cell array including a regular area and a spare area, and parity bits generated by the first error detection and correction function or the second error detection and correction function are stored in the spare area.

7. A semiconductor memory device, comprising: A memory cell array; An error detection and correction circuit including a first error detection and correction function for performing error detection and correction of m bits and a second error detection and correction function for performing error detection and correction of n bits, where m and n are natural numbers and m is less than n; A setting register for setting selection information for selecting the first error detection and correction function or the second error detection and correction function; The controller, during a read operation or a write operation, performs the first error detection and correction function or the second error detection and correction function based on the selection information; and a conversion component, when switching the operation from the first error detection and correction function to the second error detection and correction function, converts first data related to the first error detection and correction function written to the memory cell array into second data related to the second error detection and correction function, wherein the conversion component is performed using a write-back function.

8. The semiconductor memory device according to claim 7, wherein, the setting register can change the selection information from the outside by an instruction.

9. The semiconductor memory device according to claim 7, wherein, the selection information specifies a first address space of the memory cell array for selecting the first error detection and correction function and a second address space of the memory cell array for selecting the second error detection and correction function, the controller performs the first error detection and correction function or the second error detection and correction function based on the first address space or the second address space corresponding to the address of the read operation or the write operation.

10. The semiconductor memory device according to claim 7, wherein, the conversion component reads the first data from the memory cell array to a page buffer / sensing circuit, operates the first error detection and correction function to decode the read first data, and then encodes the decoded data again using the second error detection and correction function to generate the second data, and writes the generated second data to the original position of the memory cell array.

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