Image sensing device

Abstract

The present application relates to an image sensing device. The disclosed technology provides an image sensing device capable of adjusting sensitivity, the image sensing device comprising: a first pixel group, which includes a first conversion gain transistor; a second pixel group, which is arranged adjacent to the first pixel group and includes a second conversion gain transistor; and a conversion gain capacitor, which is suitable for electrically connecting the first conversion gain transistor and the second conversion gain transistor, wherein the conversion gain capacitor comprises a first wire and a second wire arranged adjacent to the first wire, and the first wire comprises a region having a ring-shaped planar shape.

Description

Technical Field

[0001] Embodiments of the disclosed technology relate to image sensing devices. Background Art

[0002] An image sensing device is a device for converting an optical image into an electrical signal. With the recent development of the computer and communication industries, the demand for image sensing devices with improved performance is growing in fields such as smart phones, digital cameras, camcorders, personal communication systems (PCS), game consoles, security cameras, medical micro cameras, the robotics industry, and infrared sensing devices.

[0003] The advantages of the CMOS image sensing device are that the sensing device can be easily reduced in size because it can be driven in a simple manner and integrated in a single chip, and the sensing device can have very low power consumption due to its high integration. In addition, the CMOS image sensing device has been widely used recently because it can be manufactured using CMOS process technology and has a low manufacturing unit cost. Summary of the invention

[0004] The disclosed techniques may be implemented in some embodiments to provide an image sensing device that adjusts the sensitivity of image sensor pixels.

[0005] An image sensing device may include: a first pixel group including a first conversion gain transistor; a second pixel group disposed adjacent to the first pixel group and including a second conversion gain transistor; and a conversion gain capacitor adapted to electrically couple the first conversion gain transistor and the second conversion gain transistor. In this case, the conversion gain capacitor may include a first conductive line and a second conductive line disposed adjacent to the first conductive line, the first conductive line including an area having a ring-shaped planar shape.

[0006] An image sensing device may include: a first pixel group including a first conversion gain transistor; a second pixel group aligned with the first pixel group in a second direction and including a second conversion gain transistor; and a conversion gain capacitor disposed on one side of the first pixel group and the second pixel group in a first direction intersecting the second direction and adapted to electrically connect the first conversion gain transistor and the second conversion gain transistor. In this case, the conversion gain capacitor may include a first conductive line adapted to electrically connect the first conversion gain transistor and the second conversion gain transistor and including a first region having a ring-type planar shape and a second region having a bracket-type planar shape having an opening portion with one side open; and a second conductive line formed in the first region of the first conductive line.

[0007] An image sensing device may include: a first pixel group including a first conversion gain transistor; a second pixel group aligned with the first pixel group in a first direction and including a second conversion gain transistor; and a conversion gain capacitor disposed between the first pixel group and the second pixel group in the first direction and adapted to electrically connect the first conversion gain transistor and the second conversion gain transistor. In this case, the conversion gain capacitor may include: a first conductive line extending in a second direction intersecting the first direction, electrically connected to the first conversion gain transistor and the second conversion gain transistor, and including a first region having a ring-type planar shape and a second region having a line-type planar shape; and a second conductive line extending in the second direction and disposed on both sides of the first conductive line.

[0008] The disclosed technology can easily adjust the sensitivity of an image sensor by including a conversion gain capacitor for electrically coupling a first conversion gain transistor of a first pixel group and a second conversion gain transistor of a second pixel group. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example configuration of an image sensing device based on some embodiments of the disclosed technology is illustrated.

[0010] Figure 2 Examples of pixel groups of an image sensing device based on some embodiments of the disclosed technology are illustrated.

[0011] Figure 3 A portion of a pixel array of an image sensing device based on some embodiments of the disclosed technology is illustrated.

[0012] Figure 4 Some embodiments of the disclosed technology are illustrated. Figure 3 The first pixel group, the second pixel group and the conversion gain capacitor shown in FIG.

[0013] FIG. 5A to FIG. 5C is a timing diagram for describing an operating method of an image sensing device based on some embodiments of the disclosed technology.

[0014] Figure 6 A portion of a pixel array of an image sensing device based on some embodiments of the disclosed technology is illustrated.

[0015] Figure 7 A portion of a pixel array of an image sensing device based on some embodiments of the disclosed technology is illustrated. DETAILED DESCRIPTION

[0016] Advantages and features of the disclosed technology and methods of achieving the advantages and features will be discussed below with reference to the accompanying drawings.

[0017] The present technology is used to provide an image sensing device capable of adjusting sensitivity. More specifically, the disclosed technology is used to provide an image sensing device capable of obtaining an image with high quality in a high illumination environment and a low illumination environment by maximizing a conversion gain ratio.

[0018] For reference, the following embodiments of the disclosed technology will be described by taking the case where the technical concept of the disclosed technology is applied to a structure in which one pixel group includes eight unit pixels (i.e., an 8-shared pixel structure) as an example. The technical concept of the disclosed technology can be equally applied to a structure in which one pixel group includes four unit pixels (i.e., a 4-shared pixel structure) or a structure in which one pixel group includes two unit pixels (i.e., a 2-shared pixel structure). In addition, the technical concept of the disclosed technology can also be applied to an image sensor that does not have a shared pixel structure.

[0019] In the following description, the first direction D1 and the second direction D2 may indicate intersecting directions. For example, in an XY coordinate system, the first direction D1 may be an X-axis direction, and the second direction D2 may be a Y-axis direction.

[0020] Figure 1 An example configuration of an image sensing device based on some embodiments of the disclosed technology is illustrated.

[0021] like Figure 1 As shown, the image sensing device 100 based on some embodiments may include a pixel array 110 in which a plurality of pixels are arranged in a matrix structure, a correlated double sampler (CDS) 120, an analog-to-digital converter (ADC) 130, a buffer 140, a row driver 150, a timing generator 160, a control register 170, and a ramp signal generator 180. Figure 1 The elements of the image sensing device 100 shown are for illustration and not limitation. In other implementations, the elements of the image sensing device 100 may be combined with additional elements or some elements may be omitted.

[0022] The image sensing device 100 may include an optical lens or a lens assembly used in conjunction with the image sensing device 100 to converge light corresponding to an image of a subject under the control of the image processor 200. The image processor 200 may transmit an electrical signal corresponding to an image sensed and output by the image sensing device 100 to an electronic device including a display or the like.

[0023] The image processor 200 may include a camera controller 220, an image signal processor 210, and an interface device (e.g., a PC interface (I / F), not shown). The camera controller 220 may control the control register 170. In some implementations, the camera controller 220 may control the control register 170 of the image sensing device 100 by using a communication bus or interface such as an inter-integrated circuit (I2C). The image signal processor 210 may receive image information such as an output signal of the buffer 140 and process the image to be viewed on a display device.

[0024] The pixel array 110 may include a plurality of pixel groups 10 arranged in a matrix array. Each of the plurality of pixel groups 10 may be configured to convert optical image information into an electrical image signal and transmit the electrical image signal to the CDS 120. The pixel array 110 includes a plurality of photoelectric converter devices such as photodiodes or photodetectors to detect incident light and convert the incident light into an electrical signal.

[0025] The CDS 120 may hold and sample the electrical image signal received from the pixels of the pixel array 110. For example, the CDS 120 may sample the voltage level of the received electrical image signal and the reference voltage level in response to the clock signal provided by the timing generator 160, and may transmit an analog signal corresponding to the difference between the reference voltage level and the voltage level to the ADC 130.

[0026] The ADC 130 may convert the analog signal into a digital signal and transmit the digital signal to the buffer 140 .

[0027] The buffer 140 may hold or latch the digital signal and sequentially output the latched signal to the image signal processor. The buffer 140 may include a memory device for holding or latching the digital signal and a sense amplifier for amplifying the digital signal.

[0028] The row driver 150 may activate a plurality of pixels of the pixel array 110 to detect or convert incident light in response to a control or clock signal of the timing generator 160. For example, the row driver 150 may generate a selection signal for selecting at least one of the plurality of row lines and / or generate a driving signal for performing an operation associated with the one row line.

[0029] The timing generator 160 may generate timing signals for controlling the CDS 120 , the ADC 130 , the row driver 150 , and the ramp signal generator 180 .

[0030] The control register 170 may generate control signals for controlling the buffer 140, the timing generator 160, and the ramp signal generator 180. The buffer 140, the timing generator 160, and the ramp signal generator 180 may perform associated operations in response to the control signals. In some implementations, the control register 170 may operate under the control of a camera controller.

[0031] The ramp signal generator 180 may generate a ramp signal for processing an image signal under the control of the timing generator 160 .

[0032] Figure 2 Examples of pixel groups of an image sensing device based on some embodiments of the disclosed technology are illustrated.

[0033] like Figure 2 As shown, the pixel array 110 (refer to Figure 1 ) may include a plurality of pixel groups 10 arranged in a matrix array. Each of the plurality of pixel groups 10 may include a plurality of unit pixels configured to convert light into current. In one example, the pixel group 10 may include first to eighth unit pixels PX1 to PX8 arranged in a 2×4 matrix array, as shown in FIG. Figure 2 As shown. In this case, the first unit pixel PX1 to the fourth unit pixel PX4 can share the first sub-floating diffusion portion (or sub-floating diffusion area) FD11 and be arranged to surround the first sub-floating diffusion portion FD11. Similarly, the fifth unit pixel PX5 to the eighth unit pixel PX8 can share the second sub-floating diffusion portion FD12 and be arranged to surround the second sub-floating diffusion portion FD12. The first sub-floating diffusion portion FD11 and the second sub-floating diffusion portion FD12 can be aligned with each other in the second direction D2. The first sub-floating diffusion portion FD11 and the second sub-floating diffusion portion FD12 can be electrically connected by a wire 40. The wire 40 may include an interconnect wiring layer formed on the gate of the pixel transistor, and may be electrically connected to other layers by a contact plug.

[0034] Each of the first unit pixel PX1 to the eighth unit pixel PX8 may include a photoelectric converter device such as a photodiode (PD). The photoelectric converter device PD may generate charge carriers corresponding to incident light. The photoelectric converter device PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof. In one example, the photodiode may include a vertically stacked N-type impurity region and a P-type impurity region.

[0035] The first to eighth unit pixels PX1 to PX8 may include first to eighth transfer transistors TX1 to TX8, respectively, to transfer the charges generated by the photoelectric converter devices in the first to eighth unit pixels PX1 to PX8 to the first sub-floating diffusion FD11 and the second sub-floating diffusion FD12 through the first to eighth transfer transistors TX1 to TX8, respectively. To this end, a transfer signal may be applied to the gate of each of the first to eighth transfer transistors TX1 to TX8, and the first to eighth transfer transistors TX1 to TX8 transmit the charges generated by the photoelectric converter devices to the first sub-floating diffusion FD11 and the second sub-floating diffusion FD12 in response to the transfer signal.

[0036] The conversion gain transistor DCGX and the reset transistor RX may be disposed on one side of the pixel group 10. Specifically, the conversion gain transistor DCGX and the reset transistor RX may be disposed at the upper end of the pixel group 10 in the second direction D2. For example, the conversion gain transistor DCGX may be located adjacent to the first unit pixel PX1, and the reset transistor RX may be located adjacent to the second unit pixel PX2. As another example, the conversion gain transistor DCGX may be located adjacent to the second unit pixel PX2, and the reset transistor RX may be located adjacent to the first unit pixel PX1.

[0037] The conversion gain transistor DCGX may increase or decrease the capacitance of the first sub-floating diffusion FD11 and the second sub-floating diffusion FD12 in response to a conversion gain signal applied to the gate of the conversion gain transistor DCGX. The reset transistor RX may reset the first sub-floating diffusion FD11 and the second sub-floating diffusion FD12 in response to a reset signal applied to the gate of the reset transistor RX. The conversion gain transistor DCGX and the reset transistor RX may share the first active area 20. The first active area 20 may extend in the first direction D1. Although not shown in the figure, a well tap may be provided adjacent to one end of the first active area 20 or both ends of the first active area 20.

[0038] The first active region 20 may include a plurality of junction regions. The junction regions may be used as impurity regions, such as a source electrode and a drain electrode of each of the conversion gain transistor DCGX and the reset transistor RX. For example, the first junction region 22 may be used as an impurity region of the conversion gain transistor DCGX, and the third junction region 26 may be used as an impurity region of the reset transistor RX. The second junction region 24 may be used as an impurity region of the conversion gain transistor DCGX and the reset transistor RX. The impurity regions of the conversion gain transistor DCGX may be electrically connected (e.g., as Figure 3The impurity region of the conversion gain transistor DCGX and the impurity region of the reset transistor RX may be electrically coupled to an electrode coupled to the power supply voltage node VDD. In addition, the impurity region of the conversion gain transistor DCGX and the impurity region of the reset transistor RX may be electrically coupled to the first sub-floating diffusion FD11 and the second sub-floating diffusion FD12 through a conductive line 40.

[0039] The driving transistor DX and the selecting transistor SX may be disposed between the subarray of the first unit pixel PX1 to the fourth unit pixel PX4 and the subarray of the fifth unit pixel PX5 to the eighth unit pixel PX8. In one example, the driving transistor DX and the selecting transistor SX may be disposed in the middle portion of the pixel group 10. Here, the driving transistor DX may be used as a source follower transistor. For example, the driving transistor DX may be disposed between the third unit pixel PX3 and the fifth unit pixel PX5, and the selecting transistor SX may be disposed between the fourth unit pixel PX4 and the sixth unit pixel PX6. As another example, the driving transistor DX may be disposed between the fourth unit pixel PX4 and the sixth unit pixel PX6, and the selecting transistor SX may be disposed between the third unit pixel PX3 and the fifth unit pixel PX5.

[0040] The drive transistor DX may have a gate electrode electrically coupled to the first sub-floating diffusion FD11 and the second sub-floating diffusion FD12, and may generate an output signal Vout corresponding to the amount of charge generated by the photoelectric converter device and stored in the first sub-floating diffusion FD11 and the second sub-floating diffusion FD12. The select transistor SX may transmit the output signal Vout to a column line (e.g., Figure 1 The drive transistor DX and the select transistor SX may share the second active region 30. The second active region 30 may extend in the first direction D1. Although not shown in the figure, a well tap may be provided adjacent to either side of the second active region 30 or an end on one side / the other side of the second active region 30.

[0041] The second active region 30 may include a plurality of junction regions. The junction regions may be used as impurity regions, such as a source electrode and a drain electrode of each of the drive transistor DX and the select transistor SX. For example, the fourth junction region 32 may be used as an impurity region of the drive transistor DX, and the sixth junction region 36 may be used as an impurity region of the select transistor SX. The fifth junction region 34 may be used as an impurity region of the drive transistor DX and an impurity region of the select transistor SX. Another impurity region of the drive transistor DX may be electrically coupled to an electrode coupled to a power supply voltage node VDD. The gate of the drive transistor DX may be electrically coupled to a conductor 40. Thus, the gate of the drive transistor DX, the impurity region of the conversion gain transistor DCGX, and the source of the reset transistor RX may be electrically coupled to the first sub-floating diffusion FD11 and the second sub-floating diffusion FD12 via the conductor 40. In addition, the source of the select transistor SX may be electrically coupled to a column line (e.g., Figure 1 Column lines shown).

[0042] Figure 3 A portion of a pixel array of an image sensing device based on some embodiments of the disclosed technology is illustrated. Figure 4 Some embodiments of the disclosed technology are illustrated. Figure 3 The first pixel group, the second pixel group and the conversion gain capacitor shown in FIG.

[0043] like Figures 2 to 4 As shown, in the pixel array 110 according to some embodiments, a plurality of pixel groups 10 may be arranged in a matrix array. In each of the plurality of pixel groups 10, the first to eighth unit pixels PX1 to PX8 may be arranged in a 2×4 matrix array.

[0044] In some implementations, the pixel array 110 may include a first pixel group 10-1 and a second pixel group 10-2 that are aligned in the second direction D2 and disposed adjacent to each other. The plurality of unit pixels PX1 to PX8 included in the first pixel group 10-1 may share a first floating diffusion FD1, and may include a first conversion gain transistor DCGX1 electrically coupled to the first floating diffusion FD1. Similarly, the plurality of unit pixels PX1 to PX8 included in the second pixel group 10-2 may share a second floating diffusion FD2, and may include a second conversion gain transistor DCGX2 electrically coupled to the second floating diffusion FD2. The first floating diffusion FD1 and the second floating diffusion FD2 may respectively include a first sub-floating diffusion FD11 and a second sub-floating diffusion FD12 electrically coupled via a conductive line 40 (see also Figure 2 ).

[0045] The first pixel group 10-1 may include a first reset transistor RX1, a first conversion gain transistor DCGX1, a first drive transistor DX1, and a first selection transistor SX1. The first reset transistor RX1 may electrically couple its electrode coupled to the power supply voltage node VDD to the first floating diffusion (or floating diffusion region) FD1 in response to a first reset signal. The first conversion gain transistor DCGX1 may electrically couple the conversion gain capacitor 300 to the first floating diffusion FD1 in response to the first conversion gain signal. The first drive transistor DX1 may have a gate electrode electrically coupled to the first floating diffusion FD1, and may generate an output signal corresponding to the corresponding unit pixels PX1 to PX8 sharing the first floating diffusion FD1. In addition, the first selection transistor SX1 may electrically couple the first floating diffusion capacitor 300 to the first floating diffusion FD1 in response to the first selection signal. Figure 1 The column line shown in FIG. 4 transmits the output signal generated by the first driving transistor DX1.

[0046] The second pixel group 10-2 may include a second reset transistor RX2, a second conversion gain transistor DCGX2, a second drive transistor DX2, and a second selection transistor SX2. The second reset transistor RX2 may electrically couple its electrode coupled to the power supply voltage node VDD to the second floating diffusion FD2 in response to a second reset signal. The second conversion gain transistor DCGX2 may electrically couple the conversion gain capacitor 300 to the second floating diffusion FD2 in response to a second conversion gain signal. The second drive transistor DX2 may have a gate electrode electrically coupled to the second floating diffusion FD2, and may generate an output signal corresponding to the corresponding unit pixels PX1 to PX8 sharing the second floating diffusion FD2. In addition, the second selection transistor SX2 may electrically couple the second floating diffusion capacitor 300 to the second floating diffusion FD2 in response to a second selection signal. Figure 1 For reference, the first selection transistor SX1 of the first pixel group 10-1 and the second selection transistor SX2 of the second pixel group 10-2 may be electrically coupled to the same column line (eg, Figure 1 Column lines shown).

[0047] The first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 may be electrically coupled to each other through a conversion gain capacitor 300 having a predetermined capacitance. The conversion gain capacitor 300 may include a plurality of wires, such as a first wire 52, a second wire 54, and a third wire 56. The first wire 52, the second wire 54, and the third wire 56 may be formed in an interconnect wiring layer disposed on the gates of the first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2, and may be electrically coupled through a contact plug. For example, the first wire 52, the second wire 54, and the third wire 56 may be formed in the same layer as the wire 40.

[0048] In some implementations, the first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 may be electrically coupled via a first conductive line 52. In one example, the impurity region of the first conversion gain transistor DCGX1 and the impurity region of the second conversion gain transistor DCGX2 may be electrically coupled to each other via the first conductive line 52. The first conductive line 52 may include a first region 52A having a ring shape or a rectangular shape and a second region 52B having a bracket shape including an open end 58. In this case, the second region 52B may have a "U" shape. The first conductive line 52 may also include a third region 52C coupling the first region 52A to the second region 52B. The third region 52C may be configured to extend between the first region 52A and the second region 52B.

[0049] In some implementations, the conversion gain capacitor 300 includes a second region 52B, a first region 52A arranged between the second regions 52B in a second direction D2, and a third region 52C configured to connect the second region 52B to the first region 52A. In one example, the second region 52B of the first conductive line 52 may be connected to both ends of the first region 52A in the second direction D2. As another example, the second region 52B of the first conductive line 52 may be connected to only one end of the first region 52A. The open end 58 of the second region 52B may be disposed to face another pixel group (not shown) adjacent to the first pixel group 10-1 and the second pixel group 10-2, and thus not face the first region 52A.

[0050] In the conversion gain capacitor 300, the second conductive line 54 may be disposed within the first region 52A of the first conductive line 52. That is, the first region 52A of the first conductive line 52 may have a shape surrounding the second conductive line 54. In some implementations, the second conductive line 54 may be configured to be coupled to a ground voltage node. In some implementations, the conversion gain capacitor 300 may have a fixed capacitance value.

[0051] As another example, when the first conversion gain transistor DCGX1 or / and the second conversion gain transistor DCGX2 are activated, the second wire 54 may be provided with a first boost voltage. In this case, the conversion gain capacitor 300 may have a variable capacitance value and may be able to more effectively adjust the sensitivity of the image sensing device in a high illumination environment.

[0052] In the conversion gain capacitor 300, the third wire 56 may be disposed in the second region 52B of the first wire 52. In this case, the third wire 56 may have a shape extending to the outside of the second region 52B through the open end 58 of the second region 52B. Therefore, two conversion gain capacitors 300 adjacent to each other may share the third wire 56. Like the second wire 54, the third wire 56 may be connected to a ground voltage node. In this case, the conversion gain capacitor 300 may have a fixed capacitance value.

[0053] As another example, when the first conversion gain transistor DCGX1 or / and the second conversion gain transistor DCGX2 are activated, the third conductor 56 may be provided with a second boost voltage. In this case, the conversion gain capacitor 300 may have a variable capacitance value and may be able to more effectively adjust the sensitivity of the image sensing device in a high illumination environment. In this case, the first boost voltage applied to the second conductor 54 and the second boost voltage applied to the third conductor 56 may be boost voltages having the same polarity and amplitude. In addition, the first boost voltage applied to the second conductor 54 and the second boost voltage applied to the third conductor 56 may be boost voltages having the same polarity but different amplitudes. Depending on whether the first boost voltage and the second boost voltage are applied and the amplitude of each of the first boost voltage and the second boost voltage, the sensitivity of the image sensing device may be even more effectively adjusted.

[0054] As described above, in the pixel array 110 of some embodiments based on the disclosed technology, the first floating diffusion FD1 and the second floating diffusion FD2 are electrically connected to the first reset transistor RX1 and the second reset transistor RX2, respectively, and are independently operated by receiving a reset signal. The first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 are connected in parallel to the first reset transistor RX1 and the second reset transistor RX2, respectively. Therefore, the reset operation of resetting each of the first floating diffusion FD1 and the second floating diffusion FD2 can be smoothly performed, such as Figure 4 as well as FIG. 5A to FIG. 5C As shown. In this case, the source of the first reset transistor RX1 and the source of the first conversion gain transistor DCGX1 are coupled to the first floating diffusion FD1. The impurity region of the first reset transistor RX1 and the impurity region of the first conversion gain transistor DCGX1 are coupled to an electrode coupled to the power supply voltage node VDD. Therefore, the first reset transistor RX1 and the first conversion gain transistor DCGX1 may be coupled in parallel. In this case, the impurity region of the first conversion gain transistor DCGX1 may be coupled to an electrode coupled to the power supply voltage node VDD through the second conversion gain transistor DCGX2 and the second reset transistor RX2.

[0055] In addition, the pixel array 110 of some embodiments of the technology disclosed herein may include a conversion gain capacitor 300 that electrically couples the first conversion gain transistor DCGX1 to the second conversion gain transistor DCGX2, thereby easily adjusting the sensitivity of the image sensor. Specifically, the pixel array 110 can obtain a high-quality image in a high-illuminance environment by providing a capacitance greater than the capacitance of a single floating diffusion FD (e.g., more than four times the capacitance of a single floating diffusion FD).

[0056] For reference, it is difficult to have multiple conversion gain transistors DCGX for each pixel group 10 due to its limited area. Therefore, there is a limit to increasing the capacitance of the floating diffusion FD by electrically coupling one conversion gain transistor DCGX to the floating diffusion FD compared to when the conversion gain transistor DCGX is deactivated.

[0057] However, the image sensing device implemented based on some embodiments of the technology disclosed herein can obtain a high-quality image by deactivating the first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 to use only the capacitance of the floating diffusion portion FD of each pixel group 10 when a high conversion gain is required to obtain an image of the object in a low illumination environment. Conversely, when a low conversion gain is required to obtain an image of the object in a high illumination environment, a high-quality image can be obtained by activating the first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 to use the capacitance of the conversion gain capacitor 300 together with the capacitance of each of the first floating diffusion portion FD1 and the second floating diffusion portion FD2 (which increases the capacitance of the floating diffusion portion FD).

[0058] although Figure 3 It is illustrated that the first pixel group 10 - 1 and the second pixel group 10 - 2 are aligned in the second direction D2 , but in other implementations, the first pixel group 10 - 1 and the second pixel group 10 - 2 may be aligned in the first direction D1 .

[0059] FIG. 5A to FIG. 5C 1 is a timing diagram for describing an operation method of an image sensing device based on some embodiments of the disclosed technology. In the following, for ease of description, a 4SUM operation mode in which four unit pixels operate simultaneously will be described as an example. In addition, the operation of the first pixel group 10-1 will be discussed below as an example.

[0060] like Figure 4 and Figure 5AAs shown, in the case of a normal mode of the image sensing device or a low illumination environment, a high conversion gain may be required to obtain an image of the object because the sensitivity increases as the sum of the capacitances of the first floating diffusion FD1 decreases. To this end, in the third period T3 in which the charges generated from the plurality of unit pixels are transmitted to the first floating diffusion FD1, the first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 may be deactivated.

[0061] For reference, the first period T1 is a period in which a reset operation for resetting the first floating diffusion FD1 is performed. In the first period T1, both the first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 may be activated. The second period T2 may be a period corresponding to an integration time when each of the plurality of unit pixels generates charges in response to incident light.

[0062] like Figure 4 and Figure 5B As shown, in the case of a high dynamic range (HDR) mode of the image sensing device or a high illumination environment, a low conversion gain may be required to obtain an image of the object because the sensitivity decreases as the sum of the capacitances of the first floating diffusion FD1 increases. To this end, in the third period T3 in which the charges generated by the plurality of unit pixels are transmitted to the first floating diffusion FD1, both the first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 may be activated.

[0063] like Figure 4 and Figure 5C As shown, if a lower conversion gain is required compared to a low illumination environment and a higher conversion gain is required compared to a high illumination environment, the first conversion gain transistor DCGX1 may be activated and the second conversion gain transistor DCGX2 may be deactivated in the third period T3.

[0064] As described above, the image sensing device implemented based on some embodiments of the technology disclosed herein can easily adjust the sensitivity of the image sensor by including a conversion gain capacitor 300 that electrically connects the first conversion gain transistor DCGX1 of the first pixel group 10-1 to the second conversion gain transistor DCGX2 of the second pixel group 10-2.

[0065] Figure 6 A portion of a pixel array of an image sensing device based on some embodiments of the disclosed technology is illustrated. Figure 6 In, with Figure 3 and Figure 4 Elements labeled with the same reference numerals (such as the first pixel group, the second pixel group, and the conversion gain capacitor) may have the same Figure 3 and Figure 4 The structure is the same as the structure shown.

[0066] like Figure 6 As shown, in a pixel array 110 based on some embodiments, a plurality of pixel groups 10 may be arranged in a matrix structure. In each of the plurality of pixel groups 10, the first unit pixel PX1 to the eighth unit pixel PX8 may be arranged in a 2×4 matrix array. Specifically, the pixel array 110 may include a first pixel group 10-1 and a second pixel group 10-2 disposed adjacent to each other. In this case, the first pixel group 10-1 and the second pixel group 10-2 may have symmetry in the first direction D1.

[0067] The first pixel group 10-1 may include a plurality of unit pixels PX1 to PX8 that share a first floating diffusion FD1, a first reset transistor RX1 that electrically couples an electrode thereof to a power supply voltage node VDD to the first floating diffusion FD1 in response to a first reset signal, a first conversion gain transistor DCGX1 that electrically couples a conversion gain capacitor 300 to the first floating diffusion FD1 in response to a first conversion gain signal, a first drive transistor DX1 that generates output signals corresponding to respective unit pixels PX1 to PX8 that share the first floating diffusion FD1, and a first selection transistor SX1 that transmits an output signal generated by the first drive transistor DX1 to a column line in response to a first selection signal.

[0068] The second pixel group 10-2 may include a plurality of unit pixels PX1 to PX8 sharing a second floating diffusion FD2, a second reset transistor RX2 electrically coupling an electrode thereof coupled to a power supply voltage node VDD to the second floating diffusion FD2 in response to a second reset signal, a second conversion gain transistor DCGX2 electrically coupling a conversion gain capacitor 300 and the second floating diffusion FD2 in response to a second conversion gain signal, a second drive transistor DX2 generating output signals corresponding to the respective unit pixels PX1 to PX8 sharing the second floating diffusion FD2, and a second selection transistor SX2 transmitting an output signal generated by the second drive transistor DX2 to a column line in response to a second selection signal. For reference, the first selection transistor SX1 of the first pixel group 10-1 and the second selection transistor SX2 of the second pixel group 10-2 may be electrically coupled to different column lines.

[0069] The first reset transistor RX1 and the first conversion gain transistor DCGX1 of the first pixel group 10-1 can share the first active area 20 together with the second reset transistor RX2 and the second conversion gain transistor DCGX2 of the second pixel group 10-2. In this case, the first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 can be arranged adjacent to each other. In addition, the first drive transistor DX1 and the first selection transistor SX1 of the first pixel group 10-1 can share a second active area 30 together with the second drive transistor DX2 and the second selection transistor SX2 of the second pixel group 10-2. In this case, the first drive transistor DX1 and the second drive transistor DX2 can be arranged adjacent to each other. As described above, since the pixel transistors share the active area, the channel area of ​​the pixel transistor can be easily increased within a limited area, and the difficulty of wire design can be reduced. Therefore, the performance of the pixel transistor can be improved, and the signal transmission characteristics can be improved by reducing the total resistance of the wire.

[0070] The first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 may be electrically coupled via a conversion gain capacitor 300 having a predetermined capacitance. The conversion gain capacitor 300 may include a plurality of wires, such as a first wire 62, a second wire 64, and a third wire 66. The first wire 62, the second wire 64, and the third wire 66 may be formed in an interconnect wiring layer disposed on the gates of the first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2, and may be electrically coupled via a contact plug. For example, the first wire 62, the second wire 64, and the third wire 66 may be connected to the wire 40 (see Figure 2 ) are formed in the same layer.

[0071] In some implementations, the first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 may be electrically coupled to the first conductive line 62. In one example, an impurity region of the first conversion gain transistor DCGX1 and an impurity region of the second conversion gain transistor DCGX2 may be electrically coupled to the first conductive line 62. The first conductive line 62 may be disposed between the first pixel group 10-1 and the second pixel group 10-2 in the first direction D1, and may extend in the second direction D2. In this case, in the second direction D2, the first conductive line 62 may have a length corresponding to the length of the first pixel group 10-1 and the length of the second pixel group 10-2. The first conductive line 62 may include a first region 62A having a ring shape and a second region 62B having a linear shape extending from the first region 62A in the second direction D2.

[0072] The first region 62A of the first conductive line 62 having a ring shape may be disposed in a middle portion between the second regions 62B of the first conductive line 62 aligned in the second direction D2, and may overlap with a middle portion of the second active region 30 shared by the first drive transistor DX1 and the second drive transistor DX2. In some implementations, a contact plug may penetrate the first region 62A of the first conductive line 62 having a ring shape to electrically connect the power supply voltage node VDD and the impurity region of the first drive transistor DX1 and the impurity region of the second drive transistor DX2. The second regions 62B of the first conductive line 62, each having a linear shape, may be connected to the first region 62A in the second direction D2, respectively. The second regions 62B connected to the first region 62A in the second direction D2 may be aligned with each other. The end portion on one side of the second region 62B of the first conductive line 62 may be electrically connected to the first active region 20 through a contact plug, and serve as the impurity region of the first conversion gain transistor DCGX1 and the impurity region of the second conversion gain transistor DCGX2.

[0073] In the conversion gain capacitor 300, the second wire 64 may be disposed on both sides of the first wire 62. In some implementations, the second wire 64 may include a discontinuous wire extending along the contour of the first wire 62 in the second direction D2 but disconnected in the first region 62A of the first wire 62. The second wire 64 may be coupled to a ground voltage node. In this case, the conversion gain capacitor 300 may have a fixed capacitance value.

[0074] In the conversion gain capacitor 300, the third wire 66 may be arranged on each of the other side of the first pixel group 10-1 and the side of the second pixel group 10-2 in the first direction D1. That is, the third wire 66 may be arranged on both sides of the first wire 62. The first pixel group 10-1, the first wire 62, the second wire 64, and the second pixel group 10-2 may be arranged between the third wire 66. Like the second wire 64, the third wire 66 may be connected to a ground voltage node. The third wire 66 may be used to enable the conversion gain capacitor 300 to have a stable and uniform capacitance value. To this end, the third wire 66 may include a third region 66A extending in the second direction and a fourth region 66B electrically connected to the third region 66A, disposed adjacent to the unit pixel and each having an "H" plane shape. The fourth region 66B may have a shape symmetrical about the third region 66A.

[0075] As described above, in the pixel array 110 based on some embodiments of the disclosed technology, the first floating diffusion FD1 and the second floating diffusion FD2 are electrically connected to the first reset transistor RX1 and the second reset transistor RX2, respectively, and operate independently by receiving the reset signal, respectively. The first conversion gain transistor DCGX1 and the second conversion gain transistor DCGX2 are connected in parallel to the first reset transistor RX1 and the second reset transistor RX2, respectively. Therefore, the reset operation of resetting each of the first floating diffusion FD1 and the second floating diffusion FD2 can be smoothly performed (such as Figure 4 and FIG. 5A to FIG. 5C shown).

[0076] In addition, the pixel array 110 of some embodiments based on the disclosed technology includes a conversion gain capacitor 300 that electrically connects the first conversion gain transistor DCGX1 to the second conversion gain transistor DCGX2, so as to obtain high-quality images in a high-illuminance environment by providing a capacitance that is larger than the capacitance of a single floating diffusion portion FD (for example, more than four times the capacitance of a single floating diffusion portion FD), and can easily adjust the sensitivity of the image sensor.

[0077] Figure 7 A portion of a pixel array of an image sensing device based on some embodiments of the disclosed technology is illustrated. Figure 7 In, with Figure 3 and Figure 6 Elements denoted by the same reference numerals may have Figure 3 and Figure 6 The structure is the same as the structure shown.

[0078] In some embodiments of the disclosed technology, an image sensing device is described in which a conversion gain capacitor can provide a capacitance greater than that of a single floating diffusion FD by electrically coupling two conversion gain transistors.

[0079] like Figure 7 As shown, in the pixel array 110 based on some embodiments, Figure 6 The illustrated conversion gain capacitor 300 may extend in the second direction D2 to electrically couple the first to fourth conversion gain transistors DCGX1 to DCGX4 and may thus provide a capacitance greater than that of a single floating diffusion FD (eg, more than eight times that of a single floating diffusion FD).

[0080] Only limited examples of implementations or embodiments of the disclosed technology are described or illustrated. Based on the content disclosed and illustrated in this patent document, variations or enhancements of the disclosed implementations or embodiments and other implementations or embodiments are also possible.

[0081] CROSS-REFERENCE TO RELATED APPLICATIONS

[0082] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2021-0041571, filed on March 31, 2021, which is hereby incorporated by reference in its entirety.

Claims

1. An image sensing device, comprising: a first pixel group including a plurality of first image sensing pixels configured to convert light into electric charge and a first conversion gain transistor coupled to the plurality of first image sensing pixels; a second pixel group, the second pixel group including a plurality of second image sensing pixels configured to convert light into electric charge and a second conversion gain transistor coupled to the plurality of second image sensing pixels, the second pixel group being disposed adjacent to the first pixel group; as well as a conversion gain capacitor configured to electrically couple the first conversion gain transistor to the second conversion gain transistor to provide capacitance for the first image sensing pixel and the second image sensing pixel, The conversion gain capacitor includes a first conductive line configured to include a region having a ring shape and a second conductive line disposed adjacent to the first conductive line.

2. The image sensing device according to claim 1, wherein: The first pixel group further includes a first floating diffusion region shared by the plurality of first image sensing pixels and a first reset transistor configured to selectively couple a power supply voltage node to the first floating diffusion region; and The second pixel group also includes a second floating diffusion region shared by the plurality of second image sensing pixels and a second reset transistor configured to selectively couple the power supply voltage node to the second floating diffusion region.

3. The image sensing device according to claim 2, wherein: The first conversion gain transistor is configured to selectively couple the conversion gain capacitor to the first floating diffusion region; and The second conversion gain transistor is configured to selectively couple the conversion gain capacitor to the second floating diffusion region.

4. The image sensing device according to claim 2, wherein: In the first pixel group, the first conversion gain transistor is connected in parallel to the first reset transistor; and In the second pixel group, the second conversion gain transistor is coupled in parallel to the second reset transistor.

5. The image sensing device according to claim 1, wherein: The first conductive line is configured to electrically couple the first conversion gain transistor to the second conversion gain transistor, and The second conductive line is disposed in the region having a ring shape and is surrounded by the first conductive line.

6. The image sensing device according to claim 1, wherein: The first conductive line is electrically coupled to the first conversion gain transistor and the second conversion gain transistor; and The second conductive line is provided on both sides of the first conductive line and extends along an outline of the first conductive line, and includes a discontinuous conductive line that is disconnected in a region having a ring-type planar shape.

7. The image sensing device according to claim 1, wherein: The second conductive line is coupled to a ground voltage node.

8. An image sensing device, comprising: a first pixel group including a plurality of first image sensing pixels configured to convert light into electric charge and a first conversion gain transistor coupled to the plurality of first image sensing pixels; a second pixel group, the second pixel group including a plurality of second image sensing pixels configured to convert light into electric charge and a second conversion gain transistor, the second conversion gain transistor being disposed adjacent to and coupled to the plurality of second image sensing pixels, the second pixel group being aligned with the first pixel group in a second direction; as well as a conversion gain capacitor disposed on one side of the first pixel group and the second pixel group in a first direction intersecting the second direction and configured to electrically couple the first conversion gain transistor to the second conversion gain transistor to provide capacitance for the first image sensing pixel and the second image sensing pixel; Wherein, the conversion gain capacitor comprises: a first conductive line configured to electrically couple the first conversion gain transistor to the second conversion gain transistor and including a first region having a closed rectangular shape and a second region having a rectangular shape including an opening portion at one end thereof; and A second conductive line is formed in the first region of the first conductive line. 9 . The image sensing device according to claim 8 , further comprising a third conductive line formed in the second region of the first conductive line.

10. The image sensing device according to claim 9, wherein: The third conductive line is configured to include a shape extending to the outside of the second area through the opening portion of the second area in the second direction; and Two conversion gain capacitors adjacent to each other are configured to share the third conducting wire.

11. The image sensing device according to claim 9, wherein: Each of the second conductive line and the third conductive line is coupled to a ground voltage node.

12. The image sensing device according to claim 8, wherein: The second regions of the first conductive line are disposed on both sides of the first region in the second direction, and the opening portion of the second region of the first conductive line is disposed not to face the first region.

13. The image sensing device according to claim 8, wherein: The first pixel group and the second pixel group further include a first selection transistor and a second selection transistor, respectively; and The first selection transistor and the second selection transistor are electrically coupled in common to a column line.

14. The image sensing device according to claim 8, wherein: The first pixel group further includes a first floating diffusion region shared by the plurality of first image sensing pixels and a first reset transistor configured to selectively couple a power supply voltage node to the first floating diffusion region, and The second pixel group also includes a second floating diffusion region shared by the plurality of second image sensing pixels and a second reset transistor configured to selectively couple the power supply voltage node to the second floating diffusion region.

15. The image sensing device according to claim 14, wherein: The first conversion gain transistor is configured to selectively couple the conversion gain capacitor and the first floating diffusion region, and The second conversion gain transistor is configured to selectively couple the conversion gain capacitor to the second floating diffusion region.

16. An image sensing device, the image sensing device comprising: a first pixel group including a plurality of first image sensing pixels configured to convert light into electric charge and a first conversion gain transistor coupled to the plurality of first image sensing pixels; a second pixel group, the second pixel group including a plurality of second image sensing pixels configured to convert light into electric charge and a second conversion gain transistor, the second conversion gain transistor being disposed adjacent to and coupled to the plurality of second image sensing pixels, the second pixel group being aligned with the first pixel group in a first direction; as well as a conversion gain capacitor disposed between the first pixel group and the second pixel group in the first direction and configured to electrically couple the first conversion gain transistor to the second conversion gain transistor to provide capacitance for the first image sensing pixel and the second image sensing pixel, Wherein, the conversion gain capacitor comprises: a first conductive line configured to extend in a second direction intersecting the first direction and electrically coupled to the first conversion gain transistor and the second conversion gain transistor, the first conductive line including a first region having a ring-type planar shape and a second region having a line-type planar shape; and A second conductive line is extended in the second direction and is disposed on both sides of the first conductive line.

17. The image sensing device according to claim 16, further comprising: a third pixel group and a fourth pixel group, the third pixel group and the fourth pixel group are respectively aligned with the first pixel group and the second pixel group in the second direction and respectively include a third conversion gain transistor and a fourth conversion gain transistor, The conversion gain capacitor is extended in the second direction and electrically connects the first conversion gain transistor to the fourth conversion gain transistor. 18 . The image sensing device according to claim 16 , further comprising a third conductive line disposed on the other side of the first pixel group and on one side of the second pixel group in the first direction and extending in the second direction.

19. The image sensing device according to claim 18, wherein: The third conductive line includes a third region and a fourth region, the third region having a linear shape extending in the second direction, the fourth regions being electrically coupled to the third region and each having an H shape, and The fourth region has a symmetrical shape with respect to the third region.

20. The image sensing device according to claim 19, wherein: Each of the second conductive line and the third conductive line is coupled to a ground voltage node.

21. The image sensing device according to claim 16, wherein: The first pixel group and the second pixel group have symmetrical shapes in the first direction.

22. The image sensing device according to claim 16, wherein: The first region of the first conductive line is disposed at a middle portion of the first pixel group and the second pixel group in the second direction, and the second regions of the first conductive line are disposed above and below the first region, respectively, and are aligned with each other; and A contact plug penetrates the first region of the first conductive line.

23. The image sensing device according to claim 16, wherein: The second conductive line includes a discontinuous conductive line extending along a contour of the first conductive line and being disconnected in the first region of the first conductive line.

24. The image sensing device according to claim 16, wherein: The first pixel group and the second pixel group further include a first selection transistor and a second selection transistor, respectively; and The first selection transistor and the second selection transistor are electrically coupled to different column lines.

25. The image sensing device according to claim 16, wherein: The first pixel group further includes a first floating diffusion region shared by the plurality of first image sensing pixels and a first reset transistor configured to selectively couple a power supply voltage node to the first floating diffusion region, and The second pixel group also includes a second floating diffusion region shared by the plurality of second image sensing pixels and a second reset transistor configured to selectively couple the power supply voltage node to the second floating diffusion region.

26. The image sensing device according to claim 25, wherein: The first conversion gain transistor is configured to selectively couple the conversion gain capacitor to the first floating diffusion region; and The second conversion gain transistor is configured to selectively couple the conversion gain capacitor to the second floating diffusion region.

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