Layout correction method for improving the process window of metal layers

Abstract

The present invention provides a layout correction method for improving the process window of a metal layer. A first corrected pattern after optical proximity correction of a pattern to be corrected is provided, and a first exposure profile thereof is obtained according to the first corrected pattern. An area where the line width in the first exposure profile does not meet the design standard is defined as a hot spot pattern; the first pattern is moved a partial distance to the side away from the third pattern to obtain a fourth pattern; the original pattern corresponding to the hot spot pattern is subjected to optical proximity correction according to the second to fourth patterns to obtain a second corrected pattern, and a second exposure profile thereof is obtained according to the second corrected pattern, so that the line width in the second corrected pattern meets the design standard, and the exposed profile after correction of the second pattern wraps the exposed profile after correction of the fourth pattern. The present invention increases the correction movement space of the hot spot line width of the metal layer and improves its process window, and does not cause the problem of insufficient wrapping area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a layout correction method for improving the process window of a metal layer. Background Art

[0002] In the back-end process of semiconductor devices, please refer to Figure 1 , a via connection layer needs to be formed between two adjacent upper and lower metal lines to achieve metal interconnection. As the device size continues to shrink, the accuracy requirements for the line widths of the via layer and the metal layer become more and more stringent, thus limiting the space for optical proximity correction and causing the hot issue of insufficient process window for the metal layer line width; at the same time, since the via layer will move or merge with reference to the upper and lower metal layers in the optical proximity correction program of this layer to ensure that the metal layer has sufficient area to wrap the via layer, but due to the insufficient process window of the upper metal layer line width, the problem of insufficient area for the metal layer to wrap the via layer will also occur.

[0003] For example, in the prior art, a design layout of a metal layer (as shown in Figure 1 ), the area where the process hot spot of the line width is located is locked through OPC (Optical Proximity Correction) simulation inspection, and a regional mark is generated centered on this area. The problems found are as shown in Figure 2 , 3 and Figure 7 : When this pattern is corrected by OPC and moved, only the wrapping of the original pattern of the via layer is considered, so that the moving space of the OPC target pattern (the edges at points 1-5) is limited. Finally, the values of the target patterns at points 1-5 are small, and the line width under non-standard conditions after OPC correction at point 1 does not meet the requirements (it should be greater than the value corresponding to 90% of the line width under standard conditions). The actual wafer verification diagram after publication is as shown in Figure 3 , and it can be seen that the morphology of the actual pattern measurement point 1 is poor, the pattern line width is not uniform enough, and the process window is insufficient.

[0004] To solve the above problems, a new layout correction method for improving the process window of the metal layer is needed. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a layout correction method for improving the process window of a metal layer, which is used to solve the hot issue in the prior art that the accuracy requirements for the line widths of the via layer and the metal layer are becoming more and more stringent, thus limiting the space for optical proximity correction and causing insufficient process window for the metal layer line width; at the same time, since the via layer will move or merge with reference to the upper and lower metal layers in the optical proximity correction program of this layer to ensure that the metal layer has sufficient area to wrap the via layer, but due to the insufficient process window of the upper metal layer line width, the problem of insufficient area for the metal layer to wrap the via layer will also occur.

[0006] To achieve the above and other related purposes, the present invention provides a layout correction method for improving the process window of a metal layer, including:

[0007] Step 1: Provide a first corrected pattern after optical proximity correction of the pattern to be corrected. Obtain the first exposure profile according to the first corrected pattern, and define the area where the line width in the first exposure profile does not meet the design standard as the hot spot pattern.

[0008] Among them, the pattern to be corrected corresponding to the hot spot pattern includes the first to third patterns. The second pattern and the third pattern are arranged at intervals, and the first pattern is arranged below or above the second pattern and within the range of the second pattern.

[0009] Step 2: Move the first pattern a certain distance away from the third pattern to obtain a fourth pattern.

[0010] Step 3: Perform optical proximity correction on the original pattern corresponding to the hot spot pattern according to the second to fourth patterns to obtain a second corrected pattern. Obtain the second exposure profile according to the second corrected pattern, so that the line width of the second corrected pattern meets the design standard, and the exposed profile after correction of the second pattern wraps the exposed profile after correction of the fourth pattern.

[0011] Preferably, in step 1, the line widths of the first exposure profiles obtained by exposing the first corrected pattern under non-standard conditions and standard conditions respectively are defined. The line width under non-standard conditions is less than 90% of the line width under standard conditions, and the graphic area where the difference in the line widths of the first exposure profiles obtained by exposure under non-standard conditions is greater than the preset value is the hot spot pattern that does not meet the design standard.

[0012] Preferably, in step 1, the first pattern is a via layer pattern.

[0013] Preferably, in step 1, the second pattern is a metal layer pattern.

[0014] Preferably, in step 1, the third pattern is a metal layer pattern.

[0015] Preferably, the method further includes step 4: Judge whether the line width in the second corrected pattern meets the design standard, and judge whether the exposed profile after correction of the second pattern wraps the exposed profile after correction of the fourth pattern to reach the target ratio. If both are satisfied, use the second corrected pattern to correct the photomask.

[0016] Preferably, the target ratio in step 4 is 90%.

[0017] Preferably, the fourth figure in step two is disposed within the range of the second figure.

[0018] Preferably, the method is used for SRAM layout or logic device layout.

[0019] As described above, the layout correction method for improving the process window of the metal layer according to the present invention has the following beneficial effects:

[0020] Based on the original correction program, the present invention takes the figure after the movement of the via layer corresponding to the hot spot line width problem as a reference to increase the correction movement space of the hot spot line width of the metal layer and improve its process window. Since the metal layer will ensure the wrapping of the via layer during correction, the problem of insufficient wrapping area will not occur. Description of the Drawings

[0021] Figure 1 Schematic diagram of the figure to be corrected showing the prior art;

[0022] Figure 2 Schematic diagram of the metal layer and via layer in the prior art only considering the wrapping of the original figure of the via layer after OPC movement (the non-slanted figure is the figure to be corrected, and the slanted figure is the figure to be corrected after movement);

[0023] Figure 3 Schematic diagram of the figure profile after wafer lithography showing the prior art;

[0024] Figure 4 Schematic diagram of the layout of the area where the hot spot problem of the present invention is located;

[0025] Figure 5 Schematic diagram of the figure of the moving via layer of the present invention;

[0026] Figure 6 Schematic diagram of the optical proximity correction movement at the hot spot figure after moving the figure of the via layer of the present invention;

[0027] Figure 7 Schematic diagram of the measurement of the line width of the first exposure profile showing the prior art;

[0028] Figure 8 Schematic diagram of the metal layer and via layer after moving the via layer in an embodiment of the present invention after OPC movement (the non-slanted figure is the figure to be corrected, and the slanted figure is the figure to be corrected after movement);

[0029] Figure 9 Schematic diagram of the figure profile after wafer lithography in an embodiment of the present invention;

[0030] Figure 10 Schematic diagram of the measurement of the line width of the second exposure profile in an embodiment of the present invention;

[0031] Figure 11 Shown is a schematic diagram of the optical proximity correction method of the present invention. Detailed implementation manners

[0032] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Please refer to Figure 9 , the present invention provides a layout correction method for improving the process window of a metal layer, including:

[0034] Step 1, please refer to Figure 4 , provide a retarget to be corrected, form a plurality of sequentially connected fragments according to the graphic outline of the original layout, a first corrected graphic (target) after optical proximity correction, obtain its first exposure profile according to the first corrected graphic, and define the area where the line width in the first exposure profile does not meet the design standard as a hot spot graphic;

[0035] Among them, the retarget corresponding to the hot spot graphic includes the first to third graphics. The second graphic 02 and the third graphic 03 are arranged at intervals. The first graphic 01 is arranged below or above the second graphic 02, and the first graphic 01 is arranged within the range of the second graphic 02. Since in optical proximity correction, in the prior art, when performing optical proximity correction on the first to third graphics, without moving the first graphic 01, the second graphic 02 and the third graphic 03 do not have enough space to move, resulting in a smaller line width of the first exposure profile of the first corrected graphic.

[0036] Regarding the wrapping of the first graphic, only the target layer after the movement of the first graphic 01 is considered here. When performing optical proximity correction on the first to third graphics, because the distance between the first graphic 01 and the third graphic 03 is small, the wrapping of the second graphic 02 around the first graphic 01 also needs to be considered. Therefore, there will be a defect that the line width of the corrected graphic does not meet the expected requirements;

[0037] It should be noted that the first to third graphics are only the necessary parts of the retarget corresponding to the hot spot graphic, and there may be other graphics in the actual process.

[0038] In an embodiment of the present invention, in step one, the line widths of the first corrected pattern after exposure under non-standard conditions and standard conditions are defined. The line width under non-standard conditions is less than 90% of the line width under standard conditions, and the pattern area where the difference in line widths of the first exposure profile obtained after exposure under non-standard conditions is greater than a preset value is a hot spot pattern that does not meet the design standard. Among them, the standard condition is the optimal condition for lithography, and the non-standard condition is other lithography conditions with changed machine parameters.

[0039] In an embodiment of the present invention, in step one, the first pattern 01 is a via layer pattern.

[0040] In an embodiment of the present invention, in step one, the second pattern 02 is a metal layer pattern, and the second pattern 02 and the third pattern 03 may be metal layer patterns on the same layer.

[0041] In an embodiment of the present invention, in step one, the third pattern 03 is a metal layer pattern, and the second pattern 02 and the third pattern 03 may be metal layer patterns on the same layer.

[0042] Step two, please refer to Figure 5 , move the first pattern 01 a certain distance away from the third pattern 03 to obtain the fourth pattern 04. By moving the first pattern 01 to obtain the fourth pattern 04, the distance between the fourth pattern 04 and the third pattern 03 is increased. That is, after the first pattern 01 is moved, the second pattern 02 and the third pattern 03 can be moved in the same direction later, and there is enough space for the minimum unit of operation to move when performing optical proximity correction operation again, so that the line width of the pattern in the simulated pattern after operation is larger. The target layer target, that is, the first corrected pattern, moves, providing space for the movement of the minimum unit of operation, that is, the fragment.

[0043] In an embodiment of the present invention, in step two, the fourth pattern 04 is located within the range of the second pattern 02. Specifically, the fourth pattern 04 can be translated a certain distance in the horizontal direction relative to the third pattern 03, or can be translated a certain distance in the vertical direction, but it should not exceed the original range of the second pattern 02.

[0044] It should be understood that in the actual layout, the setting of the pattern may be more complex. If the first pattern 01 is a via layer, the movement rule of the via layer needs to be referred to when moving. If there are other patterns near the layout here, their target patterns will also move along with the movement of the via layer.

[0045] Step three, please refer to Figure 6, perform optical proximity correction on the original graph corresponding to the hot spot graph according to the second to fourth graphs. Since the space between the third graph 03 and the fourth graph 04 (i.e., the first graph 01 after movement) increases, in subsequent optical proximity correction, the second and third graphs can be corrected with reference to the fourth graph 04 (i.e., the first graph 01 after movement), thereby obtaining the second corrected graph. In the second corrected graph, it includes the corrected graph 05 of the fourth graph 04, the corrected graph 06 of the second graph 02, and the corrected graph 07 of the third graph 03. The post-exposure contour of the corrected graph 06 of the second graph 02 wraps the post-exposure contour of the corrected graph 05 of the fourth graph 04.

[0046] It should be noted that the above post-exposure contour can be obtained by simulating the first and second corrected graphs through software, or by measuring the first and second corrected graphs after lithography.

[0047] In an embodiment of the present invention, the method further includes step four, determining whether the line width in the second corrected graph meets the design standard, and determining whether the post-exposure contour of the second graph after correction wraps the post-exposure contour of the fourth graph after correction to reach the target ratio. If both are satisfied, the reticle is corrected using the second corrected graph.

[0048] In an embodiment of the present invention, the target ratio in step four is 90%, that is, the post-exposure contour of the corrected graph 06 of the second graph 02 wraps the post-exposure contour of the corrected graph 05 of the fourth graph 04 to reach at least 90%.

[0049] In an embodiment of the present invention, any of the above methods can be used for SRAM layout or logic device layout.

[0050] In an embodiment of the present invention, please refer to Figure 8 , when re-performing optical proximity correction on the graph as Figure 1 shown, obtain the second corrected graph as Figure 8 shown, generate and refer to the graph after movement of the lower via layer in this hot spot area (marked area). After the via layer graph moves, the correction and movement space at points 2 / 3 / 4 / 5 in the hot spot area increases. The measured line width values of each marked point in the second corrected graph are as Figure 10 shown. The line width at the measurement points moves sufficiently, and the values at points 2 / 3 / 4 / 5 increase. The simulation data after OPC correction shows that the line width under non-standard conditions after OPC correction at point 1 meets the requirements (should be greater than the value corresponding to 10% of the line width under standard conditions), and at the same time, the wrapping area of the via layer also meets the requirements. The actual wafer verification after publication Figure 9 can also show that the graph morphology at the actual graph measurement point 1 is good, and the line width uniformity is improved.

[0051] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0052] In summary, on the basis of the original correction program, the present invention takes the pattern after the movement of the via layer corresponding to the hot spot line width problem as a reference to increase the correction movement space of the hot spot line width of the metal layer and improve its process window. Since the metal layer will ensure the wrapping of the via layer during correction, the problem of insufficient wrapping area will not occur. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0053] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A layout correction method for improving the process window of a metal layer, characterized in that At least including: Step 1: Provide a first corrected pattern after optical proximity correction of a pattern to be corrected, obtain a first exposure profile according to the first corrected pattern, and define a region where the line width in the first exposure profile does not meet the design standard as a hot spot pattern; Wherein, the pattern to be corrected corresponding to the hot spot pattern includes first to third patterns, the second pattern and the third pattern are arranged at intervals, the first pattern is arranged below or above the second pattern, and the first pattern is arranged within the range of the second pattern; Step 2: Move the first pattern a partial distance away from the third pattern to obtain a fourth pattern; Step 3: Perform optical proximity correction on the original pattern corresponding to the hot spot pattern according to the second to fourth patterns to increase the optical proximity correction space of the second pattern, obtain a second corrected pattern, and obtain a second exposure profile according to the second corrected pattern, so that the line width of the second corrected pattern meets the design standard, and the exposed profile of the second pattern after correction wraps the exposed profile of the fourth pattern after correction.

2. The layout correction method for improving the process window of the metal layer according to claim 1, characterized in that: In Step 1, define the line widths of the first exposure profile obtained by exposing the first corrected pattern under non-standard conditions and standard conditions respectively. The line width under non-standard conditions is less than 90% of the line width under standard conditions, and the pattern region where the difference in different line widths of the first exposure profile obtained by exposure under non-standard conditions is greater than a preset value is the hot spot pattern that does not meet the design standard.

3. The layout correction method for improving the process window of the metal layer according to claim 1, wherein: In Step 1, the first pattern is a via layer pattern.

4. The layout correction method for improving the process window of the metal layer according to claim 1, wherein: In Step 1, the second pattern is a metal layer pattern.

5. The layout correction method for improving the process window of the metal layer according to claim 1, characterized in that: In Step 1, the third pattern is a metal layer pattern.

6. The layout correction method for improving the process window of a metal layer according to claim 1, wherein: The method further includes Step 4: Judge whether the line width in the second corrected pattern meets the design standard, and judge whether the exposed profile of the second pattern after correction wraps the exposed profile of the fourth pattern after correction to reach a target ratio. If both are satisfied, use the second corrected pattern to correct the photomask.

7. The layout correction method for improving the process window of the metal layer according to claim 6, characterized in that: The target ratio in Step 4 is 90%.

8. The layout correction method for improving the process window of the metal layer according to claim 1, wherein: In Step 2, the fourth pattern is arranged within the range of the second pattern.

9. The layout correction method for improving the process window of a metal layer according to claim 1, wherein: The method is used for SRAM layout or logic device layout.

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