A low-power pixel modulation circuit system and method for microdisplay

Abstract

The present invention provides a low-power pixel modulation circuit system and method for a micro display, comprising: a main circuit, the main circuit controls the anode voltage of an LED, and the main circuit is a single-address line latch SRAM circuit unit capable of eliminating signal competition and reducing power consumption to a preset value. The present invention solves the problems of signal competition and high power consumption caused by traditional pixel latching: through a single-address bit line latching strategy, the great fluctuation of the current density of the driving substrate and unnecessary signal competition caused by the simultaneous change of the bit line pair in the traditional pixel latch circuit are eliminated; the PMOS-type T6 tube can eliminate crosstalk and shorten the gate length and gate width of the transistors T1-T4, thereby reducing power consumption.

Description

Technical Field

[0001] The present invention relates to the field of micro-display driving, and in particular to a low-power pixel modulation circuit system and method for a micro-display. Background Art

[0002] As AR devices have higher and higher requirements for display quality, silicon-based LED microdisplays, as display terminals of AR devices, have continuously improved their core parameters such as refresh rate, resolution, and pixel density. The power consumption and display quality generated are key issues that need to be solved urgently. Therefore, low-power silicon-based LED microdisplay driver substrates that meet AR display requirements are currently a technical challenge that needs to be overcome.

[0003] At present, the driving schemes of silicon-based LED microdisplays include digital driving and analog driving. In analog driving, the grayscale is closely related to the lighting intensity, but due to the mismatch of device preparation, the grayscale number generated by analog driving will lead to inaccurate values ​​of static random access; in digital driving, the grayscale is determined by the integral of the lighting time length, which can effectively prevent the potential non-ideality between stable voltage and pixels. Digital driving has SRAM mode and DRAM mode. The SRAM mode has the advantages of low power consumption and no need for refresh. However, due to the use of dual bit line control in traditional SRAM latch units, signal competition is prone to occur when two signals jump at the same time, and the leakage generated by the bit line during the hold operation is the main source of leakage power consumption.

[0004] In addition, the brightness modulation schemes of silicon-based LED microdisplays are divided into voltage modulation and current modulation schemes. The voltage modulation scheme controls the LED voltage to be constant, and the current modulation scheme controls the LED current to be constant. Due to the inconsistency of the thickness, width, contact surface and other processes of the LED interface, the luminous intensity of silicon-based LEDs at the same voltage intensity will vary greatly, so a current modulation scheme is needed. Summary of the invention

[0005] In view of the defects in the prior art, an object of the present invention is to provide a low-power pixel modulation circuit system and method for a micro display.

[0006] According to one aspect of the present invention, a low-power pixel modulation circuit system for a micro display is provided, comprising:

[0007] A main circuit controls the anode voltage of the LED, and the main circuit is a single address line latch SRAM circuit unit capable of eliminating signal competition and reducing power consumption to a preset value.

[0008] Preferably, in the SRAM circuit unit, transistors T1 and T2 form a left inverter, transistors T3 and T4 form a right inverter, and the two groups of inverters are cross-coupled to form an inverter pair; transistors T5 and T6 serve as transmission tubes, whose sources are respectively connected to the input terminals of the left and right inverters, and whose gates are commonly connected to the word line WL, the drain of T5 serves as the input of the bit line BL, and the drain of transistor T6 is connected to the input terminal Q of the left inverter; transistor T7 is a high-voltage tube, whose gate is connected to the output terminal Q of the left inverter, reads the latch voltage and transmits it to the anode of the LED through the drain.

[0009] Preferably, before the write operation, the word line WL is pulled up to the voltage VDD, and T5 is turned on while T6 is turned off;

[0010] During a write operation, only two cross-coupled inverter pairs consisting of four transistors T1, T2, T3 and T4 of the pixel latch driven by the bit line BL write data; transistor T6 eliminates crosstalk between the inverter pairs during a write operation, shortens the gate length and gate width of the four transistors T1, T2, T3 and T4, and reduces power consumption to a preset value.

[0011] Preferably, the power consumption of the main circuit is 75% of that of the pixel latch SRAM controlled by the dual bit line.

[0012] Preferably, the main circuit further includes a cascode current mirror; the cascode current mirror replicates the current by adding transistors; the replicated current does not have the current mismatch caused by the channel length modulation effect and load change of the conventional current mirror.

[0013] Preferably, the conventional current mirror comprises a transistor T8 and a transistor T9, the gate of the transistor T8 is connected to the source of the transistor T9, and the bias voltage of the transistor T8 is provided by the transistor T9 which is diode-connected (short-circuiting the gate and source of the MOS tube);

[0014] The common-source common-gate current mirror is based on the conventional current mirror, and transistors T10 and T11 are added; the transistor T10 is a common-source device, and is cascaded with the common-gate device transistor T8 to form a common-source common-gate structure, and its gate bias voltage is provided by the diode-connected transistor T11, and the reference current flows into the source of the transistor T11; the gate of the transistor T10 is connected to the source of the transistor T11, and the bias voltage of the transistor T10 is provided by the diode-connected transistor T11; the sources of the transistors T8 and T9 are connected to the drains of the transistors T10 and T11 respectively; the common-source common-gate current mirror is connected to the source of the switch tube T7 through the diode-connected transistor T12.

[0015] Preferably, the common-source and common-gate current mirror performs current replication by adding transistors, including:

[0016] The voltage at point E between transistors T8 and T9 is copied to point G between transistors T8 and T10; the current Iled flowing through the LED copies the reference current Iref flowing into the source of transistor T11.

[0017] Preferably, the voltage at point F is expressed as

[0018] V F =V GS11 +V GS9 =V GS11 =+V E

[0019] V F =V GS1 0=+V GS8 =V GS10 =+V G

[0020] If (W 10 / L 10 ) / (W 11 / L 11 )=(W8 / L8) / (W9 / L9), then:

[0021] V GS11 =V GS10 ,V E =V G ,I=I ref

[0022] Among them, V F 、V G 、V E Respectively represent the voltages at points F, G, and E; V GS8 、V GS9 、V GS10 、V GS11 Respectively represent the gate-drain voltage of T8, T9, T10, and T11; W8, W9, W 10 , W 11 Respectively represent the gate widths of T8, T9, T10, and T11; L8, L9, L 10 , L1 represent the gate lengths of T8, T9, T10, and T11 respectively.

[0023] According to a second aspect of the present invention, a low-power pixel modulation method for a micro display is provided, using any of the above-mentioned systems to adjust the voltage at point F to satisfy

[0024] V E =V G ,I=I ref

[0025] Preferably, based on the voltage adjusted at point F, the common-source and common-gate current mirror copies the reference current Iref from the source of the input terminal T11 of the current mirror to the output terminal of the current mirror, i.e., the source terminal of T10 and the input terminal of the LED, to obtain the current Iled flowing through the LED; the current Iled flowing through the LED is always equal to the reference current Iref.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The low-power pixel modulation circuit system and method for a micro display in the embodiment of the present invention well solves the problems of signal competition and high power consumption caused by traditional pixel latching.

[0028] The low-power pixel modulation circuit system and method for microdisplays in the embodiments of the present invention reduces the signal transmission path from two to one through a single-address bit line latching strategy and also reduces the capacitance controlled by the bit line BL by half, so that the current fluctuation caused by the charging and discharging of the MOS capacitor at the moment of signal change is reduced, thereby eliminating the great fluctuation of the current density of the driving substrate and unnecessary signal competition caused by the simultaneous change of the bit line pair in the traditional pixel latch circuit. The PMOS type T6 tube can eliminate crosstalk and shorten the gate length and gate width of the T1-T4 tubes to achieve the effect of reducing power consumption.

[0029] The low-power pixel modulation circuit system and method for microdisplays in the embodiments of the present invention effectively solve the problem of LED luminous intensity differences caused by process inconsistencies in the LED interface. Through a current-type modulation scheme and the addition of a common-source and common-gate current mirror, Iled can accurately replicate Iref and is not affected by channel length modulation effects and load changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0031] Figure 1 It is a structural schematic diagram of a low-power pixel modulation circuit system for a micro display in an embodiment of the present invention;

[0032] Figure 2 FIG. 4 is a circuit diagram of a main circuit, namely an SRAM circuit unit, in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several variations and improvements may be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0034] See also Figure 1 A low-power pixel modulation circuit system and method for a micro display includes a main circuit. The main circuit controls the anode voltage of an LED, and the main circuit is a single address line latch SRAM circuit unit that can eliminate signal competition and reduce power consumption to a preset value.

[0035] The traditional pixel latch SRAM will cause a great fluctuation in the current density of the driving substrate when the bit line pairs change simultaneously, and will also cause unnecessary signal competition, and consume a lot of power. Therefore, this embodiment adopts a single address line latch solution, which reduces the power consumption to about 75% of the original and eliminates the problem of signal competition.

[0036] In a preferred embodiment of the present invention, the main circuit is a single address line latch SRAM, transistors T1, T3, T5 are NMOS tubes, transistors T2, T4, T6 are PMOS tubes, and the Q point voltage controls the drain voltage of transistor T6. The specific connection method of the components of the single address line latch SRAM circuit unit is as follows:

[0037] Transistor T1 and transistor T2 form a left inverter, transistor T3 and transistor T4 form a right inverter, and the two sets of inverters are cross-coupled to form an inverter pair; transistor T5 and transistor T6 are used as transmission tubes, and their sources are connected to the input terminals of the left and right inverters respectively, and their gates are commonly connected to the word line WL, the drain of transistor T5 is used as the input of the bit line BL, and the drain of transistor T6 is connected to the input terminal (Q) of the left inverter; transistor T7 is a switch tube, and its gate is connected to the input terminal (Q) of the left inverter, and reads the latch voltage and transmits it to the anode of the LED through the drain.

[0038] In a preferred embodiment of the present invention, before the write operation, the word line WL is pulled up to the voltage VDD, and the transistor T5 is turned on while the transistor T6 is turned off. During the write operation, only the bit line BL drives the transistors T1-T4 of the pixel latch to write data as two inverters. The transistor T6 can eliminate the crosstalk between the inverter pairs during the write operation, shorten the gate length and gate width of the transistors T1-T4, and achieve the effect of reducing power consumption. The programming power consumption of the single address line SRAM is about 75% of the power consumption of the traditional SRAM.

[0039] The above-mentioned embodiment solves the problems of signal competition and high power consumption caused by the traditional pixel latching well: the signal transmission path is reduced from two to one through the single-address bit line latching strategy and the capacitance controlled by the bit line BL is also halved, so the current fluctuation caused by the charging and discharging of the MOS capacitor at the moment of signal change is reduced, thereby eliminating the great fluctuation of the current density of the driving substrate and unnecessary signal competition caused by the simultaneous change of the bit line pair in the traditional pixel latch circuit.

[0040] In a preferred embodiment of the present invention, since the process inconsistency of the LED interface will lead to inconsistent luminous intensity, a common source and common gate current mirror is added to the power supply end of the high-voltage tube, that is, a structure composed of a cascade connection of a common source device transistor T10 and a common gate device transistor T8. Since the common source and common gate current mirror can ignore the channel length modulation effect and the change of the load, it can copy the current more accurately than the ordinary current mirror, so that the luminous intensity of the LED remains consistent.

[0041] In a preferred embodiment, the specific structure of the cascode current mirror is:

[0042] The structure of the conventional current mirror is a structure composed of transistors T8 and T9, the gate of transistor T8 is connected to the source of transistor T9, and the bias voltage of transistor T8 is provided by transistor T9 connected by a diode (shorting the gate and source of the MOS tube). Add transistor pair T10 and transistor T11: transistor T10 is a common source device, cascaded with common gate device transistor T8 to form a common source and common gate structure, and its gate bias voltage is provided by transistor T11 connected by a diode; the connection between transistors T10 and T11 is the same as that between transistors T8 and T9, and the sources of transistors T8 and T9 are connected to the drains of transistors T10 and T11 respectively. The common source and common gate current mirror is connected to the source of transistor T7 through a diode-connected transistor T12.

[0043] In a preferred embodiment, the bias voltage of the current mirror is provided by diode-connected transistors. In this embodiment, a current modulation scheme is adopted to achieve the purpose of accurately replicating the current by adding transistor pairs. The voltage at point F can be expressed as:

[0044] V F =V GS11 +V GS9 =V GS11 +V E

[0045] V F =V GS10 +V GS8 =V GS10 +V G

[0046] If (W10 / L 10 ) / (W 11 / L 11 )=(W8 / L8) / (W9 / L9), then:

[0047] V GS11 =V GS10 ,V E =V G ,I=I ref

[0048] Among them, V F 、V G 、V E Respectively represent the voltages at points F, G, and E; V GS8 、V GS9 、V GS10 、V GS11 Respectively represent the gate-drain voltage of T8, T9, T10, and T11; W8, W9, W 10 , W 11 Respectively represent the gate widths of T8, T9, T10, and T11; L8, L9, L 10 , L1 represent the gate lengths of T8, T9, T10, and T11 respectively.

[0049] Therefore, by adjusting the voltage at point F, the voltage at point G can be accurately replicated at point E, allowing Iled to more accurately replicate Iref.

[0050] The above embodiment solves the problem of LED luminous intensity difference caused by process inconsistency of LED interface well: through the current modulation scheme, the common source and common gate current mirror is added, so that Iled can accurately replicate Iref and is not affected by the channel length modulation effect and load changes.

[0051] Based on the same inventive concept, a single address line latch SRAM current modulation method for controlling LED current is provided in other embodiments. The system in any embodiment is performed to adjust the voltage at point F to satisfy the above relationship. The common source and common gate current mirror copies the reference current Iref from the source of the input terminal T11 of the current mirror to the output terminal of the current mirror, that is, the source terminal of T10 and the input terminal of the LED, to obtain the current Iled flowing through the LED. The current Iled flowing through the LED is always equal to the reference current Iref.

[0052] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various modifications or variations within the scope of the claims, which does not affect the essence of the present invention. The above preferred features can be used in any combination without conflicting with each other.

Claims

1. A low-power pixel modulation circuit system for a micro display, characterized in that: include: A main circuit, the main circuit controls the anode voltage of the LED display, the main circuit being a single address line latch SRAM circuit unit capable of eliminating signal competition and reducing power consumption to a preset value; The transistors T1 and T2 in the SRAM circuit unit form a left inverter, and the transistors T3 and T4 form a right inverter. The two sets of inverters are cross-coupled to form an inverter pair; the transistors T5 and T6 are used as transmission tubes, and their sources are respectively connected to the input ends of the left and right inverters, and their gates are commonly connected to the word line WL. The drain of T5 serves as the input of the bit line BL, and the drain of the transistor T6 is connected to the input end of the left inverter, i.e., Q; Transistor T7 is a high voltage tube, the gate of which is connected to the input terminal of the left inverter, i.e., Q, and reads the latch voltage and transmits it to the anode of the LED display through the drain; Before the write operation, the word line WL is pulled up to the voltage VDD, T5 is turned on and T6 is turned off; During write operation, only the two cross-coupled inverter pairs consisting of four transistors T1, T2, T3 and T4 of the pixel latch driven by the bit line BL write data; The transistor T6 eliminates the crosstalk between the inverter pairs during the write operation, shortens the gate length and gate width of the four transistors T1 , T2 , T3 and T4 , and reduces the power consumption to a preset value.

2. A low-power pixel modulation circuit system for a micro display according to claim 1, characterized in that: The power consumption of the main circuit is 75% of that of the pixel latch SRAM controlled by the dual bit line.

3. A low-power pixel modulation circuit system for a micro display according to claim 1, characterized in that: It also includes a common-source and common-gate current mirror attached to the main circuit; the common-source and common-gate current mirror replicates the current by adding transistors; the replicated current does not have the current mismatch caused by the channel length modulation effect and load change of the conventional current mirror.

4. A low-power pixel modulation circuit system for a micro display according to claim 3, characterized in that: The conventional current mirror comprises a transistor T8 and a transistor T9, the gate of the transistor T8 is connected to the source of the transistor T9, and the bias voltage of the transistor T8 is provided by the diode-connected transistor T9; The common-source common-gate current mirror is based on the conventional current mirror, and a transistor T10 and a transistor T11 are added; the transistor T10 is a common-source device, and is cascaded with the common-gate device transistor T8 to form a common-source common-gate structure, and its gate bias voltage is provided by the diode-connected transistor T11, and the reference current flows into the source of the transistor T11; The gate of transistor T10 is connected to the source of transistor T11, and the bias voltage of transistor T10 is provided by diode-connected transistor T11; The sources of transistors T8 and T9 are connected to the drains of transistors T10 and T11 respectively; the common-source common-gate current mirror is connected to the source of switch tube T7 through a diode-connected transistor T12.

5. A low-power pixel modulation circuit system for a micro display according to claim 4, characterized in that: The cascode current mirror performs current replication by adding transistors, including: The voltage at point E between transistors T8 and T9 is copied to point G between transistors T8 and T10; the current Iled flowing through the LED copies the reference current Iref flowing into the source of transistor T11.

6. A low-power pixel modulation circuit system for a micro display according to claim 5, characterized in that: The voltage at point F is expressed as VF = VGS 11 + VGS 9 = VGS 11 + VE VF = VGS 10 + VGS 8 = VGS 10 + VG If (W 10 / L 10 ) / (W 11 / L 11 )= (W8 / L8) / (W9 / L9), then: VGS 11 = VGS 10, VE = VG , I = Iref Among them, V F 、V G 、V E Respectively represent the voltages at points F, G, and E; V GS8 、V GS9 、V GS10 、V GS11 Respectively represent the gate-drain voltage of T8, T9, T10, and T11; W8, W9, W 10 , W 11 Respectively represent the gate widths of transistors T8, T9, T10, and T11; L8, L9, L 10 , L1 represent the gate lengths of transistors T8, T9, T10, and T11 respectively.

7. A low-power pixel modulation method for a micro display, using the system according to any one of claims 1 to 6, characterized in that: Adjust the voltage at point F to satisfy VE = VG , I = Iref.

8. A low-power pixel modulation method for a micro display according to claim 7, characterized in that: Based on the voltage adjusted at point F, the cascode current mirror copies the reference current Iref from the source of the input terminal T11 of the current mirror to the output terminal of the current mirror, i.e., the source terminal of T10 and the input terminal of the LED, to obtain the current Iled flowing through the LED; The current Iled flowing through the LED is always equal to the reference current Iref.

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