Phase-locked loop chip and phase-locked loop system

Abstract

The application provides a phase-locked loop chip and a phase-locked loop system, and relates to the technical field of integrated circuits.The gain automatic switching reference sampling phase detector for a phase-locked loop proposed in the application can effectively improve the phase detection gain in the locked state while keeping the wide capture range [‑π / 2, π / 2] characteristic of the traditional reference sampling phase detector; the gain automatic switching reference sampling phase detector proposed in the application uses a gain controller to compare the branch voltages output by the first branch unit and the second branch unit with the relationship of the preset threshold voltage to determine whether it works in the normal mode or the gain multiplication mode; if both branch voltages are less than the preset threshold voltage, an enable signal of the gain multiplication mode is generated, the clock generator generates the corresponding clock control signal, and the clock control signal acts on the first branch unit and the second branch unit, so that the effect of M times gain increase is achieved, and the compromise relationship between the phase detection gain and the capture range of the existing phase detector is broken.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a phase-locked loop (PLL) chip and a PLL system. Background Technology

[0002] High-performance wireless and wired transceivers and data converters all require phase-locked loops (PLLs) with high spectral purity. Therefore, various schemes have been proposed to improve the phase noise, jitter, reference spurious emissions, and power efficiency of PLLs.

[0003] Currently, there are three main types of existing analog phase-locked loop (PLL) structures: PLLs based on a combination of frequency and charge pumps, subsampling phase detector PLLs, and reference sampling phase detector PLLs. Among them, (1) the phase-locked loop based on the combination of frequency and phase detector and charge pump has the largest capture range [-2π, 2π], but the phase detector gain is the smallest and cannot effectively suppress the in-band noise caused by the charge pump; (2) the subsampling phase detector phase-locked loop directly samples the sine wave output by the voltage-controlled oscillator with a rectangular wave reference signal to achieve high phase detection gain, but its capture range is very narrow, only [-π / 2N, π / 2N], and a frequency-locked loop (FLL) is required to achieve the correct frequency synthesis function, which increases the complexity of the system design; (3) the reference sampling phase detector phase-locked loop directly samples the sine wave reference signal with a feedback rectangular wave signal. Compared with the subsampling phase detector, its capture range is expanded to [-π / 2, π / 2], and it can work correctly without a frequency-locked loop, but its gain is much smaller than that of the subsampling phase detector and cannot effectively suppress the in-band noise caused by the charge pump.

[0004] However, all three schemes mentioned above involve a trade-off between phase detection gain and capture range. Therefore, it is urgent to propose a new phase-locked loop system structure to break the trade-off between phase detection gain and capture range in the existing three schemes, so as to realize a reference sampling phase detector that can increase the phase detection gain by M times while maintaining the capture range of [-π / 2, π / 2] of the traditional reference sampling phase detector. Summary of the Invention

[0005] The purpose of this application is to address the shortcomings of the prior art by providing a phase-locked loop (PLL) chip and PLL system, thereby breaking the trade-off between phase detection gain and capture range in the three existing schemes. This will enable a reference sampling phase detector that, while maintaining the capture range characteristics of [-π / 2, π / 2] and the reliability of transistor operation of the traditional reference sampling phase detector, increases the phase detection gain by M times.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, embodiments of this application provide a phase-locked loop chip, comprising: a voltage-controlled oscillator, a multi-mode frequency divider, a clock generator, a gain-switching reference sampling phase detector, and a control voltage generation module; wherein, the gain-switching reference sampling phase detector comprises: a differential sampling module and a gain controller, and the differential sampling module comprises: a first branch unit and a second branch unit that are symmetrical to each other.

[0008] The output terminal of the voltage-controlled oscillator is connected to the input terminal of the multi-mode frequency divider, and the output terminal of the multi-mode frequency divider is connected to the first input terminal of the clock generator.

[0009] The first input terminal of the gain controller is connected to the first output terminal of the first branch unit, the second input terminal of the gain controller is connected to the first output terminal of the second branch unit, and the output terminal of the gain controller is connected to the second input terminal of the clock generator.

[0010] The first input terminal of the first branch unit is used to receive a positive sinusoidal reference signal, the second input terminal of the first branch unit is used to receive the common-mode signal of the sinusoidal reference signal, and the second output terminal of the first branch unit is connected to the input terminal of the control voltage generation module.

[0011] The first input terminal of the second branch unit is used to receive a negative sinusoidal reference signal, the second input terminal of the second branch unit is used to receive the common-mode signal, and the second output terminal of the second branch unit is connected to the input terminal of the control voltage generation module.

[0012] The gain controller is used to generate an enable signal based on the branch voltage output by the first branch unit and the branch voltage output by the second branch unit, and send the enable signal to the clock generator through the output terminal of the gain controller;

[0013] The output of the clock generator is connected to the first branch unit and the second branch unit respectively;

[0014] The clock generator is used to generate a clock control signal according to the enable signal, and apply the clock control signal to the first branch unit and the second branch unit through the output terminal of the clock generator to control the gain automatic switching reference sampling phase detector to be in the target working mode. In the target working mode, the second output terminal of the first branch unit outputs a first holding voltage and the second output terminal of the second branch unit outputs a second holding voltage, so that the control voltage generation module controls the control voltage output by the output terminal of the control voltage generation module according to the first holding voltage and the second holding voltage.

[0015] The output terminal of the control voltage generation module is connected to the input terminal of the voltage-controlled oscillator, and outputs the control voltage to the voltage-controlled oscillator so that the voltage-controlled oscillator corrects the voltage control signal according to the control voltage and outputs the corrected voltage control signal.

[0016] Optionally, the first branch unit includes: a first set of switches, a second set of switches, a third set of switches, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first control switch, and a first holding capacitor;

[0017] The first terminal of the first set of switches is used to connect to the positive sinusoidal reference signal;

[0018] The first terminal of the second group of switches is connected to the second terminal of the first group of switches, the second terminal of the second group of switches is connected to the first terminal of the third group of switches, and the second terminal of the third group of switches is used to receive the common-mode signal.

[0019] The first terminal of the first capacitor serves as the first output terminal of the first branch unit. The first terminal of the first capacitor is connected to the second terminal of the first group of switches. The second terminal of the first capacitor is used to connect the common-mode signal.

[0020] The first terminal of the second capacitor is connected to the first terminal of the second set of switches, and the second terminal of the second capacitor is used to receive the common-mode signal;

[0021] The first terminal of the third capacitor is connected to the first terminal of the second group of switches, and the second terminal of the third capacitor is connected to the first terminal of the third group of switches.

[0022] The first terminal of the fourth capacitor is connected to the first terminal of the second group of switches, and the second terminal of the fourth capacitor is connected to the first terminal of the third group of switches.

[0023] The first terminal of the fifth capacitor is connected to the second terminal of the first set of switches and the first terminal of the first control switch, and the second terminal of the fifth capacitor is connected to the first terminal of the third set of switches.

[0024] The second terminal of the first control switch is connected to the first terminal of the first holding capacitor and the input terminal of the control voltage generating module, and the second terminal of the first holding capacitor is grounded.

[0025] Optionally, the first set of switches includes: a first switch, a second switch, a third switch, a fourth switch, and a fifth switch;

[0026] The first terminal of the first switch, the first terminal of the second switch, the first terminal of the third switch, the first terminal of the fourth switch, and the first terminal of the fifth switch are respectively used to connect to the positive sinusoidal reference signal;

[0027] The second end of the first switch is connected to the first end of the first capacitor, the second end of the second switch is connected to the first end of the second capacitor, the second end of the third switch is connected to the first end of the third capacitor, the second end of the fourth switch is connected to the first end of the fourth capacitor, and the second end of the fifth switch is connected to the first end of the fifth capacitor.

[0028] Optionally, the second set of switches includes: a sixth switch, a seventh switch, and an eighth switch;

[0029] The first end of the sixth switch is connected to the first end of the second capacitor, the second end of the sixth switch is connected to the second end of the third capacitor, the first end of the seventh switch is connected to the first end of the third capacitor, the second end of the seventh switch is connected to the second end of the fourth capacitor, the first end of the eighth switch is connected to the first end of the fourth capacitor, and the second end of the eighth switch is connected to the second end of the fifth capacitor.

[0030] Optionally, the third set of switches includes: a ninth switch, a tenth switch, and an eleventh switch;

[0031] The first terminal of the ninth switch is connected to the second terminal of the third capacitor, the first terminal of the tenth switch is connected to the second terminal of the fourth capacitor, and the first terminal of the eleventh switch is connected to the second terminal of the fifth capacitor.

[0032] The second terminals of the ninth switch, the tenth switch, and the eleventh switch are respectively used to connect to the common-mode signal.

[0033] Optionally, the second branch unit includes: a fourth group of switches, a fifth group of switches, a sixth group of switches, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a second control switch, and a second holding capacitor;

[0034] The first terminal of the fourth set of switches is used to connect to the negative sinusoidal reference signal;

[0035] The first terminal of the fifth group of switches is connected to the second terminal of the fourth group of switches, the second terminal of the fifth group of switches is connected to the first terminal of the sixth group of switches, and the second terminal of the sixth group of switches is used to receive the common mode signal;

[0036] The first terminal of the sixth capacitor serves as the first output terminal of the second branch unit, the first terminal of the sixth capacitor is connected to the second terminal of the fourth group of switches, and the second terminal of the sixth capacitor is used to connect to the common-mode signal.

[0037] The first terminal of the seventh capacitor is connected to the first terminal of the fifth group of switches, and the second terminal of the seventh capacitor is used to connect to the common-mode signal;

[0038] The first terminal of the eighth capacitor is connected to the first terminal of the fifth group of switches, and the second terminal of the eighth capacitor is connected to the first terminal of the sixth group of switches.

[0039] The first terminal of the ninth capacitor is connected to the first terminal of the fifth group of switches, and the second terminal of the ninth capacitor is connected to the first terminal of the sixth group of switches.

[0040] The first terminal of the tenth capacitor is connected to the second terminal of the fourth group of switches and the first terminal of the second control switch, and the second terminal of the tenth capacitor is connected to the first terminal of the sixth group of switches.

[0041] The second terminal of the second control switch is connected to the first terminal of the second holding capacitor and the input terminal of the control voltage generating module, and the second terminal of the second holding capacitor is grounded.

[0042] Optionally, the fourth group of switches includes: the twelfth switch, the thirteenth switch, the fourteenth switch, the fifteenth switch, and the sixteenth switch;

[0043] The first terminals of the twelfth switch, the thirteenth switch, the fourteenth switch, the fifteenth switch, and the sixteenth switch are respectively used to connect to the negative sinusoidal reference signal;

[0044] The second terminal of the twelfth switch is connected to the first terminal of the sixth capacitor, the second terminal of the thirteenth switch is connected to the first terminal of the seventh capacitor, the second terminal of the fourteenth switch is connected to the first terminal of the eighth capacitor, the second terminal of the fifteenth switch is connected to the first terminal of the ninth capacitor, and the second terminal of the sixteenth switch is connected to the first terminal of the tenth capacitor.

[0045] Optionally, the fifth group of switches includes: the seventeenth switch, the eighteenth switch, and the nineteenth switch;

[0046] The first end of the seventeenth switch is connected to the first end of the seventh capacitor, the second end of the seventeenth switch is connected to the second end of the eighth capacitor, the first end of the eighteenth switch is connected to the first end of the eighth capacitor, the second end of the eighteenth switch is connected to the second end of the ninth capacitor, the first end of the nineteenth switch is connected to the first end of the ninth capacitor, and the second end of the nineteenth switch is connected to the second end of the tenth capacitor.

[0047] Optionally, the sixth group of switches includes: the twentieth switch, the twenty-first switch, and the twenty-second switch;

[0048] The first end of the twentieth switch is connected to the second end of the eighth capacitor, the first end of the twentieth switch is connected to the second end of the ninth capacitor, and the first end of the twentieth switch is connected to the second end of the tenth capacitor.

[0049] The second terminals of the twentieth switch, the twentieth eleventh switch, and the twentieth twelfth switch are respectively used to connect to the common-mode signal.

[0050] Optionally, the gain controller includes: a first comparison unit, a second comparison unit, and a first AND gate;

[0051] The first comparison unit and the second comparison unit each include: a first dynamic comparator, a second dynamic comparator, and a second AND gate;

[0052] The first input terminal of the first dynamic comparator and the first input terminal of the second dynamic comparator of the first comparison unit are respectively connected to the first terminal of the first capacitor. The output terminal of the first dynamic comparator and the output terminal of the second dynamic comparator of the first comparison unit are respectively connected to the input terminal of the second AND gate of the first comparison unit. The output terminal of the second AND gate of the first comparison unit is connected to the first input terminal of the first AND gate.

[0053] The first input terminal of the first dynamic comparator and the first input terminal of the second dynamic comparator of the second comparison unit are respectively connected to the first terminal of the sixth capacitor. The output terminal of the first dynamic comparator and the output terminal of the second dynamic comparator of the second comparison unit are respectively connected to the input terminal of the second AND gate of the second comparison unit. The output terminal of the second AND gate of the second comparison unit is connected to the second input terminal of the first AND gate.

[0054] The output of the first AND gate is connected to the second input of the clock generator.

[0055] Optionally, the first output terminal of the clock generator is connected to the clock terminals of each dynamic comparator in the first comparison unit and the clock terminals of each dynamic comparator in the second comparison unit, respectively, for outputting clock signals to the clock terminals of each dynamic comparator in the first comparison unit and the clock terminals of each dynamic comparator in the second comparison unit.

[0056] The second output terminal of the clock generator is connected to the third terminal of each switch in the first group of switches and the third terminal of each switch in the fourth group of switches, and is used to output a first clock control signal to each switch in the first group of switches and each switch in the fourth group of switches.

[0057] The third output terminal of the clock generator is connected to the third terminal of each switch in the third group of switches and the third terminal of each switch in the sixth group of switches, and is used to output a second clock control signal to each switch in the third group of switches and each switch in the sixth group of switches.

[0058] The fourth output terminal of the clock generator is connected to the third terminal of each switch in the second group of switches and the third terminal of each switch in the fifth group of switches, and is used to output a third clock control signal to each switch in the third group of switches and each switch in the fifth group of switches.

[0059] The fifth output terminal of the clock generator is connected to the third terminal of the first control switch and the third terminal of the second control switch, and is used to output a fourth clock control signal to the first control switch and the second control switch.

[0060] Secondly, this application also provides a phase-locked loop system, the system including the phase-locked loop chip, off-chip crystal oscillator and off-chip balun provided in any of the embodiments of the first aspect above;

[0061] The output terminal of the off-chip crystal oscillator is connected to the first input terminal of the off-chip balun, and the first output terminal of the off-chip balun is connected to the first input terminal of the first branch unit in the phase-locked loop chip; the second output terminal of the off-chip balun is connected to the first input terminal of the second branch unit in the phase-locked loop chip.

[0062] The external balun is used to convert the sinusoidal signal generated by the external crystal oscillator into a positive sinusoidal signal and a negative sinusoidal signal. The positive sinusoidal signal is input to the first branch unit in the phase-locked loop chip through the first output terminal of the external balun, and the negative sinusoidal signal is input to the second branch unit in the phase-locked loop chip through the second output terminal of the external balun.

[0063] The second input terminal of the off-chip balun is used to receive the common-mode signal of the sinusoidal signal.

[0064] The beneficial effects of this application are:

[0065] This application provides a phase-locked loop (PLL) chip and a PLL system. First, since the automatic gain switching reference sampling phase detector proposed in this application is based on the existing traditional reference sampling phase detector PLL, it ensures that the capture range of the automatic gain switching reference sampling phase detector proposed in this application is [-π / 2, π / 2]. Second, the gain controller uses the branch voltages output by the first branch unit and the second branch unit to determine the error voltage V corresponding to the phase error between the reference signal input to the current PLL and the voltage-controlled signal output by the voltage-controlled oscillator.ε With the preset threshold voltage V LIM The magnitude of the error voltage V is used to achieve automatic switching between the two operating modes; if the error voltage V ε Less than the preset threshold voltage V LIM If the gain controller generates an enable signal to put the automatic gain switching reference sampling phase detector into gain multiplication mode, the gain controller will transmit the generated enable signal to the clock generator. The clock generator will then generate a clock control signal based on the enable signal. The clock control signal will then be applied to the first and second branch units through the output of the clock generator to control the automatic gain switching reference sampling phase detector to be in gain multiplication mode, achieving a gain increase of M times. Otherwise, if the error voltage V... ε The voltage is greater than the preset threshold voltage V. LIM The gain-switching reference sampling phase detector is in normal operating mode. This allows the gain-switching reference sampling phase detector provided in this application to break the trade-off between the phase detection gain and the capture range of the three existing schemes. That is, while maintaining the capture range characteristics of [-π / 2, π / 2] and the reliability of transistor operation of the traditional reference sampling phase detector, the phase detection gain is increased by M times to effectively suppress the in-band noise caused by the charge pump and reduce the area occupied by the capacitor in the loop filter, thereby realizing a type II structure reference sampling phase detector phase-locked loop with low phase noise, low jitter and low spurious emissions. Attached Figure Description

[0066] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0067] Figure 1 This is a schematic diagram of the structure of a phase-locked loop chip provided in an embodiment of this application;

[0068] Figure 2 This is a schematic diagram of a traditional reference sampling phase detector.

[0069] Figure 3 This is a schematic diagram of the transmission characteristic curve of the automatic gain switching reference sampling phase detector of this application;

[0070] Figure 4 A circuit diagram of a phase-locked loop chip provided in an embodiment of this application;

[0071] Figure 5 This is a schematic diagram of the operation of the gain-switching reference sampling phase detector provided in the embodiments of this application. Figure 1 ;

[0072] Figure 6 This is a schematic diagram of the operation of the gain-switching reference sampling phase detector provided in the embodiments of this application. Figure 2 ;

[0073] Figure 7 This is a schematic diagram of the operation of the gain-switching reference sampling phase detector provided in the embodiments of this application. Figure 3 ;

[0074] Figure 8 This is a schematic diagram of the operation of the gain-switching reference sampling phase detector provided in the embodiments of this application. Figure 4 ;

[0075] Figure 9 The schematic diagram of the multi-mode divider and clock generation circuit provided in the embodiments of this application;

[0076] Figure 10 A schematic diagram of a phase-locked loop system is provided for the embodiments of this application.

[0077] Icons: 100-Phase-Locked Loop Chip; 101-Voltage-Controlled Oscillator; 102-Multi-Mode Frequency Divider; 103-Clock Generator; 104-Gain Automatic Switching Reference Sampling Phase Detector; 105-Control Voltage Generation Module; 106-Differential Sampling Module; 107-Gain Controller; 108-First Branch Unit; 109-Second Branch Unit. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. In addition, it should be understood that the schematic drawings are not drawn to scale.

[0079] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0080] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0081] The structure of the phase-locked loop chip provided in this application will be described in detail through the following embodiments.

[0082] Figure 1 A schematic diagram of the structure of the phase-locked loop chip provided in the embodiments of this application. Figure 1 ;like Figure 1 As shown, the phase-locked loop chip 100 includes: a voltage-controlled oscillator 101, a multi-mode frequency divider 102, a clock generator 103, a gain-switching reference sampling phase detector 104, and a control voltage generation module 105.

[0083] The output of the voltage-controlled oscillator (VCO) 101 is connected to the input of the multi-modulus divider (MMD) 102, and the output of the MMD 102 is connected to the first input of the clock generator (CG) 103.

[0084] In this embodiment, the gain-switching reference sampling phase detector 104 is the core module of this application. The gain-switching reference sampling phase detector 104 includes a differential sampling module 106 and a gain controller 107. The differential sampling module 106 includes a first branch unit 108 and a second branch unit 109 that are symmetrically arranged.

[0085] It should be noted that the gain-switching reference sampling phase detector 104 proposed in this application is based on the existing conventional reference sampling phase detector phase-locked loop, the structure of which is as follows: Figure 2 As shown. In this way, the capture range of the gain-switching reference sampling phase detector 104 proposed in this application can be ensured to be [-π / 2, π / 2].

[0086] also, Figure 1 The gain-switching reference sampling phase detector 104 shown adopts a differential mode, that is, the gain-switching reference sampling phase detector 104 includes two completely symmetrical first branch units 108 and second branch units 109. In this way, the gain of the gain-switching reference sampling phase detector 104 can be increased by two times, while effectively suppressing the charge injection effect and clock feedthrough effect of the switching transistor.

[0087] The first input terminal of the gain controller 107 is connected to the first output terminal of the first branch unit 108, the second input terminal of the gain controller 107 is connected to the first output terminal of the second branch unit 109, and the output terminal of the gain controller 107 is connected to the second input terminal of the clock generator 103.

[0088] The first input terminal of the first branch unit 108 is used to receive a positive sinusoidal reference signal V. REF+ The second input terminal of the first branch unit 108 is used to input the common-mode signal V of the sinusoidal reference signal. CM The second output terminal of the first branch unit 108 is connected to the input terminal of the control voltage generation module 105.

[0089] The first input terminal of the second branch unit 109 is used to receive a negative sinusoidal reference signal V. REF- The second input terminal of the second branch unit 109 is used to connect the common-mode signal V. CM The second output terminal of the second branch unit 109 is connected to the input terminal of the control voltage generation module 105.

[0090] Among them, the common-mode signal V CM =(V REF+ +V REF- ) / 2.

[0091] It should be noted that the sinusoidal reference signal (i.e., V) REF+ V REF- A 250MHz low-noise off-chip crystal oscillator can be converted into a differential signal via an off-chip balun and then input to the first branch unit 108 and the second branch unit 109 as the reference clock signal for the phase-locked loop chip 100. For example, when the output signal frequency of the phase-locked loop is 6.75GHz, the total power consumption during locking is 7.1mW, and the output signal of the voltage-controlled oscillator is divided by two to drive the instrument for measurement.

[0092] Gain controller 107 is used to adjust the branch voltage V output by the first branch unit 108 according to the branch voltage V. S+ The branch voltage V of the second branch unit outputting 109. S- Generate enable signal EN BS And will enable signal EN BS The signal is sent to the clock generator 103 through the output of the gain controller 107.

[0093] The output terminals of clock generator 103 are connected to the first branch unit 108 and the second branch unit 109 respectively. Clock generator 103 is used to generate clock signals according to the enable signal EN. BS A clock control signal is generated and applied to the first branch unit 108 and the second branch unit 109 through the output of the clock generator to control the gain automatic switching reference sampling phase detector 104 to be in the target operating mode. In the target operating mode, the second output of the first branch unit 108 outputs a first holding voltage V. H+ The second output terminal of the second branch unit 109 outputs the second holding voltage V. H-So that the control voltage generation module 105 controls the voltage according to the first holding voltage V. H+ With the second holding voltage V H- To control the control voltage output from the output terminal of the control voltage generation module 105.

[0094] The working modes of the gain-automatic switching reference sampling phase detector 104 include: tracking mode, sampling and comparison mode, gain multiplication mode and normal mode. Among them, tracking mode and sampling and comparison mode are the necessary working modes for any sampling structure type of phase-locked loop.

[0095] It should be noted that, in order to explain the working principle of the gain-switching reference sampling phase detector 104 proposed in this application, we first need to... Figure 2 The working principle of the conventional reference sampling phase detector will be introduced first, and then the gain-switching reference sampling phase detector 104 proposed in this application will be explained.

[0096] like Figure 2 As shown, the reference sampling phase detector uses the feedback-divided clock signal f DIV For the sinusoidal reference signal f REF Sampling is performed to measure the phase error between the two. Converted to voltage error V ε The transmission characteristic curve of a traditional sampling phase detector is as follows: Figure 3 As shown in the first curve, when the phase error When the value is sufficiently small, the gain of the phase detector can be approximated as K. PD =A REF ,in V represents the amplitude of the sinusoidal signal. DD This is the power supply voltage. If the amplitude of the sinusoidal reference signal is increased to M·A... REF The gain K of the phase detector PD This also increases accordingly by a factor of M. However, when the phase error... When the value is large, the corresponding sampling voltage will exceed the power supply voltage V. DD This causes subsequent circuits to malfunction unreliably. Therefore, as... Figure 3 As shown in the second curve, a threshold voltage V is set. LIM ,satisfy

[0097] (1) When phase error The larger the value, the corresponding error voltage V ε Greater than V LIM At this time, it operates according to the traditional sampling phase detector, that is, the normal working mode.

[0098] (2) When phase error Smaller, corresponding error voltage V ε Less than VLIM At that time, the error voltage V ε The gain of the phase detector is multiplied by M to achieve the gain multiplied by M, i.e., the gain multiplication mode, and the two operating modes are required to be able to switch seamlessly and automatically.

[0099] Therefore, the transfer characteristic curve of the expected gain-switching reference sampling phase detector 104 in this application is as follows: Figure 3 The second curve in the figure is shown.

[0100] In this embodiment, reference continues to be made to Figure 1 As shown, the branch voltage V output by the first branch unit 108 is... S+ For example, the error voltage V ε =|V CM -V S+ |; Alternatively, for the branch voltage V of 109 output by the second branch unit. S- The error voltage can also be expressed as: error voltage V ε =|V CM -V S- |

[0101] In order to achieve Figure 3 The gain-automatic switching reference sampling phase detector 104 in the middle realizes the multiplication of error voltage by using the transfer characteristic curve, and the gain controller 107 uses the branch voltage V output by the first branch unit 108 to achieve the multiplication of error voltage. S+ and the branch voltage V of the second branch unit outputting 109. S- To compare the error voltage V ε With the preset threshold voltage V LIM The size is adjusted to enable automatic switching between the two working modes.

[0102] Specifically, (1) if the gain controller 107 determines the branch voltage V output by the first branch unit 108... S+ The branch voltage V of the second branch unit outputting 109. S- , to obtain V ε <V LIM Then determine the generated enable signal EN. BS =1, meaning the target operating mode is gain multiplication mode, and the generated enable signal EN is... BS =1 is transmitted to the clock generator, which uses the enable signal EN. BS =1 generates a clock control signal; then, the clock control signal is applied to the first branch unit 108 and the second branch unit 109 through the output of the clock generator to control the gain automatic switching reference sampling phase detector 104 to be in the gain multiplication mode, thereby achieving the effect of increasing the gain by M times.

[0103] Meanwhile, considering that in a traditional Type II phase-locked loop, the in-band noise is usually determined by the noise of the charge pump, the resulting phase noise is expressed as shown in the following formula (1):

[0104]

[0105] in, Let K be the one-sided power spectral density of the charge pump noise, N be the ratio of the output signal frequency to the reference signal frequency, and K be the power spectral density of the charge pump noise. PD It is the gain of the phase detector or frequency detector, K CP =g m This is the gain of the charge pump. Only the effect of thermal noise is considered. It can be expressed as shown in the following formula (2):

[0106]

[0107] Where k is the Boltzmann constant, T is the absolute temperature, γ is the noise figure of the transistor, and g m For the transconductance of a current source transistor, τ on T is the conduction time of the charge pump. REF To reference the period of the clock signal, and considering that there are two current source transistors (upper and lower) in the charge pump, we multiply by 2. Substituting formula (2) into formula (1) yields the following formula (3):

[0108]

[0109] From formula (3), we can see that by increasing g m and K PD This can improve in-band noise caused by charge pumping; however, due to the squared relationship, increasing K... PD It is more effective at suppressing noise. Furthermore, the maximum capacitance C1 of the loop filter in a Type II phase-locked loop is expressed as shown in the following formula (4):

[0110]

[0111] Among them, K VCO f is the tuning gain of the voltage-controlled oscillator. c For the open-loop bandwidth, f zero To ensure the stability of the open-loop circuit, the zeros of the loop are determined by f. To maintain sufficient phase margin in the loop, f... c with f zero The ratio remains unchanged.

[0112] From formulas (3)-(4), it can be seen that increasing K... PD Decrease g m This allows for the reduction of C1 value while effectively suppressing phase noise caused by charge pumps, thereby reducing the chip area occupied. Reducing gm It can also reduce power consumption.

[0113] Therefore, in this embodiment, when the gain-automatic switching reference sampling phase detector 104 is in gain-multiplying mode, while increasing the gain by M times, it can also effectively suppress in-band noise caused by charge pump and reduce the area occupied by capacitors in the loop filter, thereby realizing a type II structure reference sampling phase detector phase-locked loop with low phase noise, low jitter and low spurious emissions.

[0114] (2) If the gain controller 107 is based on the branch voltage V output by the first branch unit 108 S+ The branch voltage V of the second branch unit outputting 109. S- , to obtain V ε >V LIM Then determine the generated enable signal EN. BS =0, meaning the target operating mode is normal mode, and the generated enable signal EN is set to 0. BS =0 is transmitted to the clock generator, which uses the enable signal EN. BS =0 generates a clock control signal; then, the clock control signal is applied to the first branch unit 108 and the second branch unit 109 through the output of the clock generator to control the gain automatic switching reference sampling phase detector 104 to be in normal mode. At this time, the gain is the same as that of the conventional reference sampling phase detector.

[0115] In this embodiment, the enable signal EN BS Under control, the two operating modes can be automatically switched. Furthermore, since the phase-locked loop proposed in this application adopts a Type II structure, the phase error is close to zero when the loop is locked. Therefore, the characteristic of the Type II phase-locked loop providing this application, where the phase error is close to zero when locked, can be utilized to enable the proposed phase-locked loop to automatically operate in gain-multiply mode when locked, effectively improving the in-band phase noise of the phase-locked loop.

[0116] The output terminal of the control voltage generation module 105 is connected to the input terminal of the voltage-controlled oscillator 101, and outputs the control voltage to the voltage-controlled oscillator 101 so that the voltage-controlled oscillator 101 corrects the voltage control signal according to the control voltage and outputs the corrected voltage control signal.

[0117] Optionally, in this embodiment, the control voltage generation module 105 may include: a transconductor g m And loop filter (LF). Among them, the transconductance g m It is mainly used to hold the first voltage V H+ Second holding voltage V H-The current is converted into current and used to charge and discharge the loop filter LF to generate the control voltage Vc of the voltage-controlled oscillator 101, so that the voltage-controlled oscillator 101 corrects the voltage control signal according to the control voltage Vc and outputs the corrected voltage control signal.

[0118] Compared with traditional reference sampling phase detectors, the gain-switching reference sampling phase detector provided in this application improves the phase detection gain, effectively improves in-band phase noise, and reduces the chip area occupied by the loop filter.

[0119] In summary, the embodiments of this application provide a phase-locked loop (PLL). First, since the gain-switching reference sampling phase detector proposed in this application is based on the existing traditional reference sampling phase detector PLL, it can ensure that the capture range of the gain-switching reference sampling phase detector proposed in this application is [-π / 2, π / 2]. Second, the gain controller uses the branch voltages output by the first branch unit and the second branch unit to determine the error voltage V corresponding to the phase error between the reference signal input to the current PLL and the voltage-controlled signal output by the voltage-controlled oscillator. ε With the preset threshold voltage V LIM The magnitude of the error voltage V is used to achieve automatic switching between the two operating modes; if the error voltage V ε Less than the preset threshold voltage V LIM The gain controller generates an enable signal to put the automatic gain switching reference sampling phase detector into gain multiplication mode. The gain controller then transmits the generated enable signal to the clock generator, which generates a clock control signal based on the enable signal. The clock control signal is then applied to the first and second branch units through the output of the clock generator to control the automatic gain switching reference sampling phase detector to be in gain multiplication mode, achieving a gain increase of M times. In this way, the adaptive gain control reference sampling phase detector provided in this application breaks the trade-off between phase detection gain and capture range in the three existing schemes. That is, while maintaining the capture range of [-π / 2, π / 2] of the traditional reference sampling phase detector, the phase detection gain is increased by M times to effectively suppress in-band noise caused by charge pump and reduce the area occupied by capacitors in the loop filter, thereby realizing a type II structure reference sampling phase detector phase-locked loop with low phase noise, low jitter, and low spurious emissions.

[0120] The following are several specific embodiments. Figure 1 The circuit structure of the adaptive gain control reference sampling phase detector will be explained in detail.

[0121] Optionally, refer to Figure 4 As shown, the first branch unit 108 includes: a first set of switches S SP1 Second group of switches S BS1The third group of switches S CM1 First capacitor C M1 Second capacitor C S1 Third capacitor C S2 Fourth capacitor C S3 Fifth capacitor C S4 First control switch S HD1 and the first holding capacitor C H1 .

[0122] In this embodiment, the second capacitor C S1 Third capacitor C S2 Fourth capacitor C S3 Fifth capacitor C S4 It can be called a sampling capacitor, used to detect phase errors. Corresponding error voltage V ε Sampling is performed on the second capacitor C. S1 Third capacitor C S2 Fourth capacitor C S3 Fifth capacitor C S4 The number is not limited to 4; it can also be 6, 8, etc.

[0123] First group of switches S SP1 This can be called a sampling switch, the third set of switches S CM1 It can be called a common-mode switch, used to connect a common-mode signal V. CM .

[0124] Among them, the first group of switches S SP1 The first terminal is used to connect to a positive sinusoidal reference signal V. REF+ .

[0125] Second group of switches S BS1 The first terminal and the first set of switches S SP1 The second end is connected to the second set of switches S. BS1 The second terminal and the third set of switches S CM1 The first end is connected, and the third set of switches S CM1 The second terminal is used to connect the common-mode signal V. CM .

[0126] First capacitor C M1 The first terminal serves as the first output terminal of the first branch unit 108, and the first capacitor C M1 The first terminal and the first set of switches S SP1 The second terminal is connected to the first capacitor C. M1 The second terminal is used to connect the common-mode signal V. CM ;

[0127] Second capacitor C S1 The first terminal and the second set of switches S BS1The first terminal is connected to the second capacitor C. S1 The second terminal is used to connect the common-mode signal V. CM ;

[0128] Third capacitor C S2 The first terminal and the second set of switches S BS1 The first terminal is connected to the third capacitor C. S2 The second terminal and the third set of switches S CM1 The first end is connected;

[0129] Fourth capacitor C S3 The first terminal and the second set of switches S BS1 The first terminal is connected to the fourth capacitor C. S3 The second terminal and the third set of switches S CM1 The first end is connected;

[0130] Fifth capacitor C S4 The first terminal and the first set of switches S SP1 The second end and the first control switch S HD1 The first terminal is connected to the fifth capacitor C. S4 The second terminal and the third set of switches S CM1 The first end is connected.

[0131] First control switch S HD1 The second terminal is connected to the first holding capacitor C H1 The first end and the transconductor g m The input terminal is connected, and the first holding capacitor C is... H1 The second end is grounded.

[0132] Optionally, the first set of switches S SP1 Including: first switch 1, second switch 2, third switch 3, fourth switch 4, and fifth switch 5;

[0133] The first terminals of the first switch 1, the second switch 2, the third switch 3, the fourth switch 4, and the fifth switch 5 are respectively used to connect to a positive sinusoidal reference signal V. REF+ .

[0134] The second terminal of the first switch 1 is connected to the first capacitor C M1 The first terminal is connected, and the second terminal of the second switch 2 is connected to the second capacitor C. S1 The first terminal is connected, and the second terminal of the third switch 3 is connected to the third capacitor C. S2 The first terminal is connected, and the second terminal of the fourth switch 4 is connected to the fourth capacitor C. S3 The first terminal is connected, and the second terminal of the fifth switch 5 is connected to the fifth capacitor C. S4 The first end is connected.

[0135] Among them, the first capacitor C M1 First terminal, second capacitor C S1 The first terminal and the third capacitor C S2 The first terminal, the fourth capacitor C S3 The first terminal is the fifth capacitor C. S4 The first end refers to the capacitor C. M1 The upper plate, the first capacitor C M1 The second terminal, the second capacitor C S1 The second terminal and the third capacitor C S2 The second terminal, the fourth capacitor C S3 The second terminal is the fifth capacitor C. S4 The second end refers to the lower plate of each capacitor.

[0136] Optionally, the second set of switches S BS1 Including: the sixth switch 6, the seventh switch 7, and the eighth switch 8;

[0137] The first terminal of the sixth switch 6 is connected to the second capacitor C S1 The first terminal is connected, and the second terminal of the sixth switch 6 is connected to the third capacitor C. S2 The second terminal is connected, and the first terminal of the seventh switch 7 is connected to the third capacitor C. S2 The first terminal is connected, and the second terminal of the seventh switch 7 is connected to the fourth capacitor C. S3 The second terminal is connected, and the first terminal of the eighth switch 8 is connected to the fourth capacitor C. S3 The first terminal is connected, and the second terminal of the eighth switch 8 is connected to the fifth capacitor C. S4 The second end is connected.

[0138] It should be noted that the first end of the sixth switch 6 is also connected to the second end of the second switch 2, the first end of the seventh switch 7 is also connected to the second end of the third switch 3, and the first end of the eighth switch 8 is also connected to the second end of the fourth switch 4.

[0139] Optionally, the third set of switches S CM1 Including: the ninth switch 9, the tenth switch 10, and the eleventh switch 11;

[0140] The first terminal of the ninth switch 9 is connected to the third capacitor C. S2 The second terminal is connected, and the first terminal of the tenth switch 10 is connected to the fourth capacitor C. S3 The second terminal is connected, and the first terminal of the eleventh switch 11 is connected to the fifth capacitor C. S4 The second end is connected;

[0141] The second terminals of the ninth switch 9, the tenth switch 10, and the eleventh switch 11 are respectively used to connect the common-mode signal V. CM .

[0142] The specific structure of the second branch unit will be described below through several embodiments.

[0143] The second branch unit is completely symmetrical to the first branch unit, and the circuit structure and working principle are the same.

[0144] Optionally, continue to refer to Figure 4 As shown, the second branch unit 109 includes: a fourth group of switches S SP2 Fifth group of switches S BS2 Sixth group switch S CM2 The sixth capacitor C M2 Seventh capacitor C S5 Eighth capacitor C S6 Ninth capacitor C S7 The tenth capacitor C S8 Second control switch S HD2 and the second holding capacitor C H2 ;

[0145] Fourth group of switches S SP2 The first terminal is used to connect to a negative sinusoidal reference signal V. REF- ;

[0146] Fifth group of switches S BS2 The first terminal and the fourth group of switches S SP2 The second end is connected to the fifth group of switches S. BS2 The second terminal and the sixth group of switches S CM2 The first end is connected, and the sixth group of switches S CM2 The second terminal is used to connect the common-mode signal V. CM ;

[0147] Sixth capacitor S CM2 The first terminal serves as the first output terminal of the second branch unit, and the sixth capacitor C M2 The first terminal and the fourth group of switches S SP2 The second terminal is connected to the sixth capacitor C. M2 The second terminal is used to connect the common-mode signal V. CM ;

[0148] Seventh capacitor C S5 The first terminal and the fifth group of switches S BS2 The first terminal is connected to the seventh capacitor C. S5 The second terminal is used to connect the common-mode signal V. CM ;

[0149] Eighth capacitor C S6 The first terminal and the fifth group of switches S BS2 The first terminal is connected to the eighth capacitor C. S6 The second terminal and the sixth group of switches S CM2 The first end is connected;

[0150] Ninth capacitor C S7 The first terminal and the fifth group of switches S BS2 The first terminal is connected to the ninth capacitor C. S7 The second end is connected to the first end of the sixth group of switches;

[0151] Tenth capacitor C S8 The first terminal and the second terminal of the fourth group of switches and the second control switch S HD2 The first terminal is connected to the tenth capacitor C. S8 The second end is connected to the first end of the sixth group of switches;

[0152] Second control switch S HD2 The second terminal is connected to the second holding capacitor C H2 The first end and the transconductor g m The input terminal is connected, and the second holding capacitor C is... H2 The second end is grounded.

[0153] Optionally, continue to refer to Figure 4 As shown, the fourth group of switches S SP2 Including: the twelfth switch 12, the thirteenth switch 13, the fourteenth switch 14, the fifteenth switch 15, and the sixteenth switch 16;

[0154] The first terminals of the twelfth switch 12, the thirteenth switch 13, the fourteenth switch 14, the fifteenth switch 15, and the sixteenth switch 16 are respectively used to connect to the negative sinusoidal reference signal V. REF- ;

[0155] The second terminal of the twelfth switch 12 is connected to the sixth capacitor C. M2 The first terminal is connected, and the second terminal of the thirteenth switch 13 is connected to the seventh capacitor C. S5 The first terminal is connected, and the second terminal of the fourteenth switch 14 is connected to the eighth capacitor C. S6 The first terminal is connected, and the second terminal of the fifteenth switch 15 is connected to the ninth capacitor C. S7 The first terminal is connected, and the second terminal of the sixteenth switch 16 is connected to the tenth capacitor C. S8 The first end is connected.

[0156] Optionally, continue to refer to Figure 4 As shown, the fifth group of switches S BS2 Including: the seventeenth switch 17, the eighteenth switch 18, and the nineteenth switch 19;

[0157] The first terminal of the seventeenth switch 17 is connected to the seventh capacitor C. S5 The first terminal is connected, and the second terminal of the seventeenth switch 17 is connected to the eighth capacitor C. S6The second terminal is connected, and the first terminal of the eighteenth switch 18 is connected to the eighth capacitor C. S6 The first terminal is connected, and the second terminal of the eighteenth switch 18 is connected to the ninth capacitor C. S7 The second terminal is connected, and the first terminal of the nineteenth switch 19 is connected to the ninth capacitor C. S7 The first terminal is connected, and the second terminal of the nineteenth switch 19 is connected to the tenth capacitor C. S8 The second end is connected.

[0158] Optionally, continue to refer to Figure 4 As shown, the sixth group of switches S CM2 Including: the twentieth switch 20, the twenty-first switch 21, and the twenty-second switch 22;

[0159] The first terminal of the twentieth switch 20 is connected to the eighth capacitor C. S6 The second terminal is connected, and the first terminal of the twenty-first switch 21 is connected to the ninth capacitor C. S7 The second terminal is connected, and the first terminal of the twenty-second switch 22 is connected to the tenth capacitor C. S8 The second end is connected;

[0160] The second terminals of the twentieth switch 20, the twenty-first switch 21, and the twenty-second switch 22 are respectively used to connect the common-mode signal V. CM .

[0161] Optionally, continue to refer to Figure 4 As shown, the gain controller includes: a first comparison unit, a second comparison unit, and a first AND gate; Figure 4 Only the circuit structure of the first comparison unit is shown in the diagram. The second comparison unit is not shown. The circuit structure and working principle of the second comparison unit are the same as those of the first comparison unit.

[0162] The first comparison unit and the second comparison unit respectively include: a first dynamic comparator, a second dynamic comparator, and a second AND gate;

[0163] The first input terminal of the first dynamic comparator and the first input terminal of the second dynamic comparator of the first comparison unit are respectively connected to the first capacitor C. M1 The first terminal is connected, and the output terminal of the first dynamic comparator and the output terminal of the second dynamic comparator of the first comparison unit are respectively connected to the input terminal of the second AND gate of the first comparison unit. The output terminal of the second AND gate of the first comparison unit is connected to the first input terminal of the first AND gate.

[0164] Furthermore, the first input terminal of the first dynamic comparator of the first comparison unit is used to receive the sum of the common-mode signal and a preset threshold voltage (i.e., V). CM +V LIMThe first input terminal of the second dynamic comparator of the first comparison unit is used to receive the difference signal between the common-mode signal and the preset threshold voltage (i.e., V). CM -V LIM ).

[0165] The first input terminal of the first dynamic comparator and the first input terminal of the second dynamic comparator of the second comparison unit are respectively connected to the sixth capacitor C. M2 The first end is connected, the output of the first dynamic comparator and the output of the second dynamic comparator of the second comparison unit are respectively connected to the input of the second AND gate of the second comparison unit, and the output of the second AND gate of the second comparison unit is connected to the second input of the first AND gate;

[0166] Similarly, the second input terminal of the first dynamic comparator of the second comparison unit is used to receive the sum of the common-mode signal and the preset threshold voltage (i.e., V). CM +V LIM The second input terminal of the second dynamic comparator of the second comparison unit is used to receive the difference signal between the common-mode signal and the preset threshold voltage (i.e., V). CM -V LIM ).

[0167] The output of the first AND gate is connected to the second input of the clock generator.

[0168] It is worth noting that the branch voltage Vs+ output by the first branch unit and the branch voltage Vs- output by the second branch unit both satisfy the following formula (5):

[0169] |Vs+-V CM |=|Vs--V CM |=V ε (5)

[0170] Therefore, the first dynamic comparator and the second dynamic comparator in the first comparison unit can be used to determine whether the branch voltage Vs+ output from the first output terminal of the first branch unit is within the range of V. CM -V LIM <Vs+<V CM +V LIM Within the range. Similarly, the first dynamic comparator and the second dynamic comparator in the second comparison unit can be used to determine whether the branch voltage Vs- output from the first output terminal of the second branch unit is within the range of V. CM -V LIM <Vs-<V CM +V LIM Within the specified range, if the condition is met, the output of the first AND gate will be 1.

[0171] In this embodiment, a first comparator unit and a second comparator unit are used to compare the sampling voltage output by the first branch unit and the sampling voltage output by the second branch unit with a preset threshold voltage, so that the gain automatic switching reference sampling phase detector can seamlessly and automatically switch between normal mode and gain multiplication mode.

[0172] Optionally, continue to refer to Figure 4 As shown, the first output terminal of the clock generator is connected to the clock terminals of the first dynamic comparator and the second dynamic comparator in the first comparison unit, and the clock terminals of the first dynamic comparator and the second dynamic comparator in the second comparison unit, respectively, for outputting clock signal CK to the clock terminals of the first dynamic comparator and the second dynamic comparator in the first comparison unit, and the clock terminals of the first dynamic comparator and the second dynamic comparator in the second comparison unit. CMP .

[0173] The second output of the clock generator is connected to the first set of switches S SP1 The third terminal of each switch and the fourth group of switches S SP2 The third terminal of each switch in the circuit is connected to the first group of switches S. SP1 The switches in the middle, and the fourth group of switches S SP2 Each switch in the circuit outputs the first clock control signal CK. SP ;

[0174] The third output terminal of the clock generator and the third set of switches S CM1 The third terminal of each switch and the sixth group of switches S CM2 The third terminal of each switch in the circuit is connected to the third group of switches S. CM1 The switches in the middle, and the sixth group of switches S CM2 Each switch in the circuit outputs a second clock control signal CK. CM ;

[0175] The fourth output of the clock generator and the second set of switches S BS1 The third terminal of each switch and the fifth group of switches S BS2 The third terminal of each switch in the circuit is connected to the third group of switches S. BS1 Each switch in the middle, and the fifth group of switches S BS2 Each switch outputs a third clock control signal CK. BS ;

[0176] The fifth output terminal of the clock generator is connected to the first control switch S. HD1 The third terminal and the second control switch S HD2 The third terminal is connected for connecting to the first control switch S. HD1 and the second control switch S HD2Output the fourth clock control signal CK HD .

[0177] In this embodiment, multiple clock control signals generated by the clock generator can be applied to the switches in the first branch unit and the second branch unit to control the gain automatic switching reference sampling phase detector to be in a certain working mode.

[0178] The following will combine the above Figures 1-4 The circuit structure of the phase-locked loop shown illustrates the working principle of the gain-switching reference sampling phase detector provided in this application.

[0179] For ease of explanation, we will only use the first branch unit of the differential sampling module in the gain-switching reference sampling phase detector as an example.

[0180] In this embodiment, as Figures 5-8 As shown, the working principle of the automatic gain switching reference sampling phase detector can be divided into three stages, as follows:

[0181] (1) The first stage is the tracking mode, such as Figure 5 As shown.

[0182] Among them, such as Figure 5 As shown, in the first branch unit, the first group of switches S SP1 and the third switch group S CM1 All switches are closed, and the rest are open. The first capacitor C M1 Second capacitor C S1 Third capacitor C S2 Fourth capacitor C S3 Fifth capacitor C S4 The lower plate of each capacitor is connected to the common-mode voltage V of a sinusoidal reference signal. CM The first capacitor C M1 Second capacitor C S1 Third capacitor C S2 Fourth capacitor C S3 Fifth capacitor C S4 The voltage on the upper plate of each capacitor tracks the input sinusoidal signal V. REF+ The changes.

[0183] (2) The second stage is the sampling and comparison mode, such as Figure 6 As shown.

[0184] like Figure 6 As shown, when the clock generator controls the first set of switches S SP1 Clock control signal CK SP When the falling edge arrives, the first set of switches S SP1 When disconnected, phase error Corresponding error voltage V ε The first capacitor C was sampled. M Second capacitor C S1 Third capacitor C S2 Fourth capacitor C S3 Fifth capacitor C S4 The upper plates of each capacitor.

[0185] Then, the control clock signal CK of the first comparator unit CMP The arrival of the effective level affects the error voltage V. ε and limiting voltage V LIM Comparisons were made to determine the working model for the third phase.

[0186] (1) If V ε <V LIM The enable signal EN generated by the gain controller BS =1, meaning the third stage operates in gain multiplication mode. (Reference) Figure 7 As shown, the third switch group S CM1 All switches in the middle are in the open state, and switch S in the second switch group is in the open state. BS1 Each switch and the first control switch S HD Both are in the closed state, the second capacitor C S1 Third capacitor C S2 Fourth capacitor C S3 Fifth capacitor C S4 The four sampling capacitors are connected end-to-end to control the first holding capacitor C. H Charging is performed because C S ≈4.10C H This makes the first holding capacitor C H The voltage was approximately charged to 4V. ε This achieves a fourfold increase in gain;

[0187] (2) If V ε >V LIM The enable signal EN generated by the gain controller BS =0, meaning the third stage of the work is in normal mode. For example... Figure 8 As shown, only the third switch group S CM1 Each switch and the first control switch S HD The circuit is in the closed state, and all other switches are in the open state. At this time, there is only one sampling capacitor (i.e., the fifth capacitor C). S4 For the first holding capacitor C H Charging is performed because C S ≈4.10C H First holding capacitor C H The voltage is approximately charged to V. εThis means that the gain of the gain-switching reference sampling phase detector is the same as that of the conventional reference sampling phase detector, in order to ensure the reliability of transistor operation.

[0188] In this embodiment, the two operating modes of the third stage are enabled by the EN signal. BS Automatic switching is achieved under control, and due to the adoption of a Type II structure, the phase error is close to zero when the loop is locked. Therefore, during locking, the phase-locked loop operates in gain-multiplying mode, effectively improving in-band phase noise.

[0189] Optionally, in order to achieve the above Figures 5-8 The timing relationships between various control clocks are determined to ensure the orderly and correct operation of the automatic gain switching reference sampling phase detector. The designed multi-mode divider and clock generation circuit are as follows: Figure 9 As shown.

[0190] Four asynchronous frequency dividers (divided by 2 / 3) are connected in series to achieve a continuous frequency division ratio of 16-31. The first stage is a high-speed true single-phase clock circuit.

[0191] The signal F of the multi-mode frequency divider O2 First, the output signal VCO of the voltage-controlled oscillator is sampled to generate signal F. O2 _RT, then the falling and rising edges of this signal alternately drive the trigger to sample and delay the signal MOD4 of the multi-mode divider to generate a multi-phase signal D1-D separated by two VCO cycles. 10 .

[0192] These multiphase signals are combined using simple logic gates to generate the required clock control signal. Before driving the switches in the corresponding gain-switching reference sampling phase detector, the clock control signal is resampled by the VCO to eliminate accumulated jitter generated along the path. This is due to the DFF flip-flop... A Clock port to flip-flop DFF B The latency of the data port is less than one VCO cycle, so there is no metastability problem.

[0193] Optionally, the Type II reference sampling phase-locked loop chip proposed in this application is manufactured using a CMOS 65nm process, and experiments have shown that its effective chip area is 0.25mm². 2 Due to the multiplication of the phase detector gain, the area of ​​the loop filter is reduced to only about 10% of the total effective area.

[0194] The phase-locked loop provided in this application has a wide operating frequency range, low in-band noise, and low jitter characteristics.

[0195] Optionally, this application also provides a phase-locked loop system, including the phase-locked loop chip, off-chip crystal oscillator, and off-chip balun provided in the above embodiments;

[0196] refer to Figure 10 As shown, the output of the external crystal oscillator is connected to the input of the external balun; the first output of the external balun is connected to the first input of the first branch unit in the phase-locked loop chip; and the second output of the external balun is connected to the first input of the second branch unit in the phase-locked loop chip.

[0197] The external balun is used to convert the sinusoidal signal generated by the external crystal oscillator into a positive sinusoidal signal and a negative sinusoidal signal. The positive sinusoidal signal is input to the first branch unit of the phase-locked loop chip through the first output terminal of the external balun, and the negative sinusoidal signal is input to the second branch unit of the phase-locked loop chip through the second output terminal of the external balun. The second input terminal of the external balun is used to connect the common-mode signal of the sinusoidal signal generated by the crystal oscillator element.

[0198] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A phase-locked loop chip, characterized by, The application relates to a gain auto-switching reference sampling phase detector, which comprises a voltage-controlled oscillator, a multi-mode frequency divider, a clock generator, a gain auto-switching reference sampling phase detector, a control voltage generating module, wherein the gain auto-switching reference sampling phase detector comprises a differential sampling module and a gain controller, the differential sampling module comprises a first branch unit and a second branch unit which are symmetrical to each other. An output end of the voltage-controlled oscillator is connected with an input end of the multi-mode frequency divider, and an output end of the multi-mode frequency divider is connected with a first input end of the clock generator. A first input end of the gain controller is connected with a first output end of the first branch unit, a second input end of the gain controller is connected with a first output end of the second branch unit, and an output end of the gain controller is connected with a second input end of the clock generator. A first input end of the first branch unit is used for connecting a forward sine reference signal, a second input end of the first branch unit is used for connecting a common-mode signal of the sine reference signal, and a second output end of the first branch unit is connected with an input end of the control voltage generating module. A first input end of the second branch unit is used for connecting a negative sine reference signal, a second input end of the second branch unit is used for connecting the common-mode signal, and a second output end of the second branch unit is connected with an input end of the control voltage generating module. The gain controller is used for generating an enable signal according to branch voltages output by the first branch unit and the second branch unit, and sending the enable signal to the clock generator through the output end of the gain controller. Output ends of the clock generator are connected with the first branch unit and the second branch unit respectively. The clock generator is used for generating a clock control signal according to the enable signal, and applying the clock control signal to the first branch unit and the second branch unit through the output end of the clock generator, so as to control the gain auto-switching reference sampling phase detector to be in a target working mode, wherein in the target working mode, a second output end of the first branch unit outputs a first holding voltage, a second output end of the second branch unit outputs a second holding voltage, so that the control voltage generating module controls a control voltage output from an output end of the control voltage generating module according to the first holding voltage and the second holding voltage. An output end of the control voltage generating module is connected with an input end of the voltage-controlled oscillator, and the control voltage is output to the voltage-controlled oscillator, so that the voltage-controlled oscillator performs voltage-controlled signal correction according to the control voltage and outputs a corrected voltage-controlled signal. The first branch unit comprises a first group of switches, a second group of switches, a third group of switches, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first control switch and a first holding capacitor.

2. The phase-locked loop chip of claim 1, wherein, A first end of the first group of switches is used for connecting the forward sine reference signal. ​ The first end of the second group of switches is connected with the second end of the first group of switches, the second end of the second group of switches is connected with the first end of the third group of switches, and the second end of the third group of switches is used for connecting the common mode signal; The first end of the first capacitor is used as the first output end of the first branch unit, the first end of the first capacitor is connected with the second end of the first group of switches, and the second end of the first capacitor is used for connecting the common mode signal; The first end of the second capacitor is connected with the first end of the second group of switches, and the second end of the second capacitor is used for connecting the common mode signal; The first end of the third capacitor is connected with the first end of the second group of switches, and the second end of the third capacitor is connected with the first end of the third group of switches; The first end of the fourth capacitor is connected with the first end of the second group of switches, and the second end of the fourth capacitor is connected with the first end of the third group of switches; The first end of the fifth capacitor is connected with the second end of the first group of switches and the first end of the first control switch, and the second end of the fifth capacitor is connected with the first end of the third group of switches; The second end of the first control switch is connected with the first end of the first holding capacitor and the input end of the control voltage generation module, and the second end of the first holding capacitor is grounded.

3. The phase-locked loop chip of claim 2, wherein, The first group of switches comprises a first switch, a second switch, a third switch, a fourth switch and a fifth switch; The first end of the first switch, the first end of the second switch, the first end of the third switch, the first end of the fourth switch and the first end of the fifth switch are respectively used for connecting the positive sine reference signal; The second end of the first switch is connected with the first end of the first capacitor, the second end of the second switch is connected with the first end of the second capacitor, the second end of the third switch is connected with the first end of the third capacitor, the second end of the fourth switch is connected with the first end of the fourth capacitor, and the second end of the fifth switch is connected with the first end of the fifth capacitor.

4. The phase-locked loop chip of claim 3, wherein, The second group of switches comprises a sixth switch, a seventh switch and an eighth switch; The first end of the sixth switch is connected with the first end of the second capacitor, the second end of the sixth switch is connected with the second end of the third capacitor, the first end of the seventh switch is connected with the first end of the third capacitor, the second end of the seventh switch is connected with the second end of the fourth capacitor, the first end of the eighth switch is connected with the first end of the fourth capacitor, and the second end of the eighth switch is connected with the second end of the fifth capacitor.

5. The phase-locked loop chip of claim 4, wherein, The third group of switches comprises a ninth switch, a tenth switch and an eleventh switch; The first end of the ninth switch is connected with the second end of the third capacitor, the first end of the tenth switch is connected with the second end of the fourth capacitor, and the first end of the eleventh switch is connected with the second end of the fifth capacitor; The second end of the ninth switch, the second end of the tenth switch and the second end of the eleventh switch are respectively used for connecting the common mode signal.

6. The phase-locked loop chip of claim 5, wherein, The second branch unit comprises a fourth group of switches, a fifth group of switches, a sixth group of switches, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a second control switch and a second holding capacitor; The first end of the fourth group of switches is used for accessing the negative sine reference signal; The first end of the fifth group of switches is connected with the second end of the fourth group of switches, the second end of the fifth group of switches is connected with the first end of the sixth group of switches, and the second end of the sixth group of switches is used for accessing the common mode signal; The first end of the sixth capacitor is used as the first output end of the second branch unit, the first end of the sixth capacitor is connected with the second end of the fourth group of switches, and the second end of the sixth capacitor is used for accessing the common mode signal; The first end of the seventh capacitor is connected with the first end of the fifth group of switches, and the second end of the seventh capacitor is used for accessing the common mode signal; The first end of the eighth capacitor is connected with the first end of the fifth group of switches, and the second end of the eighth capacitor is connected with the first end of the sixth group of switches; The first end of the ninth capacitor is connected with the first end of the fifth group of switches, and the second end of the ninth capacitor is connected with the first end of the sixth group of switches; The first end of the tenth capacitor is connected with the second end of the fourth group of switches and the first end of the second control switch, and the second end of the tenth capacitor is connected with the first end of the sixth group of switches; The second end of the second control switch is connected with the first end of the second holding capacitor and the input end of the control voltage generation module, and the second end of the second holding capacitor is grounded.

7. The phase-locked loop chip of claim 6, wherein, The fourth group of switches comprises a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch and a sixteenth switch; The first end of the twelfth switch, the first end of the thirteenth switch, the first end of the fourteenth switch, the first end of the fifteenth switch and the first end of the sixteenth switch are respectively used for accessing the negative sine reference signal; The second end of the twelfth switch is connected with the first end of the sixth capacitor, the second end of the thirteenth switch is connected with the first end of the seventh capacitor, the second end of the fourteenth switch is connected with the first end of the eighth capacitor, the second end of the fifteenth switch is connected with the first end of the ninth capacitor, and the second end of the sixteenth switch is connected with the first end of the tenth capacitor.

8. The phase-locked loop chip of claim 7, wherein, The fifth group of switches comprises a seventeenth switch, an eighteenth switch and a nineteenth switch; The first end of the seventeenth switch is connected with the first end of the seventh capacitor, the second end of the seventeenth switch is connected with the second end of the eighth capacitor, the first end of the eighteenth switch is connected with the first end of the eighth capacitor, the second end of the eighteenth switch is connected with the second end of the ninth capacitor, the first end of the nineteenth switch is connected with the first end of the ninth capacitor, and the second end of the nineteenth switch is connected with the second end of the tenth capacitor.

9. The phase-locked loop chip of claim 8, wherein, The sixth group of switches comprises a twentieth switch, a twenty-first switch and a twenty-second switch; A first end of the twentieth switch is connected with a second end of the eighth capacitor, a first end of the twenty-first switch is connected with a second end of the ninth capacitor, and a first end of the twenty-second switch is connected with a second end of the tenth capacitor; A second end of the twentieth switch, a second end of the twenty-first switch, and a second end of the twenty-second switch are respectively used for accessing the common-mode signal.

10. The phase-locked loop chip of claim 9, wherein, The gain controller comprises a first comparison unit, a second comparison unit, and a first AND gate; The first comparison unit and the second comparison unit each comprise a first dynamic comparator, a second dynamic comparator, and a second AND gate; First input ends of the first dynamic comparator and the second dynamic comparator of the first comparison unit are connected with a first end of the first capacitor, output ends of the first dynamic comparator and the second dynamic comparator of the first comparison unit are connected with input ends of the second AND gate of the first comparison unit, and an output end of the second AND gate of the first comparison unit is connected with a first input end of the first AND gate; First input ends of the first dynamic comparator and the second dynamic comparator of the second comparison unit are connected with a first end of the sixth capacitor, output ends of the first dynamic comparator and the second dynamic comparator of the second comparison unit are connected with input ends of the second AND gate of the second comparison unit, and an output end of the second AND gate of the second comparison unit is connected with a second input end of the first AND gate; An output end of the first AND gate is connected with a second input end of the clock generator.

11. The phase-locked loop chip of claim 10, wherein, A first output end of the clock generator is connected with clock ends of the dynamic comparators in the first comparison unit and the dynamic comparators in the second comparison unit, for outputting clock signals to the clock ends of the dynamic comparators in the first comparison unit and the dynamic comparators in the second comparison unit; A second output end of the clock generator is connected with third ends of the switches in the first group of switches, third ends of the switches in the fourth group of switches, for outputting first clock control signals to the switches in the first group of switches and the switches in the fourth group of switches; A third output end of the clock generator is connected with third ends of the switches in the third group of switches and third ends of the switches in the sixth group of switches, for outputting second clock control signals to the switches in the third group of switches and the switches in the sixth group of switches; A fourth output end of the clock generator is connected with third ends of the switches in the second group of switches and third ends of the switches in the fifth group of switches, for outputting third clock control signals to the switches in the second group of switches and the switches in the fifth group of switches; A fifth output end of the clock generator is connected with third ends of the first control switch and the second control switch, for outputting fourth clock control signals to the first control switch and the second control switch.

12. A phase-locked loop system, characterized by The system comprises the phase-locked loop chip, the off-chip crystal oscillator and the off-chip balun as claimed in any one of claims 1-11; The output end of the off-chip crystal oscillator is connected with the first input end of the off-chip balun, the first output end of the off-chip balun is connected with the first input end of the first branch unit in the phase-locked loop chip, and the second output end of the off-chip balun is connected with the first input end of the second branch unit in the phase-locked loop chip; The off-chip balun is used for converting the sinusoidal signal generated by the off-chip crystal oscillator into a positive sinusoidal signal and a negative sinusoidal signal, inputting the positive sinusoidal signal into the first branch unit in the phase-locked loop chip through the first output end of the off-chip balun, and inputting the negative sinusoidal signal into the second branch unit in the phase-locked loop chip through the second output end of the off-chip balun; The second input end of the off-chip balun is used for accessing the common-mode signal of the sinusoidal signal.

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