Comparator

Abstract

The present application provides a comparator, comprising: an input circuit having an output terminal for generating a differential signal based on an input signal and a reference signal during a sampling phase; a positive feedback circuit connected to the output terminal of the input circuit for accelerating the difference between the differential signals; and an output circuit connected to the output terminal of the input circuit for amplifying and latching the voltage signal at the output terminal of the input circuit during a regeneration phase to output a comparison result. This solution uses a positive feedback circuit to accelerate the difference between the differential signals. When the reference signal is of an inappropriate size, the sampling phase can be shortened, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

Description

Technical Field

[0001] The present application relates to an integrated circuit, and in particular to a comparator. Background Art

[0002] Nowadays, people's demand for mobile devices such as mobile phones, tablets and various wearable accessories has greatly increased, which has greatly enriched our daily life and work.

[0003] However, limited battery life places higher demands on the power consumption of various components in mobile devices. Dynamic Random Access Memory (DRAM) is an essential component in mobile devices, and therefore, DRAM urgently needs to achieve lower operating voltages and lower energy consumption. Among them, comparators are key components for reading and writing DRAM data. The operating voltage and energy consumption of existing comparators no longer meet current usage requirements. Summary of the Invention

[0004] The present application provides a comparator, aiming to improve the response rate of the comparator and reduce the power consumption of the comparator.

[0005] The present application provides a comparator, comprising:

[0006] an input circuit having an output terminal for generating a differential signal according to the input signal and a reference signal during a sampling phase;

[0007] a positive feedback circuit connected to the output terminal of the input circuit and configured to accelerate the difference between the differential signals;

[0008] The output circuit is connected to the output end of the input circuit and is used to amplify and latch the voltage signal of the output end of the input circuit in the regeneration phase to output a comparison result.

[0009] Optionally, the input circuit has two output terminals, and the positive feedback circuit includes:

[0010] a first feedback unit, a control terminal of which is connected to the first output terminal of the input circuit, and a first terminal of which is connected to the second output terminal of the input circuit;

[0011] The second feedback unit has a control end connected to the second output end of the input circuit, and a first end connected to the first output end of the input circuit.

[0012] Optionally, the first feedback unit includes: a first feedback transistor, a control terminal of which is the input terminal of the first feedback unit, and a first terminal of which is the output terminal of the first feedback unit;

[0013] The second feedback unit includes: a second feedback transistor, a control end of which is the input end of the second feedback unit, and a first end of which is the output end of the second feedback unit.

[0014] Optionally, the input circuit includes:

[0015] a first input transistor, whose control terminal is used to receive an input signal, whose first terminal serves as a first output terminal of the input circuit, and whose second terminal is connected to the second terminal of the first feedback transistor;

[0016] a second input transistor, whose control terminal is used to receive the reference signal, whose first terminal serves as the second output terminal of the input circuit, and whose second terminal is connected to the second terminal of the second feedback transistor;

[0017] The third input transistor has a control end for receiving a clock signal, a first end connected to the second end of the first input transistor, the second end of the second input transistor, the second end of the first feedback transistor, and the second end of the second feedback transistor, and a second end connected to the ground end or the power supply end.

[0018] Optionally, the first feedback transistor, the second feedback transistor, the first input transistor, and the second input transistor are of the same type.

[0019] Optionally, when the first feedback transistor, the second feedback transistor, the first input transistor and the second input transistor are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal;

[0020] When the first feedback transistor, the second feedback transistor, the first input transistor and the second input transistor are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0021] Optionally, the comparator further includes:

[0022] The first reset circuit is connected between the first output terminal of the input circuit and the second output terminal of the input circuit, and is used for resetting the voltage of the first output terminal of the input circuit and the voltage of the second output terminal of the input circuit.

[0023] Optionally, the comparator further includes:

[0024] a second reset circuit connected to the first output terminal of the output circuit, for resetting the voltage of the first output terminal of the output circuit;

[0025] The third reset circuit is connected to the second output terminal of the output circuit and is used for resetting the voltage of the second output terminal of the output circuit.

[0026] Optionally, the first reset circuit includes:

[0027] a first clock-controlled transistor, a control terminal of which receives a clock signal and a second terminal of which is connected to a first output terminal of the input circuit;

[0028] The second clock-controlled transistor has a control end receiving a clock signal, a second end connected to the second output end of the input circuit, and a second end connected to the second end of the first clock-controlled transistor.

[0029] Optionally, the second reset circuit includes: a third clock-controlled transistor, a control terminal of which receives a clock signal, and a second terminal of which is connected to the first output terminal of the output circuit;

[0030] The third reset circuit includes: a fourth clock-controlled transistor, a control terminal of which receives a clock signal, and a second terminal of which is connected to the second output terminal of the output circuit.

[0031] Optionally, the first clock-controlled transistor, the second clock-controlled transistor, the third clock-controlled transistor and the fourth clock-controlled transistor are of the same type.

[0032] Optionally, the output circuit includes:

[0033] a first output transistor, a second terminal of which is a first input terminal of the output circuit;

[0034] a second output transistor, a second terminal of which is a second input terminal of the output circuit;

[0035] a third output transistor, a control end of which is connected to the control end of the first output transistor, and a control end of which is further connected to the second end of the fourth output transistor, the second end of the third output transistor serving as the first output end of the output circuit;

[0036] The fourth output transistor has a control end connected to the control end of the second output transistor and is also connected to the second end of the third output transistor. The second end of the fourth output transistor serves as the second output end of the output circuit.

[0037] Optionally, the first output transistor and the second output transistor are both N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal;

[0038] The third output transistor and the fourth output transistor are both P-type transistors, the first to fourth clock-controlled transistors are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0039] Optionally, the first input transistor and the second output transistor are both P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal;

[0040] The third output transistor and the fourth output transistor are both N-type transistors, the first to fourth clock-controlled transistors are all N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0041] Optionally, the first feedback transistor and the second feedback transistor have the same size, the first input transistor and the second input transistor have the same size, and the size of the first feedback transistor is smaller than half of the size of the first input transistor.

[0042] Optionally, the input circuit has two output terminals, and the positive feedback circuit includes at least one controllable positive feedback module; wherein each controllable positive feedback module includes:

[0043] a first feedback unit, a control end of which is connected to the first output end of the input circuit via a first switch, and a first end of which is connected to the second output end of the input circuit;

[0044] The second feedback unit has a control end connected to the second output end of the input circuit through a second switch, and a first end connected to the first output end of the input circuit.

[0045] Optionally, the first feedback unit includes: a first feedback transistor, a control terminal of which is the input terminal of the first feedback unit, and a first terminal of which is the output terminal of the first feedback unit;

[0046] The second feedback unit includes: a second feedback transistor, a control end of which is the input end of the second feedback unit, and a first end of which is the output end of the second feedback unit.

[0047] Optionally, the first switch includes a first transmission gate, the first transmission gate is controlled by a first enable signal, and the first enable signal is generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal;

[0048] The second switch includes a second transmission gate controlled by a second enable signal generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal.

[0049] Optionally, the control end of the first feedback unit is further connected to the ground end or the power end through a first zero switch; the control end of the second feedback unit is further connected to the ground end or the power end through a zeroth zero switch.

[0050] The present application provides a comparator, which includes an input circuit, an output circuit, and a positive feedback circuit. When a reference signal is not appropriately selected, it takes a relatively long time for the input signal and the reference signal to generate a differential signal at the output end of the input circuit. The input circuit generates a differential signal based on the input signal and the reference signal, and the positive feedback circuit accelerates the difference between the differential signals, shortens the time of the sampling phase, and reduces the delay time for the comparator to enter the regeneration phase. In the regeneration phase, the output circuit amplifies and latches the voltage signal at the output end of the input circuit and then outputs the comparison result, thereby improving the response rate of the comparator and reducing the power consumption of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0052] Figure 1 A specific circuit diagram of a comparator provided in this application;

[0053] Figure 2 The working timing diagram of the comparator provided in this application;

[0054] Figure 3 A structural block diagram of a comparator provided in this application;

[0055] Figure 4 Based on Figure 3 A specific circuit diagram of one of the provided comparators;

[0056] Figure 5 for Figure 4 The comparator shown shows the relationship between the input signal and the delay time of the regeneration stage when the reference signal is relatively small;

[0057] Figure 6 for Figure 4 The relationship between the input signal and power consumption of the comparator shown is when the reference signal is relatively small;

[0058] Figure 7 Based on Figure 3 A specific circuit diagram of another comparator provided;

[0059] Figure 8 for Figure 7 The relationship between the input signal and the regeneration phase delay time of the comparator shown when the reference signal is relatively large;

[0060] Figure 9 A structural block diagram of a comparator provided in this application;

[0061] Figure 10 Based on Figure 9A specific circuit diagram of one of the provided comparators;

[0062] Figure 11 for Figure 10 The specific circuit diagram of the controllable positive feedback module in the provided comparator;

[0063] Figure 12 Based on Figure 9 A specific circuit diagram of another comparator provided;

[0064] Figure 13 for Figure 12 The specific circuit diagram of the controllable positive feedback module in the provided comparator.

[0065] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0066] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0067] like Figure 1 As shown, the comparator includes an input circuit 101, an output circuit 102, and a reset circuit 103. The output end of the input circuit 101 is connected to the input end of the output circuit 102. The reset circuit 103 is also connected to the output circuit 102.

[0068] The input circuit 101 includes a transistor N1, a transistor N2, and a transistor N3. The transistor N1 and the transistor N2 constitute a differential transistor pair. The gate of the transistor N1 and the gate of the transistor N2 constitute a first input terminal IP and a second input terminal IN of the input circuit. The drain of the transistor N1 and the drain of the transistor N2 constitute two output terminals of the input circuit.

[0069] Output circuit 102 includes transistors P1, P2, N4, and N5. These four transistors form a cross-coupled transistor pair. The drains of transistors P1 and N4 form a first output terminal ON of output circuit 102, and the drains of transistors P2 and N5 form a second output terminal OP of output circuit 102. Reset circuit 103 includes transistors P3 and P4.

[0070] The working process of the comparator is divided into four stages: reset stage, sampling stage, regeneration stage and decision stage. Figure 2 describe Figure 1 The working process of the comparator shown is:

[0071] In the reset phase, that is, from time t0 to time t1, the clock signal is at a low level, transistor N3 is disconnected, the input circuit and the output circuit stop working, transistor P3 and transistor P4 are closed, and the reset circuit works, pulling the drain voltage of transistor N4 and the drain voltage of transistor N5 to a high level.

[0072] During the sampling phase, from time t1 to time t2, the clock signal is high, transistors P3 and P4 are disconnected, and the reset circuit stops operating. Transistor N3 is closed, and the input circuit collects the input signal through the first input terminal IP. The input circuit collects the reference signal through the second input terminal IN. The input signal pulls down the drain voltage of transistor N1, and the reference signal pulls down the drain voltage of transistor N2. The drain of transistor N1 pulls down the drain voltage of transistor N4, and the drain of transistor N2 pulls down the drain voltage of transistor N5. Because the input signal is higher than the reference signal, the input signal pulls up the drain voltage of transistor N1 at a faster rate, causing the drain voltage of transistor N4 to be lower than the drain voltage of transistor N5.

[0073] In the regeneration stage, that is, from time t2 to time t3, the drain voltage of transistor N4 and the drain voltage of transistor N5 reach the flip voltage, transistor P2 and transistor N4 are turned on, transistor P1 and transistor N5 are gradually disconnected, transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N5.

[0074] During the decision phase, that is, from time t3 to time t4, transistor P2 and transistor N4 are turned on, and transistor P1 and transistor N5 are turned off, continuing to pull up the drain voltage of transistor N5 and continuing to pull down the drain voltage of transistor N4. After pulling the drain of transistor N5 to a low level and the drain voltage of transistor N4 to a high level, the drain voltages of transistors N4 and N5 are maintained.

[0075] When the next working cycle comes, the clock signal becomes a low level, and the drain voltages of the transistors N4 and N5 are reset to a high level by the transistors P1 and P2.

[0076] However, when the reference signal is not properly selected, the time it takes for the input signal and the reference signal to generate a differential signal at the output of the input circuit is relatively long, which reduces the response rate of the comparator and increases the power consumption of the comparator. Figure 2In the comparator shown, when the reference signal is relatively small, transistors N1 and N2 need to be turned on for a longer time, causing the charging currents of nodes VP and VN to decrease. Transistors N1 and N2 pull transistors N5 and N4 to decrease in speed, resulting in a decrease in the response speed of the comparator and an increase in the power consumption of the comparator.

[0077] Figure 3 A structural block diagram of a comparator provided in this application is shown in FIG. Figure 3 As shown, the comparator includes an input circuit 101, an output circuit 102, and a positive feedback circuit 104. The input circuit 101 has an output terminal, the positive feedback circuit 104 is connected to the output terminal of the input circuit 101, and the output circuit 102 is connected to the output terminal of the input circuit 101.

[0078] Input circuit 101 is used to generate a differential signal based on the input signal and the reference signal during the sampling phase. The differential signal is a pair of voltage signals. Positive feedback circuit 104 is used to accelerate the difference between the differential signals. Input circuit 101 is also used to output the accelerated differential signal. Output circuit 102 is used to amplify and latch the voltage signal at the output of input circuit 101 during the regeneration phase. The voltage signal at the output of input circuit 101 is amplified and latched and then output as a comparison result.

[0079] When the reference signal is not properly selected, the response time of input circuit 101 is prolonged, meaning that it takes longer for input circuit 101 to present a differential signal at its output. The positive feedback signal accelerates the difference between the differential signals through the positive feedback mechanism, thereby shortening the time it takes for input circuit 101 to present a differential signal at its output. This shortens the time the comparator is in the sampling phase, thereby increasing the comparator's response speed and reducing its power consumption.

[0080] In one embodiment, the input circuit 101 has two output terminals, denoted as a first output terminal VN and a second output terminal VP, and the positive feedback circuit 104 includes a first feedback unit 1041 and a second feedback unit 1042. The first feedback unit 1041 and the second feedback unit 1042 both have a control terminal and a first terminal.

[0081] The control end of the first feedback unit 1041 is connected to the first output end VN of the input circuit 101, and the first end of the first feedback unit 1041 is connected to the second output end VP of the input circuit 101. The control end of the second feedback unit 1042 is connected to the second output end VP of the input circuit 101, and the first end of the second feedback unit 1042 is connected to the first output end VN of the input circuit 101.

[0082] The first feedback unit 1041 is used to pull the voltage of the second output terminal VP of the input circuit 101 according to the voltage of the first output terminal VN of the input circuit 101 during the sampling phase, and the second feedback unit 1042 is used to pull the voltage of the first output terminal VN of the input circuit 101 according to the voltage of the second output terminal VP of the input circuit 101 during the sampling phase.

[0083] The direction in which the first feedback unit 1041 pulls the voltage of the second output terminal VP of the input circuit 101 is the same as the direction in which the second feedback unit 1042 pulls the voltage of the first output terminal VN of the input circuit 101. When the first feedback unit 1041 pulls the voltage of the second output terminal VP of the input circuit 101 upward, the second feedback unit 1042 also pulls the voltage of the first output terminal VN of the input circuit 101 upward. When the first feedback unit 1041 pulls the voltage of the second output terminal VP of the input circuit 101 downward, the second feedback unit 1042 also pulls the voltage of the first output terminal VN of the input circuit 101 downward.

[0084] The following is an example of pulling down the voltages of the two output terminals of the input circuit 101: when the voltage of the first output terminal VN of the input circuit 101 is higher than the voltage of the second output terminal VP of the input circuit 101, the first feedback unit 1041 has a stronger ability to pull down the voltage of the second output terminal VP of the input circuit 101, and the second feedback unit 1042 has a weaker ability to pull down the voltage of the first output terminal VN of the input circuit 101, that is, the voltage drop rate of the first output terminal VN is lower than the voltage drop rate of the second output terminal VP, thereby making the voltage difference between the first output terminal VN voltage and the second output terminal VP increasingly larger, thereby realizing positive feedback.

[0085] When the voltage of the first output terminal VN of the input circuit 101 is lower than the voltage of the second output terminal VP of the input circuit 101, the first feedback unit 1041 has a weaker ability to pull down the voltage of the second output terminal VP of the input circuit 101, and the second feedback unit 1042 has a stronger ability to pull down the voltage of the first output terminal VN of the input circuit 101, that is, the voltage drop rate of the first output terminal VN is higher than the voltage drop rate of the second output terminal VP, thereby making the voltage difference between the first output terminal and the second output terminal increasingly larger, thereby realizing positive feedback.

[0086] In the above technical solution, when the reference signal is not appropriately selected, it takes a long time for the input signal and the reference signal to generate a differential signal at the output end of the input circuit. The input circuit 101 generates a differential signal based on the input signal and the reference signal, and the positive feedback circuit 104 accelerates the difference between the differential signals, shortening the sampling phase time, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

[0087] Figure 4A schematic diagram of a circuit structure of a comparator provided in another embodiment of the present application is shown in FIG. Figure 4 As shown, the comparator provided in this application includes an input circuit 101 , an output circuit 102 and a positive feedback circuit 104 .

[0088] The input circuit 101 includes a first input transistor 1011, a second input transistor 1012, and a third input transistor 1013. The control terminal of the first input transistor 1011 serves as the first input terminal IP of the input circuit 101, and the first terminal of the first input transistor 1011 serves as the first output terminal VN of the input circuit 101. The control terminal of the second input transistor 1012 serves as the second input terminal IN of the input circuit 101, and the first terminal of the second input transistor 1012 serves as the second output terminal VP of the input circuit 101. The first terminal of the third input transistor 1013 is connected to the second terminal of the first input transistor 1011 and the second terminal of the second input transistor 1012, and the second terminal of the third input transistor 1013 is connected to the ground terminal.

[0089] The control terminal of the third input transistor 1013 is used to receive a clock signal and to control the working state of the input circuit 101. When the third input transistor 1013 is closed, the input circuit 101 is in operation. When the third input transistor 1013 is open, the input circuit 101 stops working.

[0090] The control end of the first input transistor 1011 is used to receive an input signal, and the control end of the second input transistor 1012 is used to receive a reference signal. After the input signal and the reference signal are amplified by the first input transistor 1011 and the second input transistor 1012, a differential signal is generated between the first end of the first input transistor 1011 and the first end of the second input transistor 1012.

[0091] The output circuit 102 includes a first output transistor 1021, a second output transistor 1022, a third output transistor 1023, and a fourth output transistor 1024, forming a cross-coupled circuit. The first terminal of the first output transistor 1021 is connected to the second terminal of the third output transistor 1023, and the first terminal of the second output transistor 1022 is connected to the second terminal of the fourth output transistor 1024. The control terminal of the first output transistor 1021 is connected to the control terminal of the third output transistor 1023, and then to the second terminal of the fourth output transistor 1024. The control terminal of the second output transistor 1022 is connected to the control terminal of the fourth output transistor 1024, and then to the second terminal of the third output transistor 1023.

[0092] The second end of the first output transistor 1021 serves as the first input end of the output circuit 102, and the second end of the second output transistor 1022 serves as the second input end of the output circuit 102. The second end of the first output transistor 1021 is connected to the first end of the first input transistor 1011, and the second end of the second output transistor 1022 is connected to the first end of the second input transistor 1012. The second end of the third output transistor 1023 serves as the first output end ON of the output circuit 102, and the second end of the fourth output transistor 104 serves as the second output end OP of the output circuit 102.

[0093] After the first input transistor 1011 and the second input transistor 1012 are turned on, the voltage at the first terminal of the first output transistor 1021 and the first terminal of the second output transistor 1022 are pulled down. When the voltage is pulled down to the flip voltage, the transistors are turned on. That is, the first output transistor 1021 and the fourth output transistor 1024 are turned on, or the second output transistor 1022 and the third output transistor 1023 are turned on. If the first output transistor 1021 and the fourth output transistor 1024 are turned on, the voltage at the second terminal of the fourth output transistor 1024 is pulled up, and the voltage at the second terminal of the third output transistor 1023 is pulled down. If the second output transistor 1022 and the third output transistor 1023 are turned on, the voltage at the second terminal of the fourth output transistor 1024 is pulled down, and the voltage at the second terminal of the third output transistor 1023 is pulled up, thereby amplifying and latching the voltage signal output by the input circuit 101.

[0094] In one embodiment, the first feedback unit 1041 includes a first feedback transistor 1043. The control terminal of the first feedback transistor 1043 serves as the control terminal of the first feedback unit 1041, and the first terminal of the first feedback transistor 1043 serves as the first terminal of the first feedback unit 1041. The control terminal of the first feedback transistor 1043 is connected to the first terminal of the first input transistor 1011, and the first terminal of the first feedback transistor 1043 is connected to the first terminal of the second input transistor 1012. The second terminal of the first feedback transistor 1043 is connected to the second terminal of the first input transistor 1011. The second terminal of the first feedback transistor 1043 is also connected to the first terminal of the third input transistor 1013.

[0095] The control terminal of the second feedback transistor 1044 serves as the control terminal of the second feedback unit 1042, and the first terminal of the second feedback transistor 1044 serves as the first terminal of the second feedback unit 1042. The control terminal of the second feedback transistor 1044 is connected to the first terminal of the second input transistor 1012, and the first terminal of the second feedback transistor 1044 is connected to the first terminal of the first input transistor 1011. The second terminal of the second feedback transistor 1044 is connected to the second terminal of the second input transistor 1012, and the second terminal of the second feedback transistor 1044 is also connected to the first terminal of the third input transistor 1013.

[0096] In one embodiment, the first input transistor 1011 and the second input transistor 1012 are of the same type, so that the first input transistor 1011 and the second input transistor 1012 can generate a differential signal according to the input signal and the reference signal.

[0097] In one embodiment, the first feedback transistor 1043, the second feedback transistor 1044, the first input transistor 1011, and the second input transistor 1012 are of the same type, ensuring that the direction in which the first feedback transistor 1043 pulls the voltage of the second output terminal VP of the input circuit 101 is the same as the direction in which the second feedback transistor 1044 pulls the voltage of the first output terminal VN of the input circuit 101. Furthermore, the direction in which the feedback transistor pulls the voltage of the output terminal of the input circuit is the same as the direction in which the input transistor pulls the voltage of the output terminal of the input circuit, thereby achieving positive feedback.

[0098] When the voltage at the first end of the first input transistor 1011 is larger, the ability of the first feedback transistor 1043 to pull down the voltage at the first end of the second input transistor 1012 is larger, and the voltage at the first end of the second input transistor 1012 drops faster, thereby realizing a positive feedback mechanism and accelerating the difference in the differential voltage between the first input transistor 1011 and the second input transistor 1012.

[0099] In one embodiment, the comparator further includes a first reset circuit 1031, which is connected between the first output terminal VN of the input circuit 101 and the second output terminal VP of the input circuit 101. The first reset circuit 1031 is used to reset the voltage of the first output terminal VN of the input circuit 101 and the voltage of the second output terminal VP of the input circuit 101.

[0100] Among them, the first reset circuit 1031 includes a first clocked transistor 1032 and a second clocked transistor 1033, the second end of the first clocked transistor 1032 is connected to the first output end VN of the input circuit 101, the second end of the second clocked transistor 1033 is connected to the second output end VP of the input circuit 101, and the first end of the second clocked transistor 1033 is connected to the first end of the first clocked transistor 1032 and then connected to the power supply.

[0101] The control terminals of the first clock-controlled transistor 1032 and the second clock-controlled transistor 1033 are both used to receive a clock signal, and are turned on when the clock signal is at a low level, pulling the first output terminal VN and the second output terminal VP of the input circuit 101 to a high level.

[0102] In one embodiment, the comparator further includes a second reset circuit 1034 and a third reset circuit 1035. The second reset circuit 1034 is connected to the first output terminal of the output circuit, and the third reset circuit is connected to the second output terminal of the output circuit. The second reset circuit 1034 is used to reset the voltage at the first output terminal ON of the output circuit 102. The third reset circuit 1035 is used to reset the voltage at the second output terminal OP of the output circuit.

[0103] The second reset circuit 1034 includes a third clock-controlled transistor 1036, wherein a second terminal of the third clock-controlled transistor 1036 is connected to the first output terminal ON of the output circuit 102. A control terminal of the third clock-controlled transistor 1036 is configured to receive a clock signal and to pull the first output terminal ON of the output circuit 102 to a high level when the clock signal is at a low level.

[0104] The third reset circuit 1035 includes a fourth clocked transistor 1037, a second terminal of which is connected to the second output terminal OP of the output circuit 102. A control terminal of the fourth clocked transistor 1037 is used to receive a clock signal and to pull the second output terminal OP of the output circuit 102 to a high level when the clock signal is at a low level.

[0105] Compared with the reset achieved by the second reset circuit and the third reset circuit pulling the voltage of the two output ends of the input circuit through the output circuit, the reset is achieved by setting the first reset circuit to directly pull the voltage of the two output ends of the input circuit 101, and the reset time is shorter, thereby improving the response rate of the comparator.

[0106] In one embodiment, the first clocked transistor 1032 , the second clocked transistor 1033 , the third clocked transistor 1036 and the fourth clocked transistor 1037 are of the same type to pull the two output terminals of the input circuit and the two output terminals of the output circuit to the same level.

[0107] In one embodiment, when the first feedback transistor 1043 , the second feedback transistor 1044 , the first input transistor 1011 and the second input transistor 1012 are all N-type transistors, the drain of the N-type transistor is the first terminal and the gate of the N-type transistor is the control terminal.

[0108] In one embodiment, when the first output transistor 1021 and the second output transistor 1022 are both N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal;

[0109] When the third output transistor 1023 and the fourth output transistor 1024 are both P-type transistors, and the first to fourth clocked transistors 1032 to 1037 are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0110] In one embodiment, the first feedback transistor 1043 and the second feedback transistor 1044 have the same size, the first input transistor 1011 and the second input transistor 1012 have the same size, and the first feedback transistor 1043 is less than half the size of the first input transistor 1011. This prevents the first feedback transistor and the second feedback transistor from affecting the input signal and the reference signal sensed by the first input transistor and the second input transistor, thereby improving the accuracy of the comparator output result.

[0111] The following describes the four working stages of the comparator. Figure 4 The working process of the comparator shown is:

[0112] During the reset phase, the clock signal is at a low level, the third input transistor N3 is turned off, the input circuit 101 and the output circuit 102 stop operating, the first clocked transistor P5 and the second clocked transistor P6 are turned on, the first reset circuit 1031 operates, and the voltages at the first output terminal ON and the second output terminal OP of the input circuit are pulled up to a high level. The third clocked transistor P3 and the fourth clocked transistor P4 are closed, and the second reset circuit 1034 and the third reset circuit 1035 operate, pulling the drain voltages of the third output transistor P1 and the drain voltage of the fourth output transistor P2 to a high level.

[0113] During the sampling phase, the clock signal is high, the first through fourth clocked transistors P5 through P4 are disconnected, and the first through third reset circuits 1031 through 1035 cease operation. The third input transistor N3 is closed, and the input circuit collects the input signal through the first input terminal IP. The input circuit collects the reference signal through the second input terminal IN. The input signal pulls down the drain voltage of the first input transistor N1, and the reference signal pulls down the drain voltage of the second input transistor N2. The drain of the first input transistor N1 pulls down the drain voltage of the first output transistor N4, and the drain of the second input transistor N2 pulls down the drain voltage of the second output transistor N5.

[0114] When the reference signal is relatively small, for example, both the reference signal and the input signal are less than 0.7V, the first input transistor N1 and the second input transistor N2 need to be turned on for a longer time, that is, the voltage pull-up rate of the two output ends of the input circuit is slower, and the time to generate the differential signal at the two output ends of the input circuit is longer.

[0115] When there is a slight voltage difference between the two output terminals of the input circuit, for example, when the input signal is smaller than the reference signal, the voltage at the first output terminal of the input circuit is slightly higher than the voltage at the second output terminal of the input circuit. This makes the ability of the first feedback transistor N6 to pull down the voltage at the second output terminal of the input circuit higher than the ability of the second feedback transistor N7 to pull down the voltage at the first output terminal of the input circuit. In other words, the voltage drop rate at the first output terminal of the input circuit is lower than the voltage drop rate at the second output terminal of the input circuit. The voltage difference between the two output terminals is further amplified by the two feedback transistors, presenting a differential circuit at the two output terminals of the input circuit. This shortens the time that the comparator is in the sampling phase, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

[0116] In the regeneration stage, due to the pull-down effect of the first input transistor N1 and the second input transistor N2, the drain voltage of the first output transistor N4 and the drain voltage of the second output transistor N5 reach the flip voltage. When the drain voltage of the first input transistor N1 is higher than the drain voltage of the second input transistor N2, the first output transistor N4 and the fourth output transistor P2 are gradually disconnected, and the second output transistor P1 and the third output transistor N5 are gradually turned on. The ability to pull down the drain voltage of the fourth output transistor P2 becomes stronger and stronger, and the ability to pull up the drain voltage of the third output transistor P1 becomes stronger and stronger.

[0117] In the decision stage, the first output transistor N4 and the fourth output transistor P2 are turned off, and the second output transistor P1 and the third output transistor N5 are turned on, continuing to pull down the drain voltage of the fourth output transistor P2 and pull up the drain voltage of the third output transistor P1. After pulling the drain of the fourth output transistor P2 to a high level and the drain voltage of the third output transistor P1 to a low level, the drain voltages of the third output transistor P1 and the fourth output transistor P2 are maintained.

[0118] When the next working cycle comes, the clock signal becomes a low level, and the drain voltages of the third output transistor P1 and the fourth output transistor P2 are reset to a high level by the third clock-controlled transistor P3 and the fourth clock-controlled transistor P4.

[0119] like Figure 5 As shown, the dotted line indicates Figure 1 The solid line shows the relationship between the input signal and the delay time of the regeneration phase when the reference signal is relatively small. Figure 4 The comparator shown shows the relationship between the input signal and the delay time of the regeneration phase when the reference signal is relatively small. Figure 5 It can be seen that Figure 1When the input signal and the reference signal are both relatively small, for example, when the common-mode input voltage is 0.5V, the input signal is 0.1V, and the reference signal is 0.5V, the regeneration phase delay time of the comparator can reach 100 picoseconds. Figure 4 The comparator shown reduces the delay of the regeneration phase to 80 picoseconds when the input signal is 0.1V and the reference signal is 0.5V.

[0120] like Figure 6 As shown, the dotted line indicates Figure 1 The solid line shows the relationship between the input signal and the comparator power consumption when the reference signal is relatively small. Figure 4 The relationship between the input signal and the comparator power consumption is shown in the figure when the reference signal is relatively small. Figure 6 It can be seen that Figure 1 When the input signal and the reference signal of the comparator shown are both relatively small, for example, when the common-mode input voltage is 0.5V, the input signal is 0.1V, and the reference signal is 0.5V, the current reaches 730 microamperes. Figure 4 The comparator shown drops the current to less than 690 microamps with a common-mode input voltage of 0.5V, a 0.1V input signal, and a 0.5V reference signal.

[0121] In the above technical solution, the input circuit uses N-type transistors. If the reference signal is relatively small and the reference signal and the input signal only produce a small voltage difference at the output of the input circuit within a short period of time, the first feedback transistor and the second feedback transistor pull the voltage at the output terminal at different rates, accelerating the difference between the differential signals at the output terminals, thereby shortening the time the comparator is in the sampling phase and reducing the power consumption of the comparator. In addition, the first reset circuit directly pulls the voltage at the output terminal of the input circuit to achieve reset, which can shorten the reset time of the input circuit output terminal, thereby improving the response rate of the comparator.

[0122] Figure 7 A specific circuit diagram of a comparator is provided for the present application. The comparator includes an input circuit 101 , an output circuit 102 and a positive feedback circuit 104 .

[0123] The input circuit 101 includes a first input transistor 1011, a second input transistor 1012, and a third input transistor 1013. The connection relationship between the first input transistor 1011 to the third input transistor 1013 is the same as Figure 4 The embodiments shown are the same and will not be described again here.

[0124] It should be noted that when the first to third input transistors 1011 to 1013 are P-type transistors, the drain of the P-type transistor is the first terminal, the source of the P-type transistor is the second terminal, the gate of the P-type transistor is the control terminal, and the second terminal of the third input transistor is connected to the power supply terminal.

[0125] The output circuit includes a first output transistor 1021, a second output transistor 1022, a third output transistor 1023 and a fourth output transistor 1024. The connection relationship between the first output transistor 1021 to the fourth input transistor 1024 is the same as Figure 4 The embodiments shown are the same and will not be described again here.

[0126] It should be noted that when the first output transistor 1021 and the second output transistor 1023 are P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. When the third output transistor 1023 and the fourth output transistor 1024 are N-type transistors, the drain of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal.

[0127] The positive feedback circuit 104 includes a first feedback unit 1041 and a second feedback unit 1042. The connection relationship between the first feedback unit 1041 and the second feedback unit 1042 is the same as Figure 4 The first feedback unit 1041 includes a first feedback transistor 1043, and the second feedback unit 1042 includes a second feedback transistor 1044. The connection relationship between the first feedback transistor 1043 and the second feedback transistor 1044 is the same as Figure 4 The same, no further description here.

[0128] It should be noted that, when the first feedback transistor 1043 and the second feedback transistor 1044 are P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0129] The connection relationship between the transistors in the input circuit, the transistors in the output circuit, and the transistors in the positive feedback circuit has been Figure 4 The details are described in detail in the embodiment shown and will not be repeated here.

[0130] The comparator further includes a first reset circuit 1031, a second reset circuit 1032, and a third reset circuit 1033. The first reset circuit 1031 includes a first clock-controlled transistor 1032 and a second clock-controlled transistor 1033. The connection relationship between the first clock-controlled transistor 1032 and the second clock-controlled transistor 1033 is the same as Figure 4 The same, no further description here.

[0131] The second reset circuit 1034 includes a third clock-controlled transistor 1036, and the third clock-controlled transistor has the same connection relationship with the transistor in the output circuit. Figure 4 The third reset circuit 1035 includes a fourth clock-controlled transistor 1037, and the connection relationship between the fourth clock-controlled transistor and the transistor in the output circuit is the same as Figure 4 The same, no further description here.

[0132] It should be noted that when the first clocked transistor 1032 to the fourth clocked transistor 1034 are N-type transistors, the drain of the N-type transistor is the second end, the gate of the N-type transistor is the control end, the source of the N-type transistor is the first end, and the source of the N-type transistor is grounded.

[0133] The following describes the four working stages of the comparator. Figure 4 The working process of the comparator shown is:

[0134] During the reset phase, the clock signal is at a low level, the control terminal of the third input transistor P3 is at a high level, the third input transistor is disconnected, the input circuit 101 and the output circuit 102 stop operating, the control terminals of the first clocked transistor N5 and the second clocked transistor N6 are at a high level, the first clocked transistor N5 and the second clocked transistor N6 are turned on, the first reset circuit 1031 operates, and the voltages of the first output terminal ON and the second output terminal OP of the input circuit are pulled up to a low level. The control terminals of the third clocked transistor N3 and the fourth clocked transistor N4 are also at a high level, the third clocked transistor N3 and the fourth clocked transistor N4 are turned on, the second reset circuit 1034 and the third reset circuit 1035 operate, pulling the drain voltages of the third output transistor N1 and the drain voltage of the fourth output transistor N2 to a low level.

[0135] During the sampling phase, the clock signal is high, the control terminals of the first through fourth clocked transistors N5 through N4 are low, disconnecting them and halting the operation of the first through third reset circuits 1031 through 1035. The control terminal of the third input transistor P3 is low, closing it. The input circuit 101 collects the input signal through the first input terminal IP and the reference signal through the second input terminal IN. The input signal pulls up the drain voltage of the first input transistor P1, while the reference signal pulls up the drain voltage of the second input transistor P2. The drain of the first input transistor P1 pulls up the drain voltage of the first output transistor P4, while the drain of the second input transistor P2 pulls up the drain voltage of the second output transistor P5.

[0136] When the reference signal is relatively large, for example, both the reference signal and the input signal are greater than 0.3V, the first input transistor P1 and the second input transistor P2 need to be turned on for a longer time, that is, the voltage pull-up rate of the two output ends of the input circuit is slower, and the time it takes to generate a differential signal at the two output ends of the input circuit is relatively long.

[0137] When there is a slight voltage difference between the two output terminals of the input circuit, for example, when the input signal is smaller than the reference signal, the voltage at the first output terminal of the input circuit is slightly higher than the voltage at the second output terminal of the input circuit, so that the ability of the first feedback transistor P6 to pull up the voltage at the second output terminal of the input circuit is smaller than the ability of the second feedback transistor P7 to pull up the voltage at the first output terminal of the input circuit. In other words, the voltage rise rate of the first output terminal of the input circuit is higher than the voltage fall rate of the second output terminal of the input circuit. The voltage difference between the two output terminals is further amplified by the two feedback transistors, and a differential circuit is presented at the two output terminals of the input circuit, shortening the time that the comparator is in the sampling stage, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

[0138] In the regeneration stage, due to the pull-up effect of the first input transistor P1 and the second input transistor P2, the drain voltage of the first output transistor P4 and the drain voltage of the second output transistor P5 reach the flip voltage. When the drain voltage of the first input transistor P1 is higher than the drain voltage of the second input transistor P2, the first output transistor P4 and the fourth output transistor N2 are closed, and the second output transistor N1 and the third output transistor P5 are disconnected, pulling down the drain voltage of the fourth output transistor N2 and pulling up the drain voltage of the third output transistor N1.

[0139] In the decision stage, the first output transistor P4 and the fourth output transistor N2 are closed, the second output transistor N1 and the third output transistor P5 are disconnected, the drain voltage of the fourth output transistor N2 is continuously pulled down, and the drain voltage of the third output transistor N1 is pulled up. After the drain of the third output transistor N1 is pulled to a high level and the drain voltage of the fourth output transistor N2 is pulled to a low level, the drain voltages of the third output transistor N1 and the fourth output transistor N2 are maintained.

[0140] When the next working cycle comes, the clock signal becomes a low level, and the drain voltages of the third output transistor N1 and the fourth output transistor N2 are reset to a low level by the third clock-controlled transistor N3 and the fourth clock-controlled transistor N4.

[0141] like Figure 8 As shown, the dotted line indicates Figure 1 The solid line shows the relationship between the input signal and the regeneration phase delay time when the reference signal is relatively large. Figure 7 The relationship between the input signal and the delay time of the regeneration phase of the comparator is shown when the reference signal is relatively large. Figure 8 It can be seen that Figure 1 When the input signal and the reference signal are both relatively large, for example, when the input common mode voltage is 0.8V, the input signal is 0.6V, and the reference signal is 0.8V, the regeneration phase delay time of the comparator can reach 110 picoseconds. Figure 7 The input common-mode voltage is shown to be 0.8V, the comparator input signal is 0.6V, and the reference signal is 0.8V, reducing the delay of the regeneration phase to less than 80 picoseconds.

[0142] In the above embodiment, the input circuit uses P-type transistors. If the reference signal is relatively large, the reference signal and the input signal will only produce a small voltage difference at the output terminal of the input circuit for a short period of time. The first feedback transistor and the second feedback transistor pull the voltage at the output terminal at different rates, accelerating the difference between the differential signals at the output terminals, thereby shortening the time the comparator is in the sampling phase and reducing the power consumption of the comparator. In addition, the first reset circuit directly pulls the voltage at the output terminal of the input circuit to achieve reset, which can shorten the reset time of the input circuit output terminal, thereby improving the response speed of the comparator.

[0143] Figure 9 A structural block diagram of a comparator provided in this application is shown in FIG. Figure 9 As shown, the comparator includes an input circuit 101 , an output circuit 102 and a positive feedback circuit 104 .

[0144] The input circuit 101 has two output terminals, denoted as a first output terminal VN and a second output terminal VP. The positive feedback circuit 104 includes at least one controllable positive feedback module 1040, wherein each feedback unit includes a first feedback unit 1041, a second feedback unit 1042, a first switch 1043, and a second switch 1044. The first feedback unit 1041 and the second feedback unit 1042 each have a control terminal and a first terminal.

[0145] The control end of the first feedback unit 1041 is connected to the first output end VN of the input circuit 101 via the first switch 1043, and the first end of the first feedback unit 1041 is connected to the second output end VP of the input circuit 101. The control end of the second feedback unit 1042 is connected to the second output end VP of the input circuit 101 via the second switch 1044, and the first end of the second feedback unit 1042 is connected to the first output end VN of the input circuit 101.

[0146] First switch 1043 is used to control whether first feedback unit 1041 generates positive feedback, and second switch 1044 is used to control whether second feedback unit 1042 generates positive feedback. By controlling the closing and opening of first switch 1043 and second switch 1044, it is possible to control whether controllable positive feedback module 1040 generates positive feedback. When both first switch 1043 and second switch 1044 are closed, controllable positive feedback module 1040 can accelerate the difference between the differential signals at the output end of the input circuit through a positive feedback mechanism. When both first switch 1043 and second switch 1044 are open, controllable positive feedback module 1040 is disconnected from the input circuit, and the positive feedback mechanism cannot be generated at the output end of the input circuit.

[0147] When the comparator is operating, the number of controllable positive feedback modules generating positive feedback can be controlled, thereby controlling the positive feedback circuit's ability to shift the difference between the differential signals. This, on the one hand, controls the time the comparator spends in the sampling phase, ensuring the comparator's response rate. On the other hand, it balances the positive feedback circuit's ability to shift the voltage at the input circuit's output terminal with the input signal and reference signal's ability to shift the voltage at the input circuit's output terminal, ensuring the comparator accurately outputs a comparison result based on the input and reference signals.

[0148] Figure 10 and Figure 11 Based on Figure 9 One of the specific circuit diagrams of the comparator shown in FIG. 1 , wherein the structures of the input circuit 101 and the output circuit 102 are the same Figure 4 The comparator is the same as that shown in FIG. 1 , and will not be described in detail here. The comparator further includes a first reset circuit 1031, a second reset circuit 1034, and a third reset circuit 1035. The three reset circuits are also described in FIG. Figure 4 The embodiments shown are described in detail and will not be repeated here.

[0149] The following combination Figure 11 The first feedback unit 1041 includes a first feedback transistor 1043 , whose control terminal serves as the input terminal of the first feedback unit 1041 and whose first terminal serves as the output terminal of the first feedback unit 1041 .

[0150] The control terminal of the first feedback transistor 1043 is connected to the first terminal of the first input transistor 1011 via a first switch 1045. The first switch 1045 includes a first transmission gate G1, which is controlled by a first enable signal EN1. The first enable signal EN1 is generated based on the operating frequency of the comparator, the input common mode range of the comparator, and the test mode signal.

[0151] The second feedback unit 1042 includes a first feedback transistor 1044 . The control terminal of the second feedback transistor 1044 is the input terminal of the second feedback unit 1042 , and the first terminal of the second feedback transistor 1044 is the output terminal of the second feedback unit 1042 .

[0152] The control terminal of the second feedback transistor 1044 is connected to the first terminal of the second input transistor 1012 via a second switch 1046. The second switch 1046 includes a second transmission gate G2, which is controlled by a second enable signal EN2. The second enable signal EN2 is generated based on the operating frequency of the comparator, the input common mode range of the comparator, and the test mode signal.

[0153] The switch states of the first transmission gate G1 and the second transmission gate G2 are controlled by the enable signal, thereby controlling whether the first feedback transistor 1043 and the second feedback transistor 1044 provide a positive feedback mechanism, thereby adjusting the number of controllable positive feedback modules participating in the positive feedback.

[0154] In one embodiment, the positive feedback circuit further includes a first zeroing switch 1047 and a zeroth zeroing switch 1048. The control terminal of the first feedback unit 1041 is further connected to the ground terminal via the first zeroing switch 1047. The first zeroing switch 1047 is configured to be turned on when the first transmission gate G1 is turned off, thereby preventing the transistor in the first feedback unit 1041 from floating, thereby reducing interference from external interference on the comparator. The control terminal of the second feedback unit 1042 is further connected to the ground terminal via the zeroth zeroing switch 1048. The first zeroing switch 1047 is configured to be turned on when the first transmission gate G1 is turned off, thereby preventing the transistor in the second feedback unit 1042 from floating, thereby reducing interference from external interference on the comparator.

[0155] In one embodiment, if the first feedback transistor 1043, the second feedback transistor 1044, the first zero switch 1047, and the zeroth zero switch 1048 are N-type transistors, the drain of the N-type transistor is the first terminal, the source of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal, the first terminal of the first zero switch 1047 is connected to the control terminal of the first feedback transistor 1043, the first terminal of the zeroth zero switch 1048 is connected to the control terminal of the second feedback transistor 1044, and the second terminals of the first zero switch 1047 and the zeroth zero switch 1048 are grounded, so as to pull the first feedback transistor 1043 to a low level when the first transmission gate G1 is closed, and pull the second feedback transistor 1044 to a low level when the second transmission gate G2 is closed.

[0156] Figure 12 and Figure 13 Based on Figure 9 One of the specific circuit diagrams of the comparator shown in FIG. 1 , wherein the structures of the input circuit 101 and the output circuit 102 are the same Figure 7The connection relationship between the first feedback unit, the second feedback unit, the first switch and the second switch of each controllable module in the positive feedback circuit has been described. Figure 11 The structure is described in detail here and will not be repeated here.

[0157] It should be noted here that if the first feedback transistor and the second feedback transistor are P-type transistors, the drain of the P-type transistor is the first terminal, the source of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal.

[0158] In one embodiment, the positive feedback circuit further includes a first zeroing switch 1047 and a zeroth zeroing switch 1048. The control terminal of the first feedback unit 1041 is further connected to the power supply terminal via the first zeroing switch 1047. The first zeroing switch 1047 is configured to be turned on when the first transmission gate G1 is turned off, thereby preventing the transistor in the first feedback unit 1041 from floating, thereby reducing interference from external interference on the comparator. The control terminal of the second feedback unit 1042 is further connected to the power supply terminal via the zeroth zeroing switch 1048. The first zeroing switch 1047 is configured to be turned on when the first transmission gate G1 is turned off, thereby preventing the transistor in the second feedback unit 1042 from floating, thereby reducing interference from external interference on the comparator.

[0159] The first zero switch 1047 and the zeroth zero switch 1048 are also P-type transistors. The first end of the first zero switch 1047 is connected to the control end of the first feedback transistor, the first end of the zeroth zero switch 1048 is connected to the control end of the second feedback transistor, and the second ends of the first zero switch 1047 and the zeroth zero switch 1048 are connected to the power supply end, so as to pull the first feedback transistor 1043 to a high level when the first transmission gate G1 is closed, and pull the second feedback transistor 1044 to a high level when the second transmission gate G2 is closed.

[0160] In the above embodiment, the positive feedback circuit includes multiple controllable positive feedback modules. By controlling the number of controllable positive feedback modules that provide the positive feedback mechanism, the ability of the positive feedback circuit to pull the voltage of the two output terminals of the input circuit is adjusted, thereby controlling the time when the comparator is in the sampling stage. It can also balance the pulling ability of the positive feedback circuit and the input signal and reference signal on the output terminal of the input circuit, thereby improving the response rate and accuracy of the comparator.

[0161] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0162] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A comparator, characterized in that: include: an input circuit having an output terminal for generating a differential signal according to the input signal and a reference signal during a sampling phase; a positive feedback circuit connected to the output terminal of the input circuit and configured to accelerate the difference between the differential signals; an output circuit connected to the output terminal of the input circuit, and configured to amplify and latch the voltage signal at the output terminal of the input circuit in a regeneration phase to output a comparison result; The input circuit is provided with two output terminals, and the positive feedback circuit includes at least one controllable positive feedback module; wherein each controllable positive feedback module includes: a first feedback unit, a control end of which is connected to the first output end of the input circuit via a first switch, and a first end of which is connected to the second output end of the input circuit; The second feedback unit has a control end connected to the second output end of the input circuit through a second switch, and a first end connected to the first output end of the input circuit.

2. The comparator according to claim 1, wherein: The first feedback unit includes: a first feedback transistor, a control terminal of which is the input terminal of the first feedback unit, and a first terminal of which is the output terminal of the first feedback unit; The second feedback unit includes: a second feedback transistor, a control end of which is the input end of the second feedback unit, and a first end of which is the output end of the second feedback unit.

3. The comparator according to claim 2, wherein: The input circuit comprises: a first input transistor, whose control terminal is used to receive the input signal, whose first terminal serves as the first output terminal of the input circuit, and whose second terminal is connected to the second terminal of the first feedback transistor; a second input transistor, whose control terminal is used to receive the reference signal, whose first terminal serves as the second output terminal of the input circuit, and whose second terminal is connected to the second terminal of the second feedback transistor; a third input transistor, whose control end is used to receive a clock signal, whose first end is connected to the second end of the first input transistor, the second end of the second input transistor, the second end of the first feedback transistor, and the second end of the second feedback transistor, and whose second end is connected to the ground end or the power supply end.

4. The comparator according to claim 3, wherein: The first feedback transistor, the second feedback transistor, the first input transistor, and the second input transistor are of the same type.

5. The comparator according to claim 4, wherein: When the first feedback transistor, the second feedback transistor, the first input transistor, and the second input transistor are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal; When the first feedback transistor, the second feedback transistor, the first input transistor, and the second input transistor are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

6. The comparator according to claim 1, wherein: The comparator further includes: The first reset circuit is connected between the first output terminal of the input circuit and the second output terminal of the input circuit, and is used for resetting the voltage of the first output terminal of the input circuit and the voltage of the second output terminal of the input circuit.

7. The comparator according to claim 6, wherein: The comparator further includes: a second reset circuit connected to the first output terminal of the output circuit, for resetting the voltage of the first output terminal of the output circuit; The third reset circuit is connected to the second output terminal of the output circuit and is used to reset the voltage of the second output terminal of the output circuit.

8. The comparator according to claim 7, wherein: The first reset circuit includes: a first clock-controlled transistor, a control terminal of which receives a clock signal and a second terminal of which is connected to the first output terminal of the input circuit; A second clock-controlled transistor has a control end receiving the clock signal, a second end connected to the second output end of the input circuit, and a first end connected to the first end of the first clock-controlled transistor.

9. The comparator according to claim 8, wherein: The second reset circuit includes: a third clock-controlled transistor, a control terminal of which receives a clock signal and a second terminal of which is connected to the first output terminal of the output circuit; The third reset circuit includes: a fourth clock-controlled transistor, a control terminal of which receives a clock signal, and a second terminal of which is connected to the second output terminal of the output circuit.

10. The comparator according to claim 7 or 9, characterized in that: The first clocked transistor, the second clocked transistor, the third clocked transistor and the fourth clocked transistor are of the same type.

11. The comparator according to claim 3, wherein: The output circuit includes: a first output transistor, a second terminal of which is a first input terminal of the output circuit; a second output transistor, a second terminal of which is a second input terminal of the output circuit; a third output transistor, a control end of which is connected to the control end of the first output transistor, and a control end of which is further connected to the second end of the fourth output transistor, the second end of the third output transistor serving as the first output end of the output circuit; A fourth output transistor has a control end connected to the control end of the second output transistor and further connected to the second end of the third output transistor. The second end of the fourth output transistor serves as the second output end of the output circuit.

12. The comparator according to claim 11, wherein: The first output transistor and the second output transistor are both N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal; The third output transistor and the fourth output transistor are both P-type transistors, the first to fourth clock-controlled transistors are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

13. The comparator according to claim 11, wherein: The first input transistor and the second output transistor are both P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal; The third output transistor and the fourth output transistor are both N-type transistors, the first to fourth clock-controlled transistors are all N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

14. The comparator according to claim 4, wherein: The first feedback transistor and the second feedback transistor have the same size, the first input transistor and the second input transistor have the same size, and the size of the first feedback transistor is less than half of the size of the first input transistor.

15. The comparator according to claim 1, wherein: The first switch includes a first transmission gate, the first transmission gate is controlled by a first enable signal, and the first enable signal is generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal; The second switch includes a second transmission gate controlled by a second enable signal generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal.

16. The comparator according to claim 1, wherein: The control end of the first feedback unit is further connected to the ground end or the power end through the first zero switch; the control end of the second feedback unit is further connected to the ground end or the power end through the zeroth zero switch.

Images