Receiver, memory, and receiver control method

Abstract

The present application provides a receiver, a memory, and a control method for the receiver, wherein the receiver includes a pre-amplifier circuit, a comparator, and an output control circuit; the pre-amplifier circuit is used to receive an input signal and a reference signal, and convert the input signal into a first differential signal and a second differential signal based on the reference signal; the comparator is connected to the pre-amplifier circuit, used to compare the first differential signal and the second differential signal, and output a comparison signal; the output control circuit is connected to the pre-amplifier circuit and the comparator, used to detect the common-mode level of the first differential signal and the second differential signal, and when the voltage value of the common-mode level is greater than or equal to a preset value, control the output of an output signal at a first logic level, and when the voltage value of the common-mode level is less than the preset value, control the output of an output signal corresponding to the comparison signal.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a receiver, a memory, and a control method for the receiver. Background Art

[0002] In some memory devices, such as Low Power Double Data Rate SDRAM (LPDDR), multiple receivers corresponding to each channel typically share a common bias voltage generation circuit. When the bias voltage generation circuit is turned on, the bias voltage (Vbias) begins to build up from 0 volts. Due to the large load network of Vbias, this buildup takes time, and the receiver is already turned on at this point. When the Vbias voltage is low, the bias current is high, and the differential signals generated within the receiver are all pulled high, making the comparator output uncertain. At this point, the comparator output is prone to glitches, which can trigger certain commands and cause the memory to unexpectedly enter an undefined operating mode. Summary of the Invention

[0003] In view of this, the main purpose of this application is to provide a receiver, a memory, and a control method for the receiver.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] An embodiment of the present application provides a receiver, including a pre-amplifier circuit, a comparator, and an output control circuit; the pre-amplifier circuit is used to receive an input signal and a reference signal, and convert the input signal into a first differential signal and a second differential signal based on the reference signal; the comparator is connected to the pre-amplifier circuit, used to compare the first differential signal and the second differential signal, and output a comparison signal; the output control circuit is connected to the pre-amplifier circuit and the comparator, used to detect the common mode level of the first differential signal and the second differential signal, and when the voltage value of the common mode level is greater than or equal to a preset value, control the output of an output signal at a first logic level, and when the voltage value of the common mode level is less than the preset value, control the output of the output signal corresponding to the comparison signal.

[0006] In some embodiments, the pre-amplification circuit is further configured to receive an enable signal, and when the enable signal is valid, convert the input signal into the first differential signal and the second differential signal.

[0007] In some embodiments, the pre-amplifier circuit includes a bias current generating circuit and a differential signal generating circuit; wherein the bias current generating circuit is used to receive the enable signal and the bias voltage signal, and when the enable signal is valid, generates and outputs a bias current according to the bias voltage signal; the differential signal generating circuit is connected to the bias current generating circuit, is used to receive the bias current, the input signal and the reference signal, and under the control of the bias current, generates and outputs the first differential signal and the second differential signal according to the input signal and the reference signal.

[0008] In some embodiments, the output control circuit includes a common-mode detection circuit and a logic operation circuit; wherein the common-mode detection circuit is connected to the pre-amplifier circuit, and is used to receive the first differential signal and the second differential signal, and detect the common-mode level of the first differential signal and the second differential signal, and generate and output a clamp signal according to the common-mode level; when the voltage value of the common-mode level is greater than or equal to the preset value, the clamp signal at a valid level is output; when the voltage value of the common-mode level is less than the preset value, the clamp signal at an invalid level is output; the logic operation circuit is connected to the common-mode detection circuit and the comparator, and is used to perform a logic operation on the comparison signal and the clamp signal, and generate and output the output signal; wherein, when the clamp signal is at a valid level, the output signal at the first logic level is generated and output, and when the clamp signal is at an invalid level, the output signal corresponding to the comparison signal is generated and output.

[0009] In some embodiments, the common-mode detection circuit includes a detection circuit, an output circuit, and a feedback circuit; the detection circuit is used to receive the enable signal, the first differential signal, and the second differential signal, and when the enable signal is valid, detect the common-mode level of the first differential signal and the second differential signal, and output the common-mode level from the output end of the detection circuit; when the enable signal is invalid, the output end of the detection circuit is set to a second logic level; the output circuit is connected to the detection circuit, and is used to receive the common-mode level, and when the voltage value of the common-mode level is greater than or equal to the preset value, output the clamp signal at a valid level; when the voltage value of the common-mode level is less than the preset value, output the clamp signal at an invalid level; the feedback circuit is connected to the detection circuit and the output circuit, and is used to receive the clamp signal, and when the clamp signal is at an invalid level, set the output end of the detection circuit to a third logic level; wherein the voltage value of the second logic level is higher than the preset value, and the voltage value of the third logic level is lower than the preset value.

[0010] In some embodiments, the detection circuit is further configured to receive the clamp signal and stop detecting the common mode level of the first differential signal and the second differential signal when the clamp signal is at an invalid level.

[0011] In some embodiments, the detection circuit includes an input circuit, a voltage divider detection circuit, an isolation circuit and a reset circuit; the input circuit is used to receive the clamp signal, the first differential signal and the second differential signal, and output the first differential signal and the second differential signal to the voltage divider detection circuit when the clamp signal is at a valid level; when the clamp signal is at an invalid level, the output of the first differential signal and the second differential signal is stopped; the voltage divider detection circuit is coupled to the input circuit, and is used to receive the first differential signal and the second differential signal, perform voltage divider detection on the first differential signal and the second differential signal to obtain the common mode level, and output the common mode level from the output end of the detection circuit; the isolation circuit is connected between the input circuit and the voltage divider detection circuit, and is used to receive the enable signal, and isolate the input circuit from the voltage divider detection circuit when the enable signal is invalid; the reset circuit is connected to the voltage divider detection circuit, and is used to receive the enable signal, and set the output end of the detection circuit to the second logic level when the enable signal is invalid.

[0012] In some embodiments, the input circuit includes a first PMOS transistor and a second PMOS transistor, the gates of the first PMOS transistor and the second PMOS transistor are both used to receive the clamping signal, the source of the first PMOS transistor is used to receive the first differential signal, the source of the second PMOS transistor is used to receive the second differential signal, and the drain of the first PMOS transistor and the drain of the second PMOS transistor are both connected to the isolation circuit.

[0013] In some embodiments, the isolation circuit includes a third PMOS tube and a fourth PMOS tube, the gates of the third PMOS tube and the fourth PMOS tube are both used to receive the enable signal, the source of the third PMOS tube is connected to the drain of the first PMOS tube, the source of the fourth PMOS tube is connected to the drain of the second PMOS tube, and the drain of the third PMOS tube and the drain of the fourth PMOS tube are both connected to the voltage divider detection circuit.

[0014] In some embodiments, the voltage divider detection circuit includes a first resistor and a second resistor, the first end of the first resistor is connected to the drain of the third PMOS tube, the first end of the second resistor is connected to the drain of the fourth PMOS tube, and the connection node between the second end of the first resistor and the second end of the second resistor is the output end of the detection circuit.

[0015] In some embodiments, the reset circuit includes a fifth PMOS tube, the gate of the fifth PMOS tube is used to receive an inverted enable signal corresponding to the enable signal, the source of the fifth PMOS tube is connected to the power supply voltage, and the drain of the fifth PMOS tube is connected to the output end of the detection circuit.

[0016] In some embodiments, the output circuit includes a sixth PMOS transistor and a first NMOS transistor, the gates of the sixth PMOS transistor and the first NMOS transistor are both connected to the output end of the detection circuit, the source of the sixth PMOS transistor is connected to the power supply voltage, the drain of the sixth PMOS transistor is connected to the source of the first NMOS transistor, the connection between the drain of the sixth PMOS transistor and the source of the first NMOS transistor forms the clamping signal, and the drain of the first NMOS transistor is connected to the ground end.

[0017] In some embodiments, the feedback circuit includes a second NMOS transistor, the gate of the second NMOS transistor is used to receive the clamping signal, the source of the second NMOS transistor is connected to the output end of the detection circuit, and the drain of the second NMOS transistor is connected to the ground end.

[0018] In some embodiments, the effective level of the clamping signal is a low level, and the first logic level is a low level; the logic operation circuit includes an AND gate, the two input ends of the AND gate are respectively used to receive the comparison signal and the clamping signal, and the output end of the AND gate is used to output the output signal.

[0019] In some embodiments, the bias current generating circuit includes a seventh PMOS transistor and an eighth PMOS transistor, the gate of the seventh PMOS transistor receives the enable signal, the source of the seventh PMOS transistor is connected to the power supply voltage, the gate of the eighth PMOS transistor receives the bias voltage signal, the source of the eighth PMOS transistor is connected to the drain of the seventh PMOS transistor, and the drain of the eighth PMOS transistor is connected to the differential signal generating circuit to output the bias current.

[0020] In some embodiments, the differential signal generating circuit includes a ninth PMOS transistor, a tenth PMOS transistor, a third resistor, and a fourth resistor. The sources of the ninth PMOS transistor and the tenth PMOS transistor are both connected to the drain of the eighth PMOS transistor. The gate of the ninth PMOS transistor is used to receive the input signal. The gate of the tenth PMOS transistor is used to receive the reference signal. The first end of the third resistor is connected to the drain of the ninth PMOS transistor. The second end of the third resistor is connected to the ground. The first end of the fourth resistor is connected to the drain of the tenth PMOS transistor. The second end of the fourth resistor is connected to the ground. The drain of the ninth PMOS transistor is used to output the first differential signal, and the drain of the tenth PMOS transistor is used to output the second differential signal.

[0021] An embodiment of the present application provides a memory including the above-mentioned receiver.

[0022] An embodiment of the present application further provides a control method for a receiver, the receiver comprising a pre-amplifier circuit, a comparator, and an output control circuit, the comparator being connected to the pre-amplifier circuit, and the output control circuit being connected to the pre-amplifier circuit and the comparator; the method comprising:

[0023] The pre-amplification circuit receives an input signal and a reference signal, and converts the input signal into a first differential signal and a second differential signal based on the reference signal;

[0024] The comparator compares the first differential signal and the second differential signal and outputs a comparison signal;

[0025] The output control circuit detects a common-mode level of the first differential signal and the second differential signal, and when a voltage value of the common-mode level is greater than or equal to a preset value, controls the output of an output signal at a first logic level, and when a voltage value of the common-mode level is less than the preset value, controls the output of the output signal corresponding to the comparison signal.

[0026] A receiver provided in an embodiment of the present application includes a pre-amplifier circuit, a comparator, and an output control circuit; the pre-amplifier circuit is used to receive an input signal and a reference signal, and convert the input signal into a first differential signal and a second differential signal based on the reference signal; the comparator is connected to the pre-amplifier circuit, and is used to compare the first differential signal and the second differential signal, and output a comparison signal; the output control circuit is connected to the pre-amplifier circuit and the comparator, and is used to detect the common mode level of the first differential signal and the second differential signal, and when the voltage value of the common mode level is greater than or equal to a preset value, control the output of an output signal at a first logic level, and when the voltage value of the common mode level is less than the preset value, control the output of an output signal at a first logic level. When the voltage value of the common-mode level is less than the preset value, the comparator can work normally and control the output of the output signal corresponding to the comparison signal. In this way, the risk of the semiconductor device in which the receiver is located accidentally entering certain uncertain working modes when the voltage value of the bias voltage is low can be reduced, thereby improving the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the connection between a bias voltage generating circuit and a receiver in the related art;

[0028] Figure 2 is a schematic diagram showing the variation of bias voltage over time in the related art;

[0029] Figure 3 A schematic diagram of the connection between a pre-amplifier circuit and a comparator in the related art;

[0030] Figure 4 A schematic diagram of the structure of a receiver provided in an embodiment of the present application;

[0031] Figure 5 A schematic diagram of the specific structure of the common-mode detection circuit provided in an embodiment of the present application;

[0032] Figure 6 A flowchart of a control method for a receiver provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solution of the present application is further elaborated in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Figure 1 FIG. 1 is a schematic diagram of a bias voltage generating circuit connected to a receiver in the related art, such as Figure 1As shown, in some memories, such as low-power double data rate memories, multiple receivers (receiver 1, receiver 2, ..., receiver n) corresponding to each channel typically share a bias voltage generation circuit. The bias voltage generation circuit is turned off in power-down mode and turned on when the device exits power-down mode.

[0035] It should be noted that the EN signal received by the bias voltage generation circuit and the EN signal received by the receiver share the same signal. To save power, in shutdown mode, both the bias voltage generation circuit and the receiver are turned off. For example, when EN = 0, the device enters shutdown mode; when EN = 1, the device exits shutdown mode, where "0" represents a logic low level and "1" represents a logic high level.

[0036] like Figure 2 Figure 2 shows how the bias voltage Vbias varies over time txp in the related art. When EN transitions from "0" to "1" at time T1, the bias voltage generation circuit and receiver both exit shutdown mode, effectively turning them on. At this point, Vbias begins to build up from 0 volts. Due to the large load network, this buildup takes time.

[0037] like Figure 3 FIG. 1 is a schematic diagram illustrating the connection between the preamplifier circuit 10 and the comparator 20 in the related art. EN_n is the inverted signal of EN. When EN=1, EN_n=0, and MP7 is turned on. Because the load network of Vbias is large, Vbias takes time to establish. When the voltage of Vbias is low, the common node m above MP9 and MP10 is pulled high (close to the voltage of the power supply voltage VCC), and the bias currents of the input signal inp branch and the reference signal Vref branch are both relatively large. The generated first differential signal out1_p and second differential signal out1_n are both pulled to a high level, causing the comparator 20 to exceed its operating range and fail to perform normal comparison. This results in an uncertain output of the comparator 20. In other words, the output of the comparator 20 is prone to glitches, which may trigger certain commands, causing the low-power double data rate memory to unexpectedly enter certain uncertain operating modes.

[0038] like Figure 4, which is a schematic diagram of the structure of a receiver provided in an embodiment of the present application, the receiver includes a pre-amplifier circuit 10, a comparator 20, and an output control circuit 30; the pre-amplifier circuit 10 is used to receive an input signal inp and a reference signal Vref, and convert the input signal inp into a first differential signal out1_p and a second differential signal out1_n based on the reference signal Vref; the comparator 20 is connected to the pre-amplifier circuit 10, and is used to compare the first differential signal out1_p and the second differential signal out1_n, and output a comparison signal Vout1; the output control circuit 30 is connected to the pre-amplifier circuit 10 and the comparator 20, and is used to detect the common mode level of the first differential signal out1_p and the second differential signal out1_n, and when the voltage value of the common mode level is greater than or equal to a preset value, control the output of an output signal Vout2 at a first logic level, and when the voltage value of the common mode level is less than the preset value, control the output of the output signal Vout2 corresponding to the comparison signal Vout1.

[0039] It is understood that the present application adds an output control circuit 30 within the receiver to detect the common-mode level of the first differential signal out1_p and the second differential signal out1_n. When the voltage value of the common-mode level is greater than or equal to a preset value, the output is clamped to control the output of the output signal Vout2 at the first logic level, thereby preventing glitches. When the voltage value of the common-mode level is less than the preset value, the comparator 20 can operate normally and control the output of the output signal Vout2 corresponding to the comparison signal Vout1. In this way, the risk of the semiconductor device in which the receiver is located accidentally entering certain uncertain operating modes when the voltage value of the bias voltage Vbias is low (resulting in a high common-mode level of the differential signal) can be reduced, thereby improving the reliability of the semiconductor device. Here, the semiconductor device in which the receiver is located includes but is not limited to a memory. For ease of understanding, the following description uses a memory as an example.

[0040] It should be noted that the common-mode level refers to the portion shared by the two signals, i.e., the portion where the first differential signal out1_p and the second differential signal out1_n have the same amplitude and phase. The preset value can be set based on the actual operating parameters of the comparator 20. Specifically, the preset value is the critical value between the linear and nonlinear states of the comparator 20, which can be obtained through relevant testing experiments.

[0041] It should be noted that when the voltage value of the common-mode level is less than the preset value, the output signal Vout2 is a signal corresponding to the comparison signal Vout1. The signal corresponding to the comparison signal Vout1 here can be the comparison signal Vout1 or a signal converted according to the comparison signal Vout1 (for example, an inverted comparison signal corresponding to the comparison signal Vout1).

[0042] In some embodiments, the pre-amplifier circuit 10 is further configured to receive an enable signal EN_n, and convert the input signal inp into the first differential signal out1_p and the second differential signal out1_n when the enable signal EN_n is valid.

[0043] In some embodiments, the pre-amplifier circuit 10 includes a bias current generating circuit 101 and a differential signal generating circuit 102; wherein the bias current generating circuit 101 is used to receive the enable signal EN_n and the bias voltage Vbias signal, and when the enable signal EN_n is valid, generates and outputs a bias current according to the bias voltage Vbias signal; the differential signal generating circuit 102 is connected to the bias current generating circuit 101, and is used to receive the bias current, the input signal inp and the reference signal Vref, and under the control of the bias current, generates and outputs the first differential signal out1_p and the second differential signal out1_n according to the input signal inp and the reference signal Vref.

[0044] It can be understood that the bias current generating circuit 101 is used to provide a bias current to the differential signal generating circuit 102 when the enable signal EN_n is valid; when the bias current generating circuit 101 provides the bias current, the differential signal generating circuit 102 generates and outputs a first differential signal out1_p and a second differential signal out1_n according to the input signal inp and the reference signal Vref.

[0045] In some embodiments, the enable signal EN_n is active low, such as Figure 4 As shown, the bias current generating circuit 101 includes a seventh PMOS transistor MP7 and an eighth PMOS transistor MP8. The gate of the seventh PMOS transistor MP7 receives the enable signal EN_n, the source of the seventh PMOS transistor MP7 is connected to the power supply voltage VCC, the gate of the eighth PMOS transistor MP8 receives the bias voltage Vbias signal, the source of the eighth PMOS transistor MP8 is connected to the drain of the seventh PMOS transistor MP7, and the drain of the eighth PMOS transistor MP8 is connected to the differential signal generating circuit 102 to output the bias current.

[0046] It can be understood that when the enable signal EN_n is at a low level ("0"), the inverted enable signal EN is "1", the bias voltage generating circuit and the receiver are both turned on, the seventh PMOS tube MP7 is turned on, and the bias voltage Vbias starts to build up from 0 volts. When the bias voltage Vbias is low, the bias current flowing into the differential signal generating circuit 102 is large.

[0047] In some embodiments, as Figure 4 As shown, the differential signal generating circuit 102 includes a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a third resistor R3, and a fourth resistor R4. The sources of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are both connected to the drain of the eighth PMOS transistor MP8. The gate of the ninth PMOS transistor MP9 is used to receive the input signal inp, and the gate of the tenth PMOS transistor MP10 is used to receive the reference signal Vref. A first end of the third resistor R3 is connected to the drain of the ninth PMOS transistor MP9, and a second end of the third resistor R3 is connected to the ground terminal VSS. A first end of the fourth resistor R4 is connected to the drain of the tenth PMOS transistor MP10, and a second end of the fourth resistor R4 is connected to the ground terminal VSS. The drain of the ninth PMOS transistor MP9 is used to output the first differential signal out1_p, and the drain of the tenth PMOS transistor MP10 is used to output the second differential signal out1_n.

[0048] It can be understood that when the bias voltage Vbias is low, the bias current output by the bias current generating circuit 101 is relatively large, and the bias current flowing through the ninth PMOS transistor MP9 branch and the tenth PMOS transistor MP10 branch are both relatively large. The generated first differential signal out1_p and second differential signal out1_n are both pulled to a high level, causing the comparator 20 to exceed its operating range and fail to perform normal comparison. This makes the output of the comparator 20 uncertain, that is, the output of the comparator 20 is unrelated to the input signal inp, and the output value is different each time, causing the memory to unexpectedly enter certain uncertain operating modes. When the bias voltage Vbias is established, the bias current output by the bias current generating circuit 101 is relatively reduced, causing the first differential signal out1_p and second differential signal out1_n generated by the differential signal generating circuit 102 to be pulled to a low level, and the comparator 20 can operate normally and the signal can flow normally.

[0049] It should be noted that the input signal inp is generally emitted by a system on chip (SOC) or a memory physical layer (PHY), and is sent to the receiver's pre-amplifier circuit 10 via a printed circuit board. The input signal inp is a small-amplitude signal with a low common-mode point. The common-mode level of the input signal inp is variable, ranging from 150mV±100mV to 200mV±100mV. The first differential signal out1_p and the second differential signal out1_n, converted from the input signal inp, have fixed voltage values ​​and fixed amplitudes. The voltage of the first differential signal out1_p is determined by the current flowing through the ninth PMOS transistor MP9 and the resistance of the third resistor R3. The voltage of the second differential signal out1_n is determined by the current flowing through the tenth PMOS transistor MP10 and the resistance of the fourth resistor R4.

[0050] It can be understood that in the receiver provided in the embodiment of the present application, the pre-amplifier circuit 10 converts the input signal inp with an uncertain external common mode point into a first differential signal out1_p and a second differential signal out1_n with a determined internal common mode point; the comparator 20 is a gain stage, which can operate under relatively fixed input conditions to achieve a larger gain. When the voltage value of the first differential signal out1_p is greater than the voltage value of the second differential signal out1_n, the comparator 20 outputs a high level; when the voltage value of the first differential signal out1_p is less than the voltage value of the second differential signal out1_n, the comparator 20 outputs a low level.

[0051] It should be noted that the input signal inp is converted into a logic level signal after passing through the receiver. The logic level signal can be used to decode commands, control the working mode of the memory, etc.

[0052] In some embodiments, the output control circuit 30 includes a common-mode detection circuit 301 and a logic operation circuit 302; wherein the common-mode detection circuit 301 is connected to the pre-amplifier circuit 10, and is used to receive the first differential signal out1_p and the second differential signal out1_n, and detect the common-mode level of the first differential signal out1_p and the second differential signal out1_n, and generate and output a clamp signal En_int according to the common-mode level; when the voltage value of the common-mode level is greater than or equal to the preset value, the clamp signal En_int is output at a valid .... When the voltage value is less than the preset value, the clamping signal at an invalid level is output; the logic operation circuit 302 is connected to the common-mode detection circuit 301 and the comparator 20, and is used to perform a logic operation on the comparison signal Vout1 and the clamping signal En_int, and generate and output the output signal Vout2; wherein, when the clamping signal En_int is at a valid level, the output signal Vout2 at the first logic level is generated and output, and when the clamping signal En_int is at an invalid level, the output signal Vout2 corresponding to the comparison signal Vout1 is generated and output.

[0053] Specifically, when the clamp signal En_int is at an active level, that is, when the voltage value of the common-mode level is greater than or equal to a preset value, the value of the comparison signal Vout1 output by the comparator 20 is uncertain, which can easily cause glitches and cause the memory to enter an uncertain operating mode. In this case, the output of the logic operation circuit 302 is clamped by the clamp signal En_int, so that the output signal Vout2 output by the logic operation circuit 302 is at a first logic level, which can avoid glitches. When the clamp signal En_int is at an inactive level, that is, when the voltage value of the common-mode level is less than a preset value, the comparator 20 can operate normally. In this case, the output of the logic operation circuit 302 is released by the clamp signal En_int, so that the output signal Vout2 output by the logic operation circuit 302 is a signal corresponding to the comparison signal Vout1, and the signal can flow normally.

[0054] It should be noted that the invalid level and the valid level include: the invalid level is a low level ("0"), and the valid level is a high level ("1"); or, the invalid level is a high level ("1"), and the valid level is a low level ("0"). In some embodiments, the valid level of the clamp signal En_int is a low level ("0"), and the first logic level is a low level ("0"); the logic operation circuit 302 includes an AND gate 3021, the two input terminals of the AND gate 3021 are respectively used to receive the comparison signal Vout1 and the clamp signal En_int, and the output terminal of the AND gate 3021 is used to output the output signal Vout2.

[0055] Specifically, when the logic operation circuit 302 includes the AND gate 3021 , the truth table of each signal in the logic operation circuit 302 is as shown in Table 1, where “0” represents a logic low level and “1” represents a logic high level.

[0056] Table 1

[0057]

[0058] It is understood that when the logic operation circuit 302 includes the AND gate 3021, when the value of the clamp signal En_int is "0", regardless of whether the output value of the comparison signal Vout1 is "0" or "1", the output value of the output signal Vout2 is always "0", that is, the output of the logic operation circuit 302 is clamped to the first logic level ("0"). When the value of the clamp signal En_int is "1", if the output value of the comparison signal Vout1 is "0", the output value of the output signal Vout2 is "0"; if the output value of the comparison signal Vout1 is "1", the output value of the output signal Vout2 is "1", that is, the output signal Vout2 is the signal corresponding to the comparison signal Vout1 (i.e., the comparison signal Vout1 itself).

[0059] It is understood that Table 1 uses the example of an active level of "0" and an inactive level of "1" for illustrative purposes. The present application is not limited thereto; in other embodiments, the active level may be "1" and the inactive level may be "0." In this case, to achieve the corresponding logic control function, the logic operation circuit 302 may include other logic gates other than the AND gate 3021 or a combination of other logic gates, such as a combination of a NOT gate and an AND gate 3021. The clamp signal En_int passes through the NOT gate and is connected to one input of the AND gate 3021. The comparison signal Vout1 is connected to the other input of the AND gate 3021. The output of the AND gate outputs the output signal Vout2.

[0060] Next, see Figure 5, is a schematic diagram of the specific composition structure of the common-mode detection circuit 301 provided in an embodiment of the present application, wherein the common-mode detection circuit 301 includes a detection circuit 303, an output circuit 35, and a feedback circuit 36; the detection circuit 303 is configured to receive the enable signal EN_n, the first differential signal out1_p, and the second differential signal out1_n, and when the enable signal EN_n is valid, detect the common-mode level of the first differential signal out1_p and the second differential signal out1_n, and output the common-mode level from the output terminal Vout3 of the detection circuit 303; when the enable signal EN_n is invalid, set the output terminal Vout3 of the detection circuit 303 to a second logic level; the output circuit 35 is configured to receive the enable signal EN_n, the first differential signal out1_p, and the second differential signal out1_n, and output the common-mode level from the output terminal Vout3 of the detection circuit 303; when the enable signal EN_n is invalid, set the output terminal Vout3 of the detection circuit 303 to a second logic level; 35 is connected to the detection circuit 303, and is used to receive the common-mode level. When the voltage value of the common-mode level is greater than or equal to the preset value, the clamping signal En_int is output at a valid level; when the voltage value of the common-mode level is less than the preset value, the clamping signal En_int is output at an invalid level. The feedback circuit 36 ​​is connected to the detection circuit 303 and the output circuit 35, and is used to receive the clamping signal En_int. When the clamping signal En_int is at an invalid level, the output terminal Vout3 of the detection circuit 303 is set to a third logic level. The voltage value of the second logic level is higher than the preset value, and the voltage value of the third logic level is lower than the preset value.

[0061] It can be understood that when the enable signal EN_n is invalid, the output terminal Vout3 of the detection circuit 303 is set to the second logic level, and the voltage value of the second logic level is higher than the preset value. The output circuit 35 outputs the clamping signal En_int at the valid level. The clamping signal En_int at the valid level clamps the output of the logic operation circuit 302, so that the output signal Vout2 output by the logic operation circuit 302 is at the first logic level, which can avoid the generation of glitches.

[0062] It can be understood that when the clamp signal En_int is at an invalid level, the output terminal Vout3 of the detection circuit 303 is set to a third logic level, and the voltage value of the third logic level is lower than the preset value. The output circuit 35 continues to output the clamp signal En_int at an invalid level, forming positive feedback, and maintaining the output terminal Vout3 of the detection circuit 303 at the third logic level.

[0063] In some embodiments, the detection circuit 303 is further configured to receive the clamp signal En_int, and stop detecting the common mode level of the first differential signal out1_p and the second differential signal out1_n when the clamp signal En_int is at an invalid level.

[0064] It is understandable that when the clamp signal En_int is at an invalid level, that is, the common mode voltage is less than a preset value, the comparator 20 can operate normally and stop detecting the common mode levels of the first differential signal out1_p and the second differential signal out1_n.

[0065] In some embodiments, the detection circuit 303 includes an input circuit 31, a voltage divider detection circuit 32, an isolation circuit 34, and a reset circuit 33; the input circuit 31 is used to receive the clamp signal En_int, the first differential signal out1_p, and the second differential signal out1_n, and when the clamp signal En_int is at a valid level, output the first differential signal out1_p and the second differential signal out1_n to the voltage divider detection circuit 32; when the clamp signal En_int is at an invalid level, stop outputting the first differential signal out1_p and the second differential signal out1_n; the voltage divider detection circuit 32 is coupled to the input circuit 31, and is used to receive the first differential signal out1 _p and the second differential signal out1_n, performs voltage division detection on the first differential signal out1_p and the second differential signal out1_n to obtain the common mode level, and outputs the common mode level from the output terminal Vout3 of the detection circuit 303; the isolation circuit 34 is connected between the input circuit 31 and the voltage division detection circuit 32, for receiving the enable signal EN_n, and isolating the input circuit 31 from the voltage division detection circuit 32 when the enable signal EN_n is invalid; the reset circuit 33 is connected to the voltage division detection circuit 32, for receiving the enable signal EN_n, and setting the output terminal Vout3 of the detection circuit 303 to the second logic level when the enable signal EN_n is invalid.

[0066] It can be understood that in this embodiment, when the enable signal EN_n is invalid or disabled (EN_n=1), the inverted enable signal EN=0, that is, the receiver is in the shutdown mode, the reset circuit 33 is turned on, and the output terminal Vout3 of the detection circuit 303 is provided with an initial voltage value (second logic level) through the reset circuit 33; the reset circuit 33 is isolated from the input circuit 31 by the isolation circuit 34 to prevent the detection circuit 303 from generating leakage in the shutdown mode; according to the voltage value of the output terminal Vout3 of the detection circuit 303, the clamping signal En_int output by the output circuit 35 is controlled to be a valid level ("0"), so that the output of the output control circuit 30 is clamped to avoid glitches; when the clamping signal En_int is at a valid level, the input circuit 31 is controlled to be turned on and start receiving the first differential signal out1_p and the second differential signal out1_n.

[0067] Then, the enable signal EN_n is controlled to be valid (EN_n=0), and the inverted enable signal EN=1, so that the bias voltage generating circuit and the receiver both exit the shutdown mode, the reset circuit 33 is turned off, and the first differential signal out1_p and the second differential signal out1_n are generated by the pre-amplifier circuit 10; the AC component (AC value) of the first differential signal out1_p and the second differential signal out1_n are filtered out by the voltage divider detection circuit 32, and the DC component (DC value) of the first differential signal out1_p and the second differential signal out1_n is retained; since the bias voltage Vbias is established from 0 volts, the bias voltage Vbias is small in the initial stage of establishment. The bias current is large. During the establishment process, the bias voltage Vbias gradually increases and tends to be stable, causing the bias current to gradually decrease. The voltage value of the common-mode level of the first differential signal out1_p and the second differential signal out1_n will decrease accordingly. Until the clamp signal En_int output by the output circuit 35 jumps from the valid level to the invalid level, the control input circuit 31 is turned off and stops receiving the first differential signal out1_p and the second differential signal out1_n; when the clamp signal En_int jumps from the valid level to the invalid level, the control feedback circuit 36 ​​is turned on to form positive feedback, thereby maintaining the output terminal Vout3 of the detection circuit 303 at the third logic level.

[0068] Specifically, in some embodiments, the input circuit 31 includes a first PMOS transistor MP1 and a second PMOS transistor MP2, the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both used to receive the clamping signal En_int, the source of the first PMOS transistor MP1 is used to receive the first differential signal out1_p, the source of the second PMOS transistor MP2 is used to receive the second differential signal out1_n, and the drains of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the isolation circuit 34.

[0069] It can be understood that the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both used to receive the clamp signal En_int, that is, the opening and closing of the input circuit 31 are determined by the voltage value of the clamp signal En_int. When the clamp signal En_int is at a valid level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on to receive the first differential signal out1_p and the second differential signal out1_n; when the clamp signal En_int is at an invalid level, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned off to stop receiving the first differential signal out1_p and the second differential signal out1_n.

[0070] In some embodiments, the isolation circuit 34 includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both used to receive the enable signal EN_n. The source of the third PMOS transistor MP3 is connected to the drain of the first PMOS transistor MP1, the source of the fourth PMOS transistor MP4 is connected to the drain of the second PMOS transistor MP2, and the drains of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the voltage divider detection circuit 32.

[0071] It can be understood that the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both used to receive the enable signal EN_n, that is, the opening and closing of the isolation circuit 34 is determined by the voltage value of the enable signal EN_n. When the enable signal EN_n is invalid or disabled (EN_n=1), the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, isolating the input circuit 31 and the reset circuit 33 to prevent leakage; when the enable signal EN_n is valid (EN_n=0), the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned on, transmitting the first differential signal out1_p and the second differential signal out1_n to the voltage divider detection circuit 32.

[0072] In some embodiments, the voltage divider detection circuit 32 includes a first resistor R1 and a second resistor R2, the first end of the first resistor R1 is connected to the drain of the third PMOS transistor MP3, the first end of the second resistor R2 is connected to the drain of the fourth PMOS transistor MP4, and the connection node between the second end of the first resistor R1 and the second end of the second resistor R2 is the output end Vout3 of the detection circuit 303.

[0073] It can be understood that the first resistor R1 and the second resistor R2 respectively form a low-pass filter with the parasitic capacitance on the output terminal Vout3 of the detection circuit 303, thereby filtering out the AC component (AC value) of the first differential signal out1_p and the second differential signal out1_n, and retaining the DC component (DC value) of the first differential signal out1_p and the second differential signal out1_n, so as to obtain the common-mode level of the first differential signal out1_p and the second differential signal out1_n at the output terminal Vout3 of the detection circuit 303.

[0074] In some embodiments, the reset circuit 33 includes a fifth PMOS transistor MP5, a gate of the fifth PMOS transistor MP5 is used to receive an inverted enable signal EN corresponding to the enable signal EN_n, a source of the fifth PMOS transistor MP5 is connected to the power supply voltage VCC, and a drain of the fifth PMOS transistor MP5 is connected to the output terminal Vout3 of the detection circuit 303.

[0075] It can be understood that the opening and closing of the reset circuit 33 is determined by the voltage value of the inverted enable signal EN. When the inverted enable signal EN=0, the fifth PMOS transistor MP5 is turned on and provides an initial voltage value (second logic level) to the output terminal Vout3 of the detection circuit 303; when the inverted enable signal EN=1, the bias voltage generating circuit and the receiver both exit the shutdown mode. At this time, the fifth PMOS transistor MP5 is turned off, and the voltage value of the output terminal Vout3 of the detection circuit 303 is provided by the common mode level of the first differential signal out1_p and the second differential signal out1_n.

[0076] It should be noted that, in this embodiment, the isolation circuit 34 is arranged between the input circuit 31 and the voltage divider detection circuit 32, but the present application is not limited to this. In other embodiments, the isolation circuit 34 can also be arranged between the voltage divider detection circuit 32 and the reset circuit 33 (that is, the positions of the third PMOS tube MP3 and the first resistor R1 are swapped, and the positions of the fourth PMOS tube MP4 and the second resistor R2 are swapped), as long as the input circuit 31 and the reset circuit 33 can be isolated to avoid leakage.

[0077] In some embodiments, the output circuit 35 includes a sixth PMOS transistor MP6 and a first NMOS transistor MN1. The gates of the sixth PMOS transistor MP6 and the first NMOS transistor MN1 are both connected to the output terminal Vout3 of the detection circuit 303. The source of the sixth PMOS transistor MP6 is connected to the power supply voltage VCC. The drain of the sixth PMOS transistor MP6 is connected to the source of the first NMOS transistor MN1. The connection between the drain of the sixth PMOS transistor MP6 and the source of the first NMOS transistor MN1 forms the clamping signal En_int. The drain of the first NMOS transistor MN1 is connected to the ground terminal VSS.

[0078] It can be understood that the sixth PMOS transistor MP6 and the first NMOS transistor MN1 form an inverter, and the turning on and off of the sixth PMOS transistor MP6 and the first NMOS transistor MN1 is determined by the voltage value of the output terminal Vout3 of the detection circuit 303. When the output terminal Vout3 of the detection circuit 303 is at the initial voltage value (the second logic level), that is, when the voltage value of the output terminal Vout3 of the detection circuit 303 is greater than the preset value, the sixth PMOS transistor MP6 is turned off and the first NMOS transistor MN1 is turned on, so that the output clamp signal En_int is at a valid level (“0”); when the voltage value of the output terminal Vout3 of the detection circuit 303 decreases to less than the preset value, the sixth PMOS transistor MP6 is turned on and the first NMOS transistor MN1 is turned off, so that the output clamp signal En_int is at an invalid level (“1”). The flip threshold of the inverter corresponds to the preset value, that is, the threshold for flipping from "the sixth PMOS transistor MP6 is turned off and the first NMOS transistor MN1 is turned on" to "the sixth PMOS transistor MP6 is turned on and the first NMOS transistor MN1 is turned off" is set according to the preset value. Specifically, the threshold can be determined by designing structural features such as the width-to-length ratio of the sixth PMOS transistor MP6 and the first NMOS transistor MN1, which will not be described in detail here.

[0079] In some embodiments, the feedback circuit 36 ​​includes a second NMOS transistor MN2, a gate of the second NMOS transistor MN2 is used to receive the clamping signal En_int, a source of the second NMOS transistor MN2 is connected to the output terminal Vout3 of the detection circuit 303, and a drain of the second NMOS transistor MN2 is connected to the ground terminal VSS.

[0080] It can be understood that the opening and closing of the feedback circuit 36 ​​is determined by the voltage value of the clamp signal En_int. When the clamp signal En_int is at a valid level ("0"), the second NMOS transistor MN2 is turned off; when the clamp signal En_int is at an invalid level ("1"), the second NMOS transistor MN2 is turned on, maintaining the voltage value of the output terminal Vout3 of the detection circuit 303 within a range less than a preset value (the voltage value is substantially the same as the ground terminal VSS), and forming positive feedback through the output circuit 35 to ensure that the clamp signal En_int is always at an invalid level (the third logic level).

[0081] Next, combine Figure 4 and Figure 5To illustrate the specific working process of the receiver provided in the embodiment of the present application, when the enable signal EN_n is invalid or disabled (EN_n=1), the inverted enable signal EN=0, the receiver is in shutdown mode, the seventh PMOS transistor MP7 is turned off, the first differential signal out1_p and the second differential signal out1_n are both low, and the comparator 20 has no output; the fifth PMOS transistor MP5 is turned on, providing an initial voltage value (second logic level) to the output terminal Vout3 of the detection circuit 303.

[0082] Because the output terminal Vout3 of the detection circuit 303 has an initial voltage value, the sixth PMOS transistor MP6 is controlled to be turned off and the first NMOS transistor MN1 is controlled to be turned on, so that the output clamping signal En_int is at an active level ("0"). According to Table 1, when the value of the clamping signal En_int is "0", regardless of whether the output value of the comparison signal Vout1 is "0" or "1", the output value of the output signal Vout2 is always "0", that is, the output of the logic operation circuit 302 is clamped to the first logic level ("0").

[0083] Because the clamp signal En_int is at an active level ("0"), the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on. If the reset circuit 33 is not isolated from the input circuit 31, a current path will flow from the fifth PMOS transistor MP5 to the first resistor R1, to the first PMOS transistor MP1, to the third resistor R3, and to the ground terminal VSS. Furthermore, a current path will flow from the fifth PMOS transistor MP5 to the second resistor R2, to the second PMOS transistor MP2, to the fourth resistor R4, and to the ground terminal VSS, which may cause leakage. In the present application, by providing an isolation circuit 34, when the enable signal EN_n is invalid (EN_n=1), the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are turned off, thereby isolating the input circuit 31 from the reset circuit 33, cutting off the current path from the fifth PMOS transistor MP5 to the first resistor R1 to the first PMOS transistor MP1 to the third resistor R3 to the ground terminal VSS, and cutting off the current path from the fifth PMOS transistor MP5 to the second resistor R2 to the second PMOS transistor MP2 to the fourth resistor R4 to the ground terminal VSS, thereby preventing leakage.

[0084] Then, the enable signal EN_n is controlled to be valid (EN_n=0), and the inverted enable signal EN=1. The receiver exits the shutdown mode, the fifth PMOS transistor MP5 is turned off, and the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the seventh PMOS transistor MP7 are turned on. The bias voltage Vbias starts to build up from 0 volts. When the bias voltage Vbias is low, the bias current flowing into the differential signal generating circuit 102 is large. When the bias current is large, the bias current flowing through the ninth PMOS transistor MP9 branch and the tenth PMOS transistor MP10 branch are both large. The generated first differential signal out1_p and second differential signal out1_n are both pulled to a high level, causing the comparator 20 to exceed the operating range and fail to perform normal comparison. The output of the comparator 20 is uncertain. However, because the output of the logic operation circuit 302 is clamped, the output of the comparator 20 does not affect the output of the logic operation circuit 302, and no glitches are generated, thereby preventing the memory from accidentally entering certain uncertain operating modes.

[0085] When the bias current is large, the common-mode level of the first differential signal out1_p and the second differential signal out1_n is greater than or equal to a preset value. At this time, the clamp signal En_int is maintained at an active level ("0"), the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, and detection is continued. The output of the logic operation circuit 302 is clamped until the common-mode level is less than the preset value. At this time, the clamp signal En_int transitions from an active level ("0") to an inactive level ("1"), the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned off, and detection is disabled. The second NMOS transistor MN2 is turned on, maintaining the common-mode level less than the preset value, ensuring that the clamp signal En_int is at an inactive level ("1"), and thus not affecting the output of the comparator 20.

[0086] The present application embodiment provides a memory, including the above-mentioned receiver. The structural diagram of the receiver is shown in FIG. Figure 4 and Figure 5 In some embodiments, the memory includes a dynamic random access memory.

[0087] like Figure 6 FIG. 1 is a flowchart of a control method for a receiver provided in an embodiment of the present application. The receiver includes: a pre-amplifier circuit, a comparator, and an output control circuit. The comparator is connected to the pre-amplifier circuit, and the output control circuit is connected to the pre-amplifier circuit and the comparator. The method includes:

[0088] S1. The pre-amplifier circuit receives an input signal and a reference signal, and converts the input signal into a first differential signal and a second differential signal based on the reference signal;

[0089] S2. The comparator compares the first differential signal with the second differential signal and outputs a comparison signal;

[0090] S3. The output control circuit detects the common-mode level of the first differential signal and the second differential signal, and when the voltage value of the common-mode level is greater than or equal to a preset value, controls the output of an output signal at a first logic level, and when the voltage value of the common-mode level is less than the preset value, controls the output of the output signal corresponding to the comparison signal.

[0091] It is understood that this embodiment detects the common-mode level of the first differential signal and the second differential signal. When the voltage value of the common-mode level is greater than or equal to a preset value, the output is clamped, controlling the output signal to be at the first logic level, thereby preventing glitches. When the voltage value of the common-mode level is less than the preset value, the comparator can operate normally and control the output signal corresponding to the comparison signal. This reduces the risk of the semiconductor device in which the receiver is located accidentally entering certain uncertain operating modes when the bias voltage is low, thereby improving the reliability of the semiconductor device. Here, the semiconductor device in which the receiver is located includes but is not limited to a memory.

[0092] In summary, an embodiment of the present application provides a receiver, comprising a pre-amplifier circuit, a comparator, and an output control circuit; the pre-amplifier circuit is used to receive an input signal and a reference signal, and convert the input signal into a first differential signal and a second differential signal based on the reference signal; the comparator is connected to the pre-amplifier circuit, and is used to compare the first differential signal and the second differential signal, and output a comparison signal; the output control circuit is connected to the pre-amplifier circuit and the comparator, and is used to detect the common-mode level of the first differential signal and the second differential signal, and when the voltage value of the common-mode level is greater than or equal to a preset value, control the output of an output signal at a first logic level, and when the voltage value of the common-mode level is less than the preset value, control the output of an output signal corresponding to the comparison signal; the present application adds an output control circuit in the receiver. The output control circuit detects the common-mode level of the first differential signal and the second differential signal. When the voltage value of the common-mode level is greater than or equal to a preset value, the output is clamped to control the output to be an output signal at the first logic level without generating glitches. When the voltage value of the common-mode level is less than the preset value, the comparator can operate normally and control the output to be an output signal corresponding to the comparison signal. In this way, the risk of the semiconductor device where the receiver is located accidentally entering certain uncertain operating modes when the voltage value of the bias voltage is low can be reduced, thereby improving the reliability of the semiconductor device and solving the technical problem that when the voltage value of the bias voltage is low, the output of the comparator in the receiver is prone to glitches, causing the semiconductor device (such as a memory) where the receiver is located to accidentally enter certain uncertain operating modes.

[0093] The above description is merely a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application.

Claims

1. A receiver, characterized in that: include: a pre-amplifier circuit, configured to receive an input signal and a reference signal, and convert the input signal into a first differential signal and a second differential signal based on the reference signal; a comparator, connected to the pre-amplifier circuit, configured to compare the first differential signal with the second differential signal and output a comparison signal; an output control circuit, connected to the pre-amplifier circuit and the comparator, configured to detect a common-mode level of the first differential signal and the second differential signal, and control output of an output signal at a first logic level when a voltage value of the common-mode level is greater than or equal to a preset value, and control output of an output signal corresponding to the comparison signal when a voltage value of the common-mode level is less than the preset value; The output control circuit includes a common mode detection circuit and a logic operation circuit; wherein, The common-mode detection circuit is connected to the pre-amplification circuit, and is configured to receive the first differential signal and the second differential signal, detect the common-mode level of the first differential signal and the second differential signal, and generate and output a clamp signal according to the common-mode level; when the voltage value of the common-mode level is greater than or equal to the preset value, output the clamp signal at a valid level; when the voltage value of the common-mode level is less than the preset value, output the clamp signal at an invalid level; The logic operation circuit is connected to the common-mode detection circuit and the comparator, and is used to perform a logic operation on the comparison signal and the clamp signal to generate and output the output signal; wherein, when the clamp signal is at a valid level, the output signal at the first logic level is generated and output, and when the clamp signal is at an invalid level, the output signal corresponding to the comparison signal is generated and output.

2. The receiver according to claim 1, wherein The pre-amplifier circuit is further configured to receive an enable signal, and when the enable signal is valid, convert the input signal into the first differential signal and the second differential signal.

3. The receiver according to claim 2, wherein: The pre-amplification circuit includes a bias current generating circuit and a differential signal generating circuit; wherein, The bias current generating circuit is configured to receive the enable signal and the bias voltage signal, and generate and output a bias current according to the bias voltage signal when the enable signal is valid; The differential signal generating circuit is connected to the bias current generating circuit, and is configured to receive the bias current, the input signal, and the reference signal, and generate and output the first differential signal and the second differential signal according to the input signal and the reference signal under the control of the bias current.

4. The receiver according to claim 2, wherein: The common mode detection circuit comprises: a detection circuit, configured to receive the enable signal, the first differential signal, and the second differential signal, detect the common mode level of the first differential signal and the second differential signal when the enable signal is valid, and output the common mode level from an output terminal of the detection circuit; and set the output terminal of the detection circuit to a second logic level when the enable signal is invalid; an output circuit, connected to the detection circuit, configured to receive the common-mode level, and output the clamp signal at a valid level when the voltage value of the common-mode level is greater than or equal to the preset value; and output the clamp signal at an invalid level when the voltage value of the common-mode level is less than the preset value; a feedback circuit connected to the detection circuit and the output circuit, configured to receive the clamp signal and set the output end of the detection circuit to a third logic level when the clamp signal is at an invalid level; The voltage value of the second logic level is higher than the preset value, and the voltage value of the third logic level is lower than the preset value.

5. The receiver according to claim 4, wherein: The detection circuit is further configured to receive the clamp signal and stop detecting the common mode level of the first differential signal and the second differential signal when the clamp signal is at an invalid level.

6. The receiver according to claim 5, characterized in that The detection circuit includes: an input circuit, a voltage division detection circuit, an isolation circuit and a reset circuit; The input circuit is configured to receive the clamp signal, the first differential signal, and the second differential signal, and output the first differential signal and the second differential signal to the voltage division detection circuit when the clamp signal is at a valid level; and stop outputting the first differential signal and the second differential signal when the clamp signal is at an invalid level; The voltage division detection circuit is coupled to the input circuit, and is configured to receive the first differential signal and the second differential signal, perform voltage division detection on the first differential signal and the second differential signal to obtain the common mode level, and output the common mode level from an output terminal of the detection circuit; The isolation circuit is connected between the input circuit and the voltage-dividing detection circuit, and is used to receive the enable signal and isolate the input circuit from the voltage-dividing detection circuit when the enable signal is invalid; The reset circuit is connected to the voltage-dividing detection circuit, and is configured to receive the enable signal and set the output end of the detection circuit to the second logic level when the enable signal is invalid.

7. The receiver according to claim 6, wherein: The input circuit includes a first PMOS transistor and a second PMOS transistor, wherein the gates of the first PMOS transistor and the second PMOS transistor are both used to receive the clamping signal, the source of the first PMOS transistor is used to receive the first differential signal, the source of the second PMOS transistor is used to receive the second differential signal, and the drains of the first PMOS transistor and the second PMOS transistor are both connected to the isolation circuit.

8. The receiver according to claim 7, wherein: The isolation circuit includes a third PMOS transistor and a fourth PMOS transistor, the gates of the third PMOS transistor and the fourth PMOS transistor are both used to receive the enable signal, the source of the third PMOS transistor is connected to the drain of the first PMOS transistor, the source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, and the drains of the third PMOS transistor and the fourth PMOS transistor are both connected to the voltage divider detection circuit.

9. The receiver according to claim 8, wherein The voltage divider detection circuit includes a first resistor and a second resistor, the first end of the first resistor is connected to the drain of the third PMOS tube, the first end of the second resistor is connected to the drain of the fourth PMOS tube, and the connection node between the second end of the first resistor and the second end of the second resistor is the output end of the detection circuit.

10. The receiver according to claim 9, wherein The reset circuit includes a fifth PMOS transistor, the gate of the fifth PMOS transistor is used to receive an inverted enable signal corresponding to the enable signal, the source of the fifth PMOS transistor is connected to the power supply voltage, and the drain of the fifth PMOS transistor is connected to the output end of the detection circuit.

11. The receiver according to claim 10, wherein: The output circuit includes a sixth PMOS transistor and a first NMOS transistor. The gates of the sixth PMOS transistor and the first NMOS transistor are both connected to the output end of the detection circuit. The source of the sixth PMOS transistor is connected to the power supply voltage. The drain of the sixth PMOS transistor is connected to the source of the first NMOS transistor. The connection between the drain of the sixth PMOS transistor and the source of the first NMOS transistor forms the clamping signal. The drain of the first NMOS transistor is connected to the ground end.

12. The receiver according to claim 11, wherein The feedback circuit includes a second NMOS transistor, a gate of the second NMOS transistor is used to receive the clamping signal, a source of the second NMOS transistor is connected to the output end of the detection circuit, and a drain of the second NMOS transistor is connected to the ground end.

13. The receiver according to claim 1, wherein The effective level of the clamping signal is a low level, and the first logic level is a low level; the logic operation circuit includes an AND gate, the two input ends of the AND gate are respectively used to receive the comparison signal and the clamping signal, and the output end of the AND gate is used to output the output signal.

14. The receiver according to claim 3, wherein The bias current generating circuit includes a seventh PMOS transistor and an eighth PMOS transistor. The gate of the seventh PMOS transistor receives the enable signal, the source of the seventh PMOS transistor is connected to the power supply voltage, the gate of the eighth PMOS transistor receives the bias voltage signal, the source of the eighth PMOS transistor is connected to the drain of the seventh PMOS transistor, and the drain of the eighth PMOS transistor is connected to the differential signal generating circuit to output the bias current.

15. The receiver according to claim 14, wherein The differential signal generating circuit includes a ninth PMOS transistor, a tenth PMOS transistor, a third resistor, and a fourth resistor. The sources of the ninth PMOS transistor and the tenth PMOS transistor are both connected to the drain of the eighth PMOS transistor. The gate of the ninth PMOS transistor is used to receive the input signal. The gate of the tenth PMOS transistor is used to receive the reference signal. A first end of the third resistor is connected to the drain of the ninth PMOS transistor. A second end of the third resistor is connected to the ground. A first end of the fourth resistor is connected to the drain of the tenth PMOS transistor. A second end of the fourth resistor is connected to the ground. The drain of the ninth PMOS transistor is used to output the first differential signal, and the drain of the tenth PMOS transistor is used to output the second differential signal.

16. A memory, characterized in that: include: A receiver as claimed in any one of claims 1 to 15.

17. A method for controlling a receiver, characterized in that: The receiver includes: a pre-amplifier circuit, a comparator, and an output control circuit, the comparator is connected to the pre-amplifier circuit, and the output control circuit is connected to the pre-amplifier circuit and the comparator; the method includes: The pre-amplification circuit receives an input signal and a reference signal, and converts the input signal into a first differential signal and a second differential signal based on the reference signal; The comparator compares the first differential signal and the second differential signal and outputs a comparison signal; The output control circuit detects a common mode level of the first differential signal and the second differential signal, and controls output of an output signal at a first logic level when a voltage value of the common mode level is greater than or equal to a preset value, and controls output of the output signal corresponding to the comparison signal when the voltage value of the common mode level is less than the preset value; The output control circuit includes a common mode detection circuit and a logic operation circuit; wherein, The common-mode detection circuit is connected to the pre-amplification circuit, and is configured to receive the first differential signal and the second differential signal, detect the common-mode level of the first differential signal and the second differential signal, and generate and output a clamp signal according to the common-mode level; when the voltage value of the common-mode level is greater than or equal to the preset value, output the clamp signal at a valid level; when the voltage value of the common-mode level is less than the preset value, output the clamp signal at an invalid level; The logic operation circuit is connected to the common-mode detection circuit and the comparator, and is used to perform a logic operation on the comparison signal and the clamp signal to generate and output the output signal; wherein, when the clamp signal is at a valid level, the output signal at the first logic level is generated and output, and when the clamp signal is at an invalid level, the output signal corresponding to the comparison signal is generated and output.

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