In-memory computing circuit and resistive random access memory

Abstract

The application discloses a kind of storage computing conversion circuits, including shift addition unit, capacitor array unit, comparison unit and SAR control logic unit, by shift addition unit to the input analog signal is shifted weighted addition processing, to obtain the first voltage signal after processing;Capacitor array unit is handled to the reference voltage signal inputted from outside, to obtain the second voltage signal after processing;The first input end of comparison unit is connected with the output end of shift addition unit, the output end of comparison unit is connected with the output end of capacitor array unit, to compare first voltage signal and second voltage signal, to output comparison result;The input end of SAR control logic unit is connected with the output end of comparison unit, to output digital signal according to comparison result;Thus, by analog circuit to realize shift addition function, can reduce the delay and area overhead caused by traditional digital shift adder, to improve conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a memory-to-computer conversion circuit and a resistive random access memory. Background Technology

[0002] In related technologies, in-memory computing circuits operate on multi-bit input signals, such as... Figure 1 As shown, it is usually first split into multiple cycles of single bits, and then the single-bit data is multiplied and accumulated with the weight array. Then, the digital output signals of multiple cycles are shifted and added by an analog-to-digital converter to restore the entire multi-bit operation. The advantage of this circuit is that the data flow structure is clear and the circuit design is relatively simple. However, it requires additional digital circuits for shift and addition control, which has a large overhead in terms of area and delay, and the operation and conversion efficiency is not high. Summary of the Invention

[0003] The present invention aims to at least partially solve one of the technical problems in the aforementioned technologies. Therefore, one objective of the present invention is to provide a memory-to-computer conversion circuit that implements shift-and-add functionality using analog circuitry, thereby reducing the delay and area overhead caused by traditional digital shift-and-adder circuits and improving conversion efficiency.

[0004] To achieve the above objectives, an embodiment of the present invention proposes a memory-to-computer conversion circuit, comprising: a shift-add unit, which performs shift-weighted addition processing on an input analog signal to obtain a processed first voltage signal; a capacitor array unit, which processes an externally input reference voltage signal to obtain a processed second voltage signal; a comparison unit, wherein a first input terminal of the comparison unit is connected to the output terminal of the shift-add unit, and a second input terminal of the comparison unit is connected to the output terminal of the capacitor array unit, so as to compare the first voltage signal and the second voltage signal and output a comparison result; and a SAR control logic unit, wherein the input terminal of the SAR control logic unit is connected to the output terminal of the comparison unit, so as to output a digital signal according to the comparison result.

[0005] According to the in-memory conversion circuit proposed in this embodiment of the invention, a shift-add unit performs shift-weighted addition processing on the input analog signal to obtain a processed first voltage signal; a capacitor array unit processes an externally input reference voltage signal to obtain a processed second voltage signal; a first input terminal of a comparison unit is connected to the output terminal of the shift-add unit, and a second input terminal of the comparison unit is connected to the output terminal of the capacitor array unit, so as to compare the first voltage signal and the second voltage signal and output a comparison result; the input terminal of the SAR control logic unit is connected to the output terminal of the comparison unit, so as to output a digital signal according to the comparison result; thus, by implementing the shift-add function through an analog circuit, the delay and area overhead caused by traditional digital shift adders can be reduced, thereby improving the conversion efficiency.

[0006] In addition, the memory-to-computer conversion circuit proposed above according to the embodiments of the present invention may also have the following additional technical features:

[0007] Optionally, the shift-add unit includes a capacitor array and N control switches, each of the N control switches being disposed between each column of the capacitor array. The capacitor array includes: a first capacitor; N weighted bit capacitors, each of the N weighted bit capacitors being connected in parallel and then connected in parallel with the first capacitor; and N MOS transistors, each of the N MOS transistors being connected in series with each of the N weighted bit capacitors.

[0008] Optionally, the weights of the weighted capacitors increase sequentially from low to high with a coefficient of 2.

[0009] Optionally, when the N control switches are simultaneously turned off, the corresponding columns of the N MOS transistors are simultaneously turned on, so as to receive one input signal from multiple input signals in different columns at the same time.

[0010] Optionally, when the N control switches are closed simultaneously, the corresponding columns of the N MOS transistors are controlled to conduct, so as to receive multiple input signals at different times in the same column.

[0011] Optionally, the capacitor array unit has the same capacitor array structure as the shift-add unit.

[0012] Optionally, the capacitor array in the shift-add unit is time-division multiplexed with the capacitor array unit.

[0013] Optionally, each column of the capacitor array is provided with a corresponding control switch. The capacitor array is connected to the first input terminal of the comparator unit via a MAC switch, and the shift-add unit is connected to the second input terminal of the comparator unit via a REF switch. When all control switches are closed or all are open, and the MAC switch is closed and the REF switch is open, the capacitor array is used by the shift-add unit. When all control switches are closed, the MAC switch is open, and the REF switch is closed, the capacitor array is used by the capacitor array unit.

[0014] Optionally, it further includes: a second capacitor, one end of which is connected to the first input terminal of the comparison unit, and the other end of which is grounded; and a first MOSFET, which is connected in parallel with the second capacitor.

[0015] To achieve the above objectives, a second aspect of the present invention provides a resistive random access memory, including the memory-to-computer conversion circuit described above.

[0016] According to the resistive random access memory of the present invention, the shift-add function is implemented by analog circuitry, which can reduce the delay and area overhead caused by traditional digital shift adders, thereby improving conversion efficiency. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the existing memory-to-computer conversion circuit.

[0018] Figure 2 This is a schematic diagram of the circuit structure of a memory-to-computer conversion circuit according to an embodiment of the present invention;

[0019] Figure 3 The circuit schematic of an existing shift-adder tree digital circuit;

[0020] Figure 4 A circuit schematic diagram of an analog shift-adder circuit according to an embodiment of the present invention;

[0021] Figure 5 This is an embodiment of the present invention where different columns represent corresponding bit widths in a stored-array structure at the same time.

[0022] Figure 6 This is a circuit schematic diagram of an analog shift-adder circuit that uses different columns to represent corresponding bit widths according to an embodiment of the present invention;

[0023] Figure 7 This is an example of a storage column structure representing the corresponding bit width at different times in the same column according to an embodiment of the present invention;

[0024] Figure 8This is a circuit schematic diagram of an analog shift-adder circuit that uses the same column to represent corresponding bit widths according to an embodiment of the present invention;

[0025] Figure 9 This is a circuit schematic diagram of an in-memory conversion circuit that prepends an analog shift adder according to an embodiment of the present invention.

[0026] Figure 10 This is a circuit schematic diagram of an in-memory conversion circuit that multiplexes an analog shift array with a DAC capacitor array according to an embodiment of the present invention. Detailed Implementation

[0027] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0028] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the invention to those skilled in the art.

[0029] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0030] The memory-to-computer conversion circuit of an embodiment of the present invention will now be described with reference to the accompanying drawings.

[0031] refer to Figure 4-9 As shown, the in-memory conversion circuit proposed in this embodiment of the invention includes a shift-add unit 10, a capacitor array unit 20, a comparison unit 30, and a SAR control logic unit 40.

[0032] The shift-add unit 10 performs shift-weighted addition processing on the input analog signal to obtain a processed first voltage signal; the capacitor array unit 20 processes the externally input reference voltage signal to obtain a processed second voltage signal; the first input terminal of the comparison unit 30 is connected to the output terminal of the shift-add unit 10, and the second input terminal of the comparison unit 30 is connected to the output terminal of the capacitor array unit 20, so as to compare the first voltage signal and the second voltage signal and output the comparison result; the input terminal of the SAR control logic unit 40 is connected to the output terminal of the comparison unit 30, so as to output a digital signal according to the comparison result.

[0033] In other words, such as Figure 2 As shown, the digital circuit that performs shift-add control after analog-to-digital conversion is moved forward, and a new analog circuit is used to replace the shift-add function of the digital circuit to improve the conversion speed of the circuit. Simulation results show that in a 4-bit analog-to-digital converter circuit structure, the area of ​​the present invention can be reduced by about 10%, and the conversion efficiency (power consumption x delay) can be improved by 4 times. In addition, the improvement effect of the present invention on the conversion efficiency is more obvious as the number of bits of the input signal increases.

[0034] As an example, such as Figure 4 As shown, the shift-add unit 10 includes a capacitor array and N control switches (S0-S1). N-1 Each of the N control switches is correspondingly set between each column of the capacitor array. The capacitor array includes: a first capacitor C1, N weighted capacitors (C2-CN) and N MOSFETs (Q1-QN). Each of the N weighted capacitors (C2-CN) is connected in parallel with each other and then connected in parallel with the first capacitor C1. Each of the N MOSFETs (Q1-QN) is connected in series with each of the N weighted capacitors (C2-CN).

[0035] As an example, the weights of the weighted capacitors increase sequentially from low to high with a coefficient of 2.

[0036] It should be noted that, as Figure 3 As shown, traditional shift-add is a digital circuit, meaning that after passing through an ADC, it is... Figure 3 The circuit shown first performs register shifting and then adds the bits using a multi-bit adder tree; while the shift-add method used in this invention is as follows: Figure 4 The analog circuit shown is an analog shift-weighted adder consistent with memory-based MAC (multiply-accumulate) circuits. Its principle involves a parallel array of capacitors in a multiple relationship, controlled by a switch circuit to perform analog calculations at different time periods TO-TN (representing multiple-bit inputs, configured via Wn). The inputs can be different columns of the memory array or different periods of the same column, selectable by a switch. Compared to traditional shift-adder circuits, it is more flexible and can be time-division multiplexed with the capacitor array circuit in the analog-to-digital converter circuit. This reduces the circuit overhead of shift-adder and improves the circuit's conversion speed.

[0037] As an example, when N control switches are simultaneously turned off, the corresponding columns of N MOS transistors are simultaneously turned on, so as to receive one input signal from multiple input signals in different columns at the same time.

[0038] In other words, such as Figure 5 and Figure 6 As shown, the N control switches (S0-S1) of the shift-add unit N-1 When both are simultaneously disconnected, the MOS transistors controlled by Wn are simultaneously turned on, allowing for parallel processing and thus enabling fast processing speed.

[0039] As an example, when N control switches are closed simultaneously, the corresponding columns of N MOS transistors are turned on, so as to receive multiple input signals at different times in the same column.

[0040] In other words, such as Figure 7 and Figure 8 As shown, the N control switches (S0-S1) of the shift-add unit N-1 When both are closed, the corresponding column of the MOS transistor controlled by Wn is turned on, thereby improving accuracy.

[0041] It should be noted that the shift-add unit can be selected and used according to the accuracy requirements of the neural network hierarchy by controlling the switch.

[0042] As an example, such as Figure 9 As shown, the capacitor array unit 20 has the same capacitor array structure as the shift adder unit 10.

[0043] It should be noted that the SAR control logic unit is a successive approximation logic control, and its specific circuit adopts the existing SAR control logic unit. This invention does not make any specific limitations on this.

[0044] As an example, such as Figure 10 As shown, the capacitor array in the shift-add unit 10 is time-division multiplexed with the capacitor array unit 20.

[0045] As one example, each column in the capacitor array is equipped with a corresponding control switch, and the capacitor array is controlled by a MAC switch S. MAC The shift-add unit 10 is connected to the first input terminal of the comparator unit SA via the REF switch S. REF Connected to the second input terminal of the comparator unit SA; when all control switches are closed or all are open and the MAC switch S MAC Closed and REF switch S REF When disconnected, the capacitor array is used by the shift-add unit 10. This occurs when all control switches are closed and the MAC switch S... MAC Disconnect and REF switch S REF When closed, the capacitor array is used by capacitor array unit 20.

[0046] As one embodiment, it also includes: a second capacitor C S and the first MOSFET W S The second capacitor C SOne end is connected to the first input terminal of the comparator unit 30, and the second capacitor C S The other end is grounded; the first MOSFET W S With the second capacitor C S Parallel connection.

[0047] In other words, to save circuit area, the analog shift adder capacitor array and the DAC capacitor array in the SAR ADC circuit are time-division multiplexed. By modifying the SAR logic circuit and adding switch control logic, the originally independent analog shift adder and DAC capacitor array can be shared. The specific operation is as follows: first, control the state of the Sn switch and S... MAC S REF Disconnect the sampling for the simulated shift addition, then disconnect S. MAC Switching and controlling PMOS transistors W S Maintain the hold state while simultaneously initiating SAR control logic and closing S. REF The switch performs successive approximation comparisons and conversions, and finally outputs the calculated and converted digital signal.

[0048] In summary, the in-memory conversion circuit according to embodiments of the present invention first moves the digital circuit that performs shift-add control after analog-to-digital conversion forward, and simultaneously uses a new analog circuit to replace the shift-add function of the digital circuit. For example, the shift-add function is achieved by parallel connection of capacitor arrays of equal proportions. This reduces the delay and area overhead caused by traditional shift adders, and adds two in-memory control modes: accumulation of the same column at different times, or accumulation of different columns at the same time. This allows for the adaptation of different neural network layers to their conversion accuracy requirements; and Simultaneously, this part of the circuit is time-division multiplexed with the capacitor array circuit in the analog-to-digital converter circuit, further saving area overhead. According to layout evaluation, it can save 10% of area overhead. According to simulation results, the conversion efficiency (the product of power consumption and delay) can be improved by 4 times. For example, for a 4-bit input, the original digital shift adder requires at least 4 cycles to complete the shift and add task. Using an analog shift adder, the corresponding shift and add function can be completed in half a cycle. If the input is 8-bit precision, the corresponding conversion efficiency will be even higher.

[0049] In addition, embodiments of the present invention also propose a resistive random access memory, including the memory-to-computer conversion circuit described above.

[0050] According to the resistive random access memory of the present invention, the shift-add function is implemented by analog circuitry, which can reduce the delay and area overhead caused by traditional digital shift adders, thereby improving conversion efficiency.

[0051] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0053] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0054] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0055] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0056] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A memory-to-computer conversion circuit, characterized in that, include: A shift-add unit performs shift-weighted addition processing on the input analog signal to obtain a processed first voltage signal; A capacitor array unit processes an externally input reference voltage signal to obtain a processed second voltage signal. The comparison unit has a first input terminal connected to the output terminal of the shift-add unit and a second input terminal connected to the output terminal of the capacitor array unit, so as to compare the first voltage signal and the second voltage signal and output a comparison result. A SAR control logic unit, wherein the input terminal of the SAR control logic unit is connected to the output terminal of the comparison unit, so as to output a digital signal according to the comparison result; The shift-add unit includes a capacitor array and N control switches. Each of the N control switches is disposed between each column of the capacitor array. The capacitor array includes: First capacitor; There are N weighted capacitors, and each of the N weighted capacitors is connected in parallel with each other and then connected in parallel with the first capacitor. There are N MOS transistors, and each of the N MOS transistors is connected in series with each of the N weighted bit capacitors. Among them, the weights of the weighted capacitors increase sequentially from low to high with a coefficient of 2; When the N control switches are simultaneously turned off, the corresponding columns of the N MOS transistors are simultaneously turned on, so as to receive one input signal from multiple input signals in different columns at the same time; When the N control switches are closed simultaneously, the corresponding columns of the N MOS transistors are turned on, so as to receive multiple input signals at different times in the same column.

2. The memory-to-computer conversion circuit according to claim 1, characterized in that, The capacitor array unit has the same capacitor array structure as the shift-add unit.

3. The memory-to-computer conversion circuit according to claim 1, characterized in that, The capacitor array in the shift-add unit is time-division multiplexed with the capacitor array unit.

4. The memory-to-computer conversion circuit according to claim 3, characterized in that, Each column of the capacitor array is equipped with a corresponding control switch. The capacitor array is connected to the first input terminal of the comparator unit via a MAC switch, and the shift-add unit is connected to the second input terminal of the comparator unit via a REF switch. When all control switches are closed or all are open, and the MAC switch is closed and the REF switch is open, the capacitor array is used by the shift-add unit. When all control switches are closed, the MAC switch is open, and the REF switch is closed, the capacitor array is used by the capacitor array unit.

5. The memory-to-computer conversion circuit according to claim 4, characterized in that, Also includes: The second capacitor has one end connected to the first input terminal of the comparison unit and the other end grounded. The first MOSFET is connected in parallel with the second capacitor.

6. A resistive random access memory, characterized in that, Includes the memory-to-computer conversion circuit according to any one of claims 1-5.

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