A maximum on-time trigger circuit for a multiphase control system

Abstract

A maximum conduction time trigger circuit of a multiphase control system, characterized in that the circuit is applied to each pair of phases of the multiphase control system, and comprises a phase delay unit, a pulse generation unit and an output unit; wherein the phase delay unit generates a first delay of a previous phase pulse modulation signal and sends the first delay to the output unit; the pulse generation unit realizes the maximum conduction time limitation of the current phase based on a second delay of the previous phase pulse modulation signal and sends the maximum conduction time limitation to the output unit; the output unit realizes the inter-phase delay control and the maximum conduction time limitation of the pulse width modulation signal of the current phase simultaneously according to the first delay and the maximum conduction limitation. The present application has clear ideas, simple methods, and reasonably designed second delay time, which prevents phase delay abnormalities under large duty cycles and prevents large negative pulses of output voltage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a maximum on-time trigger circuit for a multiphase control system. Background Technology

[0002] Multiphase voltage converters (also referred to as multiphase control systems in this invention) typically consist of a group of parallel power stage devices. Each converter has independent inductors and power devices to achieve independent voltage control. The combination of multiple converters is called multiphase. Through parallel multiphase connections, each phase switches continuously at equal intervals to perform the corresponding voltage conversion function. Compared to ordinary single-phase voltage converters, multiphase voltage converters can reduce output capacitance, improve circuit thermal performance and efficiency under increased load current, and mitigate overshoot and undershoot during load transients, exhibiting excellent output characteristics. Therefore, they are widely used.

[0003] Due to the influence of the load downstream of the converter, the output voltage of the multiphase control system will undershoot when a rapid switch occurs from a lighter load to a heavier load. At this time, due to the drop in output voltage, and in order to provide sufficient energy to the system output, the output voltage EAO of the error amplifier will rise rapidly in the short time of load switching, causing the peak inductor current in the multiphase phases to increase sequentially.

[0004] Because the rise time of the peak inductor current in the multiphase circuit is extended, the conduction time of the upper power transistor in one phase of the circuit is significantly extended. As a result, the lower transistor of the next phase will continue to conduct, generating a large negative current, and ultimately slowing down the overall regulation process of the output voltage and causing excessive undershoot of the output voltage.

[0005] To address the above problems, this invention provides a maximum on-time triggering circuit for a multiphase control system. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a maximum on-time triggering circuit for a multiphase control system. While achieving phase delay, it provides a maximum on-time limit for the lower power transistor in each phase, thereby improving the circuit's response speed during load switching.

[0007] The present invention adopts the following technical solution.

[0008] The first aspect of the present invention relates to a maximum on-time triggering circuit for a multiphase control system. The circuit is applied to each phase of the multiphase control system and includes a phase delay unit, a pulse generation unit, and an output unit. The phase delay unit generates a first delay of the pulse modulation signal of the previous phase and sends the first delay to the output unit. The pulse generation unit, based on a second delay of the pulse modulation signal of the previous phase, limits the maximum on-time of the current phase and sends the maximum on-time limit to the output unit. The output unit, based on the first delay and the maximum on-time limit, simultaneously controls the inter-phase delay of the pulse width modulation signal of the current phase and limits the maximum on-time.

[0009] Preferably, the phase delay unit includes a D flip-flop and a first delay circuit; wherein, the clock terminal of the D flip-flop is connected to the previous phase pulse modulation signal, the reset terminal receives feedback from the current phase pulse modulation signal, the D terminal is connected to the inverse Q terminal, and the Q terminal is connected to the input terminal of the first delay circuit; the frequency selection terminal of the first delay circuit is connected to a frequency selection signal, and the output terminal is connected to the output unit.

[0010] Preferably, the pulse generation unit includes a NOT gate, an AND gate, a second delay circuit, and a pulse delay circuit; wherein, the input terminal of the NOT gate serves as the input terminal of the pulse generation unit, and the output terminal is connected to the first input terminal of the AND gate; the second input terminal of the AND gate is connected to the pulse width modulation signal of the previous phase, and the output terminal is connected to the input terminal of the second delay circuit; the frequency selection terminal of the second delay circuit is connected to a frequency selection signal, and the output terminal is connected to the input terminal of the pulse delay circuit; the output terminal of the pulse delay circuit is connected to the input terminal and the output unit of the pulse delay circuit respectively.

[0011] The output unit includes an OR gate and an RS flip-flop; wherein, the first and second input terminals of the OR gate are respectively connected to the output terminals of the phase delay unit and the pulse generation unit, and the output terminal is connected to the S terminal of the RS flip-flop; the R terminal of the RS flip-flop is connected to the peak signal of the inductor current, and the Q terminal outputs the pulse width modulation signal of the current phase.

[0012] Preferably, the delay time of the first delay circuit is T / N, and the delay time of the second delay circuit is T; where T is the period of steady-state operation of the multiphase control system, and N is the number of phases of the multiphase control system.

[0013] The beneficial effect of this invention is that, compared with the prior art, a maximum on-time triggering circuit for a multiphase control system provides a maximum on-time limit for the lower power transistor in each phase while achieving phase delay, thereby improving the circuit's response speed during load switching. This invention has a clear concept and simple method. By rationally designing the delay time of the second delay circuit, it prevents abnormal phase delay under large duty cycle conditions while also ensuring that the lower transistor's on-time is not too long, preventing a large negative surge in the output voltage. Attached Figure Description

[0014] Figure 1 This is a schematic diagram illustrating the principle of PWM signal generation in a multiphase control system in the prior art.

[0015] Figure 2 This is a schematic diagram of the circuit structure of a pulse width modulation signal generation unit in the prior art;

[0016] Figure 3 This is a timing diagram illustrating the output undershoot caused by a pulse width modulation signal generation unit in the prior art.

[0017] Figure 4 This is a schematic diagram of the maximum on-time trigger circuit of a multiphase control system according to the present invention;

[0018] Figure 5 This is a timing diagram of the maximum on-time trigger circuit for a multiphase control system to overcome output undershoot according to the present invention.

[0019] Figure 6 This is a timing diagram of the relevant signals in the maximum on-time trigger circuit of a multiphase control system according to the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.

[0021] Figure 1 This is a schematic diagram illustrating the PWM signal generation principle in a multiphase control system in the prior art. Figure 1 As shown, in a multiphase control system, the PWM signal of the main phase circuit is implemented by comparing the output signal EAO of the error amplifier with the inductor current sampling signal iL1. When the inductor current sampling signal reaches the voltage level of EAO, it will affect the PWM signal. <1> Toggles the PWM signal that is in a high-level state. <1> The signal drops to a low level. And PWM... <1> The rising edge of the signal is achieved through COT (Constant Off-time).

[0022] Figure 2 This is a schematic diagram of the circuit structure of a pulse width modulation signal generation unit in the prior art. For example... Figure 2As shown, each sub-phase of the multi-phase control unit generates its current phase's pulse width modulation (PWM) signal using the PWM signal of the preceding phase. Each sub-phase contains a D flip-flop, a delay circuit, and an RS flip-flop. The clock input of the D flip-flop is connected to the PWM signal of the preceding phase, the reset input receives feedback from the PWM signal of the current phase, the Q-inverse input is connected to the D input, and the Q input is connected to the input of the delay circuit. Additionally, the frequency selection input of the delay circuit receives a frequency selection signal, and its output is connected to the S input of the RS flip-flop. The R input of the RS flip-flop is connected to the inductor current peak pulse signal, and the Q input serves as the PWM signal for the current phase.

[0023] Figure 3 This is a timing diagram illustrating how a pulse width modulation signal generation unit in the prior art causes output undershoot. (Example) Figure 3 As shown, specifically taking a three-phase control system as an example, when PWM <3> When the lower transistor is in the on state and the previous phase has been in the on state for a long time, the PWM... <2> No edge was generated from low to high, meaning the second phase could not trigger the third related lower tube to open the upper tube.

[0024] In the aforementioned multiphase control circuit, when switching from a lighter load to a heavier load, as the inductor current increases, if the preceding phase remains in an on-state for an extended period, the signal for the following phase to turn on the lower-state will not be generated. This results in the following phase remaining in an on-state, generating a large negative current (i.e.,...). Figure 3 The large negative current in the circuit makes the output voltage regulation slow and the output voltage undershoot greater. To solve the above problems, we need to limit the turn-off time of the upper transistor of the multiphase control system, that is, the turn-on time of the lower transistor, according to the working state of the circuit, so as to optimize the transient response of the power supply.

[0025] Figure 4 This is a schematic diagram of the maximum on-time trigger circuit for a multiphase control system according to the present invention. Figure 4 As shown, a maximum on-time triggering circuit for a multiphase control system is disclosed. The circuit is applied to each phase of the multiphase control system and includes a phase delay unit, a pulse generation unit, and an output unit. The phase delay unit generates a first delay of the pulse modulation signal of the previous phase and sends the first delay to the output unit. The pulse generation unit, based on a second delay of the pulse modulation signal of the previous phase, limits the maximum on-time of the current phase and sends the maximum on-time limit to the output unit. The output unit, based on the first delay and the maximum on-time limit, simultaneously controls the inter-phase delay of the pulse width modulation signal of the current phase and limits the maximum on-time.

[0026] Specifically, existing technologies simply use phase delay to control the sequential delay of other sub-phases based on the PWM signal of the main phase, thereby generating the PWM signal on each phase. This invention improves upon this by adding a pulse generation unit. This unit can generate a pulse signal with a period of T+15ns through cyclic feedback, thus preventing the conduction time of the lower transistor in one sub-phase from being too long, which could cause a negative surge in the system output voltage.

[0027] Preferably, the phase delay unit includes a D flip-flop and a first delay circuit; wherein, the clock terminal of the D flip-flop is connected to the previous phase pulse modulation signal, the reset terminal receives feedback from the current phase pulse modulation signal, the D terminal is connected to the inverse Q terminal, and the Q terminal is connected to the input terminal of the first delay circuit; the frequency selection terminal of the first delay circuit is connected to a frequency selection signal, and the output terminal is connected to the output unit.

[0028] The phase delay unit of the present invention, similar to the prior art, can adjust the pulse width modulation signal of the next phase according to the state of the previous phase.

[0029] Preferably, the pulse generation unit includes a NOT gate, an AND gate, a second delay circuit, and a pulse delay circuit; wherein, the input terminal of the NOT gate serves as the input terminal of the pulse generation unit, and the output terminal is connected to the first input terminal of the AND gate; the second input terminal of the AND gate is connected to the pulse width modulation signal of the previous phase, and the output terminal is connected to the input terminal of the second delay circuit; the frequency selection terminal of the second delay circuit is connected to a frequency selection signal, and the output terminal is connected to the input terminal of the pulse delay circuit; the output terminal of the pulse delay circuit is connected to the input terminal and the output unit of the pulse delay circuit respectively.

[0030] It is understood that the pulse width modulation signal in the present invention, in the above structure, can generate a cyclic pulse within one cycle of the upper and lower power transistors being turned on and off, and refresh the logic of the cyclic pulse in the next cycle.

[0031] Figure 5 This is a timing diagram illustrating the maximum on-time trigger circuit for a multiphase control system according to the present invention, designed to overcome output undershoot. Figure 5 As shown, this invention employs a delay circuit with a delay time of T. After the pulse width modulation signal of the second phase goes high, a 15ns pulse signal is generated at point B of the circuit every delay period T, causing the signal at the S terminal of the RS latch, i.e., point C in the circuit, to go high, thereby enabling the PWM... <3> Locked to high level, i.e., the lower transistor is off and the upper transistor is on, when PWM... <3> When the upper transistor is in the on state, this pulse signal will not have any effect on the circuit, which effectively solves the problem of generating a large negative current when the lower transistor is on for a long time.

[0032] Figure 6This is a timing diagram of relevant signals in the maximum on-time trigger circuit of a multiphase control system according to the present invention. For example... Figure 6 As shown, preferably, the output unit includes an OR gate and an RS flip-flop; wherein, the first and second input terminals of the OR gate are respectively connected to the output terminals of the phase delay unit and the pulse generation unit, and the output terminal is connected to the S terminal of the RS flip-flop; the R terminal of the RS flip-flop is connected to the peak signal of the inductor current, and the Q terminal outputs the pulse width modulation signal of the current phase.

[0033] It is understood that in the method of the present invention, through the calculation of the OR gate, the pulse at point A and the pulse at point B are combined into the pulse at point C by the OR operation, thereby controlling the upper transistor of the phase circuit to be turned off and the lower transistor to be turned on at multiple pulse points, so as to limit the maximum conduction time of the lower transistor.

[0034] Preferably, the delay time of the first delay circuit is T / N, and the delay time of the second delay circuit is T; where T is the period of steady-state operation of the multiphase control system, and N is the number of phases of the multiphase control system.

[0035] It's important to note that the delay time is set to one cycle to accommodate applications with large duty cycles, where the upper transistor's on-time is relatively long. For example, at approximately 100% duty cycle, the upper transistor of the previous phase remains on for the entire cycle T, meaning the PWM controlling the upper transistor... <i-1>The signal is completely high. At this point, if the delay time is less than one cycle, it could potentially cause the next phase of the PWM to malfunction in steady state. The control of the signal-activated transistor becomes PWM. <i-1>The delay of a full steady-state period T, instead of a T / N delay, prevents the system from reaching a stable operating state. On the other hand, setting the time too long, far exceeding one period, will result in an excessively long turn-on time, generating a large negative current.

[0036] The beneficial effect of this invention is that, compared with the prior art, a maximum on-time triggering circuit for a multiphase control system provides a maximum on-time limit for the lower power transistor in each phase while achieving phase delay, thereby improving the circuit's response speed during load switching. This invention has a clear concept and simple method; by controlling the delay time of each phase in the multiphase control system, it prevents excessive voltage undershoot during unstable states such as load switching.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A maximum on-time trigger circuit for a multiphase control system, characterized in that: The circuit is applied to each phase of the multiphase control system and includes a phase delay unit, a pulse generation unit, and an output unit. The phase delay unit generates a first delay of the previous phase pulse modulation signal and sends the first delay to the output unit. The pulse generation unit limits the maximum on-time of the current phase based on the second delay of the previous phase pulse modulation signal, and sends the maximum on-time limit to the output unit. The output unit, based on the first delay and the maximum conduction time limit, simultaneously implements inter-phase delay control and maximum conduction time limit for the pulse width modulation signal of the current phase. The phase delay unit includes a D flip-flop and a first delay circuit; wherein, The clock terminal of the D flip-flop is connected to the previous phase pulse modulation signal, the reset terminal receives feedback from the current phase pulse modulation signal, the D terminal is connected to the inverse Q terminal, and the Q terminal is connected to the input terminal of the first delay circuit. The frequency selection terminal of the first delay circuit is connected to a frequency selection signal, and its output terminal is connected to the output unit.

2. The maximum on-time trigger circuit for a multiphase control system according to claim 1, characterized in that: The pulse generation unit includes NOT gates, AND gates, a second delay circuit, and a pulse delay circuit; wherein... The input terminal of the NOT gate serves as the input terminal of the pulse generation unit, and the output terminal is connected to the first input terminal of the AND gate. The second input of the AND gate is connected to the pulse width modulation signal of the previous phase, and the output is connected to the input of the second delay circuit. The frequency selection terminal of the second delay circuit is connected to a frequency selection signal, and the output terminal is connected to the input terminal of the pulse delay circuit. The output terminal of the pulse delay circuit is connected to the input terminal of the pulse delay circuit and the output unit, respectively.

3. The maximum on-time trigger circuit for a multiphase control system according to claim 2, characterized in that: The output unit includes an OR gate and an RS flip-flop; wherein... The first and second input terminals of the OR gate are respectively connected to the output terminals of the phase delay unit and the pulse generation unit, and the output terminal is connected to the S terminal of the RS flip-flop. The R terminal of the RS flip-flop is connected to the peak signal of the inductor current, and the Q terminal outputs the pulse width modulation signal of the current phase.

4. The maximum on-time trigger circuit for a multiphase control system according to claim 3, characterized in that: The delay time of the first delay circuit is T / N, and the delay time of the second delay circuit is T; Where T is the period of steady-state operation of the multiphase control system, and N is the number of phases of the multiphase control system.

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