A semiconductor dielectric layer structure and fabrication method

Abstract

This invention discloses a semiconductor dielectric layer structure and its fabrication method. The semiconductor dielectric layer structure includes a semiconductor substrate, an epitaxial layer on the surface of the substrate, multiple trenches in the epitaxial layer, a thermal oxide layer on the surface of the epitaxial layer, in-situ doped polysilicon filling the trenches, a gate oxide layer formed between the in-situ doped polysilicon and the trenches, a silicon nitride layer on the surface of the thermal oxide layer adjacent to the trenches, a first deposited oxide layer on the surface of the silicon nitride layer, a second deposited oxide layer on the surface of the first deposited oxide layer, and a portion of the second deposited oxide layer, the silicon nitride layer, and the thermal oxide layer being hollowed out to form contact holes. The bottom end of the contact hole extends to the surface of the epitaxial layer, and the bottom edge of the contact hole extends to the in-situ doped polysilicon, exposing the gate oxide layer on the inner wall of the trench. The second deposited oxide layer and the gate oxide layer together form the sidewall structure of the in-situ doped polysilicon. This invention can prevent sharp corners of the semiconductor interface from being exposed due to contact hole etching.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a semiconductor dielectric layer structure and its fabrication method. Background Technology

[0002] The Schottky barrier decreases because the charges in the semiconductor induce charges on one side of the Schottky metal. If electrons are present in the semiconductor, the Schottky metal will be positively charged. These electrons then create a mirror force pointing towards the metal. The combined effect of the electric field and the mirror force lowers the Schottky barrier. The stronger the electric field, the greater the decrease in the Schottky barrier. The reverse leakage current is exponentially related to the Schottky barrier height; as the Schottky barrier decreases, the reverse leakage current increases exponentially.

[0003] Currently, in trench MOS Schottky diodes, during contact hole etching, in order to ensure clean etching of the oxide layer, over-etching of the gate oxide layer is inevitable, thus exposing sharp corners of the semiconductor interface. Figure 1 As shown, the Schottky barrier completely replicates the exposed semiconductor interface during its formation. It is conceivable that sharp corners will inevitably appear at the Schottky barrier interface. These sharp corners will form electric field spikes when a reverse voltage is applied. The formation of these electric field spikes, under the aforementioned Schottky barrier reduction effect, will lead to a rapid increase in leakage current at the sharp corners. How to avoid or reduce the impact of sharp corners has always been a problem that needs to be solved in the design and manufacturing process of trench MOS Schottky devices. Figure 1 In the diagram: 1 represents the thermal oxide layer of the masking trench etching, 2 represents the epitaxial layer, 3 represents the gate oxide layer, 4 represents the in-situ doped polysilicon layer, and 5 represents the deposited oxide layer. Summary of the Invention

[0004] This invention provides a semiconductor dielectric layer structure and fabrication method, aiming to solve the problem of sharp corners in existing Schottky barrier interfaces.

[0005] This invention provides a semiconductor dielectric layer structure, comprising a semiconductor substrate, an epitaxial layer on the surface of the semiconductor substrate, a plurality of trenches in the epitaxial layer, a thermal oxide layer on the surface of the epitaxial layer, in-situ doped polysilicon filling the trenches, a gate oxide layer formed between the in-situ doped polysilicon and the trenches, a silicon nitride layer on the surface of the thermal oxide layer adjacent to the trenches, the filling height of the polysilicon in the trenches falling within the range of 200-400 nm above the semiconductor interface, and a first deposited oxide layer on the surface of the silicon nitride layer. The first deposited oxide layer has a second deposited oxide layer on its surface. The second deposited oxide layer, the silicon nitride layer, and a portion of the thermal oxide layer are hollowed out to form a contact hole. The first deposited oxide layer is attached to the sidewall of the contact hole. The bottom end of the contact hole extends to the surface of the epitaxial layer, exposing the epitaxial layer. The bottom edge of the bottom of the contact hole extends to the in-situ doped polysilicon, exposing the gate oxide layer on the inner wall of the trench. The second deposited oxide layer and the gate oxide layer together form the sidewall structure of the in-situ doped polysilicon.

[0006] Furthermore, the thickness of the thermal oxide layer is 27–33 nm.

[0007] Furthermore, the thickness of the silicon nitride layer is not less than 500 nm.

[0008] Furthermore, the thickness of the first deposited oxide layer is 360–440 nm.

[0009] Furthermore, the thickness of the second deposited oxide layer is 180–220 nm.

[0010] On the other hand, this application also provides a method for fabricating a semiconductor dielectric layer structure as described in any of the preceding claims, the method comprising:

[0011] Step 1: A thermal oxide layer is grown on the epitaxial layer of the semiconductor, and then a silicon nitride layer is deposited on the surface of the thermal oxide layer;

[0012] Step 2: The trench windows are etched into the thermal oxide layer and silicon nitride layer using an etching process;

[0013] Step 3: Use the window to etch trenches on the epitaxial layer, and generate a thermal oxide layer as a gate oxide layer on the inner wall of each trench;

[0014] Step 4: Deposit in-situ doped polysilicon and etch it back so that the in-situ doped polysilicon interface falls within the range of 200-400 nm above the semiconductor interface.

[0015] Step 5: Deposit on the surface of the silicon nitride layer and the in-situ doped polysilicon after the etch-back is completed to generate the first deposited oxide layer;

[0016] Step 6: Photoresist is applied and photolithography is performed on the surface of the first deposited oxide layer, and the resulting photoresist pattern serves as a masking layer for the etching of the contact holes.

[0017] Step 7: Based on the photoresist pattern, the first deposited oxide layer at the corresponding position is etched by dry etching until the silicon nitride layer and in-situ doped polysilicon are exposed to form a contact hole;

[0018] Step 8: Remove the photoresist completely and etch the exposed silicon nitride layer inside the contact hole until the exposed silicon nitride layer inside the contact hole is completely etched.

[0019] Step 9: Deposit on the surface of the in-situ doped polysilicon exposed within the first deposited oxide layer and contact holes to generate a second deposited oxide layer;

[0020] Step 10: Etch the second deposited oxide layer, with the etching depth controlled at 330±30nm. After etching, the remaining second deposited oxide layer and the gate oxide layer together form the sidewall structure of the in-situ doped polysilicon, thus obtaining the semiconductor dielectric layer structure.

[0021] Furthermore, the step of etching the first deposited oxide layer at the corresponding location using dry etching until the silicon nitride layer and in-situ doped polysilicon are exposed also includes:

[0022] The first deposited oxide layer is subjected to wet etching until the first deposited oxide layer inside the contact hole is completely etched away.

[0023] Furthermore, the exposed silicon nitride layer inside the contact hole is etched using wet etching.

[0024] Furthermore, the exposed silicon nitride layer inside the contact hole is wet-etched using phosphoric acid.

[0025] Furthermore, the second deposited oxide layer is etched using dry etching.

[0026] This invention provides a semiconductor dielectric layer structure and fabrication method. The semiconductor dielectric layer structure includes a semiconductor substrate, an epitaxial layer on the surface of the substrate, multiple trenches in the epitaxial layer, a thermal oxide layer on the surface of the epitaxial layer, in-situ doped polysilicon filling the trenches, a gate oxide layer formed between the in-situ doped polysilicon and the trenches, a silicon nitride layer on the surface of the thermal oxide layer adjacent to the trenches, the filling height of the polysilicon in the trenches falling within the range of 200-400 nm above the semiconductor interface, a first deposited oxide layer on the surface of the silicon nitride layer, a second deposited oxide layer on the surface of the first deposited oxide layer, and a portion of the second deposited oxide layer, the silicon nitride layer, and the thermal oxide layer being hollowed out to form contact holes. The sidewalls of the contact holes are attached with the first deposited oxide layer, the bottom end of the contact holes extends to the surface of the epitaxial layer, exposing the epitaxial layer, and the bottom edge of the bottom end of the contact holes extends to the in-situ doped polysilicon, exposing the gate oxide layer on the inner wall of the trenches. The second deposited oxide layer and the gate oxide layer together form the sidewall structure of the in-situ doped polysilicon. Compared to existing technologies, the semiconductor dielectric layer structure of this application forms contact holes by hollowing out a portion of the second deposited oxide layer, silicon nitride layer, and thermal oxide layer. The bottom end of the contact hole extends to the surface of the epitaxial layer, and the bottom edge of the contact hole extends to the in-situ doped polysilicon, exposing the gate oxide layer on the inner wall of the trench. The second deposited oxide layer and the gate oxide layer together form the sidewall structure of the in-situ doped polysilicon, avoiding the exposure of sharp corners of the semiconductor interface due to contact hole etching, thereby preventing sharp corners from appearing at the Schottky barrier interface and reducing the impact of Schottky barrier reduction. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of a semiconductor dielectric layer structure with sharp corners in the prior art;

[0029] Figure 2 A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0030] Figure 3 A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0031] Figure 4 A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0032] Figure 5A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0033] Figure 6 A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0034] Figure 7 A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0035] Figure 8 A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0036] Figure 9 A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0037] Figure 10 A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0038] Figure 11 A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0039] Figure 12 A schematic diagram of an embodiment of the method for fabricating a semiconductor dielectric layer structure provided by the present invention;

[0040] Figure 13 This is a schematic diagram of the semiconductor dielectric layer structure provided in an embodiment of the present invention.

[0041] Illustration: 1. Epitaxial layer; 2. Thermal oxide layer; 3. Silicon nitride layer; 4. Gate oxide layer; 5. In-situ doped polysilicon; 6. First deposited oxide layer; 7. Photoresist; 8. Second deposited oxide layer. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0044] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0045] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0046] like Figure 1 This invention provides a semiconductor dielectric layer structure, comprising a semiconductor substrate, an epitaxial layer 1 on the surface of the semiconductor substrate, the epitaxial layer 1 having a plurality of trenches, a thermal oxide layer 2 on the surface of the epitaxial layer 1, in-situ doped polysilicon 5 filling the trenches, a gate oxide layer 4 formed between the in-situ doped polysilicon 5 and the trenches, a silicon nitride layer 3 on the surface of the thermal oxide layer 2 adjacent to the trenches, the filling height of the polysilicon in the trenches falling within the range of 200-400 nm above the semiconductor interface, and a gate oxide layer 4 on the surface of the silicon nitride layer 3. A first deposited oxide layer 6 is provided on the surface of the first deposited oxide layer 6, and a second deposited oxide layer 8 is provided on the surface of the first deposited oxide layer 6. The second deposited oxide layer 8, the silicon nitride layer 3, and a portion of the thermal oxide layer 2 are hollowed out to form a contact hole. The first deposited oxide layer 6 is attached to the sidewall of the contact hole. The bottom end of the contact hole extends to the surface of the epitaxial layer 1, exposing the epitaxial layer 1. The bottom edge of the bottom of the contact hole extends to the in-situ doped polysilicon 5, exposing the gate oxide layer 4 on the inner wall of the trench. The second deposited oxide layer 8 and the gate oxide layer 4 together form the sidewall structure of the in-situ doped polysilicon 5. Compared with the prior art, the semiconductor dielectric layer structure of this application is based on the second deposited oxide layer 8, the silicon nitride layer 3, and a portion of the thermal oxide layer 2 to form contact holes. The bottom end of the contact hole extends to the surface of the epitaxial layer 1, and the bottom edge of the contact hole extends to the in-situ doped polysilicon 5, exposing the gate oxide layer 4 on the inner wall of the trench. The second deposited oxide layer and the gate oxide layer 4 together form the sidewall structure of the in-situ doped polysilicon 5, which avoids the sharp corners of the semiconductor interface being exposed due to the etching of the contact hole, so that the Schottky barrier interface will not have sharp corners, reducing the impact of the Schottky barrier reduction.

[0047] In one embodiment, the thickness of the thermal oxide layer 2 is 27-33 nm, the thickness of the silicon nitride layer 3 is not less than 500 nm, the thickness of the first deposited oxide layer 6 is 360-440 nm, and the thickness of the second deposited oxide layer 8 is 180-220 nm.

[0048] Figure 2 This is a schematic flowchart of a specific embodiment of the method for fabricating the semiconductor dielectric layer structure described above.

[0049] Step 1: Grow a thermal oxide layer 2 with a thickness of 27–33 nm on the epitaxial layer 1 of the semiconductor; then deposit a silicon nitride layer 3 with a thickness of 760–840 nm on the surface of the thermal oxide layer 2, such as... Figure 2 As shown.

[0050] Step 2, as follows Figure 3 As shown, the windows of the trenches are etched on the thermal oxide layer 2 and the silicon nitride layer 3 by an etching process, which serve as a masking layer for subsequent etching of the trenches.

[0051] Step 3, as follows Figure 4 As shown, trenches are etched on epitaxial layer 1 using a window; as Figure 5 As shown, a thermal oxide layer 2 is formed on the inner wall of each trench as the gate oxide layer 4. During trench etching, some silicon nitride will be lost, but its thickness should be ensured to be greater than 500 nm. The remaining silicon nitride thickness can be controlled by changing its deposition thickness or by adjusting the trench etching menu to improve the selectivity.

[0052] Step 4, as follows Figure 6 As shown, in-situ doped polysilicon 5 is deposited and then etched back. The interface of the in-situ doped polysilicon 5 after etching back should be controlled within the range of 200-400 nm above the semiconductor interface. Here, the semiconductor interface refers to the top of the epitaxial layer.

[0053] Step 5, as follows Figure 7 As shown, a first deposited oxide layer 6 with a thickness of 360–440 nm is deposited on the surface of the silicon nitride layer 3 and the in-situ doped polysilicon 5 after the etch-back process.

[0054] Step Six, as Figure 8 As shown, photoresist 7 is coated and photolithographically formed on the surface of the first deposited oxide layer 6, and the resulting photoresist 7 pattern serves as a masking layer for contact hole etching.

[0055] Step 7, as follows Figure 9As shown, based on the photoresist pattern 7, the first deposited oxide layer 6 at the corresponding positions is etched using dry etching until the silicon nitride layer 3 and the in-situ doped polysilicon 5 are exposed, forming contact holes. It should be noted that the loss to the silicon nitride layer 3 and the in-situ doped polysilicon 5 in this step is negligible. After dry etching, the wet etching time of the first deposited oxide layer 6 can be slightly increased to ensure that the first deposited oxide layer 6 within the contact holes is completely etched.

[0056] Step 8, as Figure 10 As shown, the photoresist 7 is completely removed; as Figure 11 As shown, wet etching with phosphoric acid is used to etch the exposed silicon nitride layer 3 inside the contact hole until the exposed silicon nitride layer 3 inside the contact hole is completely etched. In this step, the loss of the first deposited oxide layer 6 and the in-situ doped polysilicon 5 by wet etching is negligible.

[0057] Step Nine, as Figure 12 As shown, a second deposited oxide layer 8 with a thickness of 180-220 nm is deposited on the surface of the first deposited oxide layer 6 and the in-situ doped polysilicon 5 exposed in the contact hole.

[0058] Step 10, as follows Figure 13 As shown, the second deposited oxide layer 8 is etched, with the etching depth controlled at 330±30 nm. After etching, the remaining second deposited oxide layer 8 and the gate oxide layer 4 together form the sidewall structure of the in-situ doped polysilicon 5, resulting in a semiconductor dielectric layer structure. Figure 13 It can be seen that the obtained semiconductor interface has no sharp corners.

[0059] The semiconductor dielectric layer structure disclosed in this application forms a contact hole based on a portion of the second deposited oxide layer 8, silicon nitride layer 3, and thermal oxide layer 2. The bottom end of the contact hole extends to the surface of the epitaxial layer 1, and the bottom edge of the contact hole extends to the in-situ doped polysilicon 5, exposing the gate oxide layer 4 on the inner wall of the trench. The second deposited oxide layer and the gate oxide layer 4 together form the sidewall structure of the in-situ doped polysilicon 5, which avoids the sharp corners of the semiconductor interface from being exposed due to the etching of the contact hole, thereby preventing sharp corners from appearing at the Schottky barrier interface and reducing the impact of the Schottky barrier reduction.

[0060] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.

[0061] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusivity.

[0062] The term "comprises" implies that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for fabricating a semiconductor dielectric layer structure, characterized in that, The semiconductor dielectric layer structure includes a semiconductor substrate, an epitaxial layer on the surface of the semiconductor substrate, a plurality of trenches on the epitaxial layer, a thermal oxide layer on the surface of the epitaxial layer, in-situ doped polysilicon filling the trenches, a gate oxide layer formed between the in-situ doped polysilicon and the trenches, a silicon nitride layer on the surface of the thermal oxide layer adjacent to the trenches, the filling height of the polysilicon in the trenches falling within the range of 200-400 nm above the semiconductor interface, a first deposited oxide layer on the surface of the silicon nitride layer, a second deposited oxide layer on the surface of the first deposited oxide layer, a portion of the second deposited oxide layer, the silicon nitride layer, and the thermal oxide layer being hollowed out to form a contact hole, the first deposited oxide layer being attached to the sidewall of the contact hole, the bottom end of the contact hole extending to the surface of the epitaxial layer, exposing the epitaxial layer, and the bottom edge of the bottom end of the contact hole extending to the in-situ doped polysilicon, exposing the gate oxide layer on the inner wall of the trench, the second deposited oxide layer and the gate oxide layer together forming the sidewall structure of the in-situ doped polysilicon; The thickness of the thermally oxidized layer is 27–33 nm; The thickness of the silicon nitride layer is not less than 500 nm; The thickness of the first deposited oxide layer is 360–440 nm; The thickness of the second deposited oxide layer is 180–220 nm; The method for fabricating the semiconductor dielectric layer structure includes: Step 1: A thermal oxide layer is grown on the epitaxial layer of the semiconductor, and then a silicon nitride layer is deposited on the surface of the thermal oxide layer; Step 2: The trench windows are etched into the thermal oxide layer and silicon nitride layer using an etching process; Step 3: Use the window to etch trenches on the epitaxial layer, and generate a thermal oxide layer as a gate oxide layer on the inner wall of each trench; Step 4: Deposit in-situ doped polysilicon and etch it back so that the in-situ doped polysilicon interface falls within the range of 200-400 nm above the semiconductor interface. Step 5: Deposit on the surface of the silicon nitride layer and the in-situ doped polysilicon after the etch-back is completed to generate the first deposited oxide layer; Step 6: Photoresist is applied and photolithography is performed on the surface of the first deposited oxide layer, and the resulting photoresist pattern serves as a masking layer for the etching of the contact holes. Step 7: Based on the photoresist pattern, the first deposited oxide layer at the corresponding position is etched by dry etching until the silicon nitride layer and in-situ doped polysilicon are exposed to form a contact hole; Step 8: Remove the photoresist completely and etch the exposed silicon nitride layer inside the contact hole until the exposed silicon nitride layer inside the contact hole is completely etched. Step 9: Deposit on the surface of the in-situ doped polysilicon exposed within the first deposited oxide layer and contact holes to generate a second deposited oxide layer; Step 10: Etch the second deposited oxide layer, with the etching depth controlled at 330±30nm. After etching, the remaining second deposited oxide layer and the gate oxide layer together form the sidewall structure of the in-situ doped polysilicon, thus obtaining the semiconductor dielectric layer structure.

2. The method for fabricating a semiconductor dielectric layer structure according to claim 1, characterized in that, The step of etching the first deposited oxide layer at the corresponding location using dry etching until the silicon nitride layer and in-situ doped polysilicon are exposed further includes: The first deposited oxide layer is subjected to wet etching until the first deposited oxide layer inside the contact hole is completely etched away.

3. The method for fabricating a semiconductor dielectric layer structure according to claim 1, characterized in that, The exposed silicon nitride layer inside the contact hole is etched using a wet etching process.

4. The method for fabricating a semiconductor dielectric layer structure according to claim 3, characterized in that, The exposed silicon nitride layer inside the contact hole is wet-etched using phosphoric acid.

5. The method for fabricating a semiconductor dielectric layer structure according to claim 1, characterized in that, The second deposited oxide layer is etched using dry etching.

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