Capacitance mismatch detection circuit, method and detection device

Abstract

The present application relates to a capacitance mismatch detection circuit, method and detection device. The capacitance mismatch detection circuit is connected to the differential capacitance structure of the accelerometer, and the capacitance mismatch detection circuit includes an input circuit and a controller; the input circuit is respectively connected to the upper plate of the differential capacitance structure and the lower plate of the differential capacitance structure, the output end of the controller is connected to the input circuit, and the input end of the controller is connected to the middle plate of the differential capacitance structure; the input circuit is used to obtain an input signal and apply a voltage to the upper and lower plates of the differential capacitance structure according to the input signal; the controller is used to obtain the output signal of the middle plate of the differential capacitance structure, and when the output signal meets a preset condition, the capacitance mismatch quantization value of the differential capacitance structure is determined according to the input signal. The use of the capacitance mismatch detection circuit can realize the detection of the intrinsic capacitance mismatch value of the capacitive MEMS accelerometer.

Description

Technical Field

[0001] The present application relates to the field of accelerometer measurement technology, and in particular to a capacitance mismatch detection circuit, method, and detection device. Background Art

[0002] Capacitive micro-electro-mechanical system (MEMS) accelerometer is an inertial sensor used to measure the acceleration of a carrier. It is widely used in automotive electronics, aerospace, medical equipment, geological exploration and other fields.

[0003] Capacitive MEMS accelerometers primarily measure a carrier's acceleration through a differential capacitor structure. This structure consists of an upper plate, a middle plate, and a lower plate. The middle plate is located between the upper and lower plates and is equidistant from them. The upper and middle plates form one intrinsic capacitor, while the lower plate and middle plate form another.

[0004] However, due to manufacturing errors, the middle plate is not strictly located in the middle of the upper plate and the lower plate, and the capacitive MEMS accelerometer has an intrinsic capacitance mismatch phenomenon, which affects the measurement results of the capacitive MEMS accelerometer. Summary of the Invention

[0005] Based on this, the present application provides a capacitance mismatch detection circuit, method and detection device, which can detect the intrinsic capacitance mismatch value of a capacitive MEMS accelerometer.

[0006] In a first aspect, the present application provides a capacitance mismatch detection circuit. The capacitance mismatch detection circuit is connected to a differential capacitance structure of an accelerometer, and includes an input circuit and a controller; the input circuit is connected to an upper plate and a lower plate of the differential capacitance structure, respectively; an output of the controller is connected to the input circuit, and an input of the controller is connected to a middle plate of the differential capacitance structure;

[0007] An input circuit, configured to obtain an input signal and apply a voltage to the upper and lower plates of the differential capacitor structure according to the input signal;

[0008] The controller is used to obtain the output signal of the middle plate of the differential capacitor structure and determine the capacitance mismatch quantization value of the differential capacitor structure according to the input signal when the output signal meets the preset conditions.

[0009] In one embodiment, an input circuit is used to obtain an input signal and apply a first voltage to the upper plate of the differential capacitor structure and a second voltage to the lower plate of the differential capacitor structure according to the input signal; wherein the first voltage and the second voltage have opposite phases and opposite voltage values ​​during zero-bias detection, and have opposite phases and different voltage values ​​during mismatch detection; a controller is used to respectively obtain the output signal of the middle plate of the differential capacitor structure during zero-bias detection and the output signal of the middle plate of the differential capacitor structure during mismatch detection, and determine that the output signal meets a preset condition when the output signal detected by zero-bias matches the output signal detected by mismatch.

[0010] In one embodiment, the input signal includes a first input signal and a second input signal, and the input circuit includes a first input circuit and a second input circuit, the first input circuit is connected to the upper plate of the differential capacitor structure, and the second input circuit is connected to the lower plate of the differential capacitor structure; the first input circuit is used to apply a first voltage to the upper plate of the differential capacitor structure according to the first input signal; the second input circuit is used to apply a second voltage to the lower plate of the differential capacitor structure according to the second input signal.

[0011] In one embodiment, the first input circuit includes a first modulator; the first input terminal and the second input terminal of the first modulator are both connected to the controller, and the output terminal of the first modulator is connected to the upper plate of the capacitor differential structure; the first modulator is used to modulate the first modulation signal input at the second input terminal according to the first carrier signal input at the first input terminal to obtain a first voltage, and apply the first voltage to the upper plate of the differential capacitor structure; wherein the first modulation signal is 0 during zero bias detection.

[0012] In one embodiment, the second input circuit includes a second modulator; the third input terminal and the fourth input terminal of the second modulator are both connected to the controller, and the output terminal of the second modulator is connected to the lower plate of the capacitor differential structure; the second modulator is used to modulate the second modulation signal input at the fourth input terminal according to the second carrier signal input at the third input terminal to obtain a second voltage, and apply the second voltage to the lower plate of the differential capacitor structure; wherein the second modulation signal is 0 during zero bias detection.

[0013] In one embodiment, the capacitance mismatch detection circuit further includes a charge amplifier, wherein the inverting input terminal of the charge amplifier is connected to the middle plate of the capacitance differential structure, the non-inverting input terminal of the charge amplifier is grounded, and the output terminal of the charge amplifier is connected to the controller; the charge amplifier is used to amplify the output signal of the middle plate of the capacitance differential structure to obtain an amplified signal; the controller is used to use the amplified signal as the output signal, and when the output signal meets a preset condition, determine the capacitance mismatch quantization value of the differential capacitance structure according to the input signal.

[0014] In one embodiment, a charge amplifier includes: a feedback capacitor, a resistor, and an operational amplifier; the two ends of the feedback capacitor are respectively connected to the inverting input and output of the operational amplifier; the two ends of the resistor are respectively connected to the inverting input and output of the operational amplifier; the inverting input of the operational amplifier is connected to the middle plate of the capacitor differential structure, the non-inverting input of the operational amplifier is grounded, and the output of the operational amplifier is connected to a controller.

[0015] In one embodiment, the capacitance mismatch detection circuit further includes: a demodulator; an input end of the demodulator is connected to an output end of the charge amplifier, and an output end of the demodulator is connected to a controller; the demodulator is used to demodulate the output voltage of the charge amplifier to obtain a demodulated signal; and the controller is used to use the demodulated signal as an output signal, and when the output signal meets a preset condition, determine a capacitance mismatch quantization value of the differential capacitance structure according to the input signal.

[0016] In a second aspect, the present application further provides a capacitance mismatch detection method, which is applied to the capacitance mismatch detection circuit as described in the first aspect and any implementation of the first aspect. The method comprises:

[0017] Obtaining an input signal and applying a voltage to the upper and lower plates of the differential capacitor structure according to the input signal;

[0018] obtaining an output signal of a middle plate of a differential capacitor structure;

[0019] When the output signal meets the preset condition, the capacitance mismatch quantization value of the differential capacitance structure is determined according to the input signal.

[0020] In one embodiment, an input signal is obtained, and voltages are applied to the upper and lower plates of the differential capacitor structure according to the input signal, including: obtaining an input signal, applying a first voltage to the upper plate of the differential capacitor structure according to the input signal, and applying a second voltage to the lower plate of the differential capacitor structure; wherein the first voltage and the second voltage have opposite phases and opposite voltage values ​​during zero-bias detection, and have opposite phases and different voltage values ​​during mismatch detection.

[0021] In one embodiment, the capacitance mismatch detection method further includes: respectively obtaining a first output signal of the middle plate of the differential capacitance structure during zero-bias detection and a second output signal of the middle plate of the differential capacitance structure during mismatch detection, and determining that the output signal meets a preset condition when the first output signal and the second output signal match.

[0022] In a third aspect, the present application further provides a detection device, which includes the capacitance mismatch detection circuit as described in the first aspect and any implementation manner of the first aspect.

[0023] The present application provides a capacitance mismatch detection circuit, method and detection equipment, which can output a control signal (input signal) to the input circuit through a controller, so that the input circuit applies a voltage to the upper plate and the lower plate of the capacitance differential structure of the accelerometer according to the input signal, and adjusts the electrostatic force on the intermediate plate of the capacitance differential structure by adjusting the voltage applied to the upper plate and the lower plate. At the same time, the controller determines whether the electrostatic force on the intermediate plate is 0 by judging whether the output signal of the intermediate plate meets the preset conditions, and when the output signal meets the preset conditions, the capacitance mismatch quantization value of the accelerometer is calculated according to the corresponding input signal. The capacitance mismatch detection circuit provided by the present application can be adjusted by adjusting the voltage applied to the upper and lower plates of the capacitance differential structure of the accelerometer, and the capacitance mismatch quantization value of the accelerometer can be calculated according to the input signal when the electrostatic force on the intermediate plate is 0, with high accuracy. And the present application only calculates the capacitance mismatch quantization value based on the input signal output by the controller, avoiding the influence of parasitic capacitance on the detection result, and further improving the detection accuracy of the capacitance mismatch quantization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of a capacitor differential structure in one embodiment;

[0025] Figure 2 1 is a schematic structural diagram of a capacitance mismatch detection circuit in one embodiment;

[0026] Figure 3 is another structural schematic diagram of a capacitance mismatch detection circuit in one embodiment;

[0027] Figure 4 is another structural schematic diagram of a capacitance mismatch detection circuit in one embodiment;

[0028] Figure 5 is another structural schematic diagram of a capacitance mismatch detection circuit in one embodiment;

[0029] Figure 6 is another structural schematic diagram of a capacitance mismatch detection circuit in one embodiment;

[0030] Figure 7 is another structural schematic diagram of a capacitance mismatch detection circuit in one embodiment;

[0031] Figure 8 is another structural schematic diagram of a capacitance mismatch detection circuit in one embodiment;

[0032] Figure 9 FIG. 4 is a flow chart of a capacitance mismatch detection method in one embodiment. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0034] Capacitive MEMS accelerometer is an inertial sensor used to measure the acceleration of a carrier and is widely used in automotive electronics, aerospace, medical equipment, geological exploration and other fields.

[0035] Capacitive MEMS accelerometers mainly measure the acceleration of the carrier through differential capacitance structures, such as Figure 1 As shown, the differential capacitance structure of a capacitive MEMS accelerometer consists of an upper plate, an intermediate plate, and a lower plate, with the intermediate plate being located between the upper and lower plates. The upper and intermediate plates form one intrinsic capacitance, and the lower and intermediate plates form another intrinsic capacitance. The upper and lower plates of the capacitive MEMS accelerometer are fixed to anchor points, with the intermediate plate initially located midway between the upper and lower plates. However, due to manufacturing errors, the intermediate plate of the differential capacitance structure is not strictly located midway between the upper and lower plates, resulting in intrinsic capacitance mismatch in the capacitive MEMS accelerometer, thereby affecting the measurement results of the capacitive MEMS accelerometer. Therefore, how to detect the intrinsic capacitance mismatch value of a capacitive MEMS accelerometer has become a technical problem that urgently needs to be solved.

[0036] In one embodiment, a capacitance mismatch detection circuit is provided. Figure 2 As shown, the capacitance mismatch detection circuit is connected to the differential capacitance structure of the accelerometer, and the capacitance mismatch detection circuit includes an input circuit 10 and a controller 20; the input circuit 10 is respectively connected to the upper plate and the lower plate of the differential capacitance structure, the output end of the controller 20 is connected to the input circuit, and the input end of the controller is connected to the middle plate of the differential capacitance structure; the input circuit 10 is used to obtain an input signal and apply a voltage to the upper and lower plates of the differential capacitance structure according to the input signal; the controller 20 is used to obtain the output signal of the middle plate of the differential capacitance structure, and when the output signal meets a preset condition, determine the capacitance mismatch quantization value of the differential capacitance structure according to the input signal.

[0037] The capacitance mismatch quantization value is the capacitance difference between the first intrinsic capacitance formed by the upper plate and the middle plate and the second intrinsic capacitance formed by the lower plate and the middle plate, as shown in the following formula (1):

[0038]

[0039] Where ΔC is the capacitance mismatch quantization value of the differential capacitor structure; C T C is the capacitance of the first intrinsic capacitor composed of the upper plate and the middle plate;B is the capacitance value of the second intrinsic capacitor composed of the lower plate and the middle plate; ε0 is the vacuum dielectric constant; ε r is the relative dielectric constant between the plates; S is the overlapping area between the plates; d T is the distance between the middle plate and the upper plate; d B is the distance between the middle plate and the lower plate; d0 is the distance from the middle position of the upper plate and the lower plate to the upper plate (or lower plate), that is, the distance from the ideal position of the middle plate to the upper plate (or lower plate).

[0040] Where Δd is the distance that the middle plate deviates from the ideal position, as shown in the following formula (2):

[0041]

[0042] In an embodiment of the present application, the input circuit 10 is respectively connected to the upper plate and the lower plate of the differential capacitor structure, and is used to apply voltage to the upper plate and the lower plate of the differential capacitor structure according to the input signal output by the controller 20; the controller 20 can also adjust the electrostatic force on the middle plate of the differential capacitor structure by adjusting the DC voltage in the applied voltage.

[0043] The electrostatic force on the middle plate is the difference between the electrostatic force generated by the upper plate and the electrostatic force generated by the lower plate.

[0044] When the acceleration of the accelerometer is 0 and the electrostatic force on the middle plate is 0, the electrostatic force on the middle plate is expressed as follows (3):

[0045]

[0046] According to the above formula (3), the relationship between the distance between the upper and lower plates and the middle plate and the DC voltage applied to the upper and lower plates can be obtained as shown in the following formula (4):

[0047]

[0048] Among them, V T V is the DC voltage of the voltage loaded on the upper plate of the input circuit 10; B The DC voltage is the voltage applied to the lower plate of the input circuit 10 .

[0049] The above Denoted as the plate spacing coefficient α, and substituted into formula (2), it can be obtained that when the electrostatic force on the middle plate is 0, the distance the middle plate deviates from the ideal position is shown in the following formula (5):

[0050]

[0051] Substituting the above formula (5) into formula (1), we can get the quantized value of the capacitance mismatch of the accelerometer when the electrostatic force on the middle plate is 0, as shown in the following formula (6):

[0052]

[0053] As can be seen from the above formula (6), when the acceleration of the accelerometer is 0 and the electrostatic force on the middle plate is 0, the quantitative value of the capacitance mismatch of the accelerometer can be calculated from the plate spacing coefficient, that is, it can be calculated from the DC voltage loaded on the upper plate and the lower plate by the input circuit 10.

[0054] Therefore, in the embodiment of the present application, the DC voltage (ie, V T ) and the DC voltage of the lower plate (ie V B ) is adjusted, and then the DC voltage loaded on the upper plate and the lower plate when the electrostatic force on the middle plate is 0 is obtained. Then, the capacitance mismatch quantization value of the accelerometer is directly calculated according to the DC voltage obtained above through the above formula (6).

[0055] In an embodiment of the present application, the controller 20 can output an input signal to the input circuit 10, and in the process of adjusting the DC voltage loaded on the upper plate and the lower plate of the capacitor differential structure, obtain the output signal of the middle plate of the differential capacitor structure, and judge whether the output signal meets the preset conditions. If the output signal meets the preset conditions, it is determined that the electrostatic force on the middle plate is 0; if the output signal does not meet the preset conditions, it is determined that the electrostatic force on the middle plate is not 0. Then, the controller 20 can obtain the input signal when the output signal meets the preset conditions (that is, when the electrostatic force on the middle plate is 0), and determine the DC voltage loaded on the upper plate and the lower plate based on the input signal, and then calculate the capacitance mismatch quantization value of the accelerometer based on the DC voltage through the above formula (6).

[0056] The output signal meeting the preset condition may be that the output signal is equal to the output signal when the intermediate plate is not subjected to electrostatic force, or the difference between the output signal and the output signal when the intermediate plate is not subjected to electrostatic force is less than a preset threshold.

[0057] The capacitance mismatch detection circuit provided by the embodiment of the present application includes an input circuit and a controller, and a control signal (input signal) can be output to the input circuit by the controller, so that the input circuit applies a voltage to the upper plate and the lower plate of the capacitance differential structure of the accelerometer according to the input signal, and adjusts the electrostatic force received by the intermediate plate of the capacitance differential structure by adjusting the voltage applied to the upper plate and the lower plate. At the same time, the controller determines whether the electrostatic force received by the intermediate plate is 0 by judging whether the output signal of the intermediate plate meets the preset conditions, and when the output signal meets the preset conditions, according to the corresponding input signal, the capacitance mismatch quantization value of the accelerometer is calculated according to a preset formula. The capacitance mismatch detection circuit provided by the embodiment of the present application can be obtained by adjusting the voltage applied to the upper and lower plates of the capacitance differential structure of the accelerometer, that is, when the electrostatic force received by the intermediate plate is 0, the capacitance mismatch quantization value of the accelerometer is calculated by a formula, with high accuracy. And the present application is only based on the DC voltage to calculate the capacitance mismatch quantization value, which avoids the influence of parasitic capacitance on the detection result and further improves the detection accuracy of the capacitance mismatch quantization value.

[0058] In one embodiment, the input circuit 10 is used to obtain an input signal and apply a first voltage to the upper plate of the differential capacitor structure and a second voltage to the lower plate of the differential capacitor structure according to the input signal; wherein the first voltage and the second voltage have opposite phases and opposite voltage values ​​during zero-bias detection, and have opposite phases and different voltage values ​​during mismatch detection; the controller 20 is used to respectively obtain the output signal of the middle plate of the differential capacitor structure during zero-bias detection and the output signal of the middle plate of the differential capacitor structure during mismatch detection, and determine that the output signal meets the preset conditions when the output signal detected by zero-bias matches the output signal detected by mismatch.

[0059] In an embodiment of the present application, the differential capacitor structure can be first subjected to zero-bias detection to obtain the output signal of the intermediate plate when the electrostatic force applied to it is 0. Specifically, the controller 20 can control the input circuit 10 to apply a first voltage to the upper plate of the differential capacitor structure and a second voltage to the lower plate. The first voltage and the second voltage are AC voltages, and the first voltage and the second voltage have opposite phases and opposite voltage values. For example, the first voltage can be a square wave signal with a duty cycle of 50%, a low level of 0V, and a high level of 3V; the second low voltage can be a square wave signal with a duty cycle of 50%, a low level of -3V, and a high level of 0V, and when the first voltage is high, the second voltage is low. The first voltage is used to charge the first intrinsic capacitor at a high level and to discharge the first intrinsic capacitor at a low level; the second voltage is used to charge the second intrinsic capacitor at a high level and to discharge the second intrinsic capacitor at a low level. Because the first and second intrinsic capacitors have different capacitances, they accumulate different amounts of charge during the charging and discharging process. This generates a charge difference on the intermediate plate, which in turn generates and outputs a current. This current is referred to as the zero-position current, the output signal of the intermediate plate of the differential capacitor structure during zero-bias detection. The controller 20 can obtain and record this zero-position current.

[0060] Then, the differential capacitor structure can be mismatched. Specifically, the controller 20 can control the input circuit 10 to apply a first voltage to the upper plate of the differential capacitor structure and a second voltage to the lower plate. The first voltage includes an AC voltage and a DC voltage (i.e., V T ), the second voltage includes an AC voltage and a DC voltage (ie V B ), and the first and second voltages have opposite phases and different voltage values. For example, the first voltage can be a square wave signal with a 50% duty cycle, a low level of 5V, and a high level of 8V; the second low voltage can be a square wave signal with a 50% duty cycle, a low level of 1V, and a high level of 4V, with the second voltage being low when the first voltage is high. The AC voltage is used to charge and discharge the intrinsic capacitance, resulting in an output signal on the intermediate plate; the DC voltage is used to adjust the electrostatic force on the intermediate plate, thereby adjusting the output signal from the intermediate plate.

[0061] Therefore, the controller 20 can adjust the DC voltage (ie, V T ) and the DC voltage in the second voltage (ie V B) to adjust the output signal of the intermediate plate. When the output signal of the intermediate plate is equal to the output signal (zero-position current) during zero-bias detection, or when the difference between the output signal of the intermediate plate and the zero-position current is less than a preset threshold, it is determined that the output signal meets the preset condition. At this time, the electrostatic force on the intermediate plate is 0. The magnitude of the DC voltage in the first voltage and the magnitude of the DC voltage in the second voltage corresponding to the output signal are recorded. Based on the above two DC voltages and the above formula (6), the capacitance mismatch quantization value of the accelerometer can be calculated.

[0062] The capacitance mismatch detection circuit provided in the embodiment of the present application can first obtain the output signal of the intermediate plate during zero bias detection, that is, determine the output signal when the intermediate plate is not subjected to electrostatic force. Then adjust the voltage applied to the upper and lower plates, perform mismatch detection on the capacitance differential structure, and obtain the output signal of the intermediate plate at the same time. When the output signal detected by the mismatch matches the output signal detected by the zero bias, it is determined that the electrostatic force on the intermediate plate at this time is 0, and the output signal detected by the mismatch meets the preset conditions. The embodiment of the present application uses the output signal when the intermediate plate is not subjected to electrostatic force as the standard, judges the output signal detected by the mismatch, and obtains the corresponding DC voltage value when the output signal detected by the mismatch matches the standard output signal. The DC voltage value obtained is made more accurate, and then, the capacitance mismatch quantization value calculated based on the accurate DC voltage is also more accurate.

[0063] In one embodiment, Figure 3 As shown, the input signal includes a first input signal and a second input signal, and the input circuit 10 includes a first input circuit 11 and a second input circuit 12. The first input circuit 11 is connected to the upper plate of the differential capacitor structure, and the second input circuit 12 is connected to the lower plate of the differential capacitor structure; the first input circuit 11 is used to apply a first voltage to the upper plate of the differential capacitor structure according to the first input signal; the second input circuit 12 is used to apply a second voltage to the lower plate of the differential capacitor structure according to the second input signal.

[0064] In an embodiment of the present application, the input circuit may include two branches, and the controller 20 may output two input signals to apply voltages to the upper plate and the lower plate of the differential capacitor structure through the two branches. For example, the controller 20 may output a first input signal to apply voltage to the upper plate through the first input circuit 11; the controller 20 may output a second input signal to apply voltage to the lower plate through the second input circuit 12. This avoids interference between the two input signals, improves the control accuracy of the controller, and thus improves the accuracy of the voltage applied to the upper and lower plates, thereby improving the detection accuracy of the capacitance mismatch quantization value.

[0065] In one embodiment, Figure 4As shown, the first input circuit 11 includes a first modulator 111; the first input terminal and the second input terminal of the first modulator 111 are both connected to the controller 20, and the output terminal of the first modulator 111 is connected to the upper plate of the capacitor differential structure; the first modulator 111 is used to modulate the first modulation signal inputted from the second input terminal according to the first carrier signal inputted from the first input terminal to obtain a first voltage, and apply the first voltage to the upper plate of the differential capacitor structure; wherein, the first modulation signal is 0 during zero-bias detection. The second input circuit 12 includes a second modulator 121; the third input terminal and the fourth input terminal of the second modulator 121 are both connected to the controller 20, and the output terminal of the second modulator 121 is connected to the lower plate of the capacitor differential structure; the second modulator 121 is used to modulate the second modulation signal inputted from the fourth input terminal according to the second carrier signal inputted from the third input terminal to obtain a second voltage, and apply the second voltage to the lower plate of the differential capacitor structure; wherein, the second modulation signal is 0 during zero-bias detection.

[0066] The first modulator and the second modulator may be adders.

[0067] In an embodiment of the present application, the input circuit 10 can modulate a DC voltage through a modulator to obtain a voltage applied to the upper and lower plates of the capacitor differential structure. The modulation signal can be the DC signal described above, and the carrier signal can be the AC signal described above. The DC signal is modulated by the AC signal to obtain a modulated signal, which is the voltage applied to the upper and lower plates. For example, when the modulation signal is a 5V DC voltage signal, the carrier signal is a square wave signal with a duty cycle of 50%, a low level of 0V, and a high level of 3V, and the modulator is an adder, the modulator modulates the modulation signal based on the carrier signal to obtain a modulated signal with a duty cycle of 50%, a low level of 5V, and a high level of 8V. When the modulation signal is a 4V DC voltage signal, the carrier signal is a square wave signal with a duty cycle of 50%, a low level of -3V, and a high level of 0V, and the modulator is an adder, the modulator modulates the modulation signal based on the carrier signal to obtain a modulated signal with a duty cycle of 50%, a low level of 1V, and a high level of 4V. The modulation signal (ie, the DC signal) is 0 during zero-bias detection, so that the electrostatic force on the middle plate is 0 during zero-bias detection.

[0068] In the embodiment of the present application, the input circuit 10 may include two branches, a first input circuit 11 and a second input circuit 12. The first input circuit 11 includes two input terminals, a first input terminal and a second input terminal, for respectively receiving the first carrier signal (AC signal) and the first modulation signal (DC signal, i.e., V T), and modulates the first modulation signal based on the first carrier signal to obtain a first voltage, which is applied to the upper plate of the differential capacitor structure; the second input circuit 12 includes two input terminals, a third input terminal and a fourth input terminal, for respectively receiving the second carrier signal (AC signal) and the second modulation signal (DC signal, i.e., V B ), and modulates the second modulation signal based on the second carrier signal to obtain a second voltage, which is applied to the lower plate of the differential capacitor structure. The first modulation signal and the second modulation signal are zero during zero-bias detection, so that the electrostatic force on the middle plate is zero during zero-bias detection.

[0069] The capacitance mismatch detection circuit provided in the embodiments of the present application can modulate a DC voltage based on an AC voltage, so that the resulting voltage can both charge and discharge the upper and lower plates, generate an output signal on the middle plate, and adjust the magnitude of the output signal. This allows the accelerometer's capacitance mismatch quantization value to be calculated based on the corresponding first and second modulation signals when the output signal from the middle plate meets preset conditions. Simultaneously transmitting signals through two branches avoids interference between the signals and improves the detection accuracy of the capacitance mismatch quantization value.

[0070] In one embodiment, Figure 5 As shown, the capacitance mismatch detection circuit also includes a charge amplifier 30, the inverting input terminal of the charge amplifier 30 is connected to the middle plate of the capacitance differential structure, the non-inverting input terminal of the charge amplifier 30 is grounded, and the output terminal of the charge amplifier is connected to the controller; the charge amplifier 30 is used to amplify the output signal of the middle plate of the capacitance differential structure to obtain an amplified signal; the controller 20 is used to use the amplified signal as the output signal, and when the output signal meets the preset conditions, determine the capacitance mismatch quantization value of the differential capacitance structure according to the input signal.

[0071] In the embodiment of the present application, since the signal strength of the output signal generated by the intermediate plate is relatively small, directly detecting and receiving it by the controller 20 may result in the controller 20 not receiving the output signal. Therefore, a charge amplifier 30 can be connected between the intermediate plate and the controller 20. The charge amplifier 30 can amplify the signal output by the intermediate plate to obtain an amplified signal, and at the same time output the amplified signal as an output signal to the controller 20, so that the controller 20 receives the output signal and determines whether the output signal meets the preset conditions. For example, if it is determined that the output signal is equal to the output signal of the charge amplifier 30 during zero-bias detection, or the difference between the output signal and the output signal of the charge amplifier 30 during zero-bias detection is less than a preset threshold, it is determined that the output signal meets the preset conditions. When the output signal meets the preset conditions, the capacitance mismatch quantization value of the differential capacitance structure is calculated according to the input signal according to the above formula (6).

[0072] In an embodiment of the present application, the charge amplifier 30 can amplify the weak signal output by the intermediate plate, so that the controller 20 can accurately receive the signal output by the intermediate plate, making the input signal determined based on the more accurate output signal more accurate, thereby improving the accuracy of the accelerometer capacitance mismatch quantization value.

[0073] In one embodiment, the structure of the charge amplifier 30 can be as follows: Figure 6 As shown, it includes: a feedback capacitor 301, a resistor 302 and an operational amplifier 303; the two ends of the feedback capacitor 301 are respectively connected to the inverting input and output of the operational amplifier 303; the two ends of the resistor 302 are respectively connected to the inverting input and output of the operational amplifier 303; the inverting input of the operational amplifier 303 is connected to the middle plate of the capacitor differential structure, the non-inverting input of the operational amplifier 303 is grounded, and the output of the operational amplifier 303 is connected to the controller 20.

[0074] In the embodiment of the present application, the current signal output by the intermediate plate can charge the feedback capacitor in the charge amplifier 30, thereby forming a voltage signal at the output terminal of the charge amplifier, and outputting the voltage signal as an output signal to the controller 20. In the embodiment of the present application, the charge amplifier 30 can amplify the current signal output by the intermediate plate, convert it into a voltage signal, and output it to the controller 20, so that the controller 20 can accurately receive the signal output by the intermediate plate. The input signal determined based on the more accurate output signal is more accurate, thereby improving the accuracy of the quantized value of the accelerometer capacitance mismatch.

[0075] In one embodiment, Figure 7 As shown, the capacitance mismatch detection circuit further includes: a demodulator 40; an input end of the demodulator 40 is connected to an output end of the charge amplifier 30, and an output end of the demodulator 40 is connected to a controller 20; the demodulator 40 is used to demodulate the output voltage of the charge amplifier 30 to obtain a demodulated signal; the controller 20 is used to use the demodulated signal as an output signal, and when the output signal meets a preset condition, determine the capacitance mismatch quantization value of the differential capacitance structure according to the input signal.

[0076] The demodulator may be a multiplier.

[0077] In an embodiment of the present application, a demodulator 40 can also be connected between the charge amplifier 30 and the controller 20 to demodulate the voltage signal output by the charge amplifier 30 and convert the high-frequency voltage signal output by the charge amplifier 30 into a low-frequency voltage signal, thereby filtering out noise accumulation, making the voltage signal input to the controller 20 more accurate, and further improving the accuracy of the accelerometer capacitance mismatch quantization value.

[0078] It should be noted that due to the influence of factors such as mutual capacitance between wiring, parasitic capacitance is inevitably generated in the circuit. Figure 8 As shown, the capacitance mismatch detection circuit further includes a first parasitic capacitor 50, a second parasitic capacitor 60, and a third parasitic capacitor 70. The first parasitic capacitor 50 is a parasitic capacitor between the upper plate of the capacitance differential structure and the inverting input terminal of the charge amplifier 30, the second parasitic capacitor 60 is a parasitic capacitor between the lower plate of the capacitance differential structure and the inverting input terminal of the charge amplifier 30, and the third parasitic capacitor 70 is a parasitic capacitor between the inverting input terminal of the charge amplifier 30 and ground.

[0079] The capacitance mismatch detection circuit provided in the embodiment of the present application can adjust the voltage applied to the upper and lower plates of the accelerometer's capacitance differential structure, and can calculate the capacitance mismatch quantization value of the accelerometer through a formula when the electrostatic force on the middle plate is 0. The calculation result of the quantization value is only related to the voltage loaded on the upper and lower plates, avoiding the influence of parasitic capacitance in the circuit on the detection result, and improving the detection accuracy of the capacitance mismatch quantization value.

[0080] In one embodiment, Figure 9 As shown, a capacitance mismatch detection method is also provided, which is applied to the capacitance mismatch detection circuit in the above embodiment. The method includes the following steps:

[0081] Step 101: Obtain an input signal, and apply voltage to the upper and lower plates of the differential capacitor structure according to the input signal;

[0082] Step 102: obtaining an output signal of the middle plate of the differential capacitor structure;

[0083] Step 103 : When the output signal meets a preset condition, determine a capacitance mismatch quantization value of the differential capacitance structure according to the input signal.

[0084] In an embodiment of the present application, while keeping the acceleration of the accelerometer at 0, a voltage can be applied to the upper and lower plates of the differential capacitor structure according to the input signal, and the DC voltage loaded on the upper and lower plates of the capacitor differential structure can be adjusted. During the adjustment process, the output signal of the middle plate of the differential capacitor structure is obtained to determine whether the output signal meets the preset conditions. If the output signal meets the preset conditions, it is determined that the electrostatic force on the middle plate is 0; if the output signal does not meet the preset conditions, it is determined that the electrostatic force on the middle plate is not 0. Then, the input signal is obtained when the output signal meets the preset conditions (that is, when the electrostatic force on the middle plate is 0), and the DC voltage loaded on the upper and lower plates is determined based on the input signal, and then based on the DC voltage, the formula is used. The capacitance mismatch quantization value of the accelerometer is calculated.

[0085] Where ΔC is the capacitance mismatch quantization value of the differential capacitor structure; ε0 is the vacuum dielectric constant; ε r is the relative dielectric constant between the plates; S is the overlap area between the plates; d0 is the distance from the middle position of the upper plate and the lower plate to the upper plate (or lower plate), that is, the distance from the ideal position of the middle plate to the upper plate (or lower plate); α is the plate spacing coefficient, and Among them, ε0, ε r , S and d0 are known values. ε r The size of S and d0 can be determined by the factory marking of the accelerometer, or by microscopic testing, such as using a micro electron microscope to obtain S; d0 can be obtained by the accelerometer scale factor calculation formula; ε can be obtained by looking up the table based on the accelerometer packaging form. r .

[0086] The output signal meeting the preset condition may be that the output signal is equal to the output signal when the intermediate plate is not subjected to electrostatic force, or the difference between the output signal and the output signal when the intermediate plate is not subjected to electrostatic force is less than a preset threshold.

[0087] In one possible implementation, during the process of adjusting the voltage applied to the upper and lower plates, the output signal received by the controller may not be strictly equal to the output signal detected by the zero-bias detector. Therefore, the two output signals closest to the output signal detected by the zero-bias detector, along with the input signals corresponding to these two output signals, can be recorded. Interpolation is then used to calculate the input signal corresponding to the point at which the output signal and the output signal detected by the zero-bias detector are equal. The accelerometer's capacitance mismatch value can then be calculated based on this input signal.

[0088] In a possible implementation, the accelerometer may be fixedly placed on a dividing head device, and the acceleration of the accelerometer may be set to 0 by adjusting the dividing head.

[0089] In one possible implementation, the capacitance mismatch quantification value can also be used to evaluate the product quality consistency of accelerometers. Because the plate spacing coefficient reflects the capacitance mismatch quantification value of an accelerometer, the plate spacing coefficient can be directly obtained for products from the same batch. The plate spacing coefficients of each accelerometer in the batch can then be used to determine the product quality consistency of the accelerometers in the batch.

[0090] The capacitance mismatch detection circuit provided by the embodiment of the present application includes an input circuit and a controller, and a control signal (input signal) can be output to the input circuit by the controller, so that the input circuit applies a voltage to the upper plate and the lower plate of the capacitance differential structure of the accelerometer according to the input signal, and adjusts the electrostatic force received by the intermediate plate of the capacitance differential structure by adjusting the voltage applied to the upper plate and the lower plate. At the same time, the controller determines whether the electrostatic force received by the intermediate plate is 0 by judging whether the output signal of the intermediate plate meets the preset conditions, and when the output signal meets the preset conditions, according to the corresponding input signal, the capacitance mismatch quantization value of the accelerometer is calculated according to a preset formula. The capacitance mismatch detection circuit provided by the embodiment of the present application can be obtained by adjusting the voltage applied to the upper and lower plates of the capacitance differential structure of the accelerometer, that is, when the electrostatic force received by the intermediate plate is 0, the capacitance mismatch quantization value of the accelerometer is calculated by a formula, with high accuracy. And the present application is only based on the DC voltage to calculate the capacitance mismatch quantization value, which avoids the influence of parasitic capacitance on the detection result and further improves the detection accuracy of the capacitance mismatch quantization value.

[0091] The above-mentioned embodiment introduces a scheme for applying voltage to the upper and lower plates of the differential capacitor structure according to the input signal. In another embodiment of the present application, voltage can be applied to the upper plate and the lower plate respectively through two branches, specifically including the following steps:

[0092] An input signal is obtained, and a first voltage is applied to the upper plate of the differential capacitor structure and a second voltage is applied to the lower plate of the differential capacitor structure according to the input signal; wherein the first voltage and the second voltage have opposite phases and opposite voltage values ​​during zero-bias detection, and have opposite phases and different voltage values ​​during mismatch detection.

[0093] In an embodiment of the present application, voltages can be applied to the upper plate and the lower plate of the differential capacitor structure through two branches, respectively. A first voltage is applied to the upper plate of the differential capacitor structure, and a second voltage is applied to the lower plate of the differential capacitor structure, thereby avoiding interference between input signals and improving the control accuracy of the controller, that is, improving the accuracy of the voltage applied to the upper and lower plates, thereby improving the detection accuracy of the capacitance mismatch quantization value.

[0094] Among them, the first voltage and the second voltage have opposite phases and opposite voltage values ​​during zero-bias detection, so that the electrostatic force on the middle plate of the capacitor differential structure can be guaranteed to be 0 during zero-bias detection, and the first intrinsic capacitance composed of the upper plate and the middle plate can be charged and discharged by the first voltage, and the second intrinsic capacitance composed of the lower plate and the middle plate can be charged and discharged by the second voltage, so that there is an output signal on the middle plate, and the output signal is used as the zero-position signal.

[0095] During mismatch detection, the first and second voltages have opposite phases but different voltage values. The magnitude of the output signal from the intermediate plate is altered by adjusting the DC voltage of the first and second voltages. During the adjustment process, a determination is made as to whether the output signal meets a preset condition. A quantized capacitance mismatch value of the accelerometer is calculated based on the DC voltage corresponding to the output signal meeting the preset condition.

[0096] The method provided in the embodiment of the present application can apply voltage to the upper plate and the lower plate respectively through two branches, thereby avoiding interference between signals and improving the detection accuracy of the capacitance mismatch quantization value.

[0097] In another embodiment of the present application, the process of determining whether the output signal meets the preset condition may specifically include the following steps:

[0098] A first output signal of the middle plate of the differential capacitor structure during zero-bias detection and a second output signal of the middle plate of the differential capacitor structure during mismatch detection are respectively obtained, and when the first output signal and the second output signal match, it is determined that the output signal meets the preset condition.

[0099] In an embodiment of the present application, a zero-bias test can be first performed on the differential capacitor structure to obtain an output signal when the electrostatic force applied to the middle plate is 0, as a first output signal. Then, a mismatch test can be performed on the differential capacitor structure to adjust the voltage applied to the upper plate and the lower plate to obtain a second output signal. When the second output signal is equal to the first output signal, or when the difference between the second output signal and the first output signal is less than a preset threshold, it is determined that the second output signal meets the preset condition.

[0100] In the embodiment of the present application, the first output signal when the intermediate plate is not subjected to electrostatic force is used as a standard to judge the second output signal detected by the mismatch, and the second output signal that is equal to the first output signal, or the difference between the second output signal and the first output signal is less than a preset threshold, is judged to meet the preset conditions, thereby improving the accuracy of the input signal determined based on the second output signal and further improving the detection accuracy of the capacitance mismatch quantization value.

[0101] In one embodiment, a detection device is further provided, which includes a capacitance mismatch detection circuit as described in the above embodiment. The capacitance mismatch detection circuit is connected to the differential capacitance structure of the accelerometer, and the capacitance mismatch detection circuit includes an input circuit and a controller; the input circuit is respectively connected to the upper plate and the lower plate of the differential capacitance structure, the output end of the controller is connected to the input circuit, and the input end of the controller is connected to the middle plate of the differential capacitance structure; the input circuit can obtain an input signal and apply a voltage to the upper and lower plates of the differential capacitance structure according to the input signal; the controller can obtain the output signal of the middle plate of the differential capacitance structure and determine the capacitance mismatch quantization value of the differential capacitance structure according to the input signal when the output signal meets a preset condition.

[0102] In an embodiment of the present application, the input circuit can also obtain an input signal, and apply a first voltage to the upper plate of the differential capacitor structure and a second voltage to the lower plate of the differential capacitor structure according to the input signal; wherein the first voltage and the second voltage are opposite in phase and voltage value during zero-bias detection, and opposite in phase and voltage value during mismatch detection; the controller can also respectively obtain the output signal of the middle plate of the differential capacitor structure during zero-bias detection and the output signal of the middle plate of the differential capacitor structure during mismatch detection, and determine that the output signal meets the preset condition when the output signal detected by zero bias matches the output signal detected by mismatch. wherein the input signal includes a first input signal and a second input signal, the input circuit includes a first input circuit and a second input circuit, the first input circuit is connected to the upper plate of the differential capacitor structure, and the second input circuit is connected to the lower plate of the differential capacitor structure; the first input circuit can apply a first voltage to the upper plate of the differential capacitor structure according to the first input signal; the second input circuit can apply a second voltage to the lower plate of the differential capacitor structure according to the second input signal.

[0103] In an embodiment of the present application, the first input circuit may include a first modulator; the first input terminal and the second input terminal of the first modulator are both connected to the controller, and the output terminal of the first modulator is connected to the upper plate of the differential capacitor structure. The first modulator can modulate the first modulation signal input to the second input terminal according to the first carrier signal input to the first input terminal to obtain a first voltage, and apply the first voltage to the upper plate of the differential capacitor structure; wherein the first modulation signal is 0 during zero-bias detection.

[0104] In an embodiment of the present application, the second input circuit may include a second modulator; the third input terminal and the fourth input terminal of the second modulator are both connected to the controller, and the output terminal of the second modulator is connected to the lower plate of the capacitor differential structure; the second modulator can modulate the second modulation signal input at the fourth input terminal according to the second carrier signal input at the third input terminal to obtain a second voltage, and apply the second voltage to the lower plate of the differential capacitor structure; wherein the second modulation signal is 0 during zero bias detection.

[0105] In an embodiment of the present application, the capacitance mismatch detection circuit may further include a charge amplifier, wherein the inverting input of the charge amplifier is connected to the middle plate of the capacitance differential structure, the non-inverting input of the charge amplifier is grounded, and the output of the charge amplifier is connected to the controller. The charge amplifier may amplify the output signal of the middle plate of the capacitance differential structure to obtain an amplified signal; the controller may use the amplified signal as an output signal, and determine a capacitance mismatch quantization value of the differential capacitance structure based on the input signal when the output signal meets a preset condition.

[0106] In an embodiment of the present application, the capacitance mismatch detection circuit may further include a demodulator; the input end of the demodulator is connected to the output end of the charge amplifier, and the output end of the demodulator is connected to the controller; the demodulator can demodulate the output voltage of the charge amplifier to obtain a demodulated signal; the controller can use the demodulated signal as an output signal, and when the output signal meets a preset condition, determine the capacitance mismatch quantization value of the differential capacitance structure according to the input signal.

[0107] The detection device provided by the present application includes the capacitance mismatch detection circuit in the above embodiment. The capacitance mismatch detection circuit can adjust the voltage applied to the upper and lower plates of the accelerometer's capacitance differential structure, and can calculate the capacitance mismatch quantization value of the accelerometer based on the input signal when the electrostatic force on the middle plate is 0, with high accuracy. The capacitance mismatch quantization value is calculated based only on the input signal output by the controller, avoiding the influence of parasitic capacitance on the detection result, and further improving the detection accuracy of the capacitance mismatch quantization value. Therefore, the detection device including the capacitance mismatch detection circuit also has a high accuracy in detecting the capacitance mismatch quantization value of the accelerometer.

[0108] It should be understood that, although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in the various embodiments described above can include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0109] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processor involved in the various embodiments provided herein may be, but are not limited to, a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, and the like.

[0110] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0111] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A capacitance mismatch detection circuit, characterized in that: The capacitance mismatch detection circuit is connected to the differential capacitance structure of the accelerometer, and the capacitance mismatch detection circuit includes an input circuit and a controller; the input circuit is respectively connected to the upper plate of the differential capacitance structure and the lower plate of the differential capacitance structure, the output end of the controller is connected to the input circuit, and the input end of the controller is connected to the middle plate of the differential capacitance structure; The input circuit is used to obtain an input signal and apply voltage to the upper and lower plates of the differential capacitor structure according to the input signal; The controller is configured to obtain an output signal of the intermediate plate of the differential capacitor structure, and when the output signal meets a preset condition, determine that the electrostatic force on the intermediate plate is 0, and determine a capacitance mismatch quantization value of the differential capacitor structure based on the input signal; the capacitance mismatch quantization value of the differential capacitor structure Where ε0 is the dielectric constant of vacuum, ε r is the relative dielectric constant between the plates, S is the overlapping area between the plates, d0 is the distance from the middle position of the upper plate and the lower plate to the upper plate or the lower plate, α is the plate spacing coefficient, When the acceleration of the accelerometer is 0 and the electrostatic force on the middle plate is 0, d T is the distance between the middle plate and the upper plate, d B is the distance between the middle plate and the lower plate, V T V is the DC voltage in the voltage loaded on the upper plate of the input circuit. B The DC voltage in the voltage loaded on the lower plate of the input circuit; The output signal meeting the preset condition includes: the output signal of the intermediate plate matches the output signal during zero-bias detection.

2. The circuit according to claim 1, wherein: The input circuit is configured to obtain the input signal and apply a first voltage to the upper plate of the differential capacitor structure and a second voltage to the lower plate of the differential capacitor structure according to the input signal; wherein the first voltage and the second voltage have opposite phases and opposite voltage values ​​during zero-bias detection, and have opposite phases and different voltage values ​​during mismatch detection; The controller is used to respectively obtain the output signal of the middle plate of the differential capacitor structure during zero-bias detection and the output signal of the middle plate of the differential capacitor structure during mismatch detection, and when the output signal detected by zero-bias matches the output signal detected by mismatch, determine that the output signal meets the preset condition.

3. The circuit according to claim 2, characterized in that The input signal includes a first input signal and a second input signal, the input circuit includes a first input circuit and a second input circuit, the first input circuit is connected to the upper plate of the differential capacitor structure, and the second input circuit is connected to the lower plate of the differential capacitor structure; The first input circuit is configured to apply a first voltage to the upper plate of the differential capacitor structure according to the first input signal; The second input circuit is configured to apply a second voltage to the lower plate of the differential capacitor structure according to the second input signal.

4. The circuit according to claim 3, characterized in that The first input circuit includes a first modulator; the first input terminal and the second input terminal of the first modulator are both connected to the controller, and the output terminal of the first modulator is connected to the upper plate of the differential capacitor structure; The first modulator is used to modulate the first modulation signal input from the second input end according to the first carrier signal input from the first input end to obtain the first voltage, and apply the first voltage to the upper plate of the differential capacitor structure; wherein the first modulation signal is 0 during zero bias detection.

5. The circuit according to claim 3, characterized in that The second input circuit includes a second modulator; the third input terminal and the fourth input terminal of the second modulator are both connected to the controller, and the output terminal of the second modulator is connected to the lower plate of the differential capacitor structure; The second modulator is used to modulate the second modulation signal input from the fourth input terminal according to the second carrier signal input from the third input terminal to obtain the second voltage, and apply the second voltage to the lower plate of the differential capacitor structure; wherein the second modulation signal is 0 during zero bias detection.

6. The circuit according to claim 1, wherein: The circuit further includes a charge amplifier, wherein an inverting input terminal of the charge amplifier is connected to the middle plate of the differential capacitor structure, a non-inverting input terminal of the charge amplifier is grounded, and an output terminal of the charge amplifier is connected to the controller; The charge amplifier is used to amplify the output signal of the middle plate of the differential capacitor structure to obtain an amplified signal; The controller is configured to use the amplified signal as the output signal, and determine a capacitance mismatch quantization value of the differential capacitance structure according to the input signal when the output signal meets a preset condition.

7. The circuit according to claim 6, characterized in that The charge amplifier includes: a feedback capacitor, a resistor and an operational amplifier; The two ends of the feedback capacitor are respectively connected to the inverting input and output of the operational amplifier; the two ends of the resistor are respectively connected to the inverting input and output of the operational amplifier; the inverting input of the operational amplifier is connected to the middle plate of the differential capacitor structure, the non-inverting input of the operational amplifier is grounded, and the output of the operational amplifier is connected to the controller.

8. The circuit according to claim 6, characterized in that The circuit further comprises: a demodulator; an input end of the demodulator is connected to an output end of the charge amplifier, and an output end of the demodulator is connected to the controller; The demodulator is used to demodulate the output voltage of the charge amplifier to obtain a demodulated signal; The controller is configured to use the demodulated signal as the output signal, and determine a capacitance mismatch quantization value of the differential capacitance structure according to the input signal when the output signal meets a preset condition.

9. A capacitance mismatch detection method, characterized in that: Applied to the capacitance mismatch detection circuit according to any one of claims 1 to 8, the method comprising: Obtaining an input signal, and applying a voltage to the upper and lower plates of the differential capacitor structure according to the input signal; Acquiring an output signal of the middle plate of the differential capacitor structure; When the output signal meets the preset conditions, the electrostatic force on the intermediate plate is determined to be 0, and the capacitance mismatch quantization value of the differential capacitance structure is determined according to the input signal; the capacitance mismatch quantization value of the differential capacitance structure is determined. Where ε0 is the dielectric constant of vacuum, ε r is the relative dielectric constant between the plates, S is the overlapping area between the plates, d0 is the distance from the middle position of the upper plate and the lower plate to the upper plate or the lower plate, and α is the plate spacing coefficient.

10. A detection device, characterized in that: The method comprises the capacitance mismatch detection circuit according to any one of claims 1 to 8.

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